@courageheart
courageheart 暂无简介
Open-source high-performance RISC-V processor
sv2v:从SystemVerilog到Verilog , sv2v将SystemVerilog (IEEE 1800-2017)转换为Verilog (IEEE 1364-200
Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.
