The Ultra-Low Power RISC Core
A demo implementation of a clean architecture in Python
VSCode extension for enhancing verilog
HDL libraries and projects
mor1kx - an OpenRISC 1000 processor IP core
Files in this folder is a public one, used for learning Python.
sequence sythesis example using cache
A subprogram for converting dict data in txt to list
Button driver for embedded system
cache used by awg, this is an unfinished project
