# tmrg

**Repository Path**: woniududu/tmrg

## Basic Information

- **Project Name**: tmrg
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: GPL-2.0
- **Default Branch**: 37_enum_support
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-11-03
- **Last Updated**: 2025-11-03

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# TMRG toolset

The TMRG toolset assists in the process of creating digital designs immune to single event upsets. The immunity is provided by means of triple modular redundancy.

## Documentation

Documentation is avaliable at https://cern.ch/tmrg ([PDF](https://cern.ch/tmrg/tmrg.pdf) , [HTML](https://cern.ch/tmrg/)).

## Installation

Information about how to install the TMRG toolset are avaliable at https://tmrg.web.cern.ch/tmrg/getting_started.html.

## Frequently Asked Questions (FAQ)

Frequently Asked Questions can be found at https://tmrg.web.cern.ch/tmrg/faq.html.

## Build status

Master branch build status: [![build status](https://gitlab.cern.ch/tmrg/tmrg/badges/master/build.svg)](https://gitlab.cern.ch/tmrg/tmrg/commits/master) [![coverage report](https://gitlab.cern.ch/tmrg/tmrg/badges/master/coverage.svg)](https://gitlab.cern.ch/tmrg/tmrg/commits/master) 

## Citations

In papers and reports, please refer to TMRG as follows: 

```  @article{TMRG,
  author={S. Kulis},
  title={Single Event Effects mitigation with TMRG tool},
  journal={Journal of Instrumentation},
  volume={12},
  number={01},
  pages={C01082},
  url={http://stacks.iop.org/1748-0221/12/i=01/a=C01082},
  year={2017},
  abstract={Single Event Effects (SEE) are a major concern for integrated
    circuits exposed to radiation. There have been several techniques
    proposed to protect circuits against radiation-induced upsets. Among the
    others, the Triple Modular Redundancy (TMR) technique is one of the most
    popular. The purpose of the Triple Modular Redundancy Generator (TMRG)
    tool is to automatize the process of triplicating digital circuits
    freeing the designer from introducing the TMR code manually at the
    implementation stage. It helps to ensure that triplicated logic is
    maintained through the design process. Finally, the tool streamlines the
    process of introducing SEE in gate level simulations for final
    verification.}
  }
```

## Licenses

This software is distributed under the terms of the GPL Version 2 license. A copy of this license can be found in [LICENSE.md](LICENSE.md).

## Contributors

  * Szymon Kulis, EP/ESE/ME CERN (@skulis)
  * Stefan Biereigel, EP/ESE/ME CERN (@sbiereig)

## Contributing

All types of contributions, being it minor and major, are very welcome.