diff --git a/0001-x86-Enable-Prefer_No_AVX512-for-Hygon-model-0x8.patch b/0001-x86-Enable-Prefer_No_AVX512-for-Hygon-model-0x8.patch new file mode 100644 index 0000000000000000000000000000000000000000..dad0756dcaf3f1ba58962fdc689e9664eb48b698 --- /dev/null +++ b/0001-x86-Enable-Prefer_No_AVX512-for-Hygon-model-0x8.patch @@ -0,0 +1,35 @@ +From 007a45e00fe4b12685c6216bcb6c390b41b825ba Mon Sep 17 00:00:00 2001 +From: xiejiamei +Date: Wed, 29 Apr 2026 08:20:30 +0000 +Subject: [PATCH 1/2] x86: Enable Prefer_No_AVX512 for Hygon model 0x8 + +Extend the Prefer_No_AVX512 tuning to cover Hygon model 0x8. + +Benchmarks on Hygon platforms show that EVEX implementations +are often more profitable than AVX512 paths. The existing logic +already enables Prefer_No_AVX512 for model 0x7. Apply the same +preference to model 0x8 to ensure consistent IFUNC selection +behavior across newer Hygon processors. + +Signed-off-by: xiejiamei +Reviewed-by: H.J. Lu +--- + sysdeps/x86/cpu-features.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 272646355e..3b580b69f4 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -998,7 +998,7 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht + cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load] + &= ~bit_arch_AVX_Fast_Unaligned_Load; + } +- else if (model == 0x7) ++ else if (model == 0x7 || model == 0x8) + { + /* Benchmarks indicate evex can be more profitable on Hygon + hardware than AVX512. */ +-- +2.17.1 + diff --git a/0002-x86-Lower-non-temporal-copy-threshold-for-Hygon.patch b/0002-x86-Lower-non-temporal-copy-threshold-for-Hygon.patch new file mode 100644 index 0000000000000000000000000000000000000000..67e4ec57e19e651100ab43b5beb9a388bebd0019 --- /dev/null +++ b/0002-x86-Lower-non-temporal-copy-threshold-for-Hygon.patch @@ -0,0 +1,42 @@ +From 3a1976c3896d2446f59e640940fbcfdb86129325 Mon Sep 17 00:00:00 2001 +From: xiejiamei +Date: Sat, 9 May 2026 14:23:09 +0800 +Subject: [PATCH 2/2] x86: Lower non-temporal copy threshold for Hygon + +Benchmarks on Hygon processors show that the default non-temporal +threshold is higher than ideal for large copy workloads. As a result, +memcpy and memmove may continue to use the temporal copy path for +longer than is beneficial, increasing cache pollution and reducing +throughput for large copies. + +Lower the copy non-temporal threshold to 3/8 of the shared cache size +per thread on Hygon. This allows the non-temporal copy path to be +selected earlier while leaving the memset non-temporal threshold +unchanged. + +Signed-off-by: xiejiamei +--- + sysdeps/x86/dl-cacheinfo.h | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h +index a7e316b905..e6edf12e88 100644 +--- a/sysdeps/x86/dl-cacheinfo.h ++++ b/sysdeps/x86/dl-cacheinfo.h +@@ -1239,6 +1239,13 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) + if (!CPU_FEATURES_ARCH_P (cpu_features, Avoid_Non_Temporal_Memset)) + memset_non_temporal_threshold = non_temporal_threshold; + ++ /* Hygon benefits from entering the non-temporal copy path earlier. ++ Use 3/8 of the shared cache size per thread to reduce cache ++ pollution and improve throughput for large copies. Keep the memset ++ non-temporal threshold unchanged. */ ++ if (cpu_features->basic.kind == arch_kind_hygon) ++ non_temporal_threshold = shared_per_thread * 3 / 8; ++ + tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); + if (tunable_size > minimum_non_temporal_threshold + && tunable_size <= maximum_non_temporal_threshold) +-- +2.17.1 + diff --git a/glibc.spec b/glibc.spec index 1817107c575d5c883da534d0eb4c690e8aaa5353..24c6c86a8a4c9f3d67ad5b8db581a8e37c108751 100644 --- a/glibc.spec +++ b/glibc.spec @@ -1,4 +1,4 @@ -%define anolis_release 25 +%define anolis_release 26 %bcond_without testsuite %bcond_without benchtests @@ -244,6 +244,9 @@ Patch003099: 003099-bugfix-for-CVE-2026-6238.patch # https://inbox.sourceware.org/libc-alpha/1bc94ca3ff4a1aafd1b6c4877d894e9bb1960808.1777546194.git.fweimer@redhat.com/ Patch003100: 003100-bugfix-for-CVE-2026-5435.patch +Patch3101: 0001-x86-Enable-Prefer_No_AVX512-for-Hygon-model-0x8.patch +Patch3102: 0002-x86-Lower-non-temporal-copy-threshold-for-Hygon.patch + BuildRequires: audit-libs-devel >= 1.1.3 libcap-devel systemtap-sdt-devel BuildRequires: procps-ng util-linux gawk sed >= 3.95 gettext BuildRequires: python3 python3-devel @@ -1237,6 +1240,9 @@ update_gconv_modules_cache () %{_libdir}/libpthread_nonshared.a %changelog +* Fri Jun 5 2026 Jiamei Xie - 2.38-25 +- x86: Enable Hygon model 0x8 support and adjust NT threshold + * Thu Jun 11 2026 tomcruiseqi - 2.38-25 - Fix CVE-2026-5435