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### uVision Project, (C) Keil Software
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+ + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + diff --git a/bsp/at32/at32f457-start/project.uvprojx b/bsp/at32/at32f457-start/project.uvprojx index 37629633788ce36baea9bab3f9fa7dfc3e9d6b0e..c5ce20cf215b92a7d1091051acc77cd4eab45b88 100644 --- a/bsp/at32/at32f457-start/project.uvprojx +++ b/bsp/at32/at32f457-start/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread @@ -15,28 +18,28 @@ ArteryTek ArteryTek.AT32F45x_DFP.2.0.0 IRAM(0x20000000,0x24000) IROM(0x08000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F457_512 -FS08000000 -FL080000 -FP0($$Device:AT32F457ZET7$Flash\AT32F457_512.FLM)) 0 $$Device:AT32F457ZET7$Device\Include\at32f45x.h - - - - - - - - - + + + + + + + + + $$Device:AT32F457ZET7$SVD\AT32F457xx_v2.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +61,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +71,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +82,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -100,8 +103,8 @@ 0 0 3 - - + + 1 @@ -134,11 +137,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -171,7 +174,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -182,6 +185,7 @@ 2 0 0 + 0 0 0 8 @@ -305,7 +309,7 @@ 0x0 - + 1 @@ -332,9 +336,9 @@ 0 0 - + AT32F457ZET7, RT_USING_ARMLIBC, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND - + applications;..\..\..\components\drivers\include;.;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\drivers\include;board;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\common;..\..\..\components\net\utest;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\phy;..\..\..\components\drivers\smp_call;..\libraries\rt_drivers\config;..\..\..\components\libc\posix\io\epoll;..\libraries\rt_drivers;..\libraries\usbotg_library\inc;board\inc;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\eventfd;..\..\..\include;..\..\..\components\libc\posix\io\poll @@ -350,10 +354,10 @@ 0 4 - - - - + + + + @@ -365,13 +369,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -394,29 +398,21 @@ 1 ..\..\..\libcpu\arm\common\atomic_arm.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -432,8 +428,47 @@ 1 ..\..\..\components\drivers\core\device.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -444,15 +479,52 @@ - - completion_comm.c 1 ..\..\..\components\drivers\ipc\completion_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -463,15 +535,52 @@ - - completion_up.c 1 ..\..\..\components\drivers\ipc\completion_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -482,15 +591,52 @@ - - condvar.c 1 ..\..\..\components\drivers\ipc\condvar.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -501,15 +647,52 @@ - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -520,15 +703,52 @@ - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -539,15 +759,52 @@ - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -558,15 +815,52 @@ - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -577,15 +871,52 @@ - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -596,15 +927,52 @@ - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -615,15 +983,52 @@ - - dev_pin.c 1 ..\..\..\components\drivers\pin\dev_pin.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -634,15 +1039,52 @@ - - dev_serial_v2.c 1 ..\..\..\components\drivers\serial\dev_serial_v2.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ @@ -663,29 +1105,21 @@ 1 board\src\at32_msp.c - - board.c 1 board\src\board.c - - drv_common.c 1 ..\libraries\rt_drivers\drv_common.c - - drv_gpio.c 1 ..\libraries\rt_drivers\drv_gpio.c - - drv_usart_v2.c 1 @@ -701,22 +1135,16 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 @@ -732,8 +1160,47 @@ 1 ..\..\..\src\clock.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -744,15 +1211,52 @@ - - components.c 1 ..\..\..\src\components.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -763,15 +1267,52 @@ - - cpu_up.c 1 ..\..\..\src\cpu_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -782,15 +1323,52 @@ - - defunct.c 1 ..\..\..\src\defunct.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -801,15 +1379,52 @@ - - idle.c 1 ..\..\..\src\idle.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -820,15 +1435,52 @@ - - ipc.c 1 ..\..\..\src\ipc.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -839,15 +1491,52 @@ - - irq.c 1 ..\..\..\src\irq.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -858,15 +1547,52 @@ - - kservice.c 1 ..\..\..\src\kservice.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -877,15 +1603,52 @@ - - mem.c 1 ..\..\..\src\mem.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -896,15 +1659,52 @@ - - memheap.c 1 ..\..\..\src\memheap.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -915,15 +1715,52 @@ - - mempool.c 1 ..\..\..\src\mempool.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -934,15 +1771,52 @@ - - object.c 1 ..\..\..\src\object.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -953,15 +1827,52 @@ - - scheduler_comm.c 1 ..\..\..\src\scheduler_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -972,15 +1883,52 @@ - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -991,15 +1939,52 @@ - - thread.c 1 ..\..\..\src\thread.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -1010,15 +1995,52 @@ - - timer.c 1 ..\..\..\src\timer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ @@ -1039,85 +2061,61 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cunistd.c 1 ..\..\..\components\libc\compilers\common\cunistd.c - - cwchar.c 1 ..\..\..\components\libc\compilers\common\cwchar.c - - kerrno.c 1 ..\..\..\src\klibc\kerrno.c - - kstdio.c 1 ..\..\..\src\klibc\kstdio.c - - kstring.c 1 ..\..\..\src\klibc\kstring.c - - rt_vsnprintf_tiny.c 1 ..\..\..\src\klibc\rt_vsnprintf_tiny.c - - rt_vsscanf.c 1 @@ -1128,11 +2126,13 @@ + - - - + + + + @@ -1142,4 +2142,5 @@ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript index 6f2f6c5427a5b9423b32463ba5714b5d68ffd576..b52180f9ab1c40bc57e544d6cd551f6b8ac82c3f 100644 --- a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript @@ -7,18 +7,41 @@ cwd = GetCurrentDir() src = [] path = [cwd, cwd + '/config'] -if GetDepend('BSP_USING_GPIO'): +if GetDepend(['BSP_USING_GPIO', 'RT_USING_PIN']): src += ['drv_gpio.c'] -if GetDepend('BSP_USING_UART'): +if GetDepend(['BSP_USING_UART', 'RT_USING_SERIAL']): src += ['drv_uart.c'] -if GetDepend('BSP_USING_CAN'): +if GetDepend(['BSP_USING_CAN', 'RT_USING_CAN']): src += ['drv_can.c'] -if GetDepend('BSP_USING_ECAP'): +if GetDepend(['BSP_USING_ECAP']): src += ['drv_ecap.c'] +if GetDepend(['BSP_USING_IWDG1']): + src += ['drv_iwdg1.c'] + +if GetDepend(['BSP_USING_IWDG2']): + src += ['drv_iwdg2.c'] + +if GetDepend(['BSP_USING_WWDG']): + src += ['drv_wwdg.c'] + +if GetDepend(['BSP_USING_HARD_I2C']): + src += ['drv_hard_i2c.c'] + + +if GetDepend(['BSP_USING_SOFT_I2C']): + src += ['drv_soft_i2c.c'] + +if GetDepend(['BSP_USING_DAC']): + src += ['drv_dac.c'] + +if GetDepend(['BSP_USING_GPIO_INT_XINT']): + src += ['drv_gpio_int_xint.c'] + + group = DefineGroup('HAL_Drivers', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dac.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..f252752161a8277c432e61f4daa89c784ef2e7fd --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dac.c @@ -0,0 +1,157 @@ + +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WCH the first version + * 2022-09-17 hg0720 add some operation function + */ + +#include +#include +#include +#include "drv_dac.h" +#include "src_dac.h" +#if defined BSP_USING_DAC + +//#define DRV_DEBUG +#define LOG_TAG "drv.dac" +#include + +#if defined(BSP_USING_DAC1) +struct rt_dac_device ns800_dac_device1; +#endif + +#if defined(BSP_USING_DAC3) +struct rt_dac_device ns800_dac_device3; +#endif + + + + +struct ns800_dac +{ + struct rt_dac_device *ns800_dac_device; + DAC_TypeDef *Instance; + char *dacName; +}; + +static struct ns800_dac ns800_dac_obj[] = +{ +#if defined(BSP_USING_DAC1) + { + &ns800_dac_device1, + DAC1, + "dac1", + }, +#endif +#if defined(BSP_USING_DAC3) + { + &ns800_dac_device3, + DAC3, + "dac3", + }, +#endif +}; + +static rt_err_t ns800_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) +{ + struct ns800_dac *N800dac; + RT_ASSERT(device != RT_NULL); + N800dac = (struct ns800_dac*)device->parent.user_data; + DAC_enableModule(N800dac->Instance ); + return RT_EOK; +} + +static rt_err_t ns800_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) +{ + struct ns800_dac *N800dac; + RT_ASSERT(device != RT_NULL); + N800dac = (struct ns800_dac*)device->parent.user_data; + + DAC_disableModule(N800dac->Instance); + return RT_EOK; +} + +static rt_uint8_t ns800_dac_get_resolution(struct rt_dac_device *device) +{ + struct ns800_dac *N800dac; + + RT_ASSERT(device != RT_NULL); + + N800dac = (struct ns800_dac*)device->parent.user_data; + + (void) N800dac; + + /* Only has supported DAC_ALIGN_12B_R, so it will return 12 bits */ + return 12; +} + +static rt_uint32_t ns800_dac_get_channel(rt_uint32_t channel) +{ + rt_uint32_t ns800_channel = 1; + return ns800_channel; +} + +static rt_err_t ns800_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + rt_uint32_t dac_channel; + struct ns800_dac *N800dac; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + N800dac = (struct ns800_dac*)device->parent.user_data; + DAC_setShadowValue(N800dac->Instance, *value); + rt_kprintf("AAAValue=%d\n",*value); + + return RT_EOK; +} + +static const struct rt_dac_ops ns800_dac_ops = +{ + .disabled = ns800_dac_disabled, + .enabled = ns800_dac_enabled, + .convert = ns800_set_dac_value, + .get_resolution = ns800_dac_get_resolution, +}; + +static int ns800_dac_init(void) +{ + int result = RT_EOK; + /* save dac name */ + int i = 0; + + for (i = 0; i < sizeof(ns800_dac_obj) / sizeof(ns800_dac_obj[0]); i++) + { + DAC_disableModule(ns800_dac_obj[i].Instance); + /* DACVALA load on next SYSCLK. Determines when the DACVALA register is updated with the value from DACVALS */ + DAC_setLoadMode(ns800_dac_obj[i].Instance , DAC_LOAD_SYSCLK); + /* DAC delayTime */ + DAC_setDetaDelayTime(ns800_dac_obj[i].Instance, 0xFF); + /* DAC SettlingTime */ + DAC_setSettlingTime(ns800_dac_obj[i].Instance, 0xFF); + /* DAC SettlingTime */ + DAC_setDacVrefMode(ns800_dac_obj[i].Instance, DAC_REFSEL_VDAC);//选 ADC VREFHI/VSSA ，DAC1 çš„å‚考电压是 VREFHIA， DAC3 çš„å‚考电压是 VREFHIB。DAC_REFSEL_VDAC 是VDAC + /* set DAC value is zero */ + DAC_setShadowValue(ns800_dac_obj[i].Instance , 0x0); + /* Enable DAC and close output function */ + /* register dac device */ + if (rt_hw_dac_register(ns800_dac_obj[i].ns800_dac_device, ns800_dac_obj[i].dacName, &ns800_dac_ops, &ns800_dac_obj[i]) == RT_EOK) + { + LOG_D("%s init success", ns800_dac_obj[i].dacName); + } + else + { + LOG_E("%s register failed", ns800_dac_obj[i].dacName); + result = -RT_ERROR; + } + } + return result; +} +INIT_DEVICE_EXPORT(ns800_dac_init); + +#endif /* BSP_USING_DAC */ diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dac.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..7bda5f4daf23612b033ec823217e3bcd8e5a1a36 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dac.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-17 Jeffery Yuan the first version + */ + +#ifndef DRV_DAC_H__ +#define DRV_DAC_H__ + +#include +#include + + + + + +#endif diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c index b3e67ae04df03b21f26e29fb8def37d2c2b3d073..b3ba11f153ed92a74a3e43ef18e34d9925726449 100644 --- a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * + *2026-05-17 Jeffery Yuan add interrupt operation function */ #include @@ -18,6 +18,40 @@ #define PIN_ENTRY(pin_macro) {pin_macro} + + +#if defined(GPIOZ) +#define __NS800_PORT_MAX 12u +#elif defined(GPIOK) +#define __NS800_PORT_MAX 11u +#elif defined(GPIOJ) +#define __NS800_PORT_MAX 10u +#elif defined(GPIOI) +#define __NS800_PORT_MAX 9u +#elif defined(GPIOH) +#define __NS800_PORT_MAX 8u +#elif defined(GPIOG) +#define __NS800_PORT_MAX 7u +#elif defined(GPIOF) +#define __NS800_PORT_MAX 6u +#elif defined(GPIOE) +#define __NS800_PORT_MAX 5u +#elif defined(GPIOD) +#define __NS800_PORT_MAX 4u +#elif defined(GPIOC) +#define __NS800_PORT_MAX 3u +#elif defined(GPIOB) +#define __NS800_PORT_MAX 2u +#elif defined(GPIOA) +#define __NS800_PORT_MAX 1u +#else +#define __NS800_PORT_MAX 0u +#error Unsupported NS800 GPIO peripheral. +#endif + +#define PIN_STPORT_MAX __NS800_PORT_MAX + + static const rt_pin_info_t pin_map_table[225] = { /* 0-21: è¿žç»­ */ [0] = PIN_ENTRY(GPIO_0), @@ -161,6 +195,84 @@ static const rt_pin_info_t pin_map_table[225] = { [224] = PIN_ENTRY(GPIO_224), }; + + +static struct rt_pin_irq_hdr pin_irq_hdr_table[32] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + + +static const struct pin_irq_map pin_irq_map[32] = +{ + {GPIO_PIN_0, EXTI3_0_IRQn}, + {GPIO_PIN_1, EXTI3_0_IRQn}, + {GPIO_PIN_2, EXTI3_0_IRQn}, + {GPIO_PIN_3, EXTI3_0_IRQn}, + {GPIO_PIN_4, EXTI7_4_IRQn}, + {GPIO_PIN_5, EXTI7_4_IRQn}, + {GPIO_PIN_6, EXTI7_4_IRQn}, + {GPIO_PIN_7, EXTI7_4_IRQn}, + {GPIO_PIN_8, EXTI11_8_IRQn}, + {GPIO_PIN_9, EXTI11_8_IRQn}, + {GPIO_PIN_10, EXTI11_8_IRQn}, + {GPIO_PIN_11, EXTI11_8_IRQn}, + {GPIO_PIN_12, EXTI15_12_IRQn}, + {GPIO_PIN_13, EXTI15_12_IRQn}, + {GPIO_PIN_14, EXTI15_12_IRQn}, + {GPIO_PIN_15, EXTI15_12_IRQn}, + {GPIO_PIN_16, EXTI3_0_IRQn}, + {GPIO_PIN_17, EXTI3_0_IRQn}, + {GPIO_PIN_18, EXTI3_0_IRQn}, + {GPIO_PIN_19, EXTI3_0_IRQn}, + {GPIO_PIN_20, EXTI7_4_IRQn}, + {GPIO_PIN_21, EXTI7_4_IRQn}, + {GPIO_PIN_22, EXTI7_4_IRQn}, + {GPIO_PIN_23, EXTI7_4_IRQn}, + {GPIO_PIN_24, EXTI11_8_IRQn}, + {GPIO_PIN_25, EXTI11_8_IRQn}, + {GPIO_PIN_26, EXTI11_8_IRQn}, + {GPIO_PIN_27, EXTI11_8_IRQn}, + {GPIO_PIN_28, EXTI15_12_IRQn}, + {GPIO_PIN_29, EXTI15_12_IRQn}, + {GPIO_PIN_30, EXTI15_12_IRQn}, + {GPIO_PIN_31, EXTI15_12_IRQn}, +}; + + + + /* 1. PIN_NUM: 从(port, pin)获å–å¼•è„šç¼–å· */ int get_pin_num(GPIO_TypeDef *port, GPIO_PinNum pin) { @@ -271,9 +383,6 @@ const rt_pin_info_t* get_pin_info(int pin_num) return &pin_map_table[pin_num]; } -#define PIN_STPORT(pin) (pin_map_table[(pin)].port) -#define PIN_STPIN(pin) (pin_map_table[(pin)].pin) - static uint32_t pin_irq_enable_mask = 0; @@ -287,6 +396,7 @@ static rt_base_t ns800_pin_get(const char *name) uint8_t port_index; GPIO_TypeDef *port = RT_NULL; char *endptr; + if ((name == RT_NULL) || (name[0] == '\0')) { @@ -417,24 +527,614 @@ static void ns800rt7_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) } +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) +{ + rt_int32_t mapindex = get_pin_index(pinbit); + if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +} + + + + static rt_err_t ns800_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args) { + rt_base_t level; + rt_int32_t irqindex = -1; + const rt_pin_info_t *info = get_pin_info(pin); + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + switch (mode) + { + case PIN_IRQ_MODE_RISING: + case PIN_IRQ_MODE_FALLING: + case PIN_IRQ_MODE_RISING_FALLING: + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + /* hardware not supported */ + case PIN_IRQ_MODE_LOW_LEVEL: + /* hardware not supported */ + default: + return -RT_EINVAL; + } + irqindex = get_pin_index(info->pin); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_hdr_table)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_table[irqindex].pin == info->pin && + pin_irq_hdr_table[irqindex].hdr == hdr && + pin_irq_hdr_table[irqindex].mode == mode && + pin_irq_hdr_table[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_table[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_table[irqindex].pin = info->pin; + pin_irq_hdr_table[irqindex].hdr = hdr; + pin_irq_hdr_table[irqindex].mode = mode; + pin_irq_hdr_table[irqindex].args = args; + rt_hw_interrupt_enable(level); return RT_EOK; } static rt_err_t ns800_pin_dettach_irq(struct rt_device *device, rt_base_t pin) { + rt_base_t level; + rt_int32_t irqindex = -1; + const rt_pin_info_t *info = get_pin_info(pin); + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = get_pin_index(info->pin); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_table[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_table[irqindex].pin = -1; + pin_irq_hdr_table[irqindex].hdr = RT_NULL; + pin_irq_hdr_table[irqindex].mode = 0; + pin_irq_hdr_table[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); return RT_EOK; } + +static SYSCON_ExtiSel EXTI_enableGpioLine (GPIO_TypeDef *port, GPIO_PinNum pin) +{ + SYSCON_ExtiSel retLine; + retLine = (SYSCON_ExtiSel)((uint16_t)pin % 16); + /* Unlock SYSCON register writing function */ + SYSCON_UNLOCK; + + + + + if (port == GPIOA) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_0); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_8); + } + } + else if (port == GPIOB) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_1); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_9); + } + } + else if (port == GPIOC) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_2); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_10); + } + } + else if (port == GPIOD) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_3); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_11); + } + } + else if (port == GPIOE) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_4); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_12); + } + } + else if (port == GPIOF) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_5); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_13); + } + } + else if (port == GPIOG) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_6); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_14); + } + } + else if (port == GPIOH) + { + if (pin < GPIO_PIN_16) + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_7); + } + else + { + SYSCON_setExtiSel(SYSCON, retLine, SYSCON_EXTI_PINSEL_15); + } + } + + /* Lock SYSCON register writing function */ + SYSCON_LOCK; + + return retLine; +} + +static IRQn_Type EXTI_getLineIrqn (SYSCON_ExtiSel line) +{ + IRQn_Type irq = EXTI3_0_IRQn; + + switch (line) + { + case SYSCON_EXTISEL_0: + case SYSCON_EXTISEL_1: + case SYSCON_EXTISEL_2: + case SYSCON_EXTISEL_3: + { + irq = EXTI3_0_IRQn; + } + break; + + case SYSCON_EXTISEL_4: + case SYSCON_EXTISEL_5: + case SYSCON_EXTISEL_6: + case SYSCON_EXTISEL_7: + { + irq = EXTI7_4_IRQn; + } + break; + + case SYSCON_EXTISEL_8: + case SYSCON_EXTISEL_9: + case SYSCON_EXTISEL_10: + case SYSCON_EXTISEL_11: + { + irq = EXTI11_8_IRQn; + } + break; + + case SYSCON_EXTISEL_12: + case SYSCON_EXTISEL_13: + case SYSCON_EXTISEL_14: + case SYSCON_EXTISEL_15: + { + irq = EXTI15_12_IRQn; + } + break; + + default: + break; + } + + return irq; +} + +void EXTI_handler(void); + + static rt_err_t ns800_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) -{ +{ + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + rt_uint8_t gpio_port_souce=0; + const rt_pin_info_t *info = get_pin_info(pin); + uint32_t key_line_idx = 0; + IRQn_Type key_irq_idx; + RT_ASSERT(info->port >= 3 && "gpio just support A,B,C"); + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = get_pin_index(info->pin); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_table[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + key_line_idx = EXTI_enableGpioLine(info->port,info->pin); + key_irq_idx = EXTI_getLineIrqn((SYSCON_ExtiSel)key_line_idx); + EXTI_setIntrMaskReg(EXTI, (1 << key_line_idx)); + /* Interrupt handler function registration. */ + Interrupt_register(key_irq_idx, &EXTI_handler); + /* Enable the interrupt signals. Enable global interrupts.*/ + Interrupt_enable(key_irq_idx); + + switch (pin_irq_hdr_table[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_setPadConfig(info->port,info->pin, GPIO_PIN_TYPE_PULLDOWN); + EXTI_setRiseEdgeTrigSelReg(EXTI, (1 << key_line_idx)); + break; + case PIN_IRQ_MODE_FALLING: + GPIO_setPadConfig(info->port,info->pin, GPIO_PIN_TYPE_PULLUP); + EXTI_setFallEdgeTrigSelReg(EXTI, (1 << key_line_idx)); + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_setPadConfig(info->port,info->pin, GPIO_PIN_TYPE_STD); + EXTI_setRiseEdgeTrigSelReg(EXTI, (1 << key_line_idx)); + EXTI_setFallEdgeTrigSelReg(EXTI, (1 << key_line_idx)); + break; + } + /* Enable the interrupt signals. Enable global interrupts.*/ + Interrupt_enable(irqmap->irqno); + rt_kprintf("IRQn=%d\n",irqmap->irqno); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(info->pin); + if (irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + pin_irq_enable_mask &= ~irqmap->pinbit; + + if ((irqmap->pinbit>=GPIO_PIN_0)&&(irqmap->pinbit<=GPIO_PIN_3)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3))) + { + Interrupt_disable(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_4)&&(irqmap->pinbit<=GPIO_PIN_7)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7))) + { + Interrupt_disable(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_8)&&(irqmap->pinbit<=GPIO_PIN_11)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_12)&&(irqmap->pinbit<=GPIO_PIN_15)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_16)&&(irqmap->pinbit<=GPIO_PIN_19)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_16|GPIO_PIN_17|GPIO_PIN_18|GPIO_PIN_19))) + { + Interrupt_disable(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_20)&&(irqmap->pinbit<=GPIO_PIN_23)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_20|GPIO_PIN_21|GPIO_PIN_22|GPIO_PIN_23))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_24)&&(irqmap->pinbit<=GPIO_PIN_27)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_24|GPIO_PIN_25|GPIO_PIN_26|GPIO_PIN_27))) + { + Interrupt_disable(irqmap->irqno); + } + } + else if ((irqmap->pinbit>=GPIO_PIN_28)&&(irqmap->pinbit<=GPIO_PIN_31)) + { + if(!(pin_irq_enable_mask&(GPIO_PIN_28|GPIO_PIN_29|GPIO_PIN_30|GPIO_PIN_31))) + { + Interrupt_disable(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQ(irqmap->irqno); + } + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + return RT_EOK; } + + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_table[irqno].hdr) + { + pin_irq_hdr_table[irqno].hdr(pin_irq_hdr_table[irqno].args); + } +} + +void HAL_GPIO_EXTI_Callback(rt_uint16_t GPIO_Pin) +{ + pin_irq_hdr(get_pin_index(GPIO_Pin)); +} + + +void EXTI_handler(void) +{ + rt_interrupt_enter(); + + uint32_t tempPr = EXTI_getPendReg(EXTI); + + if(tempPr & (1 << SYSCON_EXTISEL_0)) + { + if(pin_irq_hdr_table[GPIO_PIN_0].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_0); + } + else if(pin_irq_hdr_table[GPIO_PIN_16].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_16); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_1)) + { + if(pin_irq_hdr_table[GPIO_PIN_1].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_1); + } + else if(pin_irq_hdr_table[GPIO_PIN_17].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_17); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_2)) + { + if(pin_irq_hdr_table[GPIO_PIN_2].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_2); + } + else if(pin_irq_hdr_table[GPIO_PIN_18].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_18); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_3)) + { + if(pin_irq_hdr_table[GPIO_PIN_3].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_3); + } + else if(pin_irq_hdr_table[GPIO_PIN_19].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_19); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_4)) + { + if(pin_irq_hdr_table[GPIO_PIN_4].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_4); + } + else if(pin_irq_hdr_table[GPIO_PIN_20].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_20); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_5)) + { + if(pin_irq_hdr_table[GPIO_PIN_5].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_5); + } + else if(pin_irq_hdr_table[GPIO_PIN_21].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_21); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_6)) + { + if(pin_irq_hdr_table[GPIO_PIN_6].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_6); + } + else if(pin_irq_hdr_table[GPIO_PIN_22].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_22); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_7)) + { + if(pin_irq_hdr_table[GPIO_PIN_7].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_7); + } + else if(pin_irq_hdr_table[GPIO_PIN_23].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_23); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_8)) + { + if(pin_irq_hdr_table[GPIO_PIN_8].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_8); + } + else if(pin_irq_hdr_table[GPIO_PIN_24].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_24); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_9)) + { + if(pin_irq_hdr_table[GPIO_PIN_9].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_9); + } + else if(pin_irq_hdr_table[GPIO_PIN_25].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_25); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_10)) + { + if(pin_irq_hdr_table[GPIO_PIN_10].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_10); + } + else if(pin_irq_hdr_table[GPIO_PIN_26].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_26); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_11)) + { + if(pin_irq_hdr_table[GPIO_PIN_11].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_11); + } + else if(pin_irq_hdr_table[GPIO_PIN_27].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_27); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_12)) + { + if(pin_irq_hdr_table[GPIO_PIN_12].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_12); + } + else if(pin_irq_hdr_table[GPIO_PIN_28].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_28); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_13)) + { + if(pin_irq_hdr_table[GPIO_PIN_13].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_13); + } + else if(pin_irq_hdr_table[GPIO_PIN_29].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_29); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_14)) + { + if(pin_irq_hdr_table[GPIO_PIN_14].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_14); + } + else if(pin_irq_hdr_table[GPIO_PIN_30].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_30); + } + } + if(tempPr & (1 << SYSCON_EXTISEL_15)) + { + if(pin_irq_hdr_table[GPIO_PIN_15].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_15); + } + else if(pin_irq_hdr_table[GPIO_PIN_31].hdr) + { + HAL_GPIO_EXTI_Callback(GPIO_PIN_31); + } + } + + EXTI_clearPendReg(EXTI, tempPr); + + rt_interrupt_leave(); + +} + + static const struct rt_pin_ops _ns800rt7_pin_ops = { ns800rt7_pin_mode, @@ -447,10 +1147,6 @@ static const struct rt_pin_ops _ns800rt7_pin_ops = RT_NULL, }; -rt_inline void pin_irq_hdr(int irqno) -{ - -} int rt_hw_pin_init(void) { diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h index 24a5980dbfa8cfd3b8cf70cc84ada4da1d2d02fb..4dfbd53a1836974861692dbc9e9297ba52e0ba54 100644 --- a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h @@ -25,6 +25,11 @@ typedef struct { GPIO_PinNum pin; } rt_pin_info_t; +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; #define PIN_NUM(...) get_pin_num(__VA_ARGS__) #define PIN_PORT(pin) get_port_index_by_num(pin) diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio_int_xint.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio_int_xint.c new file mode 100644 index 0000000000000000000000000000000000000000..133d6a69935235c9b768c622d2360fa351fd28fe --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio_int_xint.c @@ -0,0 +1,285 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Novosense Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2026-5-19 Jeffery Yuan First version +* +******************************************************************************/ +#include +#include "drv_gpio_int_xint.h" + +#if defined(BSP_USING_GPIO_INT_XINT) + +#define DBG_TAG "drv.gpio_int_xint" +#define DBG_LVL DBG_INFO +#include + + +#if defined(BSP_USING_GPIO_INT_XINT1) +struct rt_gpio_int_xint_device int_xint_device1; +#endif + +#if defined(BSP_USING_GPIO_INT_XINT2) +struct rt_gpio_int_xint_device int_xint_device2; +#endif + +#if defined(BSP_USING_GPIO_INT_XINT3) +struct rt_gpio_int_xint_device int_xint_device3; +#endif + +#if defined(BSP_USING_GPIO_INT_XINT4) +struct rt_gpio_int_xint_device int_xint_device4; +#endif + +#if defined(BSP_USING_GPIO_INT_XINT5) +struct rt_gpio_int_xint_device int_xint_device5; +#endif + + +static const struct rt_gpio_int_xint_config gpio_xint_config[] = +{ + { + "xint1", + }, + { + "xint2", + }, + { + "xint3", + }, + { + "xint4", + }, + { + "xint5", + }, +}; + +struct rt_gpio_int_xint_irq_hdr gpio_int_xint_irq_hdr[5] = +{ + {-1, RT_NULL,RT_NULL}, + {-1, RT_NULL,RT_NULL}, + {-1, RT_NULL,RT_NULL}, + {-1, RT_NULL,RT_NULL}, + {-1, RT_NULL,RT_NULL}, +}; + + + +static struct gpio_int_xint_irq_map gpio_int_xint_irq_map[5] = +{ + {GPIO_INT_XINT1, EXTI_XINT2_1_IRQn}, + {GPIO_INT_XINT2, EXTI_XINT2_1_IRQn}, + {GPIO_INT_XINT3, EXTI_XINT5_3_IRQn}, + {GPIO_INT_XINT4, EXTI_XINT5_3_IRQn}, + {GPIO_INT_XINT5, EXTI_XINT5_3_IRQn}, +}; + + + +void XIN_Handler(void) +{ + rt_interrupt_enter(); + + // ¶ÁÈ¡ËùÓÐ XINT µÄÖжϱêÖ¾£¨¼ÙÉèÓ²¼þÖ§³ÖÒ»´ÎÐÔ¶ÁÈ¡£© + + for (int i = GPIO_INT_XINT1; i <= GPIO_INT_XINT5; i++) + { + volatile uint32_t tempPr = GPIO_getInterruptFlag((GPIO_ExternalIntNum)i); + if (tempPr & (1 << i)) + { + if (gpio_int_xint_irq_hdr[i].callback != RT_NULL) + { + gpio_int_xint_irq_hdr[i].callback(gpio_int_xint_irq_hdr[i].user_data); + } + GPIO_clearInterruptFlag((GPIO_ExternalIntNum)i); + } + } + + __DSB(); + rt_interrupt_leave(); +} + + +static rt_err_t rt_gpio_int_xint_control(rt_device_t dev, int cmd, void *args) +{ + struct rt_gpio_int_xint_device *gpio_int_xint; + + RT_ASSERT(dev != RT_NULL); + + gpio_int_xint = (struct rt_gpio_int_xint_device *)dev; + + switch (cmd) + { + + case GPIO_INT_XINT_CMD_SET_CALLBACK: + { + struct gpio_int_xint_callback *cb; + + if (args == RT_NULL) + { + return -RT_EINVAL; + } + + + cb = (struct gpio_int_xint_callback *)args; + + rt_mutex_take(&gpio_int_xint->lock, RT_WAITING_FOREVER); + gpio_int_xint->callback = cb->callback; + gpio_int_xint->user_data = cb->user_data; + rt_mutex_release(&gpio_int_xint->lock); + } + break; + case GPIO_INT_XINT_CMD_SET_IINT_INFO: + { + if (args == RT_NULL) + { + return -RT_EINVAL; + } + if(gpio_int_xint->opened) + { + return -RT_EINVAL; + } + rt_mutex_take(&gpio_int_xint->lock, RT_WAITING_FOREVER); + gpio_int_xint->config_data = (struct rt_gpio_int_xint_config_data*)args; + + gpio_int_xint_irq_map[gpio_int_xint->config_data->externalIntNum].xint_num = gpio_int_xint->config_data->externalIntNum; + + gpio_int_xint_irq_hdr[gpio_int_xint->config_data->externalIntNum].callback = gpio_int_xint->callback; + gpio_int_xint_irq_hdr[gpio_int_xint->config_data->externalIntNum].user_data = gpio_int_xint->user_data; + gpio_int_xint_irq_hdr[gpio_int_xint->config_data->externalIntNum].xint_num = gpio_int_xint->config_data->externalIntNum; + + + GPIO_setInterruptType(gpio_int_xint->config_data->externalIntNum,gpio_int_xint->config_data->intType); + + GPIO_setInterruptPin(gpio_int_xint->config_data->gpio_port,gpio_int_xint->config_data->gpio_pin, gpio_int_xint->config_data->externalIntNum); + + GPIO_enableInterrupt( gpio_int_xint->config_data->externalIntNum); + /* Interrupt handler function registration. */ + Interrupt_register(gpio_int_xint_irq_map[gpio_int_xint->config_data->externalIntNum].irqno,&XIN_Handler); + + /* Enable the XIN2_1 interrupt signals. Enable global interrupts.*/ + Interrupt_enable(gpio_int_xint_irq_map[gpio_int_xint->config_data->externalIntNum].irqno); + + gpio_int_xint->opened = RT_TRUE; + rt_mutex_release(&gpio_int_xint->lock); + } + break; + + + default: + break; + } + return RT_EOK; +} + +static rt_err_t rt_hw_gpio_int_xint_register(struct rt_gpio_int_xint_device *gpio_int_xint, const struct rt_gpio_int_xint_config *config) +{ + struct rt_device *dev; + + RT_ASSERT(gpio_int_xint != RT_NULL); + RT_ASSERT(config != RT_NULL); + + gpio_int_xint->config = config; + + + dev = &gpio_int_xint->parent; + + dev->type = RT_Device_Class_Miscellaneous; + dev->rx_indicate = RT_NULL; + dev->tx_complete = RT_NULL; + + + dev->init = RT_NULL; + dev->open = RT_NULL; + dev->close = RT_NULL; + dev->read = RT_NULL; + dev->write = RT_NULL; + dev->control = rt_gpio_int_xint_control; + + return rt_device_register(dev, config->name, RT_DEVICE_FLAG_WRONLY | RT_DEVICE_OFLAG_OPEN); +} + + +int rt_hw_gpio_int_xint_init (void) +{ + rt_err_t ret; +#if defined(BSP_USING_GPIO_INT_XINT1) + int_xint_device1.opened = RT_FALSE; + rt_mutex_init(&int_xint_device1.lock,gpio_xint_config[0].name, RT_IPC_FLAG_PRIO); + rt_sem_init(&int_xint_device1.rx_sem, gpio_xint_config[0].name, 0, RT_IPC_FLAG_FIFO); + ret = rt_hw_gpio_int_xint_register(&int_xint_device1, &gpio_xint_config[0]); + + if (ret != RT_EOK) + { + LOG_E("register %s failed, ret = %d", gpio_xint_config[0].name ,ret); + return ret; + } +#endif + +#if defined(BSP_USING_GPIO_INT_XINT2) + int_xint_device2.opened = RT_FALSE; + rt_mutex_init(&int_xint_device2.lock,gpio_xint_config[1].name, RT_IPC_FLAG_PRIO); + rt_sem_init(&int_xint_device2.rx_sem, gpio_xint_config[1].name, 0, RT_IPC_FLAG_FIFO); + ret = rt_hw_gpio_int_xint_register(&int_xint_device2, &gpio_xint_config[1]); + + if (ret != RT_EOK) + { + LOG_E("register %s failed, ret = %d", gpio_xint_config[1].name ,ret); + return ret; + } +#endif + +#if defined(BSP_USING_GPIO_INT_XINT3) + int_xint_device3.opened = RT_FALSE; + rt_mutex_init(&int_xint_device3.lock,gpio_xint_config[2].name, RT_IPC_FLAG_PRIO); + rt_sem_init(&int_xint_device3.rx_sem, gpio_xint_config[2].name, 0, RT_IPC_FLAG_FIFO); + ret = rt_hw_gpio_int_xint_register(&int_xint_device3, &gpio_xint_config[2]); + + if (ret != RT_EOK) + { + LOG_E("register %s failed, ret = %d", gpio_xint_config[2].name ,ret); + return ret; + } +#endif + +#if defined(BSP_USING_GPIO_INT_XINT4) + int_xint_device4.opened = RT_FALSE; + rt_mutex_init(&int_xint_device4.lock,gpio_xint_config[3].name, RT_IPC_FLAG_PRIO); + rt_sem_init(&int_xint_device4.rx_sem, gpio_xint_config[3].name, 0, RT_IPC_FLAG_FIFO); + ret = rt_hw_gpio_int_xint_register(&int_xint_device4, &gpio_xint_config[3]); + + if (ret != RT_EOK) + { + LOG_E("register %s failed, ret = %d", gpio_xint_config[3].name ,ret); + return ret; + } +#endif + +#if defined(BSP_USING_GPIO_INT_XINT5) + int_xint_device5.opened = RT_FALSE; + rt_mutex_init(&int_xint_device5.lock,gpio_xint_config[4].name, RT_IPC_FLAG_PRIO); + rt_sem_init(&int_xint_device5.rx_sem, gpio_xint_config[4].name, 0, RT_IPC_FLAG_FIFO); + ret = rt_hw_gpio_int_xint_register(&int_xint_device5, &gpio_xint_config[4]); + + if (ret != RT_EOK) + { + LOG_E("register %s failed, ret = %d", gpio_xint_config[4].name ,ret); + return ret; + } +#endif + + + + + LOG_I("gpio_int_xint register done"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_gpio_int_xint_init); + +#endif /* #if defined(BSP_USING_GPIO_INT_XINT) */ diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio_int_xint.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio_int_xint.h new file mode 100644 index 0000000000000000000000000000000000000000..992c3c508b4cce6817be2278dd0106f8935d680b --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio_int_xint.h @@ -0,0 +1,95 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Novosense Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2026-5-19 Jeffery Yuan First version +* +******************************************************************************/ + +#ifndef __DRV_XINT_H__ +#define __DRV_XINT_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#define GPIO_INT_XINT_CMD_SET_IINT_INFO (0x01) +#define GPIO_INT_XINT_CMD_SET_CALLBACK (0x02) + + + +struct rt_gpio_int_xint_config_data +{ + GPIO_ExternalIntNum externalIntNum; + GPIO_TypeDef *gpio_port; + GPIO_PinNum gpio_pin; + GPIO_IntType intType; +}; + + +typedef void (*rt_gpio_int_xint_callback_t)(void *user_data); + +struct gpio_int_xint_callback +{ + rt_gpio_int_xint_callback_t callback; + void *user_data; +}; + + +/* + * Static GPIO_INT_XINT hardware configuration. + */ +struct rt_gpio_int_xint_config +{ + const char *name; +}; + +struct rt_gpio_int_xint_irq_hdr +{ + rt_base_t xint_num; + rt_gpio_int_xint_callback_t callback; + void *user_data; +}; + + + +struct gpio_int_xint_irq_map +{ + rt_base_t xint_num; + IRQn_Type irqno; +}; + + +/* + * GPIO_INT_XINT device object. + */ +struct rt_gpio_int_xint_device +{ + struct rt_device parent; + struct rt_mutex lock; + struct rt_semaphore rx_sem; + rt_bool_t opened; + const struct rt_gpio_int_xint_config *config; + struct rt_gpio_int_xint_config_data *config_data; + rt_gpio_int_xint_callback_t callback; + void *user_data; + +}; +int rt_hw_gpio_int_xint_init(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_hard_i2c.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_hard_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..481d5c17f058d30e14cbb8330b027c4491ef1bbd --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_hard_i2c.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-14 Jeffery Yuan the first version + */ +#include "drv_config.h" +#include "drv_hard_i2c.h" + + +#ifdef RT_USING_I2C + +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_HARD_I2C1) && !defined(BSP_USING_HARD_I2C2) +#error "Please define at least one BSP_USING_I2Cx" +/* This driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */ +#endif + +#define I2C_SPEED (100000UL) /* I2C bus speed: 100 kHz */ + +#define IS_I2C_LEGACY(periph) ((periph) == I2C1 || (periph) == I2C2) + + +#if defined(BSP_USING_HARD_I2C1) +struct rt_i2c_bus_device i2c1; /* I2C1 bus device instance */ +#endif /* BSP_USING_I2C1 */ + +#if defined(BSP_USING_HARD_I2C2) +struct rt_i2c_bus_device i2c2; /* I2C2 bus device instance */ +#endif /* BSP_USING_I2C2 */ + + + + +static const struct ns800_i2c_bus ns800_i2c_config[] = { +#ifdef BSP_USING_HARD_I2C1 + { + &i2c1, /* Pointer to I2C1 bus device */ + I2C1, /* I2C1 peripheral base address */ + "hwi2c1", /* Device name */ + GPIOB, /* SCL port: GPIOB */ + GPIO_PIN_11, /* SCL pin: 11 */ + ALT6_FUNCTION, /* SCL alternate function: ALT6 */ + GPIO_PIN_TYPE_OD, /* SCL pad type: pull-up */ + GPIO_DIR_MODE_IN, /* SCL direction: input */ + GPIOB, /* SDA port: GPIOB */ + GPIO_PIN_10, /* SDA pin: 10 */ + ALT6_FUNCTION, /* SDA alternate function: ALT6 */ + GPIO_PIN_TYPE_OD, /* SDA pad type: pull-up */ + GPIO_DIR_MODE_IN, /* SDA direction: input */ + }, +#endif + +#ifdef BSP_USING_HARD_I2C2 + { + &i2c2, /* Pointer to I2C2 bus device */ + I2C2, /* I2C2 peripheral base address */ + "hwi2c2", /* Device name */ + GPIOB, /* SCL port: GPIOB */ + GPIO_PIN_3, /* SCL pin: 3 */ + ALT6_FUNCTION, /* SCL alternate function: ALT6 */ + GPIO_PIN_TYPE_OD, /* SCL pad type: pull-up */ + GPIO_DIR_MODE_IN, /* SCL direction: input */ + GPIOB, /* SDA port: GPIOB */ + GPIO_PIN_2, /* SDA pin: 2 */ + ALT6_FUNCTION, /* SDA alternate function: ALT6 */ + GPIO_PIN_TYPE_OD, /* SDA pad type: pull-up */ + GPIO_DIR_MODE_IN, /* SDA direction: input */ + }, +#endif + }; + +/** + * @brief Initializes the I2C pins and peripheral. + * @param i2c: Pointer to the I2C bus configuration structure + * @retval None + */ +static void ns800_i2c_bus_init(const struct ns800_i2c_bus *i2c) +{ + /* I2C SCL pinmux control */ + GPIO_setPinConfig(i2c->scl_port, i2c->scl_pin, i2c->scl_mux); /* Configure SCL alternate function */ + GPIO_setAnalogMode(i2c->scl_port, i2c->scl_pin, GPIO_ANALOG_DISABLED); /* Disable analog mode for SCL */ + //GPIO_setPadConfig(i2c->scl_port,i2c->scl_pin, GPIO_PIN_TYPE_OD); /* Optional: Open-drain configuration (commented) */ + GPIO_setPadConfig(i2c->scl_port, i2c->scl_pin, i2c->scl_pad); /* Set SCL pad type (e.g., pull-up) */ + GPIO_setQualificationMode(i2c->scl_port, i2c->scl_pin, GPIO_QUAL_ASYNC); /* Set SCL asynchronous qualification */ + //GPIO_setDirectionMode(i2c->scl_port, i2c->scl_pin, i2c->scl_direction); /* Set SCL direction */ + + /* I2C SDA pinmux control */ + GPIO_setPinConfig(i2c->sda_port, i2c->sda_pin, i2c->sda_mux); /* Configure SDA alternate function */ + GPIO_setAnalogMode(i2c->sda_port, i2c->sda_pin, GPIO_ANALOG_DISABLED); /* Disable analog mode for SDA */ + //GPIO_setPadConfig(i2c->sda_port,i2c->sda_pin, GPIO_PIN_TYPE_OD); /* Optional: Open-drain configuration (commented) */ + GPIO_setPadConfig(i2c->sda_port, i2c->sda_pin, i2c->sda_pad); /* Set SDA pad type (e.g., pull-up) */ + GPIO_setQualificationMode(i2c->sda_port, i2c->sda_pin, GPIO_QUAL_ASYNC); /* Set SDA asynchronous qualification */ + //GPIO_setDirectionMode(i2c->sda_port, i2c->sda_pin, i2c->sda_direction); /* Set SDA direction */ + + /* Reset module before configuring it. */ + I2C_resetMaster(i2c->base); /* Reset I2C master module */ + + /* Disable debug mode */ + I2C_disableMasterDebug(i2c->base); /* Disable I2C debug mode to prevent interference */ + + /* Set master water marks. */ + I2C_setMasterWatermarks(i2c->base, I2C_MASTER_WATERMARK_0, I2C_MASTER_WATERMARK_0); /* Set FIFO watermarks to 0 */ + + /* Configure master glitch filters. + And set FILTSDA to 0 disables the filter, so the min value is 1. */ + I2C_setMasterGlitchFilter(i2c->base, I2C_MASTER_FILTER_PCLK1, I2C_MASTER_FILTER_PCLK1); /* Enable glitch filtering */ + + /* Configure baudrate after the SDA/SCL glitch filter setting, + since the baudrate calculation needs them as parameter. */ + I2C_configMasterBaudRate(i2c->base, RCC_getPclk2Frequency(), I2C_SPEED); /* Set I2C clock to 100 kHz */ + + /* Configure bus idle timeouts after baudrate setting. + The value is equal to BUSIDLE cycles of functional clock divided by prescaler. + And set BUSIDLE to 0 disables the filter, so the min value is 1. */ + I2C_setMasterBusIdleTimeout(i2c->base, 1U); /* Set bus idle timeout to 1 cycle */ + + /* Configure pin low timeouts after baudrate setting. + The value is equal to PINLOW cycles of functional clock divided by prescaler. + And set PINLOW to 0 disables the filter, so the min value is 1. */ + I2C_setMasterPinLowTimeout(i2c->base, I2C_MASTER_PINLOW_SCLSDA, 0U); /* Disable pin low timeout */ + + /* Config master data match mode, match code and rxmatchonly. */ + I2C_configMasterDataMatch(i2c->base, I2C_MASTER_MATCHMODE_DISABLED, 0U, 0U, I2C_MASTER_RXMATCHDATAONLY_DISABLE); /* Disable data match feature */ + + /* Enable master module */ + I2C_enableMasterModule(i2c->base); /* Enable I2C master peripheral */ +} + +/** + * @brief Master I2C transfer for NS800 I2C controller. + * + * @param bus The I2C bus device. + * @param msgs Array of I2C messages to transfer. + * @param num Number of messages in the array. + * @return Number of messages successfully transferred, or 0 on error. + */ +static rt_ssize_t ns800_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + // Obtain the hardware-specific I2C bus instance from the bus private data. + struct ns800_i2c_bus *ns800_i2c = (struct ns800_i2c_bus *)bus->priv; + I2C_TypeDef *i2c = ns800_i2c->base; // Base address of I2C registers. + I2C_Status status = I2C_STATUS_SUCCESS; // Status of I2C operations. + + // Iterate over each message in the transfer list. + for (rt_uint32_t i = 0; i < num; i++) + { + struct rt_i2c_msg *msg = &msgs[i]; // Current message. + + /* Build the 8-bit device address (7-bit address << 1) with R/W bit + * (the lowest bit will be set by the hardware start condition). */ + uint8_t addr8 = (msg->addr << 1); + I2C_Direction dir; + // Determine transfer direction from message flags. + if (msg->flags & RT_I2C_RD) + { + dir = I2C_DIRECTION_READ; // Master read. + } + else + { + dir = I2C_DIRECTION_WRITE; // Master write. + } + + /* Send START or REPEATED START condition. + * For the first message, send a normal START. + * For subsequent messages, send a RESTART unless the NO_START flag is set. */ + if (i == 0) + { + status = I2C_sendStart(i2c, addr8, dir); + } + else + { + if (!(msg->flags & RT_I2C_NO_START)) + { + status = I2C_sendReStart(i2c, addr8, dir); + } + // If RT_I2C_NO_START is set, skip the start condition and continue data transfer. + } + + // If start/restart failed, log error and abort. + if (status != I2C_STATUS_SUCCESS) + { + LOG_E("[I2C] Start/Restart failed, addr=0x%02X err=%d\n", addr8, status); + goto __exit; + } + + /* Data transfer phase. + * Depending on the direction, either receive data from the slave or send data to it. */ + if (msg->flags & RT_I2C_RD) + { + status = I2C_receiveDataMaster(i2c, msg->buf, msg->len); + } + else + { + status = I2C_sendDataMaster(i2c, msg->buf, msg->len); + } + + // If data transfer failed, log error and abort. + if (status != I2C_STATUS_SUCCESS) + { + LOG_E("[I2C] Data transfer failed, err=%d\n", status); + goto __exit; + } + + /* Send STOP condition: + * Only for the last message and if the NO_STOP flag is not set in that message. + * This ensures the bus is released after the complete transaction. */ + if (!(msg->flags & RT_I2C_NO_STOP) && (i == num - 1)) + { + // Wait for FIFO to become idle before sending STOP to avoid corruption. + status = I2C_sendStop(i2c); + if (status != I2C_STATUS_SUCCESS) + { + LOG_E("[I2C] Send stop failed, err=%d\n", status); + goto __exit; + } + } + } + + // All messages transferred successfully. + return num; + +__exit: + /* Error recovery: try to send STOP to release the bus, + * then reset the I2C master hardware to prevent deadlock. */ + I2C_sendStop(i2c); // Attempt to issue a STOP condition. + I2C_resetMaster(i2c); // Reset the I2C master module. + return 0; // Return 0 to indicate failure. +} + + + +const struct rt_i2c_bus_device_ops ns800_i2c_ops = { + .master_xfer = ns800_master_xfer, /* Master transfer operation */ + .slave_xfer = RT_NULL, /* Slave transfer not supported */ + .i2c_bus_control = RT_NULL, /* Bus control not implemented */ +}; + +/** + * @brief I2C initialization function + * @param None + * @retval RT_EOK indicates successful initialization. + */ +int rt_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(ns800_i2c_config) / sizeof(ns800_i2c_config[0]); /* Calculate number of I2C instances */ + + for(int i = 0; i < obj_num; i++) + { + /* Initialize I2C pins and peripheral */ + ns800_i2c_bus_init(&ns800_i2c_config[i]); + + /* Set I2C speed clock = 100kHz */ + if(IS_I2C_LEGACY(ns800_i2c_config[i].base)) /* Check if it's a legacy I2C peripheral */ + { + /* Set bus device operations */ + ns800_i2c_config[i].bus->ops = &ns800_i2c_ops; + /* Set private data pointer to configuration */ + ns800_i2c_config[i].bus->priv = (void *)&ns800_i2c_config[i]; + /* Register I2C bus device with RT-Thread */ + rt_i2c_bus_device_register(ns800_i2c_config[i].bus, ns800_i2c_config[i].device_name); + } + } + + return RT_EOK; /* Return success */ +} + +INIT_BOARD_EXPORT(rt_hw_i2c_init); /* Initialize I2C at board initialization phase */ + +#endif /* RT_USING_I2C */ \ No newline at end of file diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_hard_i2c.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_hard_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..cf11491639af24b8009ddc4edfd0cd2fd80a32fc --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_hard_i2c.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-14 Jeffery Yuan first version + */ + +#ifndef __DRV_HARD_I2C_H__ +#define __DRV_HARD_I2C_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct ns800_i2c_bus +{ + struct rt_i2c_bus_device *bus; + I2C_TypeDef *base; + char *device_name; + GPIO_TypeDef *scl_port; + GPIO_PinNum scl_pin; + GPIO_AltFunc scl_mux; + rt_uint32_t scl_pad; + GPIO_Direction scl_direction; + GPIO_TypeDef *sda_port; + GPIO_PinNum sda_pin; + GPIO_AltFunc sda_mux; + rt_uint32_t sda_pad; + GPIO_Direction sda_direction; +}; + +int rt_hw_hard_i2c_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HARD_I2C_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg1.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg1.c new file mode 100644 index 0000000000000000000000000000000000000000..9d55f70197e86c209e4c86844a16c2c95d5a55a1 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg1.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-13 Jeffery.Yuan Floating-point timeout support + */ + +#include +#include +#include "board.h" +#include "iwdg1.h" +#include "drv_iwdg1.h" + +#ifdef RT_USING_WDT +#ifdef BSP_USING_IWDG1 + +/* IWDG1 clock source frequency (Hz) = 10 MHz */ +#define IWDG1_CLK_FREQ_HZ (10000000U) + +/* PSC encoding to division ratio and tWDCLKD (microseconds) */ +static const uint32_t psc_div_table[] = { + 1, /* 0: DIV1 */ + 2, /* 1: DIV2 */ + 4, /* 2: DIV4 */ + 8, /* 3: DIV8 */ + 16, /* 4: DIV16 */ + 32, /* 5: DIV32 */ + 0, /* 6: Invalid */ + 0, /* 7: Invalid */ + 128, /* 8: DIV128 */ + 256, /* 9: DIV256 */ + 512, /* 10: DIV512*/ + 1024, /* 11: DIV1024*/ + 2048, /* 12: DIV2048*/ + 4096, /* 13: DIV4096*/ + 8192, /* 14: DIV8192*/ + 64 /* 15: DIV64 */ +}; +static const float tWDCLKD_us_table[] = { + 0.1f, 0.2f, 0.4f, 0.8f, 1.6f, 3.2f, + 0.0f, 0.0f, + 12.8f, 25.6f, 51.2f, 102.4f, 204.8f, 409.6f, 819.2f, 6.4f +}; + +/* TOPS encoding to ARR value */ +static const uint32_t tops_arr_table[] = { + 1023, /* 00: 0x3FF */ + 4095, /* 01: 0xFFF */ + 8191, /* 10: 0x1FFF */ + 16383 /* 11: 0x3FFF */ +}; + +/* IWDG1 device object */ +struct iwdg1_device +{ + IWDG1_TypeDef *base; + uint8_t psc_code; /* PSC encoding (0~15) */ + uint8_t tops_code; /* TOPS encoding (0~3) */ + float timeout_ms; /* Actual timeout in milliseconds (floating point) */ + rt_bool_t started; + rt_bool_t interrupt_mode; /* intterrupt flag */ +}; + +static struct iwdg1_device iwdg1_dev; +static rt_watchdog_t watchdog; + +/** + * @brief Calculate the closest hardware configuration for a desired timeout + * @param timeout_ms Desired timeout in milliseconds (float) + * @param psc_code Output PSC encoding + * @param tops_code Output TOPS encoding + * @param actual_ms Output actual timeout in milliseconds (float) + * @return RT_EOK always successful + */ +static rt_err_t iwdg1_calc_config_float(float timeout_ms, uint8_t *psc_code, uint8_t *tops_code, float *actual_ms) +{ + float target_us = timeout_ms * 1000.0f; + float best_diff = 1e9f; + uint8_t best_psc = 0, best_tops = 0; + float best_actual_us = 0; + + for (uint8_t psc = 0; psc < 16; psc++) + { + float tWDCLKD_us = tWDCLKD_us_table[psc]; + if (tWDCLKD_us == 0.0f) continue; + for (uint8_t tops = 0; tops < 4; tops++) + { + uint32_t arr = tops_arr_table[tops]; + float ov_us = (arr + 1) * tWDCLKD_us; + float diff = (ov_us > target_us) ? (ov_us - target_us) : (target_us - ov_us); + if (diff < best_diff) + { + best_diff = diff; + best_psc = psc; + best_tops = tops; + best_actual_us = ov_us; + if (diff == 0) goto found; + } + } + } + +found: + *psc_code = best_psc; + *tops_code = best_tops; + *actual_ms = best_actual_us / 1000.0f; + if (*actual_ms < 0.0001f) *actual_ms = 0.1024f; // ×îС 0.1024ms + rt_kprintf("psc_code=%d, tops_code=%d, actual=%.4f ms\n", best_psc, best_tops, *actual_ms); + return RT_EOK; +} + + +/* IWDG1 Interrupt Handler + NOTE: Due the IWDG1 operates in a low-speed clock domain and the operation + to clear the flag requires a certain number of clock cycles, so wait + for the flag status update to complete before exiting! + */ +void IWDG1_Handler(void) +{ + rt_interrupt_enter(); + rt_kprintf("Enter iwdg1 IRQ!\n"); + IWDG1_clearErrorStatus(iwdg1_dev.base); + IWDG1_clearIntStatus(iwdg1_dev.base); + while(IWDG1_getIntStatus(iwdg1_dev.base) == 1) + { + ; + } + + IWDG1_enableModule(iwdg1_dev.base); + rt_interrupt_leave(); +} + + + + +/* Apply hardware configuration (without enabling) */ +static void iwdg1_apply_config(void) +{ + uint32_t temp; + uint32_t cr = iwdg1_dev.base->CR.WORDVAL; + if (cr != 0x000033FF) { + rt_kprintf("iwdg1: CR already configured (0x%08X), skip write\n", cr); + // Reverse calculate actual timeout from existing CR + uint8_t psc = (cr >> 4) & 0xF; + uint8_t tops = cr & 0x3; + iwdg1_dev.psc_code = psc; + iwdg1_dev.tops_code = tops; + iwdg1_dev.timeout_ms = (tops_arr_table[tops] + 1) * tWDCLKD_us_table[psc] / 1000.0f; + rt_kprintf("iwdg1: using existing config, timeout=%.4f ms\n", iwdg1_dev.timeout_ms); + return; + } + if (iwdg1_dev.interrupt_mode) + { + /* Interrupt handler function registration. */ + Interrupt_register(IWDG1_IRQn, &IWDG1_Handler); + /* Enable the IWDG1 interrupt signals. Enable global interrupts.*/ + Interrupt_enable(IWDG1_IRQn); + temp = iwdg1_dev.tops_code | (IRQ_EN << IWDG_CR_RSTIRQS_S) \ + | (LPRUN << IWDG_CR_SLCSTP_S) \ + | (iwdg1_dev.psc_code << IWDG_CR_CKS_S) \ + | (END_PERCENT0 << IWDG_CR_RPES_S) \ + | (HEAD_PERCENT100 << IWDG_CR_RPSS_S); + } + else + { + temp = iwdg1_dev.tops_code | (RESET_EN << IWDG_CR_RSTIRQS_S) \ + | (LPRUN << IWDG_CR_SLCSTP_S) \ + | (iwdg1_dev.psc_code << IWDG_CR_CKS_S) \ + | (END_PERCENT0 << IWDG_CR_RPES_S) \ + | (HEAD_PERCENT100 << IWDG_CR_RPSS_S); + } + WRITE_REG(iwdg1_dev.base->CR.WORDVAL, temp); + + + IWDG1_clearErrorStatus(iwdg1_dev.base); + IWDG1_clearIntStatus(iwdg1_dev.base); +} + +/* Start watchdog (enable) */ +static void iwdg1_start_hw(void) +{ + IWDG1_enableModule(iwdg1_dev.base); + iwdg1_dev.started = RT_TRUE; + rt_kprintf("iwdg1: started, timeout=%.4f ms\n", iwdg1_dev.timeout_ms); +} + +static rt_err_t iwdg1_init(rt_watchdog_t *wdt) +{ + return RT_EOK; +} + +static rt_err_t iwdg1_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + IWDG1_refreshModule(iwdg1_dev.base); + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + { + // Standard integer millisecond interface (backward compatible) + uint32_t req_ms_int = *(uint32_t *)arg; + float req_ms = (float)req_ms_int; + uint8_t psc, tops; + float actual_ms; + iwdg1_calc_config_float(req_ms, &psc, &tops, &actual_ms); + iwdg1_dev.psc_code = psc; + iwdg1_dev.tops_code = tops; + iwdg1_dev.timeout_ms = actual_ms; + rt_kprintf("iwdg1: set timeout req=%u ms, actual=%.4f ms (PSC=%d, TOPS=%d)\n", + req_ms_int, actual_ms, psc, tops); + if (iwdg1_dev.started) + { + iwdg1_apply_config(); + IWDG1_enableModule(iwdg1_dev.base); + } + } + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + // Standard integer millisecond interface returns floor of actual timeout + *(uint32_t *)arg = (uint32_t)iwdg1_dev.timeout_ms; + break; + + case RT_DEVICE_CTRL_WDT_START: + if (!iwdg1_dev.started) + { + iwdg1_apply_config(); + iwdg1_start_hw(); + } + else + { + rt_kprintf("iwdg1: already started\n"); + } + break; + + case RT_DEVICE_CTRL_WDT_STOP: + rt_kprintf("iwdg1: stop not supported\n"); + return -RT_ENOSYS; + + default: + return -RT_ERROR; + } + return RT_EOK; +} + +/* Operation function table - constant */ +static const struct rt_watchdog_ops iwdg1_ops = { + .init = iwdg1_init, + .control = iwdg1_control, +}; + +int rt_hw_iwdg1_init(void) +{ + iwdg1_dev.base = IWDG1; + /* Default factory configuration: maximum timeout 13421.7728 ms */ + iwdg1_dev.psc_code = 14; // PSC = 14 (DIV8192), tWDCLKD = 819.2us + iwdg1_dev.tops_code = 3; // TOPS = 3 (ARR=16383) + iwdg1_dev.timeout_ms = (tops_arr_table[3] + 1) * tWDCLKD_us_table[14] / 1000.0f; // 16384*819.2/1000 = 13421.7728 ms + iwdg1_dev.started = RT_FALSE; + iwdg1_dev.interrupt_mode = RT_TRUE; + + watchdog.ops = &iwdg1_ops; + if (rt_hw_watchdog_register(&watchdog, IWDG1_DEVICE_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + rt_kprintf("iwdg1: register failed\n"); + return -RT_ERROR; + } + rt_kprintf("iwdg1: driver initialized (clock=%d Hz, max timeout=%.4f ms)\n", IWDG1_CLK_FREQ_HZ, iwdg1_dev.timeout_ms); + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_iwdg1_init); + +#endif /* BSP_USING_IWDG1 */ +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg1.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg1.h new file mode 100644 index 0000000000000000000000000000000000000000..b233159d62308226e4d235174b8627314f126dad --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg1.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-12 Jeffery Yuan first version + */ + +#ifndef DRV_IWDG1_H__ +#define DRV_IWDG1_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define IWDG1_DEVICE_NAME "iwdg1" + +/** + * @brief Initialize IWDG1 hardware and register it as a watchdog device. + * + * @return RT_EOK on success, negative error code otherwise. + */ +int rt_hw_iwdg1_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* DRV_IWDG1_H__ */ \ No newline at end of file diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg2.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg2.c new file mode 100644 index 0000000000000000000000000000000000000000..9105895e24dc9b9d74c0c1e4fa82e526902d34b7 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg2.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-13 Jeffery Yuan IWDG2 driver based on chip manual + */ + +#include +#include +#include "board.h" +#include "iwdg2.h" +#include "drv_iwdg2.h" +#ifdef RT_USING_WDT +#ifdef BSP_USING_IWDG2 + +/* IWDG2 ʱÖÓԴƵÂÊ (Hz) = 128 kHz (LIRC) */ +#define IWDG2_CLK_FREQ_HZ (128000U) + +/* PSC ±àÂë¶ÔÓ¦µÄ·ÖƵ±È */ +static const uint32_t psc_div_table[] = { + 128, /* 0: DIV128 */ + 2048, /* 1: DIV2048 */ + 1024, /* 2: DIV1024 */ + 512, /* 3: DIV512 */ + 256, /* 4: DIV256 */ + 64, /* 5: DIV64 */ + 32, /* 6: DIV32 */ + 16, /* 7: DIV16 */ + 8, /* 8: DIV8 */ + 4, /* 9: DIV4 */ + 0, /* 10: ÎÞЧ */ + 0, /* 11: ÎÞЧ */ + 0, /* 12: ÎÞЧ */ + 0, /* 13: ÎÞЧ */ + 0, /* 14: ÎÞЧ */ + 0 /* 15: ÎÞЧ */ +}; + +/* ¸ù¾Ý·ÖƵ±È¼ÆËã tWDCLKD (Ãë) */ +static float get_wdclk_period(uint8_t psc_code) +{ + uint32_t div = psc_div_table[psc_code]; + if (div == 0) return 0.0f; + return (float)div / IWDG2_CLK_FREQ_HZ; +} + +/* IWDG2 É豸¶ÔÏó */ +struct iwdg2_device +{ + IWDG2_TypeDef *base; + uint8_t psc_code; /* PSC ±àÂë (0~15) */ + uint16_t reload; /* ÖØ×°ÔØÖµ (12λ: 0~4095) */ + float timeout_s; /* ʵ¼ÊÒç³öʱ¼ä (Ãë) */ + rt_bool_t started; + rt_bool_t interrupt_mode; /* ÖжÏģʽ±êÖ¾ */ +}; + +static struct iwdg2_device iwdg2_dev; +static rt_watchdog_t watchdog; + +/** + * @brief ¸ù¾ÝÆÚÍû³¬Ê±Ê±¼ä¼ÆËã×î½Ó½üµÄÓ²¼þÅäÖà (PSC ºÍ RELOAD) + * @param timeout_s ÆÚÍû³¬Ê±Ê±¼ä (Ãë) + * @param psc_code Êä³ö PSC ±àÂë + * @param reload Êä³ö RELOAD Öµ + * @param actual_s Êä³öʵ¼Ê³¬Ê±Ê±¼ä (Ãë) + * @return RT_EOK ³É¹¦, -RT_ERROR ÎÞЧ²ÎÊý + */ +static rt_err_t iwdg2_calc_config(float timeout_s, uint8_t *psc_code, uint16_t *reload, float *actual_s) +{ + float best_diff = 1e9f; + uint8_t best_psc = 0; + uint16_t best_reload = 0; + float best_actual = 0; + + if (timeout_s <= 0) return -RT_ERROR; + + for (uint8_t psc = 0; psc < 16; psc++) + { + float tWDCLKD = get_wdclk_period(psc); + if (tWDCLKD == 0.0f) continue; /* ÎÞЧ±àÂë */ + + /* ¼ÆËãËùÐè RELOAD Öµ (ÏòϼÆÊýÆ÷£ºÒç³öʱ¼ä = (RELOAD+1) * tWDCLKD) */ + float reload_f = timeout_s / tWDCLKD - 1.0f; + uint16_t reload_val; + + if (reload_f < 0) + { + reload_val = 0; /* ×îС³¬Ê± */ + } + else if (reload_f > 4095.0f) + { + reload_val = 4095; /* ×î´ó³¬Ê± */ + } + else + { + reload_val = (uint16_t)(reload_f + 0.5f); /* ËÄÉáÎåÈë */ + } + + /* È·±£ÔÚÓÐЧ·¶Î§ */ + if (reload_val > 4095) reload_val = 4095; + + float ov_s = (reload_val + 1) * tWDCLKD; + float diff = (ov_s > timeout_s) ? (ov_s - timeout_s) : (timeout_s - ov_s); + + if (diff < best_diff) + { + best_diff = diff; + best_psc = psc; + best_reload = reload_val; + best_actual = ov_s; + /* Èç¹ûÎó²îСÓÚ1ms£¬Ö±½ÓʹÓà */ + if (diff < 0.001f) break; + } + } + + *psc_code = best_psc; + *reload = best_reload; + *actual_s = best_actual; + return RT_EOK; +} + +/** + * @brief IWDG2 ÖжϷþÎñº¯Êý + * @note º¯ÊýÃûÐèÓëÆô¶¯ÎļþÖеÄÈõ¶¨ÒåÒ»Ö£¬Ö±½Ó¸²¸Ç¼´¿É¡£ + * ²»ÒªÔÚ³õʼ»¯Ê±¶îÍâ×¢²á£¬±ÜÃâÏòÁ¿±í³åÍ»¡£ + */ +void IWDG2_Handler(void) +{ + rt_interrupt_enter(); + if (IWDG2_getIntStatus(iwdg2_dev.base)) + { + rt_kprintf("iwdg2: timeout interrupt occurred!\n"); + IWDG2_clearIntStatus(iwdg2_dev.base); + /* µÈ´ý±êÖ¾Çå³ýÍê³É */ + while (IWDG2_getIntStatus(iwdg2_dev.base)) + { + ; + } + } + rt_interrupt_leave(); +} + +/* Ó¦ÓÃÓ²¼þÅäÖà (²»Ê¹ÄÜ) */ +static void iwdg2_apply_config(void) +{ + /* ÅäÖà IWDG2: ÖжÏģʽ»ò¸´Î»Ä£Ê½ */ + if (iwdg2_dev.interrupt_mode) + { + /* ×¢²á²¢ÆôÓÃÖÐ¶Ï */ + Interrupt_register(IWDG2_IRQn, &IWDG2_Handler); + Interrupt_enable(IWDG2_IRQn); + IWDG2_configModule(iwdg2_dev.base, IRQ_SEL, + (IWDG2_Prescaler)iwdg2_dev.psc_code, + iwdg2_dev.reload); + } + else + { + IWDG2_configModule(iwdg2_dev.base, RESET_SEL, + (IWDG2_Prescaler)iwdg2_dev.psc_code, + iwdg2_dev.reload); + } + + /* µÈ´ýÖØ×°ÔØÖµ¸üÐÂÍê³É */ + while (IWDG2_getRVUStatus(iwdg2_dev.base) != 0) + { + ; + } +} + +/* Æô¶¯¿´ÃŹ· (ʹÄÜ) */ +static void iwdg2_start_hw(void) +{ + if (iwdg2_dev.interrupt_mode) + { + /* Çå³ý¿ÉÄܲÐÁôµÄÖжϱêÖ¾ */ + IWDG2_clearIntStatus(iwdg2_dev.base); + /* ʹÄÜ IWDG2 ÖÐ¶Ï */ + IWDG2_enableInterrupt(iwdg2_dev.base); + } + + /* ʹÄÜ IWDG2 Ä£¿é */ + IWDG2_enableModule(iwdg2_dev.base); + + /* Á¢¼´Î¹¹·£¬È·±£ RELOAD ÖµÕæÕý¼ÓÔص½¼ÆÊýÆ÷ */ + IWDG2_refreshModule(iwdg2_dev.base); + + iwdg2_dev.started = RT_TRUE; + + rt_kprintf("iwdg2: started, timeout = %.3f s, mode = %s\n", + (double)iwdg2_dev.timeout_s, + iwdg2_dev.interrupt_mode ? "interrupt" : "reset"); +} + +static rt_err_t iwdg2_init(rt_watchdog_t *wdt) +{ + /* ʹÄÜ LIRC Õñµ´Æ÷²¢µÈ´ýÎȶ¨ */ + RCC_unlockRccRegister(); + RCC_enableLircOscillator(); + RCC_lockRccRegister(); + + rt_kprintf("iwdg2: LIRC clock enabled (%d Hz)\n", IWDG2_CLK_FREQ_HZ); + return RT_EOK; +} + +static rt_err_t iwdg2_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + /* ι¹· */ + IWDG2_refreshModule(iwdg2_dev.base); + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + { + uint32_t req_ms = *(uint32_t *)arg; + float req_s = req_ms / 1000.0f; + uint8_t psc; + uint16_t reload; + float actual_s; + + /* ¼ÆËãÅäÖà */ + if (iwdg2_calc_config(req_s, &psc, &reload, &actual_s) != RT_EOK) + { + rt_kprintf("iwdg2: invalid timeout value %d ms\n", req_ms); + return -RT_ERROR; + } + + /* ¼ì²é³¬Ê±·¶Î§ */ + if (actual_s < 0.00003125f || actual_s > 65.536f) + { + rt_kprintf("iwdg2: timeout out of range (%.6f ~ 65.536 s)\n", 0.00003125); + return -RT_ERROR; + } + + iwdg2_dev.psc_code = psc; + iwdg2_dev.reload = reload; + iwdg2_dev.timeout_s = actual_s; + + rt_kprintf("iwdg2: set timeout req=%d ms, actual=%.3f s (PSC=%d, RELOAD=%d)\n", + req_ms, (double)actual_s, psc, reload); + + if (iwdg2_dev.started) + { + /* Èç¹ûÒѾ­Æô¶¯£¬ÐèÒªÖØÐÂÅäÖò¢ÖØÆô */ + iwdg2_apply_config(); + IWDG2_enableModule(iwdg2_dev.base); + IWDG2_refreshModule(iwdg2_dev.base); + } + } + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + /* ·µ»Ø³¬Ê±Ê±¼ä£¨ºÁÃ룩 */ + *(uint32_t *)arg = (uint32_t)(iwdg2_dev.timeout_s * 1000.0f); + break; + + case RT_DEVICE_CTRL_WDT_START: + if (!iwdg2_dev.started) + { + iwdg2_apply_config(); + iwdg2_start_hw(); + } + else + { + rt_kprintf("iwdg2: already started\n"); + } + break; + + case RT_DEVICE_CTRL_WDT_STOP: + /* IWDG2 Ò»µ©Æô¶¯ÎÞ·¨Í£Ö¹£¬ÕâÊÇÓ²¼þÌØÐÔ */ + rt_kprintf("iwdg2: stop not supported (hardware limitation)\n"); + return -RT_ENOSYS; + + default: + return -RT_ERROR; + } + return RT_EOK; +} + + +/* ²Ù×÷º¯Êý±í */ +static const struct rt_watchdog_ops iwdg2_ops = { + .init = iwdg2_init, + .control = iwdg2_control, +}; + +int rt_hw_iwdg2_init(void) +{ + iwdg2_dev.base = IWDG2; + + /* ĬÈÏÅäÖãº128·ÖƵ£¬×î´ó³¬Ê±Ô¼4.096Ãë */ + iwdg2_dev.psc_code = 0; /* PSC = 0: DIV128 */ + iwdg2_dev.reload = 4095; /* RELOAD = 0xFFF: ×î´ó¼ÆÊýÖµ */ + iwdg2_dev.timeout_s = 4.096f; /* (4095+1) * 128/128000 = 4.096s */ + iwdg2_dev.started = RT_FALSE; + iwdg2_dev.interrupt_mode = RT_TRUE; /* ĬÈÏÖжÏģʽ£¨°´ÐèÇó¿É¸Ä£© */ + + /* ×¢Ò⣺ + * 1. IWDG2_Handler ÒÑÔÚÆô¶¯ÎļþÖÐÈõ¶¨Ò壬ֱ½ÓдͬÃûº¯Êý¼´¿É£¬ÎÞÐèµ÷Óà Interrupt_register¡£ + * 2. ÖжÏʹÄܲ»ÔÚ³õʼ»¯½×¶Î½øÐУ¬¸ÄΪÆô¶¯¿´ÃŹ·Ê±Ê¹ÄÜ£¬±ÜÃâÌáÇ°½øÈëÖжϡ£ */ + + /* ×¢²á¿´ÃŹ·É豸 */ + watchdog.ops = &iwdg2_ops; + if (rt_hw_watchdog_register(&watchdog, IWDG2_DEVICE_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + rt_kprintf("iwdg2: register failed\n"); + return -RT_ERROR; + } + + rt_kprintf("iwdg2: driver initialized (clock=%d Hz)\n", IWDG2_CLK_FREQ_HZ); + rt_kprintf("iwdg2: timeout range: %.6f ~ 65.536 s\n", 0.00003125); + rt_kprintf("iwdg2: default mode: %s, timeout: 4.096 s\n", + iwdg2_dev.interrupt_mode ? "interrupt" : "reset"); + + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_iwdg2_init); + +#endif /* BSP_USING_IWDG2 */ +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg2.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg2.h new file mode 100644 index 0000000000000000000000000000000000000000..f69b97270b8b23e43284bf921da506fa439e5392 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_iwdg2.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-13 Jeffery Yuan first version + */ + +#ifndef DRV_IWDG2_H__ +#define DRV_IWDG2_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define IWDG2_DEVICE_NAME "iwdg2" + +/** + * @brief Initialize IWDG2 peripheral and register watchdog device. + * + * @return RT_EOK on success, otherwise negative error code. + */ +int rt_hw_iwdg2_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* DRV_IWDG2_H__ */ \ No newline at end of file diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_soft_i2c.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..cc82a079d8386a243f823eb404bb2fea3e711f93 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_soft_i2c.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-15 Jeffery Yuan the first version + */ + +#include +#include "drv_soft_i2c.h" + +#ifdef BSP_USING_SOFT_I2C + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_SOFT_I2C1) && !defined(BSP_USING_SOFT_I2C2) +#error "Please define at least one BSP_USING_I2Cx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +static const struct ns800_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_SOFT_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_SOFT_I2C2 + I2C2_BUS_CONFIG, +#endif +}; + +static struct ns800_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/* + * This function initializes the i2c pin. + * + * @param ns800 i2c dirver class. + */ +static void ns800_i2c_gpio_init(struct ns800_i2c *i2c) +{ + struct ns800_soft_i2c_config* cfg = (struct ns800_soft_i2c_config*)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +static void ns800_i2c_pin_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ns800_i2c); + + for(rt_size_t i = 0; i < obj_num; i++) + { + ns800_i2c_gpio_init(&i2c_obj[i]); + } +} + +/* + * This function sets the sda pin. + * + * @param ns800 config class. + * @param The sda pin state. + */ +static void ns800_set_sda(void *data, rt_int32_t state) +{ + struct ns800_soft_i2c_config* cfg = (struct ns800_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/* + * This function sets the scl pin. + * + * @param ns800 config class. + * @param The scl pin state. + */ +static void ns800_set_scl(void *data, rt_int32_t state) +{ + struct ns800_soft_i2c_config* cfg = (struct ns800_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/* + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t ns800_get_sda(void *data) +{ + struct ns800_soft_i2c_config* cfg = (struct ns800_soft_i2c_config*)data; + return rt_pin_read(cfg->sda); +} + +/* + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t ns800_get_scl(void *data) +{ + struct ns800_soft_i2c_config* cfg = (struct ns800_soft_i2c_config*)data; + return rt_pin_read(cfg->scl); +} + +/* + * The time delay function. + * + * @param microseconds. + */ +static void ns800_udelay(rt_uint32_t us) +{ + rt_hw_us_delay(us); +} + +static const struct rt_i2c_bit_ops ns800_bit_ops_default = +{ + .data = RT_NULL, + .pin_init = ns800_i2c_pin_init, + .set_sda = ns800_set_sda, + .set_scl = ns800_set_scl, + .get_sda = ns800_get_sda, + .get_scl = ns800_get_scl, + .udelay = ns800_udelay, + .delay_us = 1, + .timeout = 100, + .i2c_pin_init_flag = RT_FALSE +}; + +/* + * if i2c is locked, this function will unlock it + * + * @param ns800 config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t ns800_i2c_bus_unlock(const struct ns800_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + ns800_udelay(100); + rt_pin_write(cfg->scl, PIN_LOW); + ns800_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int rt_soft_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ns800_i2c); + rt_err_t result; + + for (rt_size_t i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = ns800_bit_ops_default; + i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; + + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + ns800_i2c_bus_unlock(&soft_i2c_config[i]); + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, + soft_i2c_config[i].sda); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_soft_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_soft_i2c.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..a0c17e27a2e4e42309e26e5f53da81fd87e636e1 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_soft_i2c.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-15 Jeffery Yuan the first version + */ + +#ifndef __DRV_SOFT_I2C__ +#define __DRV_I2C__ + +#include +#include +#include + +/* ns800 config class */ +struct ns800_soft_i2c_config +{ + rt_uint16_t scl; + rt_uint16_t sda; + const char *bus_name; +}; + +/* ns800 i2c dirver class */ +struct ns800_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c_bus; +}; + +#ifdef BSP_USING_SOFT_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl = BSP_SOFT_I2C1_SCL_PIN, \ + .sda = BSP_SOFT_I2C1_SDA_PIN, \ + .bus_name = "soft_i2c1", \ + } +#endif + +#ifdef BSP_USING_SOFT_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_SOFT_I2C2_SCL_PIN, \ + .sda = BSP_SOFT_I2C2_SDA_PIN, \ + .bus_name = "soft_i2c2", \ + } +#endif + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_wwdg.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_wwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..2c52f40d254e9e8dbdb3c5841a8e0fed3a00f240 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_wwdg.c @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-13 User WWDG driver based on chip manual + */ + +#include +#include +#include "board.h" +#include "wwdg.h" +#include "drv_wwdg.h" + + +#ifdef RT_USING_WDT +#ifdef BSP_USING_WWDG + +/* WWDG clock frequency (Hz) = HCLK. Here 200MHz as an example; should be obtained from BSP. */ +#ifndef HCLK_FREQ_HZ +#define HCLK_FREQ_HZ (200000000U) +#endif + +/* Prescaler divider table: divider = 2^WDGTB */ +static const uint8_t wdgtb_div_table[] = { + 1, /* 0: 1 */ + 2, /* 1: 2 */ + 4, /* 2: 4 */ + 8, /* 3: 8 */ + 16, /* 4: 16 */ + 32, /* 5: 32 */ + 64, /* 6: 64 */ + 128 /* 7: 128 */ +}; + +/** + * @brief Calculate the tick period for a given prescaler setting. + * @param wdgtb Prescaler code (0~7) + * @return Tick period in seconds (4096 * prescaler / HCLK) + */ +static float get_tick_period(uint8_t wdgtb) +{ + uint32_t div = wdgtb_div_table[wdgtb]; + return (float)(4096U * div) / HCLK_FREQ_HZ; +} + +/* WWDG device structure */ +struct wwdg_device +{ + WWDG_TypeDef *base; /* Base address of WWDG registers */ + uint8_t wdgtb; /* Prescaler code (0~7) */ + uint8_t reload; /* Counter reload value (0x40~0x7F) */ + uint8_t window; /* Window value (0x40~0x7F) */ + float timeout_s; /* Actual timeout in seconds */ + rt_bool_t started; /* True if watchdog is started */ + rt_bool_t interrupt_mode;/* True = interrupt mode, false = reset mode */ +}; + +static struct wwdg_device wwdg_dev; /* Global WWDG device instance */ +static rt_watchdog_t watchdog; /* RT-Thread watchdog device structure */ + +/** + * @brief Calculate the closest hardware configuration (WDGTB and CR.T) for a desired timeout. + * @param timeout_s Desired timeout in seconds + * @param wdgtb Output: prescaler code + * @param reload Output: counter reload value (CR.T) + * @param actual_s Output: actual timeout achieved + * @return RT_EOK on success, -RT_ERROR on invalid parameter + */ +static rt_err_t wwdg_calc_config(float timeout_s, uint8_t *wdgtb, uint8_t *reload, float *actual_s) +{ + float best_diff = 1e9f; + uint8_t best_wdgtb = 0; + uint8_t best_reload = 0x40; /* Minimum valid reload value */ + float best_actual = 0.0f; + + if (timeout_s <= 0.0f) return -RT_ERROR; + + /* Try all possible prescaler values to find the one giving closest timeout */ + for (uint8_t tb = 0; tb < 8; tb++) + { + float tick = get_tick_period(tb); + if (tick == 0.0f) continue; + + /* + * Timeout formula: Tov = (CR.T - 0x3F) * tick + * So required (CR.T - 0x3F) = timeout_s / tick + * Therefore CR.T = timeout_s / tick + 0x3F + */ + float reload_f = timeout_s / tick + 0x3F; + uint8_t reload_val; + + /* Clip to valid range [0x40, 0x7F] */ + if (reload_f < (float)0x40) + { + reload_val = 0x40; /* Minimum timeout */ + } + else if (reload_f > (float)0x7F) + { + reload_val = 0x7F; /* Maximum timeout */ + } + else + { + reload_val = (uint8_t)(reload_f + 0.5f); /* Round to nearest integer */ + if (reload_val < 0x40) reload_val = 0x40; + if (reload_val > 0x7F) reload_val = 0x7F; + } + + float ov_s = (reload_val - 0x3F) * tick; + float diff = (ov_s > timeout_s) ? (ov_s - timeout_s) : (timeout_s - ov_s); + + /* Keep the best match */ + if (diff < best_diff) + { + best_diff = diff; + best_wdgtb = tb; + best_reload = reload_val; + best_actual = ov_s; + /* If error is less than 100us, stop searching early */ + if (diff < 0.0001f) break; + } + } + + *wdgtb = best_wdgtb; + *reload = best_reload; + *actual_s = best_actual; + return RT_EOK; +} + +/* WWDG interrupt handler */ +void wwdg_isr(void) +{ + rt_kprintf("A"); + rt_interrupt_enter(); + WWDG_clearIntStatus(WWDG); /* Clear interrupt flag */ + while(WWDG_getIntStatus(WWDG) == 1) /* Wait until cleared */ + { + ; + } + WWDG_refreshModule(WWDG, wwdg_dev.window); /* Refresh to prevent reset */ + rt_interrupt_leave(); +} + +/* Apply hardware configuration (prescaler, window, mode) without starting the module */ +static void wwdg_apply_config(void) +{ + uint32_t ewi_flag; + + if (wwdg_dev.interrupt_mode) + { + ewi_flag = WWDG_EARLY_WAKEUP_INT; /* Interrupt mode */ + /* Register ISR and enable interrupt */ + Interrupt_register(WWDG_IRQn, &wwdg_isr); + Interrupt_enable(WWDG_IRQn); + } + else + { + ewi_flag = WWDG_DIRECT_RESET; /* Reset mode (no interrupt) */ + } + + /* + * WWDG_configModule(base, early_wakeup_flag, prescaler, window) + * Configure prescaler, window, and mode (interrupt or reset), but does not start. + */ + WWDG_configModule(wwdg_dev.base, ewi_flag, + (WWDG_Prescaler)wwdg_dev.wdgtb, + wwdg_dev.window); +} + +/* Start the watchdog hardware */ +static void wwdg_start_hw(void) +{ + /* Enable the module and load the initial counter value (set WDGA bit) */ + WWDG_enableModule(wwdg_dev.base, wwdg_dev.reload); + wwdg_dev.started = RT_TRUE; + + rt_kprintf("wwdg: started, timeout = %.6f s, mode = %s\n", + (double)wwdg_dev.timeout_s, + wwdg_dev.interrupt_mode ? "interrupt" : "reset"); +} + +/** + * @brief Initialize the watchdog device (called by RT-Thread watchdog framework). + * @param wdt Pointer to watchdog device + * @return RT_EOK on success + */ +static rt_err_t wwdg_init(rt_watchdog_t *wdt) +{ + /* No need to enable extra clock; WWDG uses HCLK directly */ + rt_kprintf("wwdg: HCLK frequency = %d Hz\n", HCLK_FREQ_HZ); + return RT_EOK; +} + +/** + * @brief Control function for the watchdog device. + * @param wdt Pointer to watchdog device + * @param cmd Command to execute + * @param arg Optional argument + * @return RT_EOK on success, error code otherwise + */ +static rt_err_t wwdg_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + /* Feed the dog: refresh counter within the window */ + WWDG_refreshModule(wwdg_dev.base, wwdg_dev.reload); + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + { + uint32_t req_ms = *(uint32_t *)arg; /* Requested timeout in ms */ + float req_s = req_ms / 1000.0f; + uint8_t wdgtb, reload; + float actual_s; + + if (wwdg_calc_config(req_s, &wdgtb, &reload, &actual_s) != RT_EOK) + { + rt_kprintf("wwdg: invalid timeout value %d ms\n", req_ms); + return -RT_ERROR; + } + + /* Check hardware limits */ + if (actual_s < 0.00002048f || actual_s > 0.16777216f) + { + rt_kprintf("wwdg: timeout out of range (20.48 us ~ 167.772 ms)\n"); + return -RT_ERROR; + } + + /* Store new configuration */ + wwdg_dev.wdgtb = wdgtb; + wwdg_dev.reload = reload; + wwdg_dev.timeout_s = actual_s; + + rt_kprintf("wwdg: set timeout req=%d ms, actual=%.6f s (WDGTB=%d, CR.T=0x%02X)\n", + req_ms, (double)actual_s, wdgtb, reload); + + /* If watchdog is already started, reconfigure and restart */ + if (wwdg_dev.started) + { + wwdg_apply_config(); + WWDG_enableModule(wwdg_dev.base, wwdg_dev.reload); + } + } + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + /* Return current timeout in milliseconds */ + *(uint32_t *)arg = (uint32_t)(wwdg_dev.timeout_s * 1000.0f); + break; + + case RT_DEVICE_CTRL_WDT_START: + if (!wwdg_dev.started) + { + wwdg_apply_config(); /* Apply prescaler, window, mode */ + wwdg_start_hw(); /* Start the watchdog */ + } + else + { + rt_kprintf("wwdg: already started\n"); + } + break; + + case RT_DEVICE_CTRL_WDT_STOP: + /* WWDG cannot be stopped once started (hardware limitation) */ + rt_kprintf("wwdg: stop not supported (hardware limitation)\n"); + return -RT_ENOSYS; + + default: + return -RT_ERROR; + } + return RT_EOK; +} + +/* Watchdog operation function table */ +static const struct rt_watchdog_ops wwdg_ops = { + .init = wwdg_init, + .control = wwdg_control, +}; + +/** + * @brief Initialize the WWDG hardware and register the watchdog device with RT-Thread. + * @return RT_EOK on success, -RT_ERROR on failure + */ +int rt_hw_wwdg_init(void) +{ + wwdg_dev.base = WWDG; /* Assign base address from board definition */ + + /* Default configuration: max prescaler (128), reload 0x7F, window 0x7F -> ~167.772 ms */ + wwdg_dev.wdgtb = 7; + wwdg_dev.reload = 0x7F; + wwdg_dev.window = 0x7F; + wwdg_dev.timeout_s = 0.16777216f; + wwdg_dev.started = RT_FALSE; + wwdg_dev.interrupt_mode = RT_FALSE; /* Default to reset mode (no interrupt) */ + + /* Set operations and register watchdog device */ + watchdog.ops = &wwdg_ops; + if (rt_hw_watchdog_register(&watchdog, WWDG_DEVICE_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + rt_kprintf("wwdg: register failed\n"); + return -RT_ERROR; + } + + rt_kprintf("wwdg: driver initialized (HCLK=%d Hz)\n", HCLK_FREQ_HZ); + rt_kprintf("wwdg: timeout range: 20.48 us ~ 167.772 ms\n"); + rt_kprintf("wwdg: default mode: reset, timeout: 167.772 ms\n"); + + return RT_EOK; +} + +/* Auto-initialize the driver during board initialization */ +INIT_BOARD_EXPORT(rt_hw_wwdg_init); + +#endif /* BSP_USING_WWDG */ +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_wwdg.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..10c9f1a0e2e944e69e595749342ca7ec3b3f462d --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_wwdg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-13 Jeffery Yuan first version + */ + +#ifndef DRV_WWDG_H__ +#define DRV_WWDG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* WWDG device name used for registration */ +#define WWDG_DEVICE_NAME "wwdg" + +/** + * @brief Initialize the WWDG (Window Watchdog) hardware and register the device. + * + * This function is called during system initialization (via INIT_BOARD_EXPORT). + * It configures the WWDG peripheral with default settings, registers the + * watchdog device with RT-Thread's watchdog framework, and makes it available + * to applications. + * + * @return RT_EOK on success, negative error code otherwise. + */ +int rt_hw_wwdg_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* DRV_WWDG_H__ */ \ No newline at end of file diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config index 5eb647dc85a767b8251faf3822599d7caad9d765..105b8eac18ce7e9c4784e968c82f8fb00a49c02d 100644 --- a/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config @@ -244,13 +244,17 @@ CONFIG_RT_CANSND_MSG_TIMEOUT=100 CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 # CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set # CONFIG_RT_USING_CLOCK_TIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set # CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set +CONFIG_RT_USING_DAC=y +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_PULSE_ENCODER is not set @@ -261,13 +265,14 @@ CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set +CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set @@ -318,7 +323,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Interprocess Communication (IPC) # end of POSIX (Portable Operating System Interface) layer -# CONFIG_RT_USING_CPLUSPLUS is not set +CONFIG_RT_USING_CPLUSPLUS=y +# CONFIG_RT_USING_CPLUSPLUS11 is not set +# CONFIG_RT_USING_CPP_WRAPPER is not set +# CONFIG_RT_USING_CPP_EXCEPTIONS is not set # end of C/C++ and POSIX layer # @@ -556,7 +564,111 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_U8G2_USE_HW_SPI is not set +CONFIG_U8G2_USE_HW_I2C=y +CONFIG_U8G2_I2C_DEVICE_NAME="soft_i2c2" +CONFIG_U8G2_USE_CPP=y +# CONFIG_U8G2_USING_I2C_YL40 is not set +# CONFIG_U8G2_USING_SW_I2C_SSD1306 is not set +CONFIG_U8G2_USING_HW_I2C_SSD1306=y +# CONFIG_U8G2_USING_SW_SPI_SSD1306 is not set +# CONFIG_U8G2_USING_8080_ST7920 is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_FONT_USAGE is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_FPS is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_GRAPHIC_TEST is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_HELLO_WORLD is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_ICON_MENU is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_PRINT_UTF8 is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_SELECTION_LIST is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_U8G2_LOGO is not set +# CONFIG_U8G2_USING_FRAME_EXAMPLE_UPDATE_AREA is not set +CONFIG_U8G2_USING_FRAME_EXAMPLE_WEATHER=y +# CONFIG_U8G2_USING_PAGE_EXAMPLE_CHINESE is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_CLIP_WINDOW is not set +CONFIG_U8G2_USING_PAGE_EXAMPLE_CLOCK=y +# CONFIG_U8G2_USING_PAGE_EXAMPLE_CONTRAST_TEST is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_DEVANAGARI is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_DIRECT_ACCESS is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_DRAW_LOG is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_EXT_UTF8 is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_FLIP_MODE is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_FPS is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_GRAPHIC_TEST is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_HELLO_WORLD is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_ICON_MENU is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_JAPANESE is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_KOREAN is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_POWER_SAVE_TEST is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_PRINT_HELLO_WORLD is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_SCROLLING_TEXT is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_SELECTION_LIST is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_SERIAL is not set +CONFIG_U8G2_USING_PAGE_EXAMPLE_STATE_BUFFER_LOOP=y +# CONFIG_U8G2_USING_PAGE_EXAMPLE_TERMINAL is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_U8G2_LOGO is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_UPDATE_PARTLY is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_WEATHER is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_XBM is not set +# CONFIG_U8G2_USING_PAGE_EXAMPLE_XOR_TEST is not set +# CONFIG_U8G2_USING_U8x8_EXAMPLE_16x16_FONT is not set +# CONFIG_U8G2_USING_U8x8_EXAMPLE_FLIP_MODE is not set +# CONFIG_U8G2_USING_U8x8_EXAMPLE_GRAPHIC_TEST is not set +# CONFIG_U8G2_USING_U8x8_EXAMPLE_HELLO_WORLD is not set +# CONFIG_U8G2_USING_U8x8_EXAMPLE_MESSAGE_BOX is not set +CONFIG_U8G2_USING_U8x8_EXAMPLE_TERMINAL=y +# CONFIG_U8G2_USING_GAME_EXAMPLE_SPACE_TRASH is not set +# CONFIG_U8G2_USING_GAME_EXAMPLE_TREX is not set +CONFIG_PKG_USING_U8G2=y +CONFIG_PKG_U8G2_PATH="/packages/multimedia/u8g2/u8g2" + +# +# U8G2 Examples +# + +# +# full buffer examples (fast, large RAM consumption) +# +# end of full buffer examples (fast, large RAM consumption) + +# +# page buffer examples (slow, small RAM consumption) +# +# end of page buffer examples (slow, small RAM consumption) + +# +# u8x8 text only examples (fonts with fixed size) +# +# end of u8x8 text only examples (fonts with fixed size) + +# +# game examples +# +# end of game examples +# end of U8G2 Examples + +# CONFIG_PKG_USING_U8G2_V100 is not set +# CONFIG_PKG_USING_U8G2_V110 is not set +# CONFIG_PKG_USING_U8G2_V120 is not set +# CONFIG_PKG_USING_U8G2_V200 is not set +# CONFIG_PKG_USING_U8G2_V210 is not set +# CONFIG_PKG_USING_U8G2_V300 is not set +# CONFIG_PKG_USING_U8G2_C_LATEST_VERSION is not set +# CONFIG_PKG_USING_U8G2_CPP_LATEST_VERSION is not set +CONFIG_PKG_USING_U8G2_LATEST_VERSION=y +CONFIG_PKG_U8G2_VER="latest" + +# +# C version: v1.x.x +# + +# +# C++ version: v2.x.x +# + +# +# C/C++ version: v3.x.x +# +CONFIG_PKG_U8G2_VER_NUM=0x99999 # end of u8g2: a monochrome graphic library # CONFIG_PKG_USING_NES_SIMULATOR is not set @@ -1027,7 +1139,28 @@ CONFIG_PKG_NOVOSNS_SERIES_DRIVER_VER="latest" # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set +CONFIG_PKG_USING_AT24CXX=y +CONFIG_PKG_AT24CXX_PATH="/packages/peripherals/at24cxx" +CONFIG_PKG_AT24CXX_FINSH=y + +# +# Select the Type of AT24CXX EEPROM +# +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C01 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C02 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C04 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C08 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C16 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C032 is not set +CONFIG_PKG_AT24CXX_EE_TYPE_AT24C64=y +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C128 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C256 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C512 is not set +CONFIG_PKG_AT24CXX_EE_TYPE=6 +# end of Select the Type of AT24CXX EEPROM + +CONFIG_PKG_USING_AT24CXX_LATEST_VERSION=y +CONFIG_PKG_AT24CXX_VER="latest" # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_ILI9341 is not set @@ -1442,6 +1575,10 @@ CONFIG_PKG_NOVOSNS_SERIES_DRIVER_VER="latest" # # On-chip Peripheral Drivers # +CONFIG_BOARD_CLK_CONF=y +CONFIG_SYSCLK_USE_PLL=y +CONFIG_SYSCLK_SOURCE_USE_HXTL=y +CONFIG_PLLCLK_SOURCE_USE_HXTL=y CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_GPIO_PIN_IRQ is not set CONFIG_BSP_USING_UART=y @@ -1450,7 +1587,31 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART4 is not set -CONFIG_BSP_USING_ECAP=y -CONFIG_BSP_USING_CAN=y -CONFIG_BSP_USING_CANFD1=y +# CONFIG_BSP_USING_ECAP is not set +# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_WDG=y +CONFIG_BSP_USING_IWDG1=y +CONFIG_BSP_USING_IWDG2=y +CONFIG_BSP_USING_WWDG=y +CONFIG_BSP_USING_HARD_I2C=y +CONFIG_BSP_USING_HARD_I2C1=y +# CONFIG_BSP_USING_HARD_I2C2 is not set +CONFIG_BSP_USING_SOFT_I2C=y +# CONFIG_BSP_USING_SOFT_I2C1 is not set +CONFIG_BSP_USING_SOFT_I2C2=y + +# +# Notice: PB2(i2c2_sda) --> 34; PB3(i2c_scl) --> 35 +# +CONFIG_BSP_SOFT_I2C2_SCL_PIN=35 +CONFIG_BSP_SOFT_I2C2_SDA_PIN=34 +CONFIG_BSP_USING_DAC=y +CONFIG_BSP_USING_DAC1=y +CONFIG_BSP_USING_DAC3=y +CONFIG_BSP_USING_GPIO_INT_XINT=y +CONFIG_BSP_USING_GPIO_INT_XINT1=y +CONFIG_BSP_USING_GPIO_INT_XINT2=y +CONFIG_BSP_USING_GPIO_INT_XINT3=y +CONFIG_BSP_USING_GPIO_INT_XINT4=y +CONFIG_BSP_USING_GPIO_INT_XINT5=y # end of On-chip Peripheral Drivers diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/.configs b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.configs new file mode 100644 index 0000000000000000000000000000000000000000..f30ad8e7df6e10e73249c8886c58a343763b9fa1 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.configs @@ -0,0 +1,1491 @@ +CONFIG_SOC_SERIES_NS800RT7=y +CONFIG_SOC_NS800RT7P6XX=y +CONFIG_BOARD_NS800RT7P65X=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_CAN_USING_CANFD=y +CONFIG_RT_CANMSG_BOX_SZ=16 +CONFIG_RT_CANSND_BOX_NUM=1 +CONFIG_RT_CANSND_MSG_TIMEOUT=100 +CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 +# CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +# CONFIG_RT_USING_I2C_BITOPS is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +CONFIG_PKG_USING_CMSIS_CORE=y +CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core" +CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y +CONFIG_PKG_CMSIS_CORE_VER="latest" +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER=y +CONFIG_PKG_NOVOSNS_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/novosns/novosns-series" +CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NOVOSNS_SERIES_DRIVER_VER="latest" +# end of NOVOSNS Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +CONFIG_PKG_USING_AT24CXX=y +CONFIG_PKG_AT24CXX_PATH="/packages/peripherals/at24cxx" +CONFIG_PKG_AT24CXX_FINSH=y + +# +# Select the Type of AT24CXX EEPROM +# +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C01 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C02 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C04 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C08 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C16 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C032 is not set +CONFIG_PKG_AT24CXX_EE_TYPE_AT24C64=y +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C128 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C256 is not set +# CONFIG_PKG_AT24CXX_EE_TYPE_AT24C512 is not set +CONFIG_PKG_AT24CXX_EE_TYPE=6 +# end of Select the Type of AT24CXX EEPROM + +CONFIG_PKG_USING_AT24CXX_LATEST_VERSION=y +CONFIG_PKG_AT24CXX_VER="latest" +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# On-chip Peripheral Drivers +# +CONFIG_BOARD_CLK_CONF=y +CONFIG_SYSCLK_USE_PLL=y +CONFIG_SYSCLK_SOURCE_USE_HXTL=y +CONFIG_PLLCLK_SOURCE_USE_HXTL=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_GPIO_PIN_IRQ is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_NS800_UART_TX_TIMEOUT=6000 +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_ECAP is not set +# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_WDG=y +CONFIG_BSP_USING_IWDG1=y +CONFIG_BSP_USING_IWDG2=y +CONFIG_BSP_USING_WWDG=y +CONFIG_BSP_USING_HARD_I2C=y +CONFIG_BSP_USING_HARD_I2C1=y +CONFIG_BSP_USING_HARD_I2C2=y +# end of On-chip Peripheral Drivers diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/EventRecorderStub.scvd b/bsp/novosns/ns800/ns800rt7p65-nssinepad/EventRecorderStub.scvd new file mode 100644 index 0000000000000000000000000000000000000000..2956b29683898915efa436cc948384a2c431dc31 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c index 62ab0863ff13dcb3c6f70b46bed3bf65fa9ce32f..3152bf1679fa8dfdbf44b01ec419a15cf454102d 100644 --- a/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c @@ -1,31 +1,327 @@ +///* +// * Copyright (c) 2006-2026, RT-Thread Development Team +// * +// * SPDX-License-Identifier: Apache-2.0 +// * +// * Change Logs: +// * Date Author Notes +// * 2026-05-06 Jiawei.Deng first version +// */ + +//#include +//#include +//#include + +///* defined the LED1 pin: GPIO_68 = PC4 */ +//#define LED1_PIN PIN_NUM(GPIO_68) +//#define PIN_KEY0 PIN_NUM(GPIO_31) + +///* 中断回调函数 ---------------------------------------------------------------------------- */ +//static void hdr_callback(void *args) +//{ +// char *str = args; +// rt_kprintf("KEY0 pressed. %s\n", str); +//} +////PA12 PF12 PD3 PD10 PF18 PF19 PG30 PG31 +//int main(void) +//{ +// rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); +// /* é…ç½®KEY0引脚为上拉输入 */ +// rt_pin_mode(PIN_KEY0, PIN_MODE_INPUT_PULLUP); +// +// /* 绑定中断回调函数，下é™æ²¿æ¨¡å¼ï¼Œå›žè°ƒå‡½æ•°å‚数为字符串"--By ZhengNian" */ +// rt_pin_attach_irq(PIN_KEY0, PIN_IRQ_MODE_RISING_FALLING, hdr_callback, (void*)"--By Jeffery"); +// +// /* 使能引脚中断 */ +// rt_pin_irq_enable(PIN_KEY0, PIN_IRQ_ENABLE); +// +// rt_kprintf("IR1=%08X IR2=%08X IRQn=%08X\n",SYSCON->EXTICR1.WORDVAL,SYSCON->EXTICR2.WORDVAL,NVIC->IP); +// while (1) +// { +// /*rt_kprintf("\r\n led1_thread_entry running! \r\n");*/ +// rt_pin_write(LED1_PIN, PIN_HIGH); +// rt_thread_mdelay(1000); +// rt_pin_write(LED1_PIN, PIN_LOW); +// rt_thread_mdelay(1000); +// } +//} + + /* - * Copyright (c) 2006-2026, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2026-05-06 Jiawei.Deng first version + * Date Author Notes + * 2024-01-15 RT-Thread first version */ #include #include -#include +#include +#define DBG_TAG "main" +#define DBG_LVL DBG_LOG +#include -/* defined the LED1 pin: GPIO_68 = PC4 */ -#define LED1_PIN PIN_NUM(GPIO_68) +// A0 ------> DAC_OUT1 +// B1 ------> DAC_OUT3 -int main(void) +#define DAC_DEV_NAME "dac3" /* DAC 设备å称 */ +#define DAC_DEV_CHANNEL 1 /* DAC é€šé“ */ +#define REFER_VOLTAGE 3.3 /* å‚考电压 3.3V,æ•°æ®ç²¾åº¦ä¹˜ä»¥100ä¿ç•™2ä½å°æ•°*/ +#define CONVERT_BITS (1 << 12) /* 转æ¢ä½æ•°ä¸º12ä½ */ + + +// 设置dac的使用命令 dac_set dac1 1 200 +// 第一个å‚数为命令，第二个å‚数为 dac 设备å称，第 3 个å‚数为 dac 通é“， +// 第 4 个å‚数为 dac 输出数值 +static int dac_set(int argc, char *argv[]) { - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + if(argc!=4) + { + rt_kprintf("Usage: dac_set \n"); + rt_kprintf("Example: dac_set dac1 1 1000\n"); + return RT_ERROR; + } + rt_dac_device_t dac_dev; + rt_uint32_t value, channel; + float volt; + rt_err_t ret = RT_EOK; + + char dacdevname[RT_NAME_MAX]; + + rt_strncpy(dacdevname, argv[1], RT_NAME_MAX); + channel = atoi(argv[2]); // DAC channel + value = atoi(argv[3]); + + /* 查找设备 */ + dac_dev = (rt_dac_device_t)rt_device_find(dacdevname); + if (dac_dev == RT_NULL) + { + rt_kprintf("dac sample run failed! can't find %s device!\n", dacdevname); + return RT_ERROR; + } + + /* æ‰“å¼€é€šé“ */ + ret = rt_dac_enable(dac_dev, channel); + + /* 设置输出值 */ + rt_dac_write(dac_dev, channel, value); + rt_kprintf("the value is :%d \n", value); + + /* 转æ¢ä¸ºå¯¹åº”电压值 */ + volt = (float)value * (float)REFER_VOLTAGE / (float)CONVERT_BITS; + rt_kprintf("the voltage is :%f \n", volt); + + /* 延时查看效果，关闭通é“åŽæ— è¾“出 */ +// rt_thread_mdelay(500); + + /* å…³é—­é€šé“ */ +// ret = rt_dac_disable(dac_dev, channel); + + return ret; +} + +static int dac1_vol_sample() +{ + rt_dac_device_t dac_dev; + float value, vol; + rt_err_t ret = RT_EOK; + + /* 查找设备 */ + dac_dev = (rt_dac_device_t)rt_device_find(DAC_DEV_NAME); + if (dac_dev == RT_NULL) + { + rt_kprintf("dac sample run failed! can't find %s device!\n", DAC_DEV_NAME); + return RT_ERROR; + } + + /* æ‰“å¼€é€šé“ */ + ret = rt_dac_enable(dac_dev, DAC_DEV_CHANNEL); + + /* 设置输出值 */ + value=4095.0f; + rt_dac_write(dac_dev, DAC_DEV_CHANNEL, (uint16_t)value); + rt_kprintf("the value is :%f \n", value); + + /* 转æ¢ä¸ºå¯¹åº”电压值 */ + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%f\n", vol ); + + /* 延时查看效果，关闭通é“åŽæ— è¾“出 */ + // rt_thread_mdelay(500); + + /* å…³é—­é€šé“ */ + // ret = rt_dac_disable(dac_dev, DAC_DEV_CHANNEL); - while (1) + return ret; +} + +int main(void) +{ + int count = 1; + LOG_D("Hello RT-Thread! 2026.5.18"); + LOG_D("System CLock information"); + LOG_D("Current tick = %d", rt_tick_get()); + dac1_vol_sample(); + while (count++) { -/* rt_kprintf("\r\n led1_thread_entry running! \r\n"); */ - rt_pin_write(LED1_PIN, PIN_HIGH); - rt_thread_mdelay(1000); - rt_pin_write(LED1_PIN, PIN_LOW); - rt_thread_mdelay(1000); + // LOG_D("Hello RT-Thread! %d", rt_tick_get()); + rt_thread_mdelay(6000); } + + return RT_EOK; } +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(dac_set, set dac voltage. Useage: dac_set adc1 1 200); + + + + +///* +// * Copyright (c) 2006-2026, RT-Thread Development Team +// * +// * SPDX-License-Identifier: Apache-2.0 +// * +// * Change Logs: +// * Date Author Notes +// * 2026-05-06 Jiawei.Deng first version +// */ + +//#include +//#include +//#include +//#include "drv_gpio_int_xint.h" + +//#define DBG_TAG "mian." +//#define DBG_LVL DBG_INFO +//#include +///* defined the LED1 pin: GPIO_68 = PC4 */ +//#define LED1_PIN PIN_NUM(GPIO_68)//获å–å¼•è„šç¼–å· + +///* 设备å称 */ +//#define XINT_DEV_NAME "xint1" +//#define XINT_DEV_NAME1 "xint5" + + +//static rt_device_t xint_dev = RT_NULL; +//static uint32_t trigger_count = 0; +//static rt_device_t xint_dev1 = RT_NULL; +//static uint32_t trigger_count1 = 0; +///* 中断回调函数 */ +//static void xint_callback(void *user_data) +//{ +// uint32_t *count_ptr = (uint32_t *)user_data; +// if (count_ptr != NULL) { +// (*count_ptr)++; +// LOG_I("XINT interrupt triggered! count: %u", *count_ptr); +// } +// else +// { +// rt_kprintf("kkkk\n"); +// } +// /* 注æ„：这里在中断上下文，ä¸è¦æ‰§è¡Œè€—æ—¶æ“作 */ +//} + +///* 中断回调函数 */ +//static void xint_callback1(void *user_data) +//{ +// uint32_t *count_ptr = (uint32_t *)user_data; +// if (count_ptr != NULL) { +// (*count_ptr)++; +// LOG_I("XINT interrupt triggered! count1: %u", *count_ptr); +// } +// else +// { +// rt_kprintf("kkkk\n"); +// } +// /* 注æ„：这里在中断上下文，ä¸è¦æ‰§è¡Œè€—æ—¶æ“作 */ +//} + +//int main(void) +//{ +// rt_err_t ret; +// struct rt_gpio_int_xint_config_data config = {GPIO_INT_XINT1,GPIO_224,GPIO_INT_TYPE_FALLING_EDGE}; +// struct gpio_int_xint_callback cb; +// struct rt_gpio_int_xint_config_data config1 = {GPIO_INT_XINT5,GPIO_41,GPIO_INT_TYPE_FALLING_EDGE}; +// struct gpio_int_xint_callback cb1; +// +// rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); +// rt_pin_mode(PIN_NUM(GPIO_224),PIN_MODE_INPUT); +// rt_pin_mode(PIN_NUM(GPIO_41),PIN_MODE_INPUT); +// rt_kprintf("conf_info:externalIntNum=%d gpio_port=%d config.gpio_pin=%d config.intType=%d\n",config.externalIntNum,config.gpio_port,config.gpio_pin,config.intType); +// +// LOG_I("XINT test thread started"); +// +// /* 1. 打开设备 */ +// xint_dev = rt_device_find(XINT_DEV_NAME); +// if (xint_dev == RT_NULL) +// { +// LOG_E("Cannot find device: %s", XINT_DEV_NAME); +// } +// +// +// if(xint_dev != RT_NULL) +// { +// /* 3. 设置回调函数 */ +// cb.callback = xint_callback; +// cb.user_data = (void *)&trigger_count; +// ret = rt_device_control(xint_dev, GPIO_INT_XINT_CMD_SET_CALLBACK, &cb); +// if (ret != RT_EOK) +// { +// LOG_E("Set callback failed: %d", ret); +// } +// +// /* 4. åˆå§‹åŒ–中断 */ +// ret = rt_device_control(xint_dev, GPIO_INT_XINT_CMD_SET_IINT_INFO, &config); +// if (ret != RT_EOK) +// { +// LOG_E("Set interrupt info failed: %d", ret); +// } +// +// LOG_I("XINT test initialized successfully!"); +// LOG_I("Please trigger interrupt on GPIO pin to test..."); +// } +// +// /* 1. 打开设备 */ +// xint_dev1 = rt_device_find(XINT_DEV_NAME1); +// if (xint_dev1 == RT_NULL) +// { +// LOG_E("Cannot find device: %s", XINT_DEV_NAME1); +// } +// +// +// if(xint_dev1 != RT_NULL) +// { +// /* 3. 设置回调函数 */ +// cb1.callback = xint_callback1; +// cb1.user_data = (void *)&trigger_count1; +// ret = rt_device_control(xint_dev1, GPIO_INT_XINT_CMD_SET_CALLBACK, &cb1); +// if (ret != RT_EOK) +// { +// LOG_E("Set callback failed: %d", ret); +// } +// +// /* 4. åˆå§‹åŒ–中断 */ +// ret = rt_device_control(xint_dev1, GPIO_INT_XINT_CMD_SET_IINT_INFO, &config1); +// if (ret != RT_EOK) +// { +// LOG_E("Set interrupt info failed: %d", ret); +// } +// +// LOG_I("XINT test initialized successfully!"); +// LOG_I("Please trigger interrupt on GPIO pin to test..."); +// } +// while (1) +// { +// /*rt_kprintf("\r\n led1_thread_entry running! \r\n");*/ +// rt_pin_write(LED1_PIN, PIN_HIGH); +// rt_thread_mdelay(1000); +// rt_pin_write(LED1_PIN, PIN_LOW); +// rt_thread_mdelay(1000); +// } +//} + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.cpp b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99565e2c5b5ad4e2e07e42e4a65bb2f874a10fa0 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.cpp @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-06 Jiawei.Deng first version + */ + +#include +#include +#include + +/* defined the LED1 pin: GPIO_68 = PC4 */ +#define LED1_PIN PIN_NUM(GPIO_68) + + +int main(void) +{ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + char* buffer = new char[1024]; + if(buffer) + { + rt_kprintf("buffer_size=%d\n",sizeof(buffer)); + } + while (1) + { + /*rt_kprintf("\r\n led1_thread_entry running! \r\n");*/ + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(1000); + } +} + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig index c4bbdf3080b9755f59eda48f07ae7531513c2d76..65f13ff7a36105f7ecf14c65166b0de9bab5291d 100644 --- a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig @@ -1,5 +1,23 @@ menu "On-chip Peripheral Drivers" + menuconfig BOARD_CLK_CONF + bool "Clock Configuration" + default y + if BOARD_CLK_CONF + config SYSCLK_USE_PLL + bool "Use PLL as system clock source" + default y + + config SYSCLK_SOURCE_USE_HXTL + bool "Use High-Speed Crystal Oscillator (HXTL) as system clock source" + default y + depends on SYSCLK_USE_PLL + config PLLCLK_SOURCE_USE_HXTL + bool "Use High-Speed Crystal Oscillator (HXTL) as PLL clock source" + default y + depends on SYSCLK_USE_PLL + endif + menuconfig BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN @@ -102,7 +120,121 @@ menu "On-chip Peripheral Drivers" bool "Enable CANFD1" select RT_CAN_USING_CANFD default n + endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + select RT_USING_WDT + default n + if BSP_USING_WDG + menuconfig BSP_USING_IWDG1 + bool "Enable IWDG1" + default n + + menuconfig BSP_USING_IWDG2 + bool "Enable IWDG1" + default n + + menuconfig BSP_USING_WWDG + bool "Enable WWDG" + default n + endif + + menuconfig BSP_USING_HARD_I2C + bool "Enable Hard I2C" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + menuconfig BSP_USING_HARD_I2C1 + bool "Enable Hard I2C1" + default n + menuconfig BSP_USING_HARD_I2C2 + bool "Enable Hard I2C2" + default n endif + + menuconfig BSP_USING_SOFT_I2C + bool "Enable I2C Bus" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + + if BSP_USING_SOFT_I2C + config BSP_USING_SOFT_I2C1 + bool "Enable I2C1 Bus (software simulation)" + default n + + if BSP_USING_SOFT_I2C1 + comment "Notice: PB10(i2c1_sda) --> 42; PB11 (i2c1_scl)--> 43" + + config BSP_SOFT_I2C1_SCL_PIN + int "i2c1 SCL pin number" + range 0 224 + default 43 + config BSP_SOFT_I2C1_SDA_PIN + int "i2c1 SDA pin number" + range 0 224 + default 42 + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable I2C2 Bus (software simulation)" + default n + + if BSP_USING_SOFT_I2C2 + comment "Notice: PB2(i2c2_sda) --> 34; PB3(i2c_scl) --> 35" + config BSP_SOFT_I2C2_SCL_PIN + int "i2c2 SCL pin number" + range 0 224 + default 35 + config BSP_SOFT_I2C2_SDA_PIN + int "i2c2 SDA pin number" + range 0 224 + default 34 + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + menuconfig BSP_USING_DAC1 + bool "Enable DAC1" + default n + + menuconfig BSP_USING_DAC3 + bool "Enable DAC3" + default n + endif + + menuconfig BSP_USING_GPIO_INT_XINT + bool "Enable gpio int xint" + default n + if BSP_USING_GPIO_INT_XINT + menuconfig BSP_USING_GPIO_INT_XINT1 + bool "Enable GPIO INT XINT1" + default n + + menuconfig BSP_USING_GPIO_INT_XINT2 + bool "Enable GPIO INT XINT2" + default n + menuconfig BSP_USING_GPIO_INT_XINT3 + bool "Enable GPIO INT XINT3" + default n + + menuconfig BSP_USING_GPIO_INT_XINT4 + bool "Enable GPIO INT XINT4" + default n + + menuconfig BSP_USING_GPIO_INT_XINT5 + bool "Enable GPIO INT XINT5" + default n + + endif + + endmenu diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvoptx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..f438721aab96ce051633136914935efec32beca5 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvoptx @@ -0,0 +1,3149 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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a/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvprojx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..3529ddb0d5b7d45ad6cade2c0363ac410fcaf556 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvprojx @@ -0,0 +1,3440 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 6240000::V6.24::ARMCLANG + 6240000::V6.24::ARMCLANG + 1 + + + NS800RT7P65D-DHQFBY2 + Novosense + NOVOSENSE.NS800RT7XXX.0.5.3 + https://www.novosns.com/ + IRAM(0x20000000,0x00020000) IRAM2(0x00000000,0x00020000) IROM(0x08000000,0x00080000) IROM2(0x08080000,0x00080000) XRAM(0x20100000,0x00020000) XRAM2(0x20120000,0x00020000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20120000 -FC2000 -FN2 -FF0NS800RT7xxx_FlashBank1 -FS08000000 -FL080000 -FF1NS800RT7xxx_FlashBank2 -FS18080000 -FL180000 -FP0($$Device:NS800RT7P65D-DHQFBY2$CMSIS\Flash\NS800RT7xxx_FlashBank1.FLM) -FP1($$Device:NS800RT7P65D-DHQFBY2$CMSIS\Flash\NS800RT7xxx_FlashBank2.FLM)) + 0 + + + + + + + + + + + $$Device:NS800RT7P65D-DHQFBY2$CMSIS\SVD\NS800RT7P65x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x20100000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x8080000 + 0x80000 + + + 0 + 0x20100000 + 0x20000 + + + 0 + 0x20120000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 0 + 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packages\u8g2-latest\src\u8x8_u8toa.c + + + u8g2_port.c + 1 + packages\u8g2-latest\port\u8g2_port.c + + + Print.cpp + 8 + packages\u8g2-latest\port\Print.cpp + + + U8g2lib.cpp + 8 + packages\u8g2-latest\port\U8g2lib.cpp + + + U8x8lib.cpp + 8 + packages\u8g2-latest\port\U8x8lib.cpp + + + ssd1306_12864_hw_i2c_example.cpp + 8 + packages\u8g2-latest\examples\ssd1306_12864_hw_i2c_example.cpp + + + Weather.cpp + 8 + packages\u8g2-latest\examples\full_buffer\Weather.cpp + + + Clock.cpp + 8 + packages\u8g2-latest\examples\page_buffer\Clock.cpp + + + StateBufferLoop.cpp + 8 + packages\u8g2-latest\examples\page_buffer\StateBufferLoop.cpp + + + Terminal_8x8.cpp + 8 + packages\u8g2-latest\examples\u8x8\Terminal_8x8.cpp + + + + + + + + + + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h b/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h index 380f2986c76e9d4250b17763411291e6760a8fe8..9b1ea75317b0d6b381124a4934322624c696ce4c 100644 --- a/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h @@ -149,6 +149,12 @@ #define RT_CANSND_BOX_NUM 1 #define RT_CANSND_MSG_TIMEOUT 100 #define RT_CAN_NB_TX_FIFO_SIZE 256 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_DAC +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_WDT #define RT_USING_PIN /* end of Device Drivers */ @@ -175,6 +181,7 @@ /* end of Interprocess Communication (IPC) */ /* end of POSIX (Portable Operating System Interface) layer */ +#define RT_USING_CPLUSPLUS /* end of C/C++ and POSIX layer */ /* Network */ @@ -254,6 +261,43 @@ /* u8g2: a monochrome graphic library */ +#define U8G2_USE_HW_I2C +#define U8G2_I2C_DEVICE_NAME "soft_i2c2" +#define U8G2_USE_CPP +#define U8G2_USING_HW_I2C_SSD1306 +#define U8G2_USING_FRAME_EXAMPLE_WEATHER +#define U8G2_USING_PAGE_EXAMPLE_CLOCK +#define U8G2_USING_PAGE_EXAMPLE_STATE_BUFFER_LOOP +#define U8G2_USING_U8x8_EXAMPLE_TERMINAL +#define PKG_USING_U8G2 + +/* U8G2 Examples */ + +/* full buffer examples (fast, large RAM consumption) */ + +/* end of full buffer examples (fast, large RAM consumption) */ + +/* page buffer examples (slow, small RAM consumption) */ + +/* end of page buffer examples (slow, small RAM consumption) */ + +/* u8x8 text only examples (fonts with fixed size) */ + +/* end of u8x8 text only examples (fonts with fixed size) */ + +/* game examples */ + +/* end of game examples */ +/* end of U8G2 Examples */ +#define PKG_USING_U8G2_LATEST_VERSION + +/* C version: v1.x.x */ + +/* C++ version: v2.x.x */ + +/* C/C++ version: v3.x.x */ + +#define PKG_U8G2_VER_NUM 0x99999 /* end of u8g2: a monochrome graphic library */ /* end of multimedia packages */ @@ -344,6 +388,15 @@ /* touch drivers */ /* end of touch drivers */ +#define PKG_USING_AT24CXX +#define PKG_AT24CXX_FINSH + +/* Select the Type of AT24CXX EEPROM */ + +#define PKG_AT24CXX_EE_TYPE_AT24C64 +#define PKG_AT24CXX_EE_TYPE 6 +/* end of Select the Type of AT24CXX EEPROM */ +#define PKG_USING_AT24CXX_LATEST_VERSION /* end of peripheral libraries and drivers */ /* AI packages */ @@ -417,13 +470,36 @@ /* On-chip Peripheral Drivers */ +#define BOARD_CLK_CONF +#define SYSCLK_USE_PLL +#define SYSCLK_SOURCE_USE_HXTL +#define PLLCLK_SOURCE_USE_HXTL #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_NS800_UART_TX_TIMEOUT 6000 #define BSP_USING_UART1 -#define BSP_USING_ECAP -#define BSP_USING_CAN -#define BSP_USING_CANFD1 +#define BSP_USING_WDG +#define BSP_USING_IWDG1 +#define BSP_USING_IWDG2 +#define BSP_USING_WWDG +#define BSP_USING_HARD_I2C +#define BSP_USING_HARD_I2C1 +#define BSP_USING_SOFT_I2C +#define BSP_USING_SOFT_I2C2 + +/* Notice: PB2(i2c2_sda) --> 34; PB3(i2c_scl) --> 35 */ + +#define BSP_SOFT_I2C2_SCL_PIN 35 +#define BSP_SOFT_I2C2_SDA_PIN 34 +#define BSP_USING_DAC +#define BSP_USING_DAC1 +#define BSP_USING_DAC3 +#define BSP_USING_GPIO_INT_XINT +#define BSP_USING_GPIO_INT_XINT1 +#define BSP_USING_GPIO_INT_XINT2 +#define BSP_USING_GPIO_INT_XINT3 +#define BSP_USING_GPIO_INT_XINT4 +#define BSP_USING_GPIO_INT_XINT5 /* end of On-chip Peripheral Drivers */ #endif diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvoptx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..c822556e688ec2f5167d4707e29f585f56f790bc --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U775238036 -O110 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20120000 -FC2000 -FN2 -FF0NS800RT7xxx_FlashBank1.FLM -FS08000000 -FL080000 -FP0($$Device:NS800RT7P65D-DHQFBY2$CMSIS\Flash\NS800RT7xxx_FlashBank1.FLM) -FF1NS800RT7xxx_FlashBank2.FLM -FS18080000 -FL180000 -FP1($$Device:NS800RT7P65D-DHQFBY2$CMSIS\Flash\NS800RT7xxx_FlashBank2.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20120000 -FC2000 -FN2 -FF0NS800RT7xxx_FlashBank1 -FS08000000 -FL080000 -FF1NS800RT7xxx_FlashBank2 -FS18080000 -FL180000 -FP0($$Device:NS800RT7P65D-DHQFBY2$CMSIS\Flash\NS800RT7xxx_FlashBank1.FLM) -FP1($$Device:NS800RT7P65D-DHQFBY2$CMSIS\Flash\NS800RT7xxx_FlashBank2.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx index 9a1baf2a14bcf6c007e6965df5fbafad3e19f59d..5e3cc5da3a38aa9f72eda068981de0e59b011b5c 100644 --- a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx @@ -10,13 +10,14 @@ rt-thread 0x4 ARM-ADS + 6240000::V6.24::ARMCLANG 6220000::V6.22::ARMCLANG 1 NS800RT7P65D-DHQFBY2 Novosense - NOVOSENSE.NS800RT7XXX.0.4.0 + NOVOSENSE.NS800RT7XXX.0.5.3 https://www.novosns.com/ IRAM(0x20000000,0x00020000) IRAM2(0x00000000,0x00020000) IROM(0x08000000,0x00080000) IROM2(0x08080000,0x00080000) XRAM(0x20100000,0x00020000) XRAM2(0x20120000,0x00020000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE @@ -52,7 +53,7 @@ rt-thread 1 0 - 0 + 1 1 1 .\build\ @@ -323,7 +324,7 @@ 1 0 0 - 3 + 1 0 0 1 diff --git a/bsp/novosns/ns800/tools/sdk_dist.py b/bsp/novosns/ns800/tools/sdk_dist.py index 0b75bf8cee88db5e27d6a2a2b3bf79b8cf4fce83..7ef49f3a2ba97ecce62a46c008adde4d0beb3109 100644 --- a/bsp/novosns/ns800/tools/sdk_dist.py +++ b/bsp/novosns/ns800/tools/sdk_dist.py @@ -11,7 +11,7 @@ def dist_do_building(BSP_ROOT, dist_dir): from mkdist import bsp_copy_files import rtconfig - print("=> copy novosns bsp library") + print("=> copy stm32 bsp library") library_dir = os.path.join(dist_dir, 'libraries') library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') if rtconfig.BSP_LIBRARY_TYPE is not None: @@ -20,3 +20,4 @@ def dist_do_building(BSP_ROOT, dist_dir): print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'HAL_Drivers'), os.path.join(library_dir, 'HAL_Drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) diff --git a/src/kservice.c b/src/kservice.c index db321552616f7d97e927e8398c4681298c80871e..08d911e63e4c28524aa7d901d9ea8c7992ba1c97 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -388,6 +388,7 @@ void rt_kputs(const char *str) * * @return The number of characters actually written to buffer. */ +#include rt_weak int rt_kprintf(const char *fmt, ...) { va_list args; @@ -407,7 +408,7 @@ rt_weak int rt_kprintf(const char *fmt, ...) * large excluding the terminating null byte. If the output string * would be larger than the rt_log_buf, we have to adjust the output * length. */ - length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); + length = vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); if (length > RT_CONSOLEBUF_SIZE - 1) { length = RT_CONSOLEBUF_SIZE - 1;