# VectorCGRA

**Repository Path**: phlix123/VectorCGRA

## Basic Information

- **Project Name**: VectorCGRA
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: BSD-3-Clause
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-03-13
- **Last Updated**: 2026-03-13

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

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VectorCGRA (vectorizable Coarse-Grained Reconfigurable Accelerator) generator is a parameterizable CGRA generator to generate synthesizable Verilog for different CGRAs based on user-specified configurations (e.g., CGRA size, type of the computing units in each tile, number of lanes for vectorization, communication connection, etc.).

Installation
--------------------------------------------------------

VectorCGRA should work well on Python 3.7/3.8/3.9/3.10/3.12 with the following additional prerequisites:

 - graphviz, verilator
 - git, Python headers, and libffi
 - virtualenv
 - PyMTL3

The steps for installing these prerequisites and VectorCGRA on a fresh Ubuntu
distribution are shown below. They have been tested with Ubuntu Trusty
14.04 ~ 22.04.

### Install python3

```
 % sudo apt-get install python3.7
```

### Install graphviz

```
 % sudo apt-get install -y graphviz
```

### Install Verilator

[Verilator][4] is an open-source toolchain for compiling Verilog RTL
models into C++ simulators. VectorCGRA uses Verilator for Verilog import.

```
 $ sudo apt-get install git make autoconf g++ libfl-dev bison
 $ mkdir -p ${HOME}/src
 $ cd ${HOME}/src
 $ wget http://www.veripool.org/ftp/verilator-4.036.tgz
 $ tar -xzvf verilator-4.036.tgz
 $ cd verilator-4.036
 $ ./configure
 $ make
 $ sudo make install
```

 [4]: http://www.veripool.org/wiki/verilator

### Install git, Python headers, and libffi

We need to install the Python headers and libffi in order to be able to
install the cffi Python package. cffi provides an elegant way to call C
functions from Python, and PyMTL uses cffi to call C code generated by
Verilator. We will use git to grab the PyMTL source. The following
commands will install the appropriate packages:

```
 % sudo apt-get install git python-dev libffi-dev
```

### Create virtual environment

While not strictly necessary, we strongly recommend using [virtualenv][5]
to install PyMTL3 and the Python packages that PyMTL3 depends on.
virtualenv enables creating isolated Python environments. The following
commands will create and activate the virtual environment:

```
 % python3 -m venv ${HOME}/venv
 % source ${HOME}/venv/bin/activate
```

 [5]: https://virtualenv.pypa.io/en/latest/

### Install PyMTL3 and Python requirements

```
 % pip install py==1.11.0
 % pip install -U git+https://github.com/tancheng/pymtl3.1@yo-struct-list-fix
 % pip install wheel
 % pip install --upgrade pip setuptools twine
 % pip install hypothesis
 % pip install pytest
 % pip install py-markdown-table
 % pip list
```
Take a look at the [workflow](https://github.com/tancheng/VectorCGRA/blob/master/.github/workflows/python-package.yml) if you encounter any problem to run the test in this repo.

### Clone VectorCGRA repo

We can now use git to clone the VectorCGRA repo.

```
 % mkdir -p ${HOME}/cgra
 % cd ${HOME}/cgra
 % git clone https://github.com/tancheng/VectorCGRA.git
 % cd VectorCGRA/
 % git submodule update --init
```

### Run an example to generate Verilog

For [CGRA translation](https://github.com/tancheng/VectorCGRA/tree/master/cgra/translate), just type:

```
 % pytest VectorCGRAKingMeshRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
```
`--test-verilog` is used to generate Verilog Code, `--dump-vtb` is used to generate the test bench, `--dump-vcd` is used to generate the Value Change Dump (VCD) file.
Note that the `--dump-vtb` need to be used with `--test-verilog`. `--dump-vcd` can be used without Verilog translation for different modules. For example, for [Tile testing](https://github.com/tancheng/VectorCGRA/tree/master/tile/test):
```
 % pytest --tb=short -sv TileRTL_test.py --dump-vcd
```

When you're done testing/developing, you can deactivate the virtualenv::

```
 % deactivate
```

Docker
--------------------------------------------------------
### Clone VectorCGRA repo
```shell
$ mkdir -p ${HOME}/cgra
$ cd ${HOME}/cgra
$ git clone https://github.com/tancheng/VectorCGRA.git
$ cd VectorCGRA/docker/
```

### Build Docker image
```shell
$ docker build -t vectorcgra:v1 .
```

### Run Docker container
```shell
$ docker run --name myvectorcgra vectorcgra:v1 &
$ docker exec -it myvectorcgra bash
```

### Run test in Docker container
```shell
root@host:/# source ${HOME}/venv/bin/activate
root@host:/# cd ${HOME}/cgra/VectorCGRA/build
(venv) root@host:~/cgra/VectorCGRA/build# pytest ../tile/test/TileRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd
```

Publication
--------------------------------------------------------
```
@inproceedings{tan2023vecpac,
  title={VecPAC: A Vectorizable and Precision-Aware CGRA},
  author={Tan, Cheng and Patil, Deepak and Tumeo, Antonino and Weisz, Gabriel and Reinhardt, Steve and Zhang, Jeff},
  booktitle={2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD)},
  year={2023},
  organization={IEEE}
}
```