# DesignCPU

**Repository Path**: caipb/DesignCPU

## Basic Information

- **Project Name**: DesignCPU
- **Description**: Design a computer model based on micro program CPU using Verilog HDL in MAXPLUSⅡ.
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2020-03-06
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# DesignCPU
Design a computer model based on microprogram CPU using Verilog HDL in MAXPLUSⅡ(But I recommend you to use Quartus)