From 337ba587eabd898e39267de1e6ec6925087ff02c Mon Sep 17 00:00:00 2001 From: AlanSong Date: Mon, 2 Mar 2026 16:02:25 +0800 Subject: [PATCH] Extension of OPENSSL_ia32cap to accommodate Padlock/GMI CPUID bits --- crypto/cpuid.c | 4 ++-- crypto/info.c | 5 +++-- crypto/perlasm/x86gas.pl | 2 +- crypto/perlasm/x86masm.pl | 2 +- crypto/perlasm/x86nasm.pl | 2 +- crypto/x86_64cpuid.pl | 34 +++++++++++++++++++++++++++++++++- crypto/x86cpuid.pl | 33 +++++++++++++++++++++++++++++++++ doc/man3/OPENSSL_ia32cap.pod | 24 ++++++++++++++++++++++++ 8 files changed, 98 insertions(+), 8 deletions(-) diff --git a/crypto/cpuid.c b/crypto/cpuid.c index 090f6fe03ec..c4a5fe10aa9 100644 --- a/crypto/cpuid.c +++ b/crypto/cpuid.c @@ -14,7 +14,7 @@ defined(__x86_64) || defined(__x86_64__) || \ defined(_M_AMD64) || defined(_M_X64) -extern unsigned int OPENSSL_ia32cap_P[4]; +extern unsigned int OPENSSL_ia32cap_P[5]; # if defined(OPENSSL_CPUID_OBJ) @@ -156,7 +156,7 @@ void OPENSSL_cpuid_setup(void) OPENSSL_ia32cap_P[1] = (unsigned int)(vec >> 32); } # else -unsigned int OPENSSL_ia32cap_P[4]; +unsigned int OPENSSL_ia32cap_P[5]; # endif #endif diff --git a/crypto/info.c b/crypto/info.c index a0dc2e80136..1d944026de6 100644 --- a/crypto/info.c +++ b/crypto/info.c @@ -44,11 +44,12 @@ DEFINE_RUN_ONCE_STATIC(init_info_strings) const char *env; BIO_snprintf(ossl_cpu_info_str, sizeof(ossl_cpu_info_str), - CPUINFO_PREFIX "OPENSSL_ia32cap=0x%llx:0x%llx", + CPUINFO_PREFIX "OPENSSL_ia32cap=0x%llx:0x%llx:0x%lx", (unsigned long long)OPENSSL_ia32cap_P[0] | (unsigned long long)OPENSSL_ia32cap_P[1] << 32, (unsigned long long)OPENSSL_ia32cap_P[2] | - (unsigned long long)OPENSSL_ia32cap_P[3] << 32); + (unsigned long long)OPENSSL_ia32cap_P[3] << 32, + (unsigned long)OPENSSL_ia32cap_P[4]); if ((env = getenv("OPENSSL_ia32cap")) != NULL) BIO_snprintf(ossl_cpu_info_str + strlen(ossl_cpu_info_str), sizeof(ossl_cpu_info_str) - strlen(ossl_cpu_info_str), diff --git a/crypto/perlasm/x86gas.pl b/crypto/perlasm/x86gas.pl index 1b2b27c0228..817ac197be3 100644 --- a/crypto/perlasm/x86gas.pl +++ b/crypto/perlasm/x86gas.pl @@ -167,7 +167,7 @@ sub ::file_end } } if (grep {/\b${nmdecor}OPENSSL_ia32cap_P\b/i} @out) { - my $tmp=".comm\t${nmdecor}OPENSSL_ia32cap_P,16"; + my $tmp=".comm\t${nmdecor}OPENSSL_ia32cap_P,20"; if ($::macosx) { push (@out,"$tmp,2\n"); } elsif ($::elf) { push (@out,"$tmp,4\n"); } else { push (@out,"$tmp\n"); } diff --git a/crypto/perlasm/x86masm.pl b/crypto/perlasm/x86masm.pl index 2dcd3f79f6e..a28ed80bb70 100644 --- a/crypto/perlasm/x86masm.pl +++ b/crypto/perlasm/x86masm.pl @@ -141,7 +141,7 @@ ___ if (grep {/\b${nmdecor}OPENSSL_ia32cap_P\b/i} @out) { my $comm=<<___; .bss SEGMENT 'BSS' -COMM ${nmdecor}OPENSSL_ia32cap_P:DWORD:4 +COMM ${nmdecor}OPENSSL_ia32cap_P:DWORD:5 .bss ENDS ___ # comment out OPENSSL_ia32cap_P declarations diff --git a/crypto/perlasm/x86nasm.pl b/crypto/perlasm/x86nasm.pl index 7017b88e80a..cdcbe5e2c36 100644 --- a/crypto/perlasm/x86nasm.pl +++ b/crypto/perlasm/x86nasm.pl @@ -126,7 +126,7 @@ sub ::file_end { if (grep {/\b${nmdecor}OPENSSL_ia32cap_P\b/i} @out) { my $comm=<<___; ${drdecor}segment .bss -${drdecor}common ${nmdecor}OPENSSL_ia32cap_P 16 +${drdecor}common ${nmdecor}OPENSSL_ia32cap_P 20 ___ # comment out OPENSSL_ia32cap_P declarations grep {s/(^extern\s+${nmdecor}OPENSSL_ia32cap_P)/\;$1/} @out; diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl index 53685ec2639..957ae93e845 100644 --- a/crypto/x86_64cpuid.pl +++ b/crypto/x86_64cpuid.pl @@ -33,7 +33,7 @@ print<<___; call OPENSSL_cpuid_setup .hidden OPENSSL_ia32cap_P -.comm OPENSSL_ia32cap_P,16,4 +.comm OPENSSL_ia32cap_P,20,4 .text @@ -93,6 +93,28 @@ OPENSSL_ia32_cpuid: or %eax,%r9d # 0 indicates Intel CPU jz .Lintel + cmp \$0x746E6543,%ebx # "Cent" + setne %al + mov %eax,%esi + cmp \$0x48727561,%edx # "aurH" + setne %al + or %eax,%esi + cmp \$0x736C7561,%ecx # "auls" + setne %al + or %eax,%esi # 0 indicates Zhaoxin CPU + jz .Lzhaoxin + + cmp \$0x68532020,%ebx # " Sh" + setne %al + mov %eax,%esi + cmp \$0x68676E61,%edx # "angh" + setne %al + or %eax,%esi + cmp \$0x20206961,%ecx # "ai " + setne %al + or %eax,%esi # 0 indicates Zhaoxin CPU + jz .Lzhaoxin + cmp \$0x68747541,%ebx # "Auth" setne %al mov %eax,%r10d @@ -133,6 +155,16 @@ OPENSSL_ia32_cpuid: and \$0xefffffff,%edx # ~(1<<28) jmp .Lgeneric +.Lzhaoxin: + mov \$0xC0000000,%eax + cpuid + cmp \$0xC0000001,%eax + jb .Lintel + mov \$0xC0000001,%eax + cpuid + or \$0x10,%edx + mov %edx,16(%rdi) + .Lintel: cmp \$4,%r11d mov \$-1,%r10d diff --git a/crypto/x86cpuid.pl b/crypto/x86cpuid.pl index a7bcb27e262..f5506fef6a2 100644 --- a/crypto/x86cpuid.pl +++ b/crypto/x86cpuid.pl @@ -47,6 +47,28 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } &or ("ebp","eax"); # 0 indicates Intel CPU &jz (&label("intel")); + &cmp ("ebx",0x746E6543); # "Cent" + &setne (&LB("eax")); + &mov ("esi","eax"); + &cmp ("edx",0x48727561); # "aurH" + &setne (&LB("eax")); + &or ("esi","eax"); + &cmp ("ecx",0x736C7561); # "auls" + &setne (&LB("eax")); + &or ("esi","eax"); # 0 indicates Zhaoxin CPU + &jz (&label("zhaoxin")); + + &cmp ("ebx",0x68532020); # " Sh" + &setne (&LB("eax")); + &mov ("esi","eax"); + &cmp ("edx",0x68676E61); # "angh" + &setne (&LB("eax")); + &or ("esi","eax"); + &cmp ("ecx",0x20206961); # "ai " + &setne (&LB("eax")); + &or ("esi","eax"); # 0 indicates Zhaoxin CPU + &jz (&label("zhaoxin")); + &cmp ("ebx",0x68747541); # "Auth" &setne (&LB("eax")); &mov ("esi","eax"); @@ -88,6 +110,17 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } &and ("edx",0xefffffff); # clear hyper-threading bit &jmp (&label("generic")); +&set_label("zhaoxin"); + &mov ("eax",0xC0000000); + &cpuid (); + &cmp ("eax",0xC0000001); + &jb (&label("intel")); + &mov ("eax",0xC0000001); + &cpuid (); + &or ("edx",1<<4); + &mov ("esi",&wparam(0)); + &mov (&DWP(16,"esi"),"edx"); + &set_label("intel"); &cmp ("edi",4); &mov ("esi",-1); diff --git a/doc/man3/OPENSSL_ia32cap.pod b/doc/man3/OPENSSL_ia32cap.pod index c6c1c0185ad..58edd39357a 100644 --- a/doc/man3/OPENSSL_ia32cap.pod +++ b/doc/man3/OPENSSL_ia32cap.pod @@ -118,6 +118,30 @@ aka AVX512IFMA extension; =back +=over 4 + +=item bit #128 denoting present of SM2 instruction; + +=item bit #128+1 denoting enabled of SM2 instruction; + +=item bit #128+4 denoting present of CCS extension; + +=item bit #128+5 denoting enabled of CCS extension; + +=item bit #128+6 denoting present of ACE extension; + +=item bit #128+7 denoting enabled of ACE extension; + +=item bit #128+10 denoting present of PHE extension; + +=item bit #128+11 denoting enabled of PHE extension; + +=item bit #128+25 denoting present of PHE2 extension; + +=item bit #128+26 denoting enabled of PHE2 extension; + +=back + To control this extended capability word use C<:> as delimiter when setting up B environment variable. For example assigning C<:~0x20> would disable AVX2 code paths, and C<:0> - all post-AVX -- Gitee