From 1e9d5799ccde374346d49162e79fddb45f35ccd0 Mon Sep 17 00:00:00 2001 From: zhangjun Date: Thu, 18 Jun 2026 11:11:43 +0800 Subject: [PATCH] cpu vulnerabilities: Software changes are required for the MSR 0xC001102E modifications. ANBZ: #38123 Corresponding software changes are required for the modifications to bits 55 and 56 in MSR 0xC001102E, as these bits are relocated to bits 59 and 60 for processor models newer than 0x6. Signed-off-by: zhangjun --- arch/x86/kernel/cpu/bugs.c | 23 +++++++++++++++++------ arch/x86/kernel/cpu/hygon.c | 8 ++++++-- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index bff0ea7d35d7..cdabe380de67 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1376,8 +1376,11 @@ static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_ case SPECTRE_V2_EIBRS_RETPOLINE: /* Hygon Enhanced IBRS flushes RAS upon privilege level changes from low to high. */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) - return; + if (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) { + setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT); + pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n"); + } + return; case SPECTRE_V2_RETPOLINE: case SPECTRE_V2_LFENCE: case SPECTRE_V2_IBRS: @@ -2083,7 +2086,8 @@ static int __init ibpb_brtype_cmdline(char *str) } early_param("ibpb_brtype", ibpb_brtype_cmdline); -#define IBPB_FLUSH_ALL_BIT 55 +#define MODEL_4_IBPB_FLUSH_ALL_BIT 55 +#define MODEL_7_IBPB_FLUSH_ALL_BIT 59 void x86_spec_ctrl_setup_ap(void) { @@ -2096,8 +2100,12 @@ void x86_spec_ctrl_setup_ap(void) if ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 == 0x18)) { if ((boot_cpu_data.x86_model > 0x3) && - (ibpb_brtype == IBPB_FLUSH_ALL)) - msr_set_bit(MSR_ZEN4_BP_CFG, IBPB_FLUSH_ALL_BIT); + (ibpb_brtype == IBPB_FLUSH_ALL)) { + if (boot_cpu_data.x86_model < 0x7) + msr_set_bit(MSR_ZEN4_BP_CFG, MODEL_4_IBPB_FLUSH_ALL_BIT); + else + msr_set_bit(MSR_ZEN4_BP_CFG, MODEL_7_IBPB_FLUSH_ALL_BIT); + } } } @@ -2295,7 +2303,10 @@ bool ibpb_can_flush_all(void) if (boot_cpu_data.x86_model <= 0x3) { return true; } else if (ibpb_brtype == IBPB_FLUSH_ALL) { - msr_set_bit(MSR_ZEN4_BP_CFG, IBPB_FLUSH_ALL_BIT); + if (boot_cpu_data.x86_model < 0x7) + msr_set_bit(MSR_ZEN4_BP_CFG, MODEL_4_IBPB_FLUSH_ALL_BIT); + else + msr_set_bit(MSR_ZEN4_BP_CFG, MODEL_7_IBPB_FLUSH_ALL_BIT); return true; } return false; diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 0959269727c2..4c688c66985b 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -24,7 +24,8 @@ #include "cpu.h" -#define IBRS_FLUSH_RAS_BIT 56 +#define MODEL_4_IBRS_FLUSH_RAS_BIT 56 +#define MODEL_7_IBRS_FLUSH_RAS_BIT 60 #define APICID_SOCKET_ID_BIT 6 /* @@ -342,7 +343,10 @@ static void cpu_vul_mitigation(void) */ if ((boot_cpu_data.x86 == 0x18) && (boot_cpu_data.x86_model > 0x3)) { - msr_set_bit(MSR_ZEN4_BP_CFG, IBRS_FLUSH_RAS_BIT); + if (boot_cpu_data.x86_model < 0x7) + msr_set_bit(MSR_ZEN4_BP_CFG, MODEL_4_IBRS_FLUSH_RAS_BIT); + else + msr_set_bit(MSR_ZEN4_BP_CFG, MODEL_7_IBRS_FLUSH_RAS_BIT); } } -- Gitee