# Five Stages Pipeline RISCV Processor

**Repository Path**: aheck/risc-v-learning

## Basic Information

- **Project Name**: Five Stages Pipeline RISCV Processor
- **Description**: risc-v架构五级流水线cpu，完成基本功能
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 3
- **Forks**: 0
- **Created**: 2024-04-02
- **Last Updated**: 2025-08-09

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# RV32IM 5 stages pipeline CPU

## 指令支持情况

PASS: add, addi, and, andi, auipc, beq, bge, bgeu, blt, bltu, bne, jal, jalr, lb, lbu, lh, lhu, lui, lw, or, ori, sb, sh, simple, sll, slli, slt, slti, sltiu, sltu, sra, srai, srl, srli, sub, sw, xor, xori, csrrw, csrrs, csrrc, csrrwi, csrrsi,csrrci, ecall, ebreak, mret


## 测试脚本

需要安装iverilog和python环境。

点击sim文件夹的test.bat即可仿真。

![芜湖](./img/test_img0.png)