diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 423258a3f0dfe7b5b64d56d16cce84b196a79bf0..67fde196860f30b25f96304df1051571da7cf72f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -110,6 +110,11 @@ static u32 get_umc_base_f18h_m4h(u16 node, u8 channel)
 	return get_umc_base(channel) + (0x80000000 + (0x10000000 * df_id));
 }
 
+static u32 get_umc_base_f18h_m18h(u8 channel)
+{
+	return 0x70000000 + (channel << 20);
+}
+
 /*
  * Select DCT to which PCI cfg accesses are routed
  */
@@ -1310,6 +1315,8 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
 
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
+		else if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18)
+			umc_base = get_umc_base_f18h_m18h(i);
 		else
 			umc_base = get_umc_base(i);
 		umc = &pvt->umc[i];
@@ -1437,6 +1444,8 @@ static void read_umc_base_mask(struct amd64_pvt *pvt)
 
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, umc);
+		else if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18)
+			umc_base = get_umc_base_f18h_m18h(umc);
 		else
 			umc_base = get_umc_base(umc);
 
@@ -2973,6 +2982,8 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt)
 
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
+		else if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18)
+			umc_base = get_umc_base_f18h_m18h(i);
 		else
 			umc_base = get_umc_base(i);
 
@@ -3662,6 +3673,13 @@ static int per_family_init(struct amd64_pvt *pvt)
                         pvt->ctl_name                   = "F18h_M10h";
                         pvt->max_mcs                    = 2;
                         break;
+		case 0x18:
+			pvt->ctl_name			= "F18h_M18h";
+			pvt->max_mcs			= 1;
+			break;
+ 		default:
+ 			pvt->ctl_name			= "F18h";
+ 			break;
                 }
 		break;