From fd38777627e3325d520db7de54dd190d941b8059 Mon Sep 17 00:00:00 2001 From: jia_kongfeng Date: Fri, 8 May 2026 17:47:31 +0800 Subject: [PATCH 1/2] =?UTF-8?q?drm=E6=98=BE=E7=A4=BA=E6=A1=86=E6=9E=B6?= =?UTF-8?q?=E9=80=82=E9=85=8Dhdmi=20audio=20player?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: jia_kongfeng --- .../common/hal/media/audio/source/Makefile | 1 + .../audio/source/plugins/hi35xx/Makefile | 1 + .../audio_primary_sub_port_out.c | 82 +- .../audio_usb_port_plugin.c | 6 +- .../audio_usb_sub_port_in.c | 4 +- .../audio_usb_sub_port_out.c | 4 +- .../media/audio/source/src/audio_adapter.c | 56 + .../hal/media/audio/source/src/audio_render.c | 62 +- .../0004-kernel-drm-driver-support.patch | 61115 ++++++++++++++++ .../0004-kernel-drm-support.patch | 60739 --------------- .../patch_hispark_aifly.sh | 1 + .../media_lite/media_lite_002.patch | 247 +- .../third_party/alsa-lib/alsa-lib_001.patch | 166 +- 13 files changed, 61618 insertions(+), 60866 deletions(-) create mode 100755 os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-driver-support.patch diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/Makefile b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/Makefile index 76b68523..1cb77535 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/Makefile +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/Makefile @@ -37,6 +37,7 @@ ifneq ($(strip $(CreateResult)),) endif CFLAGS_CUR := $(CFLAGS) -fdata-sections -fno-omit-frame-pointer -DENABLE_DL_AUDIO_PLUGIN +CFLAGS_CUR += -DDRM_AUDIO_OPTION_ENABLE LDFLAGS_SO := $(LDFLAGS) SRC_DEPS_LIB += -lsecurec -lpthread -ldl -lm -lmedia_hal_common diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/Makefile b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/Makefile index 8830c561..ad98ffe5 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/Makefile +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/Makefile @@ -54,6 +54,7 @@ LDFLAGS_SO := $(LDFLAGS) ifeq ($(filter $(CFG_CHIP_TYPE),hi3403v100),$(CFG_CHIP_TYPE)) CFLAGS_CUR += -D__SS626V100__ -D__LINUX__ +CFLAGS_CUR += -DDRM_AUDIO_OPTION_ENABLE SRC_DEPS_LIB += -lmedia_hal_common -lss_mpi -lsecurec -lpthread -ldl -lm -lmwlog -lotconfaccess -laac_sbr_enc -laac_sbr_dec -lvqe_record -lvqe_res -lss_otp else SRC_DEPS_LIB += -lmedia_hal_common -lss_mpi_audio -lsecurec -lpthread -ldl -lm -lmwlog -lotconfaccess -lss_mpi_audio_adp -lopus -laac_sbr_enc -laac_sbr_dec -lmp3_dec -lmp3_enc -lvqe_record -lvqe_res diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/audio_primary_sub_port_out/audio_primary_sub_port_out.c b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/audio_primary_sub_port_out/audio_primary_sub_port_out.c index 607d9d67..77a61e48 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/audio_primary_sub_port_out/audio_primary_sub_port_out.c +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/audio_primary_sub_port_out/audio_primary_sub_port_out.c @@ -18,6 +18,14 @@ #include #include +#ifdef DRM_AUDIO_OPTION_ENABLE +#include +#include +#include +#include +#include +#include +#endif #ifndef __HuaweiLite__ #include #endif @@ -48,7 +56,15 @@ extern "C" { #define TIME_S_TO_US_SCALE 1000000 #define TIME_US_TO_NS_SCALE 1000 #define NO_WAIT 0 - +#ifdef DRM_AUDIO_OPTION_ENABLE +#define DRM_IOCTL_BASE 'd' +#define DRM_COMMAND_BASE 0x40 +#define DRM_HI3403V100_AUDIO_SET_CONFIG 2 +#define SMART_DRM_AUDIO_DEFAULT_TMDS_CLK 148500 +#define SMART_DRM_AUDIO_BIT_DEPTH_16 16 +#define SMART_DRM_AUDIO_INTF_I2S 0 +#define SMART_DRM_CARD_PATH "/dev/dri/card0" +#endif #define AUDIO_VQE_AGC_NOISE_FLOOR (-50) #define AUDIO_VQE_AGC_TARGET_LEVEL (-40) #define AUDIO_VQE_ANR_NOISE_DB_THR 30 @@ -89,6 +105,23 @@ struct AudioSubPortOutMng { struct AudioSubPortOut *hwOutputPort; }; +#ifdef DRM_AUDIO_OPTION_ENABLE +struct SmartDrmAudioFrame { + uint32_t enable; + uint32_t sampleRate; + uint32_t bitDepth; + uint32_t channels; + uint32_t soundIntf; + uint32_t tmdsClk; + uint64_t pcmAddr; + uint32_t pcmBytes; + uint32_t reserved; +}; + +#define DRM_IOCTL_HI3403V100_AUDIO_SET_CONFIG \ + _IOWR(DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_HI3403V100_AUDIO_SET_CONFIG, struct SmartDrmAudioFrame) +#endif + static struct AudioSubPortOutMng g_audioHwOutputPorts[MAX_OUTPUT_PORT_CNT]; static bool g_audioOutputMngInited = false; static pthread_mutex_t g_audioOutputMngLock = PTHREAD_MUTEX_INITIALIZER; @@ -210,6 +243,38 @@ int32_t AudioPrimarySubPortOutGetCapability(const struct AudioPort *port, return MEDIA_HAL_OK; } +#ifdef DRM_AUDIO_OPTION_ENABLE +static int32_t AudioHdmiPathIoctlSet(bool enable, const struct PortPluginAttr *portAttr) +{ + struct SmartDrmAudioFrame frame = { + .enable = enable ? 1 : 0, + .sampleRate = portAttr != NULL ? portAttr->sampleRate : 0, + .bitDepth = SMART_DRM_AUDIO_BIT_DEPTH_16, + .channels = portAttr != NULL ? portAttr->channelCount : AUDIO_STEREO_SOUND_MODE_CHN_CNT, + .soundIntf = SMART_DRM_AUDIO_INTF_I2S, + .tmdsClk = SMART_DRM_AUDIO_DEFAULT_TMDS_CLK, + }; + int32_t fd; + int32_t ret; + + fd = open(SMART_DRM_CARD_PATH, O_RDWR | O_CLOEXEC); + if (fd < 0) { + MEDIA_HAL_LOGE(MODULE_NAME, "open %s failed, errno:%d(%s)", SMART_DRM_CARD_PATH, errno, strerror(errno)); + return MEDIA_HAL_ERR; + } + + ret = ioctl(fd, DRM_IOCTL_HI3403V100_AUDIO_SET_CONFIG, &frame); + if (ret < 0) { + MEDIA_HAL_LOGE(MODULE_NAME, "DRM audio ioctl failed, errno:%d(%s)", errno, strerror(errno)); + close(fd); + return MEDIA_HAL_ERR; + } + + close(fd); + return MEDIA_HAL_OK; +} +#endif + static int32_t AoInit(ot_audio_dev aoDeviceId, ot_aio_attr *aoAttr) { int32_t ret = ss_mpi_ao_set_pub_attr(aoDeviceId, aoAttr); @@ -286,12 +351,24 @@ static int32_t ConfigAndEnableAO( } ot_aio_attr aoAttr = hwPortCtx->aoSourceAttr; if (audioPortPin == PIN_OUT_HDMI) { +#ifdef DRM_AUDIO_OPTION_ENABLE + ret = AudioHdmiPathIoctlSet(true, portAttr); + if (ret != MEDIA_HAL_OK) { + MEDIA_HAL_LOGE(MODULE_NAME, "enable HDMI audio path by DRM ioctl failed"); + return ret; + } +#endif ret = AoInit(hwPortCtx->aoHDMIDeviceId, &aoAttr); } else if (audioPortPin == PIN_OUT_SPEAKER) { ret = AoInit(hwPortCtx->aoDeviceId, &aoAttr); } if (ret != MEDIA_HAL_OK) { MEDIA_HAL_LOGE(MODULE_NAME, "AoInit failed %#x", ret); + if (audioPortPin == PIN_OUT_HDMI) { +#ifdef DRM_AUDIO_OPTION_ENABLE + (void)AudioHdmiPathIoctlSet(false, portAttr); +#endif + } return ret; } hwPortCtx->aoEnabled = true; @@ -348,6 +425,9 @@ int32_t AudioPrimarySubPortOutClose(AudioHandle portHandle) if (ret != MEDIA_HAL_OK) { MEDIA_HAL_LOGE(MODULE_NAME, "aoHDMIDeviceId ss_mpi_ao_disable fail,ret:0x%x", ret); } +#ifdef DRM_AUDIO_OPTION_ENABLE + (void)AudioHdmiPathIoctlSet(false, NULL); +#endif hwPortCtx->aoEnabled = false; } ret = AudioOutputPortMngFreeChn(hwPortCtx->aoDeviceId); diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_port_plugin/audio_usb_port_plugin.c b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_port_plugin/audio_usb_port_plugin.c index 8b2e2b55..678de49f 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_port_plugin/audio_usb_port_plugin.c +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_port_plugin/audio_usb_port_plugin.c @@ -74,7 +74,7 @@ int IsUsbAudioDevice(const char *cardDir) FILE *usbbusFile; int snprintfRet = snprintf_s(usbbusPath, sizeof(usbbusPath), sizeof(usbbusPath) - 1, "%s/usbbus", cardDir); - if (snprintfRet != 0) { + if (snprintfRet < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed"); return 0; } @@ -99,7 +99,7 @@ static bool CheckDeviceExists(int card, const char *deviceStr) cardDir, sizeof(cardDir), sizeof(cardDir) - 1, "/proc/asound/card%d/%s/sub0", card, deviceStr); - if (ret != 0) { + if (ret < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed to format cardDir"); return false; } @@ -136,7 +136,7 @@ int ListUsbAudioDevices(int *cardNum, const char *deviceStr) } int32_t ret = snprintf_s(cardDir, sizeof(cardDir), sizeof(cardDir) - 1, "/proc/asound/%s", entry->d_name); - if (ret != 0) { + if (ret < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed to format cardDir"); continue; } diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_in/audio_usb_sub_port_in.c b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_in/audio_usb_sub_port_in.c index 3f49386f..60e8c2fa 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_in/audio_usb_sub_port_in.c +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_in/audio_usb_sub_port_in.c @@ -446,7 +446,7 @@ static int32_t ConfigureAndOpenPcm(SubPortInContext *portInCtx, int card_usb) { char pcmDevice[32]; int snprintfRet = snprintf_s(pcmDevice, sizeof(pcmDevice), sizeof(pcmDevice) - 1, "hw:%d,0", card_usb); - if (snprintfRet != 0) { + if (snprintfRet < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed"); return MEDIA_HAL_ERR; } @@ -467,7 +467,7 @@ static int32_t ConfigureAndOpenMixer(SubPortInContext *portInCtx, int card_usb) } char ctlDevice[32]; int snprintfRet = snprintf_s(ctlDevice, sizeof(ctlDevice), sizeof(ctlDevice) - 1, "hw:%d", card_usb); - if (snprintfRet != 0) { + if (snprintfRet < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed"); snd_mixer_close(portInCtx->ai_mixer_handle); return MEDIA_HAL_ERR; diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_out/audio_usb_sub_port_out.c b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_out/audio_usb_sub_port_out.c index ad42e02e..0a82fd0e 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_out/audio_usb_sub_port_out.c +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/plugins/usb/audio_usb_sub_port_out/audio_usb_sub_port_out.c @@ -293,7 +293,7 @@ static int32_t InitMixerAndVolumeControl(struct AudioSubPortOut *hwOutputPort, i } char ctlDevice[32]; int snprintfRet = snprintf_s(ctlDevice, sizeof(ctlDevice), sizeof(ctlDevice) - 1, "hw:%d", card_usb); - if (snprintfRet != 0) { + if (snprintfRet < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed"); snd_mixer_close(hwOutputPort->ao_mixer_handle); return MEDIA_HAL_ERR; @@ -362,7 +362,7 @@ int32_t AudioUsbSubPortOutOpen(AudioHandle *portHandle, int card_usb) hwOutputPort->aoDeviceId = portIndex; char pcmDevice[32]; int snprintfRet = snprintf_s(pcmDevice, sizeof(pcmDevice), sizeof(pcmDevice) - 1, "hw:%d,0", card_usb); - if (snprintfRet != 0) { + if (snprintfRet < 0) { MEDIA_HAL_LOGE(MODULE_NAME, "snprintf_s failed"); return MEDIA_HAL_ERR; } diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_adapter.c b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_adapter.c index 426a1f18..0ebfaa58 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_adapter.c +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_adapter.c @@ -15,9 +15,19 @@ */ #include +#ifdef DRM_AUDIO_OPTION_ENABLE +#include +#include +#include +#include +#include +#include +#endif #include "audio_internal.h" #include "audio_port_plugin.h" #include "audio_adapter.h" + +#ifndef DRM_AUDIO_OPTION_ENABLE #define ENABLE_H8 #if defined(ENABLE_H8) #include "ot_common_hdmi.h" @@ -26,9 +36,27 @@ #include "hi_comm_hdmi.h" #include "mpi_hdmi.h" #endif +#endif #define CONFIG_CHANNEL_COUNT 2 // two channels +#ifdef DRM_AUDIO_OPTION_ENABLE +#define DRM_IOCTL_BASE 'd' +#define DRM_COMMAND_BASE 0x40 +#define DRM_HI3403V100_HDMI_GET_SINK_STATUS 3 +#define SMART_DRM_CARD_PATH "/dev/dri/card0" + +struct SmartDrmHdmiSinkStatus { + uint32_t connected; + uint32_t sinkHasAudio; + uint32_t connectorStatus; + uint32_t reserved; +}; + +#define DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS \ + _IOWR(DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_HI3403V100_HDMI_GET_SINK_STATUS, struct SmartDrmHdmiSinkStatus) +#endif + static int32_t AudioAdapterInitPortCapability(const struct AudioHwAdapter *hwAdapter) { CHK_NULL_RETURN(hwAdapter->capability, MEDIA_HAL_INVALID_PARAM, "Input param capability is null"); @@ -208,6 +236,33 @@ static int32_t AudioAdapterFreeChn(struct AudioAdapter *adapter, uint32_t chnId, static int32_t CheckHdmiStatus(void) { +#ifdef DRM_AUDIO_OPTION_ENABLE + struct SmartDrmHdmiSinkStatus sinkStatus = {}; + int32_t fd; + int32_t ret; + + fd = open(SMART_DRM_CARD_PATH, O_RDWR | O_CLOEXEC); + if (fd < 0) { + MEDIA_HAL_LOGE(MODULE_NAME, "open %s failed, errno:%d(%s)", SMART_DRM_CARD_PATH, errno, strerror(errno)); + return false; + } + + ret = ioctl(fd, DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS, &sinkStatus); + if (ret < 0) { + MEDIA_HAL_LOGE(MODULE_NAME, "DRM HDMI sink status ioctl failed, errno:%d(%s)", errno, strerror(errno)); + close(fd); + return false; + } + close(fd); + + if (sinkStatus.connected) { + MEDIA_HAL_LOGI(MODULE_NAME, "HDMI is connected by DRM"); + return true; + } + + MEDIA_HAL_LOGI(MODULE_NAME, "HDMI is not connected by DRM"); + return false; +#else ot_hdmi_sink_capability sinkCap = {0}; int32_t ret = MEDIA_HAL_OK; @@ -224,6 +279,7 @@ static int32_t CheckHdmiStatus(void) MEDIA_HAL_LOGE(MODULE_NAME, "Failed to get HDMI sink capability, ret=%d", ret); return false; } +#endif } static void SetupRenderFunctionPointers(struct AudioHwRender *hwRender) diff --git a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_render.c b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_render.c index b697efc5..61d5d09f 100644 --- a/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_render.c +++ b/os/OpenHarmony/device/soc/hisilicon/common/hal/media/audio/source/src/audio_render.c @@ -16,8 +16,18 @@ #include #include +#ifdef DRM_AUDIO_OPTION_ENABLE +#include +#include +#include +#include +#include +#include +#endif #include "audio_internal.h" #include "audio_port_plugin.h" + +#ifndef DRM_AUDIO_OPTION_ENABLEn #define ENABLE_H8 #if defined(ENABLE_H8) #include "ot_common_hdmi.h" @@ -26,11 +36,27 @@ #include "hi_comm_hdmi.h" #include "mpi_hdmi.h" #endif +#endif #define CONFIG_OUT_LATENCY_MS 100 // unit: ms #define CONFIG_HDMI_OUT_CONNECT 200 #define CONFIG_HDMI_OUT_DISCONNECT 201 - +#ifdef DRM_AUDIO_OPTION_ENABLE +#define DRM_IOCTL_BASE 'd' +#define DRM_COMMAND_BASE 0x40 +#define DRM_HI3403V100_HDMI_GET_SINK_STATUS 3 +#define SMART_DRM_CARD_PATH "/dev/dri/card0" + +struct SmartDrmHdmiSinkStatus { + uint32_t connected; + uint32_t sinkHasAudio; + uint32_t connectorStatus; + uint32_t reserved; +}; + +#define DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS \ + _IOWR(DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_HI3403V100_HDMI_GET_SINK_STATUS, struct SmartDrmHdmiSinkStatus) +#endif // 1 buffer: 8000(8kHz sample rate) * 2(bytes, PCM_16_BIT) * 1(channel) // 1 frame: 1024(sample) * 2(bytes, PCM_16_BIT) * 1(channel) @@ -448,6 +474,26 @@ int32_t AudioRenderGetRenderSpeed(struct AudioRender *render, float *speed) MEDIA_HAL_LOCK(hwRender->mutex); *speed = hwRender->speed; +#ifdef DRM_AUDIO_OPTION_ENABLE + struct SmartDrmHdmiSinkStatus sinkStatus = {}; + int32_t fd = open(SMART_DRM_CARD_PATH, O_RDWR | O_CLOEXEC); + if (fd < 0) { + MEDIA_HAL_LOGE(MODULE_NAME, "open %s failed, errno:%d(%s)", SMART_DRM_CARD_PATH, errno, strerror(errno)); + MEDIA_HAL_UNLOCK(hwRender->mutex); + return MEDIA_HAL_OK; + } + + int32_t ret = ioctl(fd, DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS, &sinkStatus); + if (ret < 0) { + MEDIA_HAL_LOGE(MODULE_NAME, "DRM HDMI sink status ioctl failed, errno:%d(%s)", errno, strerror(errno)); + close(fd); + MEDIA_HAL_UNLOCK(hwRender->mutex); + return MEDIA_HAL_OK; + } + close(fd); + + if (sinkStatus.connected) { +#else ot_hdmi_sink_capability sinkCap = {0}; int32_t ret = MEDIA_HAL_OK; MEDIA_HAL_LOGI(MODULE_NAME, "ss_mpi_hdmi_get_sink_capability enter"); @@ -455,15 +501,13 @@ int32_t AudioRenderGetRenderSpeed(struct AudioRender *render, float *speed) ret = ss_mpi_hdmi_get_sink_capability(OT_HDMI_ID_0, &sinkCap); if (ret == MEDIA_HAL_OK) { if (sinkCap.is_connected) { - MEDIA_HAL_LOGI(MODULE_NAME, "HDMI is connected"); - - *speed = CONFIG_HDMI_OUT_CONNECT; - } else { - MEDIA_HAL_LOGI(MODULE_NAME, "HDMI is not connected"); - *speed = CONFIG_HDMI_OUT_DISCONNECT; - } +#endif + MEDIA_HAL_LOGI(MODULE_NAME, "HDMI is connected"); + *speed = CONFIG_HDMI_OUT_CONNECT; + } else { + MEDIA_HAL_LOGI(MODULE_NAME, "HDMI is not connected"); + *speed = CONFIG_HDMI_OUT_DISCONNECT; } - MEDIA_HAL_LOGI(MODULE_NAME, "ss_mpi_hdmi_get_sink_capability after"); MEDIA_HAL_UNLOCK(hwRender->mutex); return MEDIA_HAL_OK; diff --git a/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-driver-support.patch b/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-driver-support.patch new file mode 100755 index 00000000..12d78d2e --- /dev/null +++ b/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-driver-support.patch @@ -0,0 +1,61115 @@ +diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig +index cc5a244db..6c34adda9 100644 +--- a/drivers/gpu/drm/hisilicon/Kconfig ++++ b/drivers/gpu/drm/hisilicon/Kconfig +@@ -5,3 +5,4 @@ + + source "drivers/gpu/drm/hisilicon/hibmc/Kconfig" + source "drivers/gpu/drm/hisilicon/kirin/Kconfig" ++source "drivers/gpu/drm/hisilicon/smart_vision/Kconfig" +diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile +index 69dec6084..26b3a4d86 100644 +--- a/drivers/gpu/drm/hisilicon/Makefile ++++ b/drivers/gpu/drm/hisilicon/Makefile +@@ -5,3 +5,4 @@ + + obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc/ + obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/ ++obj-$(CONFIG_DRM_HISI_SMART_VISION) += smart_vision/ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/Kconfig b/drivers/gpu/drm/hisilicon/smart_vision/Kconfig +new file mode 100755 +index 000000000..2b466eeb7 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/Kconfig +@@ -0,0 +1,12 @@ ++config DRM_HISI_SMART_VISION ++ tristate "DRM support for SMART VISION Graphics" ++ depends on DRM && OF ++ select DRM_KMS_HELPER ++ select DRM_DISPLAY_HELPER ++ select DRM_DISPLAY_DP_HELPER ++ select DRM_DISPLAY_HDCP_HELPER ++ select DRM_DISPLAY_HDMI_HELPER ++ select DRM_GEM_DMA_HELPER ++ help ++ Choose this option if you have a Unisoc chipset. ++ If M is selected the module will be called smart_drm. +\ No newline at end of file +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/Makefile b/drivers/gpu/drm/hisilicon/smart_vision/Makefile +new file mode 100755 +index 000000000..b9f501be3 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/Makefile +@@ -0,0 +1,26 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ccflags-y := -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100 ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include ++ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100 ++ ++ ++ ++smart_drm-y := \ ++ smart_drm_drv.o \ ++ hi3403v100/hdmi_product_define.o \ ++ hi3403v100/regs/hdmi_reg_crg.o \ ++ ctrl/v100/regs/hdmi_reg_aon.o \ ++ ctrl/v100/regs/hdmi_reg_audio_path.o \ ++ ctrl/v100/regs/hdmi_reg_ctrl.o \ ++ ctrl/v100/regs/hdmi_reg_tx.o \ ++ ctrl/v100/regs/hdmi_reg_video_path.o \ ++ phy/v200/regs/hdmi_reg_dphy.o \ ++ smart_vo.o \ ++ smart_hdmi.o ++ ++obj-$(CONFIG_DRM_HISI_SMART_VISION) += smart_drm.o +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100/ot_defines.h b/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100/ot_defines.h +new file mode 100755 +index 000000000..01a0b4616 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100/ot_defines.h +@@ -0,0 +1,42 @@ ++ ++/* For VO */ ++#define OT_VO_MAX_PHYS_DEV_NUM 2 /* max physical dev num */ ++#define OT_VO_MAX_VIRT_DEV_NUM 32 /* max virtual dev num */ ++#define OT_VO_MAX_CAS_DEV_NUM 0 /* max cascade dev num */ ++/* max dev num */ ++#define OT_VO_MAX_DEV_NUM (OT_VO_MAX_PHYS_DEV_NUM + OT_VO_MAX_VIRT_DEV_NUM + OT_VO_MAX_CAS_DEV_NUM) ++ ++#define OT_VO_VIRT_DEV_0 2 /* virtual device 0 */ ++#define OT_VO_VIRT_DEV_1 3 /* virtual device 1 */ ++#define OT_VO_VIRT_DEV_2 4 /* virtual device 2 */ ++#define OT_VO_VIRT_DEV_3 5 /* virtual device 3 */ ++ ++#define OT_VO_MAX_PHYS_VIDEO_LAYER_NUM 3 /* max physical video layer num */ ++#define OT_VO_MAX_GFX_LAYER_NUM 3 /* max graphic layer num */ ++/* max physical layer num */ ++#define OT_VO_MAX_PHYS_LAYER_NUM (OT_VO_MAX_PHYS_VIDEO_LAYER_NUM + OT_VO_MAX_GFX_LAYER_NUM) ++/* max layer num */ ++#define OT_VO_MAX_LAYER_NUM (OT_VO_MAX_PHYS_LAYER_NUM + OT_VO_MAX_VIRT_DEV_NUM + OT_VO_MAX_CAS_DEV_NUM) ++#define OT_VO_MAX_LAYER_IN_DEV 2 /* max video layer num of each dev */ ++ ++#define OT_VO_LAYER_V0 0 /* video layer 0 */ ++#define OT_VO_LAYER_V1 1 /* video layer 1 */ ++#define OT_VO_LAYER_V2 2 /* video layer 2 */ ++#define OT_VO_LAYER_G0 3 /* graphics layer 0 */ ++#define OT_VO_LAYER_G1 4 /* graphics layer 1 */ ++#define OT_VO_LAYER_G3 5 /* graphics layer 3 */ ++#define ot_vo_get_virt_layer(vo_virt_dev) ((vo_virt_dev) + 4) /* get virtual layer of virtual dev */ ++ ++#define OT_VO_MAX_PRIORITY 3 /* max layer priority */ ++#define OT_VO_MIN_TOLERATE 1 /* min play toleration 1ms */ ++#define OT_VO_MAX_TOLERATE 100000 /* max play toleration 100s */ ++ ++#define OT_VO_MAX_CHN_NUM 64 /* max chn num */ ++#define OT_VO_MIN_CHN_WIDTH 32 /* channel minimal width */ ++#define OT_VO_MIN_CHN_HEIGHT 32 /* channel minimal height */ ++#define OT_VO_MAX_ZOOM_RATIO 1000 /* max zoom ratio, 1000 means 100% scale */ ++#define OT_VO_MAX_NODE_NUM 16 /* max node num */ ++ ++#define OT_VO_MAX_WBC_NUM 0 /* max wbc num */ ++#define OT_VO_MAX_IMG_WIDTH 16384 /* vo max img width */ ++#define OT_VO_MAX_IMG_HEIGHT 8192 /* vo max img height */ +\ No newline at end of file +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.c +new file mode 100755 +index 000000000..bf90d972d +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.c +@@ -0,0 +1,192 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#include "hdmi_reg_aon.h" ++#include "hdmi_product_define.h" ++ ++volatile tx_aon_regs *g_tx_aon_regs = NULL; ++ ++int hdmi_reg_aon_regs_init(const char *addr) ++{ ++ g_tx_aon_regs = (volatile tx_aon_regs *)(addr + (HDMI_TX_BASE_ADDR_AON)); ++ return 0; ++} ++ ++int hdmi_reg_aon_regs_deinit(void) ++{ ++ if (g_tx_aon_regs != NULL) { ++ g_tx_aon_regs = NULL; ++ } ++ return 0; ++} ++ ++void hdmi_reg_aon_intr_mask0_set(unsigned char aon_intr_mask0) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_intr_mask mask; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_mask.u32); ++ mask.u32 = hdmi_tx_reg_read(reg_addr); ++ mask.bits.aon_intr_mask0 = aon_intr_mask0; ++ hdmi_tx_reg_write(reg_addr, mask.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aon_intr_stat1_set(unsigned char aon_intr_stat1) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_intr_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); ++ state.u32 = 0; ++ state.bits.aon_intr_stat1 = aon_intr_stat1; ++ hdmi_tx_reg_write(reg_addr, state.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aon_intr_stat0_set(unsigned char aon_intr_stat0) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_intr_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); ++ state.u32 = 0; ++ state.bits.aon_intr_stat0 = aon_intr_stat0; ++ hdmi_tx_reg_write(reg_addr, state.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dcc_man_en_set(unsigned char dcc_man_en) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_mst_ctrl ctrl; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.dcc_man_en = dcc_man_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ddc_sda_oen_set(unsigned char ddc_sda_oen) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_man_ctrl ctrl; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.ddc_sda_oen = ddc_sda_oen; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ddc_scl_oen_set(unsigned char ddc_scl_oen) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_man_ctrl ctrl; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.ddc_scl_oen = ddc_scl_oen; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_ddc_i2c_no_ack_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_mst_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->mst_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.ddc_i2c_no_ack; ++} ++ ++unsigned char hdmi_reg_ddc_i2c_bus_low_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_mst_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->mst_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.ddc_i2c_bus_low; ++} ++ ++unsigned char hdmi_reg_hpd_polarity_ctl_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ hotplug_st_cfg cfg; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->hpd_cfg.u32); ++ cfg.u32 = hdmi_tx_reg_read(reg_addr); ++ return cfg.bits.hpd_polarity_ctl; ++} ++ ++unsigned char hdmi_reg_phy_rx_sense_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.phy_rx_sense; ++} ++ ++unsigned char hdmi_reg_hotplug_state_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.hotplug_state; ++} ++ ++unsigned char hdmi_reg_aon_intr_stat1_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_intr_state state; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.aon_intr_stat1; ++} ++ ++unsigned char hdmi_reg_aon_intr_stat0_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_aon_intr_state state; ++ if (!g_tx_aon_regs) { ++ return 0; ++ } ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.aon_intr_stat0; ++} ++ ++unsigned char hdmi_reg_ddc_sda_st_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_man_ctrl ctrl; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.ddc_sda_st; ++} ++ ++unsigned char hdmi_reg_ddc_scl_st_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_man_ctrl ctrl; ++ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.ddc_scl_st; ++} ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.h +new file mode 100755 +index 000000000..44af4e0c5 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.h +@@ -0,0 +1,259 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef HDMI_REG_AON_H ++#define HDMI_REG_AON_H ++ ++ ++typedef union { ++ struct { ++ unsigned int tx_hw_day : 8; /* [7:0] */ ++ unsigned int tx_hw_month : 8; /* [15:8] */ ++ unsigned int tx_hw_year : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} tx_hw_info; ++ ++typedef union { ++ struct { ++ unsigned int tx_reg_version : 8; /* [7:0] */ ++ unsigned int tx_drv_version : 8; /* [15:8] */ ++ unsigned int tx_rtl_version : 8; /* [23:16] */ ++ unsigned int rsv_0 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} tx_hw_version; ++ ++typedef union { ++ struct { ++ unsigned int rsv_1 : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} tx_hw_feature; ++ ++typedef union { ++ struct { ++ unsigned int tx_aon_soft_arst_req : 1; /* [0] */ ++ unsigned int rsv_2 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} tx_aon_rst_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int hpd_fillter_en : 1; /* [0] */ ++ unsigned int hpd_override_en : 1; /* [1] */ ++ unsigned int hpd_polarity_ctl : 1; /* [2] */ ++ unsigned int hpd_soft_value : 1; /* [3] */ ++ unsigned int osc_div_cnt : 12; /* [15:4] */ ++ unsigned int rsv_3 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} hotplug_st_cfg; ++ ++typedef union { ++ struct { ++ unsigned int hpd_high_reshold : 16; /* [15:0] */ ++ unsigned int hpd_low_reshold : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} hotplug_fillter_cfg; ++ ++typedef union { ++ struct { ++ unsigned int hotplug_state : 1; /* [0] */ ++ unsigned int phy_rx_sense : 1; /* [1] */ ++ unsigned int rsv_4 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} tx_aon_state; ++ ++typedef union { ++ struct { ++ unsigned int aon_intr_mask0 : 1; /* [0] */ ++ unsigned int aon_intr_mask1 : 1; /* [1] */ ++ unsigned int rsv_5 : 1; /* [2] */ ++ unsigned int rsv_6 : 1; /* [3] */ ++ unsigned int aon_intr_mask4 : 1; /* [4] */ ++ unsigned int aon_intr_mask5 : 1; /* [5] */ ++ unsigned int aon_intr_mask6 : 1; /* [6] */ ++ unsigned int aon_intr_mask7 : 1; /* [7] */ ++ unsigned int aon_intr_mask8 : 1; /* [8] */ ++ unsigned int aon_intr_mask9 : 1; /* [9] */ ++ unsigned int aon_intr_mask10 : 1; /* [10] */ ++ unsigned int aon_intr_mask11 : 1; /* [11] */ ++ unsigned int aon_intr_mask12 : 1; /* [12] */ ++ unsigned int aon_intr_mask13 : 1; /* [13] */ ++ unsigned int rsv_7 : 18; /* [31:14] */ ++ } bits; ++ unsigned int u32; ++} tx_aon_intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int aon_intr_stat0 : 1; /* [0] */ ++ unsigned int aon_intr_stat1 : 1; /* [1] */ ++ unsigned int rsv_8 : 1; /* [2] */ ++ unsigned int rsv_9 : 1; /* [3] */ ++ unsigned int aon_intr_stat4 : 1; /* [4] */ ++ unsigned int aon_intr_stat5 : 1; /* [5] */ ++ unsigned int aon_intr_stat6 : 1; /* [6] */ ++ unsigned int aon_intr_stat7 : 1; /* [7] */ ++ unsigned int aon_intr_stat8 : 1; /* [8] */ ++ unsigned int aon_intr_stat9 : 1; /* [9] */ ++ unsigned int aon_intr_stat10 : 1; /* [10] */ ++ unsigned int aon_intr_stat11 : 1; /* [11] */ ++ unsigned int aon_intr_stat12 : 1; /* [12] */ ++ unsigned int aon_intr_stat13 : 1; /* [13] */ ++ unsigned int rsv_10 : 18; /* [31:14] */ ++ } bits; ++ unsigned int u32; ++} tx_aon_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int ddc_aon_access : 1; /* [0] */ ++ unsigned int dcc_man_en : 1; /* [1] */ ++ unsigned int rsv_11 : 2; /* [3:2] */ ++ unsigned int ddc_speed_cnt : 9; /* [12:4] */ ++ unsigned int rsv_12 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int ddc_fifo_data_out : 8; /* [7:0] */ ++ unsigned int rsv_13 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} ddc_fifo_rdata; ++ ++typedef union { ++ struct { ++ unsigned int ddc_fifo_data_in : 8; /* [7:0] */ ++ unsigned int rsv_14 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} ddc_fifo_wdata; ++ ++typedef union { ++ struct { ++ unsigned int ddc_fifo_data_cnt : 5; /* [4:0] */ ++ unsigned int rsv_15 : 3; /* [7:5] */ ++ unsigned int ddc_data_out_cnt : 10; /* [17:8] */ ++ unsigned int rsv_16 : 14; /* [31:18] */ ++ } bits; ++ unsigned int u32; ++} ddc_data_cnt; ++ ++typedef union { ++ struct { ++ unsigned int ddc_slave_addr : 8; /* [7:0] */ ++ unsigned int ddc_slave_offset : 8; /* [15:8] */ ++ unsigned int ddc_slave_seg : 8; /* [23:16] */ ++ unsigned int rsv_17 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} ddc_slave_cfg; ++ ++typedef union { ++ struct { ++ unsigned int ddc_i2c_no_ack : 1; /* [0] */ ++ unsigned int ddc_i2c_bus_low : 1; /* [1] */ ++ unsigned int ddc_i2c_in_prog : 1; /* [2] */ ++ unsigned int ddc_fifo_wr_in_use : 1; /* [3] */ ++ unsigned int ddc_fifo_rd_in_use : 1; /* [4] */ ++ unsigned int ddc_fifo_empty : 1; /* [5] */ ++ unsigned int ddc_fifo_half_full : 1; /* [6] */ ++ unsigned int ddc_fifo_full : 1; /* [7] */ ++ unsigned int rsv_18 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_state; ++ ++typedef union { ++ struct { ++ unsigned int ddc_mst_cmd : 4; /* [3:0] */ ++ unsigned int rsv_19 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_cmd; ++ ++typedef union { ++ struct { ++ unsigned int ddc_scl_st : 1; /* [0] */ ++ unsigned int ddc_sda_st : 1; /* [1] */ ++ unsigned int ddc_scl_oen : 1; /* [2] */ ++ unsigned int ddc_sda_oen : 1; /* [3] */ ++ unsigned int rsv_20 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} ddc_man_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int ddc_clr_bus_low : 1; /* [0] */ ++ unsigned int ddc_clr_no_ack : 1; /* [1] */ ++ unsigned int rsv_21 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} ddc_state_clr; ++ ++typedef struct { ++ volatile tx_hw_info hw_info; /* 4000 */ ++ volatile tx_hw_version tx_hw_vers; /* 4004 */ ++ volatile tx_hw_feature hw_feature; /* 4008 */ ++ unsigned int reserved_0[4]; /* 400C-4018 */ ++ volatile tx_aon_rst_ctrl aon_rst; /* 401C */ ++ volatile hotplug_st_cfg hpd_cfg; /* 4020 */ ++ volatile hotplug_fillter_cfg hpd_filt_cfg; /* 4024 */ ++ volatile tx_aon_state aon_state; /* 4028 */ ++ unsigned int reserved_2[1]; /* 402C */ ++ volatile tx_aon_intr_mask aon_irq_mask; /* 4030 */ ++ volatile tx_aon_intr_state aon_irq_state; /* 4034 */ ++ unsigned int reserved_3[2]; /* 4038-403C */ ++ volatile ddc_mst_ctrl ddc_ctrl; /* 4040 */ ++ volatile ddc_fifo_rdata ddc_rdata; /* 4044 */ ++ volatile ddc_fifo_wdata ddc_wdata; /* 4048 */ ++ volatile ddc_data_cnt data_count; /* 404C */ ++ volatile ddc_slave_cfg slave_cfg; /* 4050 */ ++ volatile ddc_mst_state mst_state; /* 4054 */ ++ volatile ddc_mst_cmd mst_cmd; /* 4058 */ ++ volatile ddc_man_ctrl ddc_sw_ctrl; /* 405C */ ++ volatile ddc_state_clr state_clr; /* 4060 */ ++} tx_aon_regs; ++ ++int hdmi_reg_aon_regs_init(const char *addr); ++int hdmi_reg_aon_regs_deinit(void); ++void hdmi_reg_aon_intr_mask0_set(unsigned char aon_intr_mask0); ++void hdmi_reg_aon_intr_stat0_set(unsigned char aon_intr_stat0); ++void hdmi_reg_aon_intr_stat1_set(unsigned char aon_intr_stat1); ++void hdmi_reg_dcc_man_en_set(unsigned char dcc_man_en); ++void hdmi_reg_ddc_scl_oen_set(unsigned char ddc_scl_oen); ++void hdmi_reg_ddc_sda_oen_set(unsigned char ddc_sda_oen); ++unsigned char hdmi_reg_ddc_i2c_bus_low_get(void); ++unsigned char hdmi_reg_ddc_i2c_no_ack_get(void); ++unsigned char hdmi_reg_hpd_polarity_ctl_get(void); ++unsigned char hdmi_reg_hotplug_state_get(void); ++unsigned char hdmi_reg_phy_rx_sense_get(void); ++unsigned char hdmi_reg_aon_intr_stat0_get(void); ++unsigned char hdmi_reg_aon_intr_stat1_get(void); ++unsigned char hdmi_reg_ddc_scl_st_get(void); ++unsigned char hdmi_reg_ddc_sda_st_get(void); ++#endif /* HDMI_REG_AON_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.c +new file mode 100755 +index 000000000..2d2179702 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.c +@@ -0,0 +1,462 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#include "hdmi_reg_audio_path.h" ++#include "hdmi_product_define.h" ++ ++volatile hdmi_reg_audio_path *g_audio_path_regs = NULL; ++ ++int hdmi_reg_audio_path_regs_init(const char *addr) ++{ ++ g_audio_path_regs = (volatile hdmi_reg_audio_path *)(addr + (HDMI_TX_BASE_ADDR_AUDIO)); ++ return 0; ++} ++ ++int hdmi_reg_audio_path_regs_deinit(void) ++{ ++ if (g_audio_path_regs != NULL) { ++ g_audio_path_regs = NULL; ++ } ++ return 0; ++} ++ ++void hdmi_reg_aud_spdif_en_set(unsigned char aud_spdif_en) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.aud_spdif_en = aud_spdif_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aud_i2s_en_set(unsigned char aud_i2s_en) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.aud_i2s_en = aud_i2s_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aud_layout_set(unsigned char aud_layout) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.aud_layout = aud_layout; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aud_in_en_set(unsigned char aud_in_en) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.aud_in_en = aud_in_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_ch_swap_set(unsigned char i2s_ch_swap) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_ch_swap = i2s_ch_swap; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_length_set(unsigned char i2s_length) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_length = i2s_length; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_vbit_set(unsigned char i2s_vbit) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_vbit = i2s_vbit; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_data_dir_set(unsigned char i2s_data_dir) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_data_dir = i2s_data_dir; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_justify_set(unsigned char i2s_justify) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_justify = i2s_justify; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_ws_polarity_set(unsigned char i2s_ws_polarity) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_ws_polarity = i2s_ws_polarity; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_1st_shift_set(unsigned char i2s_1st_shift) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_1st_shift = i2s_1st_shift; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_i2s_hbra_on_set(unsigned char i2s_hbra_on) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_i2s_ctrl.bits.i2s_hbra_on = i2s_hbra_on; ++ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_chst_byte3_clock_accuracy_set(unsigned char chst_byte3_clock_accuracy) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg0 aud_chst_cfg0; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); ++ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_chst_cfg0.bits.chst_byte3_clock_accuracy = chst_byte3_clock_accuracy; ++ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); ++ ++ return; ++} ++ ++void hdmi_reg_chst_byte3_fs_set(unsigned char chst_byte3_fs) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg0 aud_chst_cfg0; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); ++ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_chst_cfg0.bits.chst_byte3_fs = chst_byte3_fs; ++ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); ++ ++ return; ++} ++ ++void hdmi_reg_chst_byte0_bset(unsigned char chst_byte0_b) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg0 aud_chst_cfg0; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); ++ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_chst_cfg0.bits.chst_byte0_b = chst_byte0_b; ++ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); ++ ++ return; ++} ++ ++void hdmi_reg_chst_byte0_aset(unsigned char chst_byte0_a) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg0 aud_chst_cfg0; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); ++ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_chst_cfg0.bits.chst_byte0_a = chst_byte0_a; ++ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); ++ ++ return; ++} ++ ++void hdmi_reg_chst_byte4_org_fs_set(unsigned char chst_byte4_org_fs) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg1 aud_chst_cfg1; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); ++ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_chst_cfg1.bits.chst_byte4_org_fs = chst_byte4_org_fs; ++ hdmi_tx_reg_write(reg_addr, aud_chst_cfg1.u32); ++ ++ return; ++} ++ ++void hdmi_reg_chst_byte4_length_set(unsigned char chst_byte4_length) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg1 aud_chst_cfg1; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); ++ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_chst_cfg1.bits.chst_byte4_length = chst_byte4_length; ++ hdmi_tx_reg_write(reg_addr, aud_chst_cfg1.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aud_fifo_hbr_mask_set(unsigned char aud_fifo_hbr_mask) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_fifo_ctrl aud_fifo_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->fifo_ctl.u32); ++ aud_fifo_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_fifo_ctrl.bits.aud_fifo_hbr_mask = aud_fifo_hbr_mask; ++ hdmi_tx_reg_write(reg_addr, aud_fifo_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aud_fifo_test_set(unsigned char aud_fifo_test) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_fifo_ctrl aud_fifo_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->fifo_ctl.u32); ++ aud_fifo_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_fifo_ctrl.bits.aud_fifo_test = aud_fifo_test; ++ hdmi_tx_reg_write(reg_addr, aud_fifo_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_acr_cts_hw_sw_sel_set(unsigned char acr_cts_hw_sw_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_acr_ctrl aud_acr_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_ctl.u32); ++ aud_acr_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ aud_acr_ctrl.bits.acr_cts_hw_sw_sel = acr_cts_hw_sw_sel; ++ hdmi_tx_reg_write(reg_addr, aud_acr_ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_acr_n_val_sw_set(unsigned int acr_n_value) ++{ ++ unsigned int *reg_addr = NULL; ++ acr_n_val_sw acr_n_val; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_sw_n.u32); ++ acr_n_val.u32 = hdmi_tx_reg_read(reg_addr); ++ acr_n_val.bits.acr_n_val_sw = acr_n_value; ++ hdmi_tx_reg_write(reg_addr, acr_n_val.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_aud_spdif_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.aud_spdif_en; ++} ++ ++unsigned char hdmi_reg_aud_i2s_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.aud_i2s_en; ++} ++ ++unsigned char hdmi_reg_aud_layout_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.aud_layout; ++} ++ ++unsigned char hdmi_reg_aud_mute_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.aud_mute_en; ++} ++ ++unsigned char hdmi_reg_aud_in_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.aud_in_en; ++} ++ ++unsigned char hdmi_reg_i2s_hbra_on_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_i2s_ctrl aud_i2s_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); ++ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return aud_i2s_ctrl.bits.i2s_hbra_on; ++} ++ ++unsigned char hdmi_reg_chst_byte3_fs_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg0 aud_chst_cfg0; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); ++ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); ++ return aud_chst_cfg0.bits.chst_byte3_fs; ++} ++ ++unsigned char hdmi_reg_chst_byte4_org_fs_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg1 aud_chst_cfg1; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); ++ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); ++ return aud_chst_cfg1.bits.chst_byte4_org_fs; ++} ++ ++unsigned char hdmi_reg_chst_byte4_length_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_chst_cfg1 aud_chst_cfg1; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); ++ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); ++ return aud_chst_cfg1.bits.chst_byte4_length; ++} ++ ++unsigned char hdmi_reg_aud_length_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_audio_state state; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->aud_state.u32); ++ state.u32 = hdmi_tx_reg_read(reg_addr); ++ return state.bits.aud_length; ++} ++ ++unsigned char hdmi_reg_acr_cts_hw_sw_sel_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ audio_acr_ctrl aud_acr_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_ctl.u32); ++ aud_acr_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return aud_acr_ctrl.bits.acr_cts_hw_sw_sel; ++} ++ ++unsigned int hdmi_reg_acr_n_val_sw_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ acr_n_val_sw acr_n_val; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_sw_n.u32); ++ acr_n_val.u32 = hdmi_tx_reg_read(reg_addr); ++ return acr_n_val.bits.acr_n_val_sw; ++} ++ ++unsigned int hdmi_reg_acr_cts_val_sw_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ acr_cts_val_sw acr_cts_val; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_sw_cts.u32); ++ acr_cts_val.u32 = hdmi_tx_reg_read(reg_addr); ++ return acr_cts_val.bits.acr_cts_val_sw; ++} ++ ++unsigned int hdmi_reg_acr_cts_val_hw_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ acr_cts_val_hw acr_cts_val; ++ ++ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_hw_cts.u32); ++ acr_cts_val.u32 = hdmi_tx_reg_read(reg_addr); ++ return acr_cts_val.bits.acr_cts_val_hw; ++} ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.h +new file mode 100755 +index 000000000..97a046301 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.h +@@ -0,0 +1,226 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef HDMI_REG_AUDIO_PATH_H ++#define HDMI_REG_AUDIO_PATH_H ++ ++ ++typedef union { ++ struct { ++ unsigned int aud_in_en : 1; /* [0] */ ++ unsigned int aud_mute_en : 1; /* [1] */ ++ unsigned int aud_layout : 1; /* [2] */ ++ unsigned int rsv_0 : 1; /* [3] */ ++ unsigned int aud_i2s_en : 4; /* [7:4] */ ++ unsigned int aud_spdif_en : 1; /* [8] */ ++ unsigned int aud_src_en : 1; /* [9] */ ++ unsigned int aud_src_ctrl : 1; /* [10] */ ++ unsigned int rsv_1 : 1; /* [11] */ ++ unsigned int aud_fifo0_map : 2; /* [13:12] */ ++ unsigned int aud_fifo1_map : 2; /* [15:14] */ ++ unsigned int aud_fifo2_map : 2; /* [17:16] */ ++ unsigned int aud_fifo3_map : 2; /* [19:18] */ ++ unsigned int rsv_2 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} tx_audio_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int i2s_hbra_on : 1; /* [0] */ ++ unsigned int i2s_1st_shift : 1; /* [1] */ ++ unsigned int i2s_ws_polarity : 1; /* [2] */ ++ unsigned int i2s_justify : 1; /* [3] */ ++ unsigned int i2s_data_dir : 1; /* [4] */ ++ unsigned int i2s_vbit : 1; /* [5] */ ++ unsigned int rsv_3 : 2; /* [7:6] */ ++ unsigned int i2s_length : 4; /* [11:8] */ ++ unsigned int i2s_ch_swap : 4; /* [15:12] */ ++ unsigned int rsv_4 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} audio_i2s_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int spdif_1ui_lock : 1; /* [0] */ ++ unsigned int spdif_2ui_lock : 1; /* [1] */ ++ unsigned int i2s_cbit_order : 1; /* [2] */ ++ unsigned int spdif_fs_ovr_en : 1; /* [3] */ ++ unsigned int spdif_err_thresh : 6; /* [9:4] */ ++ unsigned int spdif_size_sw : 2; /* [11:10] */ ++ unsigned int spdif_1ui_max : 8; /* [19:12] */ ++ unsigned int spdif_2ui_max : 8; /* [27:20] */ ++ unsigned int rsv_5 : 4; /* [31:28] */ ++ } bits; ++ unsigned int u32; ++} audio_spdif_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int chst_byte0_a : 1; /* [0] */ ++ unsigned int chst_byte0_b : 1; /* [1] */ ++ unsigned int chst_byte0_other : 6; /* [7:2] */ ++ unsigned int chst_byte1 : 8; /* [15:8] */ ++ unsigned int chst_byte2 : 8; /* [23:16] */ ++ unsigned int chst_byte3_fs : 4; /* [27:24] */ ++ unsigned int chst_byte3_clock_accuracy : 4; /* [31:28] */ ++ } bits; ++ unsigned int u32; ++} audio_chst_cfg0; ++ ++typedef union { ++ struct { ++ unsigned int chst_byte4_length : 4; /* [3:0] */ ++ unsigned int chst_byte4_org_fs : 4; /* [7:4] */ ++ unsigned int chst_byte5_6 : 16; /* [23:8] */ ++ unsigned int rsv_6 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} audio_chst_cfg1; ++ ++typedef union { ++ struct { ++ unsigned int aud_inavailable : 1; /* [0] */ ++ unsigned int aud_spdif_new_fs : 1; /* [1] */ ++ unsigned int rsv_7 : 2; /* [3:2] */ ++ unsigned int aud_length : 4; /* [7:4] */ ++ unsigned int aud_spdif_fs : 6; /* [13:8] */ ++ unsigned int rsv_8 : 2; /* [15:14] */ ++ unsigned int spdif_max_1ui_st : 8; /* [23:16] */ ++ unsigned int spdif_max_2ui_st : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} tx_audio_state; ++ ++typedef union { ++ struct { ++ unsigned int aud_fifo_test : 5; /* [4:0] */ ++ unsigned int rsv_9 : 3; /* [7:5] */ ++ unsigned int aud_fifo_hbr_mask : 4; /* [11:8] */ ++ unsigned int rsv_10 : 4; /* [15:12] */ ++ unsigned int aud_fifo_ptr_diff : 6; /* [21:16] */ ++ unsigned int rsv_11 : 10; /* [31:22] */ ++ } bits; ++ unsigned int u32; ++} audio_fifo_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int acr_cts_req_en : 1; /* [0] */ ++ unsigned int acr_cts_hw_sw_sel : 1; /* [1] */ ++ unsigned int acr_cts_gen_sel : 1; /* [2] */ ++ unsigned int acr_cts_flt_en : 1; /* [3] */ ++ unsigned int acr_use_sw_cts : 1; /* [4] */ ++ unsigned int acr_cts_ave_en : 1; /* [5] */ ++ unsigned int rsv_12 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} audio_acr_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int acr_fm_val_sw : 3; /* [2:0] */ ++ unsigned int acr_ave_max : 5; /* [7:3] */ ++ unsigned int acr_cts_thre : 8; /* [15:8] */ ++ unsigned int acr_cts_chg_thre : 8; /* [23:16] */ ++ unsigned int rsv_13 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} audio_acr_cfg; ++ ++typedef union { ++ struct { ++ unsigned int acr_n_val_sw : 20; /* [19:0] */ ++ unsigned int rsv_14 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} acr_n_val_sw; ++ ++typedef union { ++ struct { ++ unsigned int acr_cts_val_sw : 20; /* [19:0] */ ++ unsigned int rsv_15 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} acr_cts_val_sw; ++ ++typedef union { ++ struct { ++ unsigned int acr_cts_val_hw : 20; /* [19:0] */ ++ unsigned int rsv_16 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} acr_cts_val_hw; ++ ++typedef struct { ++ volatile tx_audio_ctrl audio_ctl; /* 1000 */ ++ volatile audio_i2s_ctrl i2s_ctl; /* 1004 */ ++ volatile audio_spdif_ctrl spdif_ctl; /* 1008 */ ++ volatile audio_chst_cfg0 chst_cfg0; /* 100C */ ++ volatile audio_chst_cfg1 chst_cfg1; /* 1010 */ ++ volatile tx_audio_state aud_state; /* 1014 */ ++ volatile audio_fifo_ctrl fifo_ctl; /* 1018 */ ++ unsigned int reserved_0[9]; ++ volatile audio_acr_ctrl acr_ctl; /* 1040 */ ++ volatile audio_acr_cfg acr_cfg; /* 1044 */ ++ volatile acr_n_val_sw acr_sw_n; /* 1048 */ ++ volatile acr_cts_val_sw acr_sw_cts; /* 104C */ ++ volatile acr_cts_val_hw acr_hw_cts; /* 1050 */ ++} hdmi_reg_audio_path; ++ ++int hdmi_reg_audio_path_regs_init(const char *addr); ++int hdmi_reg_audio_path_regs_deinit(void); ++void hdmi_reg_aud_in_en_set(unsigned char aud_in_en); ++void hdmi_reg_aud_layout_set(unsigned char aud_layout); ++void hdmi_reg_aud_i2s_en_set(unsigned char aud_i2s_en); ++void hdmi_reg_aud_spdif_en_set(unsigned char aud_spdif_en); ++void hdmi_reg_i2s_hbra_on_set(unsigned char i2s_hbra_on); ++void hdmi_reg_i2s_1st_shift_set(unsigned char i2s_1st_shift); ++void hdmi_reg_i2s_ws_polarity_set(unsigned char i2s_ws_polarity); ++void hdmi_reg_i2s_justify_set(unsigned char i2s_justify); ++void hdmi_reg_i2s_data_dir_set(unsigned char i2s_data_dir); ++void hdmi_reg_i2s_vbit_set(unsigned char i2s_vbit); ++void hdmi_reg_i2s_length_set(unsigned char i2s_length); ++void hdmi_reg_i2s_ch_swap_set(unsigned char i2s_ch_swap); ++void hdmi_reg_chst_byte0_aset(unsigned char chst_byte0_a); ++void hdmi_reg_chst_byte0_bset(unsigned char chst_byte0_b); ++void hdmi_reg_chst_byte3_fs_set(unsigned char chst_byte3_fs); ++void hdmi_reg_chst_byte3_clock_accuracy_set(unsigned char chst_byte3_clock_accuracy); ++void hdmi_reg_chst_byte4_length_set(unsigned char chst_byte4_length); ++void hdmi_reg_chst_byte4_org_fs_set(unsigned char chst_byte4_org_fs); ++void hdmi_reg_aud_fifo_test_set(unsigned char aud_fifo_test); ++void hdmi_reg_aud_fifo_hbr_mask_set(unsigned char aud_fifo_hbr_mask); ++void hdmi_reg_acr_cts_hw_sw_sel_set(unsigned char acr_cts_hw_sw_sel); ++void hdmi_reg_acr_n_val_sw_set(unsigned int acr_n_value); ++unsigned char hdmi_reg_aud_in_en_get(void); ++unsigned char hdmi_reg_aud_mute_en_get(void); ++unsigned char hdmi_reg_aud_layout_get(void); ++unsigned char hdmi_reg_aud_i2s_en_get(void); ++unsigned char hdmi_reg_aud_spdif_en_get(void); ++unsigned char hdmi_reg_i2s_hbra_on_get(void); ++unsigned char hdmi_reg_chst_byte3_fs_get(void); ++unsigned char hdmi_reg_chst_byte4_length_get(void); ++unsigned char hdmi_reg_chst_byte4_org_fs_get(void); ++unsigned char hdmi_reg_aud_length_get(void); ++unsigned char hdmi_reg_acr_cts_hw_sw_sel_get(void); ++unsigned int hdmi_reg_acr_n_val_sw_get(void); ++unsigned int hdmi_reg_acr_cts_val_sw_get(void); ++unsigned int hdmi_reg_acr_cts_val_hw_get(void); ++ ++#endif /* HDMI_REG_AUDIO_PATH_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.c +new file mode 100755 +index 000000000..92741d19f +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.c +@@ -0,0 +1,213 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#include "hdmi_reg_ctrl.h" ++#include "hdmi_product_define.h" ++ ++volatile hdmi_reg_tx_ctrl *g_tx_ctrl_regs = NULL; ++ ++int hdmi_reg_tx_ctrl_regs_init(const char *addr) ++{ ++ g_tx_ctrl_regs = (volatile hdmi_reg_tx_ctrl *)(addr + HDMI_TX_BASE_ADDR_CTRL); ++ return 0; ++} ++ ++int hdmi_reg_tx_ctrl_regs_deinit(void) ++{ ++ if (g_tx_ctrl_regs != NULL) { ++ g_tx_ctrl_regs = NULL; ++ } ++ return 0; ++} ++ ++void hdmi_reg_tx_afifo_srst_req_set(unsigned char tx_afifo_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pwd_rst_ctrl tx_pwd_rst; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); ++ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); ++ tx_pwd_rst.bits.tx_afifo_srst_req = tx_afifo_srst_req; ++ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); ++ ++ return; ++} ++ ++void hdmi_reg_tx_acr_srst_req_set(unsigned char tx_acr_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pwd_rst_ctrl tx_pwd_rst; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); ++ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); ++ tx_pwd_rst.bits.tx_acr_srst_req = tx_acr_srst_req; ++ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); ++ ++ return; ++} ++ ++void hdmi_reg_tx_aud_srst_req_set(unsigned char tx_aud_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pwd_rst_ctrl tx_pwd_rst; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); ++ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); ++ tx_pwd_rst.bits.tx_aud_srst_req = tx_aud_srst_req; ++ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); ++ ++ return; ++} ++ ++void hdmi_reg_tx_hdmi_srst_req_set(unsigned char tx_hdmi_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pwd_rst_ctrl tx_pwd_rst; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); ++ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); ++ tx_pwd_rst.bits.tx_hdmi_srst_req = tx_hdmi_srst_req; ++ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pwd_fifo_data_in_set(unsigned char pwd_fifo_data_in) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_fifo_wdata fifo_wdata; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->wdata.u32); ++ fifo_wdata.u32 = hdmi_tx_reg_read(reg_addr); ++ fifo_wdata.bits.pwd_fifo_data_in = pwd_fifo_data_in; ++ hdmi_tx_reg_write(reg_addr, fifo_wdata.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pwd_data_out_cnt_set(unsigned short pwd_data_out_cnt) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_data_cnt data_cnt; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->data_cnt.u32); ++ data_cnt.u32 = hdmi_tx_reg_read(reg_addr); ++ data_cnt.bits.pwd_data_out_cnt = pwd_data_out_cnt; ++ hdmi_tx_reg_write(reg_addr, data_cnt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pwd_slave_seg_set(unsigned char pwd_slave_seg) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_slave_cfg cfg; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->slave_cfg.u32); ++ cfg.u32 = hdmi_tx_reg_read(reg_addr); ++ cfg.bits.pwd_slave_seg = pwd_slave_seg; ++ hdmi_tx_reg_write(reg_addr, cfg.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pwd_slave_offset_set(unsigned char pwd_slave_offset) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_slave_cfg cfg; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->slave_cfg.u32); ++ cfg.u32 = hdmi_tx_reg_read(reg_addr); ++ cfg.bits.pwd_slave_offset = pwd_slave_offset; ++ hdmi_tx_reg_write(reg_addr, cfg.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pwd_slave_addr_set(unsigned char pwd_slave_addr) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_slave_cfg cfg; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->slave_cfg.u32); ++ cfg.u32 = hdmi_tx_reg_read(reg_addr); ++ cfg.bits.pwd_slave_addr = pwd_slave_addr; ++ hdmi_tx_reg_write(reg_addr, cfg.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pwd_mst_cmd_set(unsigned char mst_cmd) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_mst_cmd cmd; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->mst_cmd.u32); ++ cmd.u32 = hdmi_tx_reg_read(reg_addr); ++ cmd.bits.pwd_mst_cmd = mst_cmd; ++ hdmi_tx_reg_write(reg_addr, cmd.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cpu_ddc_req_set(unsigned char cpu_ddc_req) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_mst_arb_reql arb_req; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->ddc_arb_req.u32); ++ arb_req.u32 = hdmi_tx_reg_read(reg_addr); ++ arb_req.bits.cpu_ddc_req = cpu_ddc_req; ++ hdmi_tx_reg_write(reg_addr, arb_req.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_rdata_pwd_fifo_data_out_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_fifo_rdata fifo_rdata; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->rdata.u32); ++ fifo_rdata.u32 = hdmi_tx_reg_read(reg_addr); ++ return fifo_rdata.bits.pwd_fifo_data_out; ++} ++ ++unsigned char hdmi_reg_pwd_fifo_data_out_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_data_cnt data_cnt; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->data_cnt.u32); ++ data_cnt.u32 = hdmi_tx_reg_read(reg_addr); ++ return data_cnt.bits.pwd_fifo_data_cnt; ++} ++ ++unsigned char hdmi_reg_pwd_fifo_empty_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_mst_state mst_state; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->mst_state.u32); ++ mst_state.u32 = hdmi_tx_reg_read(reg_addr); ++ return mst_state.bits.pwd_fifo_empty; ++} ++ ++unsigned char hdmi_reg_pwd_i2c_in_prog_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ pwd_mst_state mst_state; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->mst_state.u32); ++ mst_state.u32 = hdmi_tx_reg_read(reg_addr); ++ return mst_state.bits.pwd_i2c_in_prog; ++} ++ ++unsigned char hdmi_reg_cpu_ddc_req_ack_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ ddc_mst_arb_ack arb_ack; ++ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->ddc_arb_ack.u32); ++ arb_ack.u32 = hdmi_tx_reg_read(reg_addr); ++ return arb_ack.bits.cpu_ddc_req_ack; ++} ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.h +new file mode 100755 +index 000000000..024e5a24f +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.h +@@ -0,0 +1,394 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef HDMI_REG_CTRL_H ++#define HDMI_REG_CTRL_H ++ ++ ++typedef union { ++ struct { ++ unsigned int tx_pwd_srst_req : 1; /* [0] */ ++ unsigned int tx_sys_srst_req : 1; /* [1] */ ++ unsigned int tx_vid_srst_req : 1; /* [2] */ ++ unsigned int tx_hdmi_srst_req : 1; /* [3] */ ++ unsigned int tx_hdcp1x_srst_req : 1; /* [4] */ ++ unsigned int tx_phy_srst_req : 1; /* [5] */ ++ unsigned int tx_aud_srst_req : 1; /* [6] */ ++ unsigned int tx_acr_srst_req : 1; /* [7] */ ++ unsigned int tx_afifo_srst_req : 1; /* [8] */ ++ unsigned int tx_hdcp2x_srst_req : 1; /* [9] */ ++ unsigned int tx_mcu_srst_req : 1; /* [10] */ ++ unsigned int rsv_0 : 21; /* [31:11] */ ++ } bits; ++ unsigned int u32; ++} tx_pwd_rst_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int scdc_ddcm_abort : 1; /* [0] */ ++ unsigned int scdc_access_en : 1; /* [1] */ ++ unsigned int scdc_auto_reply : 1; /* [2] */ ++ unsigned int scdc_auto_poll : 1; /* [3] */ ++ unsigned int scdc_auto_reply_stop : 1; /* [4] */ ++ unsigned int scdc_poll_sel : 1; /* [5] */ ++ unsigned int scdc_hdcp_det_en : 1; /* [6] */ ++ unsigned int scdc_stall_req : 1; /* [7] */ ++ unsigned int rsv_1 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} scdc_fsm_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int scdc_poll_timer : 22; /* [21:0] */ ++ unsigned int rsv_2 : 10; /* [31:22] */ ++ } bits; ++ unsigned int u32; ++} scdc_poll_timerl; ++ ++typedef union { ++ struct { ++ unsigned int scdc_fsm_state : 4; /* [3:0] */ ++ unsigned int scdc_rreq_state : 4; /* [7:4] */ ++ unsigned int scdc_active : 1; /* [8] */ ++ unsigned int scdc_in_prog : 1; /* [9] */ ++ unsigned int scdc_rreq_in_prog : 1; /* [10] */ ++ unsigned int rsv_3 : 21; /* [31:11] */ ++ } bits; ++ unsigned int u32; ++} scdc_fsm_state; ++ ++typedef union { ++ struct { ++ unsigned int scdc_flag_byte0 : 8; /* [7:0] */ ++ unsigned int scdc_flag_byte1 : 8; /* [15:8] */ ++ unsigned int rsv_4 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} scdc_flag_byte; ++ ++typedef union { ++ struct { ++ unsigned int pwd_fifo_data_out : 8; /* [7:0] */ ++ unsigned int rsv_5 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} pwd_fifo_rdata; ++ ++typedef union { ++ struct { ++ unsigned int pwd_fifo_data_in : 8; /* [7:0] */ ++ unsigned int rsv_6 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} pwd_fifo_wdata; ++ ++typedef union { ++ struct { ++ unsigned int pwd_fifo_data_cnt : 5; /* [4:0] */ ++ unsigned int rsv_7 : 3; /* [7:5] */ ++ unsigned int pwd_data_out_cnt : 10; /* [17:8] */ ++ unsigned int rsv_8 : 14; /* [31:18] */ ++ } bits; ++ unsigned int u32; ++} pwd_data_cnt; ++ ++typedef union { ++ struct { ++ unsigned int pwd_slave_addr : 8; /* [7:0] */ ++ unsigned int pwd_slave_offset : 8; /* [15:8] */ ++ unsigned int pwd_slave_seg : 8; /* [23:16] */ ++ unsigned int rsv_9 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} pwd_slave_cfg; ++ ++typedef union { ++ struct { ++ unsigned int pwd_i2c_no_ack : 1; /* [0] */ ++ unsigned int pwd_i2c_bus_low : 1; /* [1] */ ++ unsigned int pwd_i2c_in_prog : 1; /* [2] */ ++ unsigned int pwd_fifo_wr_in_use : 1; /* [3] */ ++ unsigned int pwd_fifo_rd_in_use : 1; /* [4] */ ++ unsigned int pwd_fifo_empty : 1; /* [5] */ ++ unsigned int pwd_fifo_half_full : 1; /* [6] */ ++ unsigned int pwd_fifo_full : 1; /* [7] */ ++ unsigned int rsv_10 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} pwd_mst_state; ++ ++typedef union { ++ struct { ++ unsigned int pwd_mst_cmd : 4; /* [3:0] */ ++ unsigned int rsv_11 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} pwd_mst_cmd; ++ ++typedef union { ++ struct { ++ unsigned int pwd_clr_bus_low : 1; /* [0] */ ++ unsigned int pwd_clr_no_ack : 1; /* [1] */ ++ unsigned int rsv_12 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} pwd_mst_clr; ++ ++typedef union { ++ struct { ++ unsigned int cpu_ddc_force_req : 1; /* [0] */ ++ unsigned int reg_auto_abort_en : 1; /* [1] */ ++ unsigned int rsv_13 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_arb_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int cpu_ddc_req : 1; /* [0] */ ++ unsigned int rsv_14 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_arb_reql; ++ ++typedef union { ++ struct { ++ unsigned int cpu_ddc_req_ack : 1; /* [0] */ ++ unsigned int rsv_15 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_arb_ack; ++ ++typedef union { ++ struct { ++ unsigned int ddc_arb_state : 9; /* [8:0] */ ++ unsigned int rsv_16 : 23; /* [31:9] */ ++ } bits; ++ unsigned int u32; ++} ddc_mst_arb_state; ++ ++typedef union { ++ struct { ++ unsigned int tx_pwd_intr_state : 1; /* [0] */ ++ unsigned int rsv_17 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} tx_pwd_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int tx_sys_intr_state : 1; /* [0] */ ++ unsigned int vidpath_intr_state : 1; /* [1] */ ++ unsigned int audpath_intr_state : 1; /* [2] */ ++ unsigned int txhdmi_intr_state : 1; /* [3] */ ++ unsigned int txhdcp_intr_state : 1; /* [4] */ ++ unsigned int hdcp2x_intr_state : 1; /* [5] */ ++ unsigned int rsv_18 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} pwd_sub_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int tx_sys_intr_mask : 1; /* [0] */ ++ unsigned int vidpath_intr_mask : 1; /* [1] */ ++ unsigned int audpath_intr_mask : 1; /* [2] */ ++ unsigned int txhdmi_intr_mask : 1; /* [3] */ ++ unsigned int txhdcp_intr_mask : 1; /* [4] */ ++ unsigned int hdcp2x_intr_mask : 1; /* [5] */ ++ unsigned int rsv_19 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} pwd_sub_intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int tx_sys_intr_state0 : 1; /* [0] */ ++ unsigned int tx_sys_intr_state1 : 1; /* [1] */ ++ unsigned int tx_sys_intr_state2 : 1; /* [2] */ ++ unsigned int tx_sys_intr_state3 : 1; /* [3] */ ++ unsigned int tx_sys_intr_state4 : 1; /* [4] */ ++ unsigned int tx_sys_intr_state5 : 1; /* [5] */ ++ unsigned int rsv_20 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} txsys_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int tx_sys_intr_mask0 : 1; /* [0] */ ++ unsigned int tx_sys_intr_mask1 : 1; /* [1] */ ++ unsigned int tx_sys_intr_mask2 : 1; /* [2] */ ++ unsigned int tx_sys_intr_mask3 : 1; /* [3] */ ++ unsigned int tx_sys_intr_mask4 : 1; /* [4] */ ++ unsigned int tx_sys_intr_mask5 : 1; /* [5] */ ++ unsigned int rsv_21 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} txsys_intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int vidpath_intr_state0 : 1; /* [0] */ ++ unsigned int vidpath_intr_state1 : 1; /* [1] */ ++ unsigned int vidpath_intr_state2 : 1; /* [2] */ ++ unsigned int vidpath_intr_state3 : 1; /* [3] */ ++ unsigned int vidpath_intr_state4 : 1; /* [4] */ ++ unsigned int vidpath_intr_state5 : 1; /* [5] */ ++ unsigned int vidpath_intr_state6 : 1; /* [6] */ ++ unsigned int rsv_22 : 25; /* [31:7] */ ++ } bits; ++ unsigned int u32; ++} video_path_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int vidpath_intr_mask0 : 1; /* [0] */ ++ unsigned int vidpath_intr_mask1 : 1; /* [1] */ ++ unsigned int vidpath_intr_mask2 : 1; /* [2] */ ++ unsigned int vidpath_intr_mask3 : 1; /* [3] */ ++ unsigned int vidpath_intr_mask4 : 1; /* [4] */ ++ unsigned int vidpath_intr_mask5 : 1; /* [5] */ ++ unsigned int vidpath_intr_mask6 : 1; /* [6] */ ++ unsigned int rsv_23 : 25; /* [31:7] */ ++ } bits; ++ unsigned int u32; ++} video_path_intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int audpath_intr_state0 : 1; /* [0] */ ++ unsigned int audpath_intr_state1 : 1; /* [1] */ ++ unsigned int audpath_intr_state2 : 1; /* [2] */ ++ unsigned int audpath_intr_state3 : 1; /* [3] */ ++ unsigned int audpath_intr_state4 : 1; /* [4] */ ++ unsigned int audpath_intr_state5 : 1; /* [5] */ ++ unsigned int audpath_intr_state6 : 1; /* [6] */ ++ unsigned int audpath_intr_state7 : 1; /* [7] */ ++ unsigned int audpath_intr_state8 : 1; /* [8] */ ++ unsigned int rsv_24 : 23; /* [31:9] */ ++ } bits; ++ unsigned int u32; ++} audio_path_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int audpath_intr_mask0 : 1; /* [0] */ ++ unsigned int audpath_intr_mask1 : 1; /* [1] */ ++ unsigned int audpath_intr_mask2 : 1; /* [2] */ ++ unsigned int audpath_intr_mask3 : 1; /* [3] */ ++ unsigned int audpath_intr_mask4 : 1; /* [4] */ ++ unsigned int audpath_intr_mask5 : 1; /* [5] */ ++ unsigned int audpath_intr_mask6 : 1; /* [6] */ ++ unsigned int audpath_intr_mask7 : 1; /* [7] */ ++ unsigned int audpath_intr_mask8 : 1; /* [8] */ ++ unsigned int rsv_25 : 23; /* [31:9] */ ++ } bits; ++ unsigned int u32; ++} audio_path_intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int txhdmi_intr_state0 : 1; /* [0] */ ++ unsigned int rsv_26 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} txhdmi_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int txhdmi_intr_mask0 : 1; /* [0] */ ++ unsigned int rsv_27 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} txhdmi_intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int hdcp_intr_state0 : 1; /* [0] */ ++ unsigned int hdcp_intr_state1 : 1; /* [1] */ ++ unsigned int rsv_28 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} hdcp_intr_state; ++ ++typedef union { ++ struct { ++ unsigned int hdcp_intr_mask0 : 1; /* [0] */ ++ unsigned int hdcp_intr_mask1 : 1; /* [1] */ ++ unsigned int rsv_29 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} hdcp_intr_mask; ++ ++typedef struct { ++ unsigned int reserved_0[4]; /* 0-C */ ++ volatile tx_pwd_rst_ctrl pwd_rst_ctrl; /* 10 */ ++ volatile scdc_fsm_ctrl fsm_ctrl; /* 14 */ ++ volatile scdc_poll_timerl poll_timer; /* 18 */ ++ volatile scdc_fsm_state fsm_state; /* 1C */ ++ volatile scdc_flag_byte flag; /* 20 */ ++ unsigned int reserved_1[5]; /* 0-c */ ++ volatile pwd_fifo_rdata rdata; /* 38 */ ++ volatile pwd_fifo_wdata wdata; /* 3C */ ++ volatile pwd_data_cnt data_cnt; /* 40 */ ++ volatile pwd_slave_cfg slave_cfg; /* 44 */ ++ volatile pwd_mst_state mst_state; /* 48 */ ++ volatile pwd_mst_cmd mst_cmd; /* 4C */ ++ volatile pwd_mst_clr mst_clr; /* 50 */ ++ unsigned int reserved_2[4]; /* 54-60 */ ++ volatile ddc_mst_arb_ctrl ddc_arb_ctrl; /* 64 */ ++ volatile ddc_mst_arb_reql ddc_arb_req; /* 68 */ ++ volatile ddc_mst_arb_ack ddc_arb_ack; /* 6C */ ++ volatile ddc_mst_arb_state ddc_arb_state; /* 70 */ ++ unsigned int reserved_3[35]; /* 74-FC */ ++ volatile tx_pwd_intr_state pwd_irq_state; /* 100 */ ++ volatile pwd_sub_intr_state sub_irq_state; /* 104 */ ++ volatile pwd_sub_intr_mask sub_irq_mask; /* 108 */ ++ volatile txsys_intr_state sys_irq_state; /* 10C */ ++ volatile txsys_intr_mask sys_irq_mask; /* 110 */ ++ volatile video_path_intr_state video_irq_state; /* 114 */ ++ volatile video_path_intr_mask video_irq_mask; /* 118 */ ++ volatile audio_path_intr_state audio_irq_state; /* 11C */ ++ volatile audio_path_intr_mask audio_irq_mask; /* 120 */ ++ volatile txhdmi_intr_state hdmi_irq_state; /* 124 */ ++ volatile txhdmi_intr_mask hdmi_irq_mask; /* 128 */ ++ volatile hdcp_intr_state hdcp_irq_state; /* 12C */ ++ volatile hdcp_intr_mask hdcp_irq_mask; /* 130 */ ++} hdmi_reg_tx_ctrl; ++ ++int hdmi_reg_tx_ctrl_regs_init(const char *addr); ++int hdmi_reg_tx_ctrl_regs_deinit(void); ++void hdmi_reg_tx_afifo_srst_req_set(unsigned char tx_afifo_srst_req); ++void hdmi_reg_tx_acr_srst_req_set(unsigned char tx_acr_srst_req); ++void hdmi_reg_tx_aud_srst_req_set(unsigned char tx_aud_srst_req); ++void hdmi_reg_tx_hdmi_srst_req_set(unsigned char tx_hdmi_srst_req); ++void hdmi_reg_pwd_fifo_data_in_set(unsigned char pwd_fifo_data_in); ++void hdmi_reg_pwd_data_out_cnt_set(unsigned short pwd_data_out_cnt); ++void hdmi_reg_pwd_slave_addr_set(unsigned char pwd_slave_addr); ++void hdmi_reg_pwd_slave_offset_set(unsigned char pwd_slave_offset); ++void hdmi_reg_pwd_slave_seg_set(unsigned char pwd_slave_seg); ++void hdmi_reg_pwd_mst_cmd_set(unsigned char pwd_mst_cmd); ++void hdmi_reg_cpu_ddc_req_set(unsigned char cpu_ddc_req); ++unsigned char hdmi_reg_rdata_pwd_fifo_data_out_get(void); ++unsigned char hdmi_reg_pwd_fifo_data_out_get(void); ++unsigned char hdmi_reg_pwd_i2c_in_prog_get(void); ++unsigned char hdmi_reg_pwd_fifo_empty_get(void); ++unsigned char hdmi_reg_cpu_ddc_req_ack_get(void); ++#endif /* HDMI_REG_CTRL_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.c +new file mode 100755 +index 000000000..61b860359 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.c +@@ -0,0 +1,1352 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#include "hdmi_reg_tx.h" ++#include "hdmi_product_define.h" ++ ++volatile tx_hdmi_reg_regs_type *g_tx_hdmi_regs = NULL; ++ ++int hdmi_reg_tx_hdmi_regs_init(const char *addr) ++{ ++ g_tx_hdmi_regs = (volatile tx_hdmi_reg_regs_type *)(addr + HDMI_TX_BASE_ADDR_HDMITX); ++ return 0; ++} ++ ++int hdmi_reg_tx_hdmi_regs_deinit(void) ++{ ++ if (g_tx_hdmi_regs != NULL) { ++ g_tx_hdmi_regs = NULL; ++ } ++ return 0; ++} ++ ++void hdmi_reg_tmds_pack_mode_set(unsigned char tmds_pack_mode) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pack_fifo_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.tmds_pack_mode = tmds_pack_mode; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt_header_hb_set(unsigned char hb0, unsigned char hb1, unsigned char hb2) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_pkt_header tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_pkt_hb2 = hb2; ++ tmp.bits.avi_pkt_hb1 = hb1; ++ tmp.bits.avi_pkt_hb0 = hb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt0_low_set(unsigned char avi_pkt0_pb0, unsigned char avi_pkt0_pb1, unsigned char avi_pkt0_pb2, unsigned char avi_pkt0_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt0_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt0_pb3 = avi_pkt0_pb3; ++ tmp.bits.avi_sub_pkt0_pb2 = avi_pkt0_pb2; ++ tmp.bits.avi_sub_pkt0_pb1 = avi_pkt0_pb1; ++ tmp.bits.avi_sub_pkt0_pb0 = avi_pkt0_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt0_high_set(unsigned char avi_pkt0_pb4, unsigned char avi_pkt0_pb5, unsigned char avi_pkt0_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt0_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt0_pb6 = avi_pkt0_pb6; ++ tmp.bits.avi_sub_pkt0_pb5 = avi_pkt0_pb5; ++ tmp.bits.avi_sub_pkt0_pb4 = avi_pkt0_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt1_low_set(unsigned char avi_pkt1_pb0, ++ unsigned char avi_pkt1_pb1, unsigned char avi_pkt1_pb2, unsigned char avi_pkt1_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt1_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt1_pb3 = avi_pkt1_pb3; ++ tmp.bits.avi_sub_pkt1_pb2 = avi_pkt1_pb2; ++ tmp.bits.avi_sub_pkt1_pb1 = avi_pkt1_pb1; ++ tmp.bits.avi_sub_pkt1_pb0 = avi_pkt1_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt1_high_set(unsigned char avi_pkt1_pb4, unsigned char avi_pkt1_pb5, unsigned char avi_pkt1_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt1_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt1_pb6 = avi_pkt1_pb6; ++ tmp.bits.avi_sub_pkt1_pb5 = avi_pkt1_pb5; ++ tmp.bits.avi_sub_pkt1_pb4 = avi_pkt1_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt2_low_set(unsigned char avi_pkt2_pb0, ++ unsigned char avi_pkt2_pb1, unsigned char avi_pkt2_pb2, unsigned char avi_pkt2_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt2_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt2_pb3 = avi_pkt2_pb3; ++ tmp.bits.avi_sub_pkt2_pb2 = avi_pkt2_pb2; ++ tmp.bits.avi_sub_pkt2_pb1 = avi_pkt2_pb1; ++ tmp.bits.avi_sub_pkt2_pb0 = avi_pkt2_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt2_high_set(unsigned char avi_pkt2_pb4, unsigned char avi_pkt2_pb5, unsigned char avi_pkt2_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt2_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt2_pb6 = avi_pkt2_pb6; ++ tmp.bits.avi_sub_pkt2_pb5 = avi_pkt2_pb5; ++ tmp.bits.avi_sub_pkt2_pb4 = avi_pkt2_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt3_low_set(unsigned char avi_pkt3_pb0, unsigned char avi_pkt3_pb1, unsigned char avi_pkt3_pb2, ++ unsigned char avi_pkt3_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt3_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt3_pb3 = avi_pkt3_pb3; ++ tmp.bits.avi_sub_pkt3_pb2 = avi_pkt3_pb2; ++ tmp.bits.avi_sub_pkt3_pb1 = avi_pkt3_pb1; ++ tmp.bits.avi_sub_pkt3_pb0 = avi_pkt3_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt3_high_set(unsigned char avi_pkt3_pb4, unsigned char avi_pkt3_pb5, unsigned char avi_pkt3_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt3_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.avi_sub_pkt3_pb6 = avi_pkt3_pb6; ++ tmp.bits.avi_sub_pkt3_pb5 = avi_pkt3_pb5; ++ tmp.bits.avi_sub_pkt3_pb4 = avi_pkt3_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt_header_hb_get(avi_pkt_header *avi_header) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_pkt_header tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_header->bits.avi_pkt_hb2 = tmp.bits.avi_pkt_hb2; ++ avi_header->bits.avi_pkt_hb1 = tmp.bits.avi_pkt_hb1; ++ avi_header->bits.avi_pkt_hb0 = tmp.bits.avi_pkt_hb0; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt0_low_get(avi_sub_pkt0_low *avi_pkt0_low) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt0_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt0_low->bits.avi_sub_pkt0_pb3 = tmp.bits.avi_sub_pkt0_pb3; ++ avi_pkt0_low->bits.avi_sub_pkt0_pb2 = tmp.bits.avi_sub_pkt0_pb2; ++ avi_pkt0_low->bits.avi_sub_pkt0_pb1 = tmp.bits.avi_sub_pkt0_pb1; ++ avi_pkt0_low->bits.avi_sub_pkt0_pb0 = tmp.bits.avi_sub_pkt0_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt0_high_get(avi_sub_pkt0_high *avi_pkt0_high) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt0_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt0_high->bits.avi_sub_pkt0_pb6 = tmp.bits.avi_sub_pkt0_pb6; ++ avi_pkt0_high->bits.avi_sub_pkt0_pb5 = tmp.bits.avi_sub_pkt0_pb5; ++ avi_pkt0_high->bits.avi_sub_pkt0_pb4 = tmp.bits.avi_sub_pkt0_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt1_low_get(avi_sub_pkt1_low *avi_pkt1_low) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt1_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt1_low->bits.avi_sub_pkt1_pb3 = tmp.bits.avi_sub_pkt1_pb3; ++ avi_pkt1_low->bits.avi_sub_pkt1_pb2 = tmp.bits.avi_sub_pkt1_pb2; ++ avi_pkt1_low->bits.avi_sub_pkt1_pb1 = tmp.bits.avi_sub_pkt1_pb1; ++ avi_pkt1_low->bits.avi_sub_pkt1_pb0 = tmp.bits.avi_sub_pkt1_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt1_high_get(avi_sub_pkt1_high *avi_pkt1_h) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt1_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt1_h->bits.avi_sub_pkt1_pb6 = tmp.bits.avi_sub_pkt1_pb6; ++ avi_pkt1_h->bits.avi_sub_pkt1_pb5 = tmp.bits.avi_sub_pkt1_pb5; ++ avi_pkt1_h->bits.avi_sub_pkt1_pb4 = tmp.bits.avi_sub_pkt1_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt2_low_get(avi_sub_pkt2_low *avi_pkt2_l) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt2_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt2_l->bits.avi_sub_pkt2_pb3 = tmp.bits.avi_sub_pkt2_pb3; ++ avi_pkt2_l->bits.avi_sub_pkt2_pb2 = tmp.bits.avi_sub_pkt2_pb2; ++ avi_pkt2_l->bits.avi_sub_pkt2_pb1 = tmp.bits.avi_sub_pkt2_pb1; ++ avi_pkt2_l->bits.avi_sub_pkt2_pb0 = tmp.bits.avi_sub_pkt2_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt2_high_get(avi_sub_pkt2_high *avi_pkt2_h) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt2_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt2_h->bits.avi_sub_pkt2_pb6 = tmp.bits.avi_sub_pkt2_pb6; ++ avi_pkt2_h->bits.avi_sub_pkt2_pb5 = tmp.bits.avi_sub_pkt2_pb5; ++ avi_pkt2_h->bits.avi_sub_pkt2_pb4 = tmp.bits.avi_sub_pkt2_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt3_low_get(avi_sub_pkt3_low *avi_pkt3_low) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt3_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt3_low->bits.avi_sub_pkt3_pb3 = tmp.bits.avi_sub_pkt3_pb3; ++ avi_pkt3_low->bits.avi_sub_pkt3_pb2 = tmp.bits.avi_sub_pkt3_pb2; ++ avi_pkt3_low->bits.avi_sub_pkt3_pb1 = tmp.bits.avi_sub_pkt3_pb1; ++ avi_pkt3_low->bits.avi_sub_pkt3_pb0 = tmp.bits.avi_sub_pkt3_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_avi_pkt3_high_get(avi_sub_pkt3_high *avi_pkt3_high) ++{ ++ unsigned int *reg_addr = NULL; ++ avi_sub_pkt3_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ avi_pkt3_high->bits.avi_sub_pkt3_pb6 = tmp.bits.avi_sub_pkt3_pb6; ++ avi_pkt3_high->bits.avi_sub_pkt3_pb5 = tmp.bits.avi_sub_pkt3_pb5; ++ avi_pkt3_high->bits.avi_sub_pkt3_pb4 = tmp.bits.avi_sub_pkt3_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_pkt_header tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_pkt_hb2 = hb2; ++ tmp.bits.aif_pkt_hb1 = hb1; ++ tmp.bits.aif_pkt_hb0 = hb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt0_low_set(unsigned char audio_pkt0_pb0, ++ unsigned char audio_pkt0_pb1, unsigned char audio_pkt0_pb2, unsigned char audio_pkt0_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt0_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt0_pb3 = audio_pkt0_pb3; ++ tmp.bits.aif_sub_pkt0_pb2 = audio_pkt0_pb2; ++ tmp.bits.aif_sub_pkt0_pb1 = audio_pkt0_pb1; ++ tmp.bits.aif_sub_pkt0_pb0 = audio_pkt0_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt0_high_set(unsigned char audio_pkt0_pb4, ++ unsigned char audio_pkt0_pb5, unsigned char audio_pkt0_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt0_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt0_pb6 = audio_pkt0_pb6; ++ tmp.bits.aif_sub_pkt0_pb5 = audio_pkt0_pb5; ++ tmp.bits.aif_sub_pkt0_pb4 = audio_pkt0_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt1_low_set(unsigned char audio_pkt1_pb0, ++ unsigned char audio_pkt1_pb1, unsigned char audio_pkt1_pb2, unsigned char audio_pkt1_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt1_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt1_pb3 = audio_pkt1_pb3; ++ tmp.bits.aif_sub_pkt1_pb2 = audio_pkt1_pb2; ++ tmp.bits.aif_sub_pkt1_pb1 = audio_pkt1_pb1; ++ tmp.bits.aif_sub_pkt1_pb0 = audio_pkt1_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt1_high_set(unsigned char audio_pkt1_pb4, ++ unsigned char audio_pkt1_pb5, unsigned char audio_pkt1_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt1_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt1_pb6 = audio_pkt1_pb6; ++ tmp.bits.aif_sub_pkt1_pb5 = audio_pkt1_pb5; ++ tmp.bits.aif_sub_pkt1_pb4 = audio_pkt1_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt2_low_set(unsigned char audio_pkt2_pb0, ++ unsigned char audio_pkt2_pb1, unsigned char audio_pkt2_pb2, unsigned char audio_pkt2_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt2_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt2_pb3 = audio_pkt2_pb3; ++ tmp.bits.aif_sub_pkt2_pb2 = audio_pkt2_pb2; ++ tmp.bits.aif_sub_pkt2_pb1 = audio_pkt2_pb1; ++ tmp.bits.aif_sub_pkt2_pb0 = audio_pkt2_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt2_high_set(unsigned char audio_pkt2_pb4, ++ unsigned char audio_pkt2_pb5, unsigned char audio_pkt2_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt2_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt2_pb6 = audio_pkt2_pb6; ++ tmp.bits.aif_sub_pkt2_pb5 = audio_pkt2_pb5; ++ tmp.bits.aif_sub_pkt2_pb4 = audio_pkt2_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt3_low_set(unsigned char audio_pkt3_pb0, ++ unsigned char audio_pkt3_pb1, unsigned char audio_pkt3_pb2, unsigned char audio_pkt3_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt3_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt3_pb3 = audio_pkt3_pb3; ++ tmp.bits.aif_sub_pkt3_pb2 = audio_pkt3_pb2; ++ tmp.bits.aif_sub_pkt3_pb1 = audio_pkt3_pb1; ++ tmp.bits.aif_sub_pkt3_pb0 = audio_pkt3_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_audio_pkt3_high_set(unsigned char audio_pkt3_pb4, ++ unsigned char audio_pkt3_pb5, unsigned char audio_pkt3_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt3_high tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.aif_sub_pkt3_pb6 = audio_pkt3_pb6; ++ tmp.bits.aif_sub_pkt3_pb5 = audio_pkt3_pb5; ++ tmp.bits.aif_sub_pkt3_pb4 = audio_pkt3_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt_header_get(aif_pkt_header *aif_header) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_pkt_header tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_header->bits.aif_pkt_hb2 = tmp.bits.aif_pkt_hb2; ++ aif_header->bits.aif_pkt_hb1 = tmp.bits.aif_pkt_hb1; ++ aif_header->bits.aif_pkt_hb0 = tmp.bits.aif_pkt_hb0; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt0_low_get(aif_sub_pkt0_low *aif_pkt0_low) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt0_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt0_low->bits.aif_sub_pkt0_pb3 = tmp.bits.aif_sub_pkt0_pb3; ++ aif_pkt0_low->bits.aif_sub_pkt0_pb2 = tmp.bits.aif_sub_pkt0_pb2; ++ aif_pkt0_low->bits.aif_sub_pkt0_pb1 = tmp.bits.aif_sub_pkt0_pb1; ++ aif_pkt0_low->bits.aif_sub_pkt0_pb0 = tmp.bits.aif_sub_pkt0_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt0_high_get(aif_sub_pkt0_high *aif_pkt0_high) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt0_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt0_high->bits.aif_sub_pkt0_pb6 = tmp.bits.aif_sub_pkt0_pb6; ++ aif_pkt0_high->bits.aif_sub_pkt0_pb5 = tmp.bits.aif_sub_pkt0_pb5; ++ aif_pkt0_high->bits.aif_sub_pkt0_pb4 = tmp.bits.aif_sub_pkt0_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt1_low_get(aif_sub_pkt1_low *aif_pkt1_low) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt1_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt1_low->bits.aif_sub_pkt1_pb3 = tmp.bits.aif_sub_pkt1_pb3; ++ aif_pkt1_low->bits.aif_sub_pkt1_pb2 = tmp.bits.aif_sub_pkt1_pb2; ++ aif_pkt1_low->bits.aif_sub_pkt1_pb1 = tmp.bits.aif_sub_pkt1_pb1; ++ aif_pkt1_low->bits.aif_sub_pkt1_pb0 = tmp.bits.aif_sub_pkt1_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt1_high_get(aif_sub_pkt1_high *aif_pkt1_high) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt1_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt1_high->bits.aif_sub_pkt1_pb6 = tmp.bits.aif_sub_pkt1_pb6; ++ aif_pkt1_high->bits.aif_sub_pkt1_pb5 = tmp.bits.aif_sub_pkt1_pb5; ++ aif_pkt1_high->bits.aif_sub_pkt1_pb4 = tmp.bits.aif_sub_pkt1_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt2_low_get(aif_sub_pkt2_low *aif_pkt2_low) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt2_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt2_low->bits.aif_sub_pkt2_pb3 = tmp.bits.aif_sub_pkt2_pb3; ++ aif_pkt2_low->bits.aif_sub_pkt2_pb2 = tmp.bits.aif_sub_pkt2_pb2; ++ aif_pkt2_low->bits.aif_sub_pkt2_pb1 = tmp.bits.aif_sub_pkt2_pb1; ++ aif_pkt2_low->bits.aif_sub_pkt2_pb0 = tmp.bits.aif_sub_pkt2_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt2_high_get(aif_sub_pkt2_high *aif_pkt2_high) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt2_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt2_high->bits.aif_sub_pkt2_pb6 = tmp.bits.aif_sub_pkt2_pb6; ++ aif_pkt2_high->bits.aif_sub_pkt2_pb5 = tmp.bits.aif_sub_pkt2_pb5; ++ aif_pkt2_high->bits.aif_sub_pkt2_pb4 = tmp.bits.aif_sub_pkt2_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt3_low_get(aif_sub_pkt3_low *aif_pkt3_low) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt3_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt3_low->bits.aif_sub_pkt3_pb3 = tmp.bits.aif_sub_pkt3_pb3; ++ aif_pkt3_low->bits.aif_sub_pkt3_pb2 = tmp.bits.aif_sub_pkt3_pb2; ++ aif_pkt3_low->bits.aif_sub_pkt3_pb1 = tmp.bits.aif_sub_pkt3_pb1; ++ aif_pkt3_low->bits.aif_sub_pkt3_pb0 = tmp.bits.aif_sub_pkt3_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_aif_pkt3_high_get(aif_sub_pkt3_high *aif_pkt3_high) ++{ ++ unsigned int *reg_addr = NULL; ++ aif_sub_pkt3_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ aif_pkt3_high->bits.aif_sub_pkt3_pb6 = tmp.bits.aif_sub_pkt3_pb6; ++ aif_pkt3_high->bits.aif_sub_pkt3_pb5 = tmp.bits.aif_sub_pkt3_pb5; ++ aif_pkt3_high->bits.aif_sub_pkt3_pb4 = tmp.bits.aif_sub_pkt3_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt_header_get(gamut_pkt_header *gamut_header) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_pkt_header tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_header->bits.gamut_pkt_hb2 = tmp.bits.gamut_pkt_hb2; ++ gamut_header->bits.gamut_pkt_hb1 = tmp.bits.gamut_pkt_hb1; ++ gamut_header->bits.gamut_pkt_hb0 = tmp.bits.gamut_pkt_hb0; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt0_low_get(gamut_sub_pkt0_low *gamut_pkt0_low) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt0_low tmp; ++ ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt0_low->bits.gamut_sub_pkt0_pb3 = tmp.bits.gamut_sub_pkt0_pb3; ++ gamut_pkt0_low->bits.gamut_sub_pkt0_pb2 = tmp.bits.gamut_sub_pkt0_pb2; ++ gamut_pkt0_low->bits.gamut_sub_pkt0_pb1 = tmp.bits.gamut_sub_pkt0_pb1; ++ gamut_pkt0_low->bits.gamut_sub_pkt0_pb0 = tmp.bits.gamut_sub_pkt0_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt0_high_get(gamut_sub_pkt0_high *gamut_pkt0_high) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt0_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt0_high->bits.gamut_sub_pkt0_pb6 = tmp.bits.gamut_sub_pkt0_pb6; ++ gamut_pkt0_high->bits.gamut_sub_pkt0_pb5 = tmp.bits.gamut_sub_pkt0_pb5; ++ gamut_pkt0_high->bits.gamut_sub_pkt0_pb4 = tmp.bits.gamut_sub_pkt0_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt1_low_get(gamut_sub_pkt1_low *gamut_pkt1_low) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt1_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt1_low->bits.gamut_sub_pkt1_pb3 = tmp.bits.gamut_sub_pkt1_pb3; ++ gamut_pkt1_low->bits.gamut_sub_pkt1_pb2 = tmp.bits.gamut_sub_pkt1_pb2; ++ gamut_pkt1_low->bits.gamut_sub_pkt1_pb1 = tmp.bits.gamut_sub_pkt1_pb1; ++ gamut_pkt1_low->bits.gamut_sub_pkt1_pb0 = tmp.bits.gamut_sub_pkt1_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt1_high_get(gamut_sub_pkt1_high *gamut_pkt1_high) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt1_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt1_high->bits.gamut_sub_pkt1_pb6 = tmp.bits.gamut_sub_pkt1_pb6; ++ gamut_pkt1_high->bits.gamut_sub_pkt1_pb5 = tmp.bits.gamut_sub_pkt1_pb5; ++ gamut_pkt1_high->bits.gamut_sub_pkt1_pb4 = tmp.bits.gamut_sub_pkt1_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt2_low_get(gamut_sub_pkt2_low *gamut_pkt2_low) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt2_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt2_low->bits.gamut_sub_pkt2_pb3 = tmp.bits.gamut_sub_pkt2_pb3; ++ gamut_pkt2_low->bits.gamut_sub_pkt2_pb2 = tmp.bits.gamut_sub_pkt2_pb2; ++ gamut_pkt2_low->bits.gamut_sub_pkt2_pb1 = tmp.bits.gamut_sub_pkt2_pb1; ++ gamut_pkt2_low->bits.gamut_sub_pkt2_pb0 = tmp.bits.gamut_sub_pkt2_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt2_high_get(gamut_sub_pkt2_high *gamut_pkt2_high) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt2_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt2_high->bits.gamut_sub_pkt2_pb6 = tmp.bits.gamut_sub_pkt2_pb6; ++ gamut_pkt2_high->bits.gamut_sub_pkt2_pb5 = tmp.bits.gamut_sub_pkt2_pb5; ++ gamut_pkt2_high->bits.gamut_sub_pkt2_pb4 = tmp.bits.gamut_sub_pkt2_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt3_low_get(gamut_sub_pkt3_low *gamut_pkt3_low) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt3_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt3_low->bits.gamut_sub_pkt3_pb3 = tmp.bits.gamut_sub_pkt3_pb3; ++ gamut_pkt3_low->bits.gamut_sub_pkt3_pb2 = tmp.bits.gamut_sub_pkt3_pb2; ++ gamut_pkt3_low->bits.gamut_sub_pkt3_pb1 = tmp.bits.gamut_sub_pkt3_pb1; ++ gamut_pkt3_low->bits.gamut_sub_pkt3_pb0 = tmp.bits.gamut_sub_pkt3_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_gamut_pkt3_high_get(gamut_sub_pkt3_high *gamut_pkt3_high) ++{ ++ unsigned int *reg_addr = NULL; ++ gamut_sub_pkt3_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ gamut_pkt3_high->bits.gamut_sub_pkt3_pb6 = tmp.bits.gamut_sub_pkt3_pb6; ++ gamut_pkt3_high->bits.gamut_sub_pkt3_pb5 = tmp.bits.gamut_sub_pkt3_pb5; ++ gamut_pkt3_high->bits.gamut_sub_pkt3_pb4 = tmp.bits.gamut_sub_pkt3_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_pkt_header tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_pkt_hb2 = hb2; ++ tmp.bits.vsif_pkt_hb1 = hb1; ++ tmp.bits.vsif_pkt_hb0 = hb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt0_low_set(unsigned char vsif_pkt0_pb0, ++ unsigned char vsif_pkt0_pb1, unsigned char vsif_pkt0_pb2, unsigned char vsif_pkt0_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt0_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt0_pb3 = vsif_pkt0_pb3; ++ tmp.bits.vsif_sub_pkt0_pb2 = vsif_pkt0_pb2; ++ tmp.bits.vsif_sub_pkt0_pb1 = vsif_pkt0_pb1; ++ tmp.bits.vsif_sub_pkt0_pb0 = vsif_pkt0_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt0_high_set(unsigned char vsif_pkt0_pb4, unsigned char vsif_pkt0_pb5, unsigned char vsif_pkt0_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt0_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt0_pb6 = vsif_pkt0_pb6; ++ tmp.bits.vsif_sub_pkt0_pb5 = vsif_pkt0_pb5; ++ tmp.bits.vsif_sub_pkt0_pb4 = vsif_pkt0_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt1_low_set(unsigned char vsif_pkt1_pb0, ++ unsigned char vsif_pkt1_pb1, unsigned char vsif_pkt1_pb2, unsigned char vsif_pkt1_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt1_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt1_pb3 = vsif_pkt1_pb3; ++ tmp.bits.vsif_sub_pkt1_pb2 = vsif_pkt1_pb2; ++ tmp.bits.vsif_sub_pkt1_pb1 = vsif_pkt1_pb1; ++ tmp.bits.vsif_sub_pkt1_pb0 = vsif_pkt1_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt1_high_set(unsigned char vsif_pkt1_pb4, unsigned char vsif_pkt1_pb5, unsigned char vsif_pkt1_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt1_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt1_pb6 = vsif_pkt1_pb6; ++ tmp.bits.vsif_sub_pkt1_pb5 = vsif_pkt1_pb5; ++ tmp.bits.vsif_sub_pkt1_pb4 = vsif_pkt1_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt2_low_set(unsigned char vsif_pkt2_pb0, ++ unsigned char vsif_pkt2_pb1, unsigned char vsif_pkt2_pb2, unsigned char vsif_pkt2_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt2_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt2_pb3 = vsif_pkt2_pb3; ++ tmp.bits.vsif_sub_pkt2_pb2 = vsif_pkt2_pb2; ++ tmp.bits.vsif_sub_pkt2_pb1 = vsif_pkt2_pb1; ++ tmp.bits.vsif_sub_pkt2_pb0 = vsif_pkt2_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt2_high_set(unsigned char vsif_pkt2_pb4, unsigned char vsif_pkt2_pb5, unsigned char vsif_pkt2_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt2_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt2_pb6 = vsif_pkt2_pb6; ++ tmp.bits.vsif_sub_pkt2_pb5 = vsif_pkt2_pb5; ++ tmp.bits.vsif_sub_pkt2_pb4 = vsif_pkt2_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt3_low_set(unsigned char vsif_pkt3_pb0, ++ unsigned char vsif_pkt3_pb1, unsigned char vsif_pkt3_pb2, unsigned char vsif_pkt3_pb3) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt3_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt3_pb3 = vsif_pkt3_pb3; ++ tmp.bits.vsif_sub_pkt3_pb2 = vsif_pkt3_pb2; ++ tmp.bits.vsif_sub_pkt3_pb1 = vsif_pkt3_pb1; ++ tmp.bits.vsif_sub_pkt3_pb0 = vsif_pkt3_pb0; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt3_high_set(unsigned char vsif_pkt3_pb4, unsigned char vsif_pkt3_pb5, unsigned char vsif_pkt3_pb6) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt3_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.vsif_sub_pkt3_pb6 = vsif_pkt3_pb6; ++ tmp.bits.vsif_sub_pkt3_pb5 = vsif_pkt3_pb5; ++ tmp.bits.vsif_sub_pkt3_pb4 = vsif_pkt3_pb4; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_avi_rpt_en_set(unsigned char cea_avi_rpt_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avi_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_avi_rpt_en = cea_avi_rpt_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_avi_en_set(unsigned char cea_avi_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avi_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_avi_en = cea_avi_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt_header_get(vsif_pkt_header *vsif_header) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_pkt_header tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt_head.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_header->bits.vsif_pkt_hb2 = tmp.bits.vsif_pkt_hb2; ++ vsif_header->bits.vsif_pkt_hb1 = tmp.bits.vsif_pkt_hb1; ++ vsif_header->bits.vsif_pkt_hb0 = tmp.bits.vsif_pkt_hb0; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt0_low_get(vsif_sub_pkt0_low *vsif_pkt0_low) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt0_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt0_low->bits.vsif_sub_pkt0_pb3 = tmp.bits.vsif_sub_pkt0_pb3; ++ vsif_pkt0_low->bits.vsif_sub_pkt0_pb2 = tmp.bits.vsif_sub_pkt0_pb2; ++ vsif_pkt0_low->bits.vsif_sub_pkt0_pb1 = tmp.bits.vsif_sub_pkt0_pb1; ++ vsif_pkt0_low->bits.vsif_sub_pkt0_pb0 = tmp.bits.vsif_sub_pkt0_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt0_high_get(vsif_sub_pkt0_high *vsif_pkt0_high) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt0_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt0_high->bits.vsif_sub_pkt0_pb6 = tmp.bits.vsif_sub_pkt0_pb6; ++ vsif_pkt0_high->bits.vsif_sub_pkt0_pb5 = tmp.bits.vsif_sub_pkt0_pb5; ++ vsif_pkt0_high->bits.vsif_sub_pkt0_pb4 = tmp.bits.vsif_sub_pkt0_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt1_low_get(vsif_sub_pkt1_low *vsif_pkt1_low) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt1_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt1_low->bits.vsif_sub_pkt1_pb3 = tmp.bits.vsif_sub_pkt1_pb3; ++ vsif_pkt1_low->bits.vsif_sub_pkt1_pb2 = tmp.bits.vsif_sub_pkt1_pb2; ++ vsif_pkt1_low->bits.vsif_sub_pkt1_pb1 = tmp.bits.vsif_sub_pkt1_pb1; ++ vsif_pkt1_low->bits.vsif_sub_pkt1_pb0 = tmp.bits.vsif_sub_pkt1_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt1_high_get(vsif_sub_pkt1_high *vsif_pkt1_high) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt1_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt1_high->bits.vsif_sub_pkt1_pb6 = tmp.bits.vsif_sub_pkt1_pb6; ++ vsif_pkt1_high->bits.vsif_sub_pkt1_pb5 = tmp.bits.vsif_sub_pkt1_pb5; ++ vsif_pkt1_high->bits.vsif_sub_pkt1_pb4 = tmp.bits.vsif_sub_pkt1_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt2_low_get(vsif_sub_pkt2_low *vsif_pkt2_low) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt2_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt2_low->bits.vsif_sub_pkt2_pb3 = tmp.bits.vsif_sub_pkt2_pb3; ++ vsif_pkt2_low->bits.vsif_sub_pkt2_pb2 = tmp.bits.vsif_sub_pkt2_pb2; ++ vsif_pkt2_low->bits.vsif_sub_pkt2_pb1 = tmp.bits.vsif_sub_pkt2_pb1; ++ vsif_pkt2_low->bits.vsif_sub_pkt2_pb0 = tmp.bits.vsif_sub_pkt2_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt2_high_get(vsif_sub_pkt2_high *vsif_pkt2_high) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt2_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt2_high->bits.vsif_sub_pkt2_pb6 = tmp.bits.vsif_sub_pkt2_pb6; ++ vsif_pkt2_high->bits.vsif_sub_pkt2_pb5 = tmp.bits.vsif_sub_pkt2_pb5; ++ vsif_pkt2_high->bits.vsif_sub_pkt2_pb4 = tmp.bits.vsif_sub_pkt2_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt3_low_get(vsif_sub_pkt3_low *vsif_pkt3_low) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt3_low tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3l.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt3_low->bits.vsif_sub_pkt3_pb3 = tmp.bits.vsif_sub_pkt3_pb3; ++ vsif_pkt3_low->bits.vsif_sub_pkt3_pb2 = tmp.bits.vsif_sub_pkt3_pb2; ++ vsif_pkt3_low->bits.vsif_sub_pkt3_pb1 = tmp.bits.vsif_sub_pkt3_pb1; ++ vsif_pkt3_low->bits.vsif_sub_pkt3_pb0 = tmp.bits.vsif_sub_pkt3_pb0; ++ ++ return; ++} ++ ++void hdmi_reg_vsif_pkt3_high_get(vsif_sub_pkt3_high *vsif_pkt3_high) ++{ ++ unsigned int *reg_addr = NULL; ++ vsif_sub_pkt3_high tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3h.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ vsif_pkt3_high->bits.vsif_sub_pkt3_pb6 = tmp.bits.vsif_sub_pkt3_pb6; ++ vsif_pkt3_high->bits.vsif_sub_pkt3_pb5 = tmp.bits.vsif_sub_pkt3_pb5; ++ vsif_pkt3_high->bits.vsif_sub_pkt3_pb4 = tmp.bits.vsif_sub_pkt3_pb4; ++ ++ return; ++} ++ ++void hdmi_reg_cea_aud_rpt_en_set(unsigned char cea_aud_rpt_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_aud_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aud_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_aud_rpt_en = cea_aud_rpt_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_aud_en_set(unsigned char cea_aud_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_aud_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aud_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_aud_en = cea_aud_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_cp_rpt_cnt_set(unsigned char cea_cp_rpt_cnt) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_cp_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_cp_rpt_cnt = cea_cp_rpt_cnt; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_cp_rpt_en_set(unsigned char cea_cp_rpt_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_cp_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_cp_rpt_en = cea_cp_rpt_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_cp_en_set(unsigned char cea_cp_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_cp_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_cp_en = cea_cp_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_vsif_rpt_en_set(unsigned char cea_vsif_rpt_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_vsif_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_vsif_rpt_en = cea_vsif_rpt_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cea_vsif_en_set(unsigned char cea_vsif_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_vsif_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cea_vsif_en = cea_vsif_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dc_pkt_en_set(unsigned char dc_pkt_en) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avmixer_config tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.dc_pkt_en = dc_pkt_en; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_hdmi_mode_set(unsigned char hdmi_mode) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avmixer_config tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.hdmi_mode = hdmi_mode; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cp_clr_avmute_set(unsigned char cp_clr_avmute) ++{ ++ unsigned int *reg_addr = NULL; ++ cp_pkt_avmute tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pkt_avmute.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cp_clr_avmute = cp_clr_avmute; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_cp_set_avmute_set(unsigned char cp_set_avmute) ++{ ++ unsigned int *reg_addr = NULL; ++ cp_pkt_avmute tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pkt_avmute.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.cp_set_avmute = cp_set_avmute; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_enc_bypass_set(unsigned char enc_bypass) ++{ ++ unsigned int *reg_addr = NULL; ++ hdmi_enc_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.enc_bypass = enc_bypass; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_enc_scr_on_set(unsigned char enc_scr_on) ++{ ++ unsigned int *reg_addr = NULL; ++ hdmi_enc_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.enc_scr_on = enc_scr_on; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_enc_hdmi2_on_set(unsigned char enc_hdmi2_on) ++{ ++ unsigned int *reg_addr = NULL; ++ hdmi_enc_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ tmp.bits.enc_hdmi2_on = enc_hdmi2_on; ++ hdmi_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_tmds_pack_mode_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pack_fifo_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.tmds_pack_mode; ++} ++ ++unsigned char hdmi_reg_pclk2tclk_stable_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_pack_fifo_st tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pack_fifo_status.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.pclk2tclk_stable; ++} ++ ++unsigned char hdmi_reg_cea_avi_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avi_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.cea_avi_en; ++} ++ ++unsigned char hdmi_reg_cea_aud_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_aud_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aud_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.cea_aud_en; ++} ++ ++unsigned char hdmi_reg_cea_cp_rpt_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_cp_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.cea_cp_rpt_en; ++} ++ ++unsigned char hdmi_reg_cea_gamut_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_gamut_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.cea_gamut_en; ++} ++ ++unsigned char hdmi_reg_cea_vsif_rpt_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_vsif_cfg tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.cea_vsif_rpt_en; ++} ++ ++unsigned char hdmi_reg_dc_pkt_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avmixer_config tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.dc_pkt_en; ++} ++ ++unsigned char hdmi_reg_hdmi_mode_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cea_avmixer_config tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.hdmi_mode; ++} ++ ++unsigned char hdmi_reg_cp_set_avmute_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ cp_pkt_avmute tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pkt_avmute.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.cp_set_avmute; ++} ++ ++unsigned char hdmi_reg_enc_scr_on_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ hdmi_enc_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.enc_scr_on; ++} ++ ++unsigned char hdmi_reg_enc_hdmi2_on_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ hdmi_enc_ctrl tmp; ++ ++ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.enc_hdmi2_on; ++} ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.h +new file mode 100755 +index 000000000..0062af92e +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.h +@@ -0,0 +1,1482 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef HHDMI_REG_TX_H ++#define HHDMI_REG_TX_H ++ ++ ++typedef union { ++ struct { ++ unsigned int tmds_pack_mode : 2; /* [1:0] */ ++ unsigned int reg_fifo_auto_rst_en : 1; /* [2] */ ++ unsigned int reg_fifo_manu_rst : 1; /* [3] */ ++ unsigned int reg_clock_det_en : 1; /* [4] */ ++ unsigned int reg_ext_tmds_para : 1; /* [5] */ ++ unsigned int rsv_0 : 2; /* [7:6] */ ++ unsigned int reg_fifo_delay_cnt : 8; /* [15:8] */ ++ unsigned int rsv_1 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} tx_pack_fifo_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int pclk2tclk_stable : 1; /* [0] */ ++ unsigned int rsv_2 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} tx_pack_fifo_st; ++ ++typedef union { ++ struct { ++ unsigned int reg_pclk_refer_cnt : 18; /* [17:0] */ ++ unsigned int rsv_3 : 14; /* [31:18] */ ++ } bits; ++ unsigned int u32; ++} pclk_refer_cnt; ++ ++typedef union { ++ struct { ++ unsigned int reg_tcnt_lower_threshold : 18; /* [17:0] */ ++ unsigned int rsv_4 : 14; /* [31:18] */ ++ } bits; ++ unsigned int u32; ++} tclk_lower_threshold; ++ ++typedef union { ++ struct { ++ unsigned int reg_tcnt_upper_threshold : 18; /* [17:0] */ ++ unsigned int rsv_5 : 14; /* [31:18] */ ++ } bits; ++ unsigned int u32; ++} tclk_upper_threshold; ++ ++typedef union { ++ struct { ++ unsigned int avi_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int avi_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int avi_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_6 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int avi_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_7 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int avi_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_8 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int avi_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_9 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int avi_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int avi_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int avi_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int avi_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_10 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} avi_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int aif_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int aif_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int aif_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_11 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int aif_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_12 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int aif_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_13 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int aif_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_14 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int aif_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int aif_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int aif_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int aif_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_15 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} aif_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int spd_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int spd_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int spd_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_16 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int spd_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_17 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int spd_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_18 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int spd_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_19 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int spd_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int spd_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int spd_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int spd_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_20 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} spif_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int mpeg_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int mpeg_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_21 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} speg_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int mpeg_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} speg_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_22 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} speg_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int mpeg_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} speg_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_23 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} mpeg_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int mpeg_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} mpeg_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_24 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} mpeg_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int mpeg_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} mpeg_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int mpeg_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int mpeg_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int mpeg_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_25 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} mpeg_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int gen_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int gen_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int gen_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_26 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int gen_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_27 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int gen_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_28 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int gen_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_29 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int gen_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int gen_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int gen_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int gen_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_30 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int gen2_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int gen2_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int gen2_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_31 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int gen2_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_32 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int gen2_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_33 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int gen2_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_34 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int gen2_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int gen2_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int gen2_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int gen2_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_35 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen2_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int gen3_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int gen3_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int gen3_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_36 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int gen3_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_37 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int gen3_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_38 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int gen3_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_39 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int gen3_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int gen3_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int gen3_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int gen3_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_40 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen3_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int gen4_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int gen4_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int gen4_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_41 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int gen4_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_42 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int gen4_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_43 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int gen4_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_44 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int gen4_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int gen4_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int gen4_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int gen4_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_45 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen4_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int gen5_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int gen5_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int gen5_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_46 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int gen5_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_47 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int gen5_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_48 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int gen5_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_49 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int gen5_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int gen5_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int gen5_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int gen5_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_50 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gen5_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int gamut_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int gamut_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int gamut_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_51 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int gamut_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_52 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int gamut_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_53 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int gamut_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_54 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int gamut_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int gamut_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int gamut_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int gamut_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_55 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} gamut_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int vsif_pkt_hb0 : 8; /* [7:0] */ ++ unsigned int vsif_pkt_hb1 : 8; /* [15:8] */ ++ unsigned int vsif_pkt_hb2 : 8; /* [23:16] */ ++ unsigned int rsv_56 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_pkt_header; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt0_pb0 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt0_pb1 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt0_pb2 : 8; /* [23:16] */ ++ unsigned int vsif_sub_pkt0_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt0_low; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt0_pb4 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt0_pb5 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt0_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_57 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt0_high; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt1_pb0 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt1_pb1 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt1_pb2 : 8; /* [23:16] */ ++ unsigned int vsif_sub_pkt1_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt1_low; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt1_pb4 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt1_pb5 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt1_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_58 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt1_high; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt2_pb0 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt2_pb1 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt2_pb2 : 8; /* [23:16] */ ++ unsigned int vsif_sub_pkt2_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt2_low; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt2_pb4 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt2_pb5 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt2_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_59 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt2_high; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt3_pb0 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt3_pb1 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt3_pb2 : 8; /* [23:16] */ ++ unsigned int vsif_sub_pkt3_pb3 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt3_low; ++ ++typedef union { ++ struct { ++ unsigned int vsif_sub_pkt3_pb4 : 8; /* [7:0] */ ++ unsigned int vsif_sub_pkt3_pb5 : 8; /* [15:8] */ ++ unsigned int vsif_sub_pkt3_pb6 : 8; /* [23:16] */ ++ unsigned int rsv_60 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsif_sub_pkt3_high; ++ ++typedef union { ++ struct { ++ unsigned int cea_avi_en : 1; /* [0] */ ++ unsigned int cea_avi_rpt_en : 1; /* [1] */ ++ unsigned int rsv_61 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_avi_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_spf_en : 1; /* [0] */ ++ unsigned int cea_spf_rpt_en : 1; /* [1] */ ++ unsigned int rsv_62 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_spf_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_aud_en : 1; /* [0] */ ++ unsigned int cea_aud_rpt_en : 1; /* [1] */ ++ unsigned int rsv_63 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_aud_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_mpeg_en : 1; /* [0] */ ++ unsigned int cea_mpeg_rpt_en : 1; /* [1] */ ++ unsigned int rsv_64 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_mpeg_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_gen_en : 1; /* [0] */ ++ unsigned int cea_gen_rpt_en : 1; /* [1] */ ++ unsigned int rsv_65 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_gen_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_cp_en : 1; /* [0] */ ++ unsigned int cea_cp_rpt_en : 1; /* [1] */ ++ unsigned int cea_cp_rpt_cnt : 8; /* [2:7] */ ++ unsigned int rsv_66 : 22; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} cea_cp_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_gen2_en : 1; /* [0] */ ++ unsigned int cea_gen2_rpt_en : 1; /* [1] */ ++ unsigned int rsv_67 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_gen2_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_gen3_en : 1; /* [0] */ ++ unsigned int cea_gen3_rpt_en : 1; /* [1] */ ++ unsigned int rsv_68 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_gen3_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_gen4_en : 1; /* [0] */ ++ unsigned int cea_gen4_rpt_en : 1; /* [1] */ ++ unsigned int rsv_69 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_gen4_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_gen5_en : 1; /* [0] */ ++ unsigned int cea_gen5_rpt_en : 1; /* [1] */ ++ unsigned int rsv_70 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_gen5_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_gamut_en : 1; /* [0] */ ++ unsigned int cea_gamut_rpt_en : 1; /* [1] */ ++ unsigned int rsv_71 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_gamut_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_vsif_en : 1; /* [0] */ ++ unsigned int cea_vsif_rpt_en : 1; /* [1] */ ++ unsigned int rsv_72 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cea_vsif_cfg; ++ ++typedef union { ++ struct { ++ unsigned int cea_avi_state : 1; /* [0] */ ++ unsigned int cea_aud_state : 1; /* [1] */ ++ unsigned int cea_cp_state : 1; /* [2] */ ++ unsigned int cea_gen_state : 1; /* [3] */ ++ unsigned int cea_gen2_state : 1; /* [4] */ ++ unsigned int cea_gen3_state : 1; /* [5] */ ++ unsigned int cea_gen4_state : 1; /* [6] */ ++ unsigned int cea_gen5_state : 1; /* [7] */ ++ unsigned int cea_spd_state : 1; /* [8] */ ++ unsigned int cea_mpeg_state : 1; /* [9] */ ++ unsigned int cea_gamut_state : 1; /* [10] */ ++ unsigned int cea_vsif_state : 1; /* [11] */ ++ unsigned int rsv_73 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} cea_pktf_state; ++ ++typedef union { ++ struct { ++ unsigned int hdmi_mode : 1; /* [0] */ ++ unsigned int dc_pkt_en : 1; /* [1] */ ++ unsigned int null_pkt_en : 1; /* [2] */ ++ unsigned int null_pkt_en_vs_high : 1; /* [3] */ ++ unsigned int intr_encryption : 1; /* [4] */ ++ unsigned int ovr_dc_pkt_en : 1; /* [5] */ ++ unsigned int priotity_ctl : 1; /* [6] */ ++ unsigned int pkt_bypass_mode : 1; /* [7] */ ++ unsigned int avmute_in_phase : 1; /* [8] */ ++ unsigned int hdmi_dvi_sel : 1; /* [9] */ ++ unsigned int eess_mode_en : 1; /* [10] */ ++ unsigned int rsv_74 : 21; /* [31:11] */ ++ } bits; ++ unsigned int u32; ++} cea_avmixer_config; ++ ++typedef union { ++ struct { ++ unsigned int cp_set_avmute : 1; /* [0] */ ++ unsigned int cp_clr_avmute : 1; /* [1] */ ++ unsigned int rsv_75 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} cp_pkt_avmute; ++ ++typedef union { ++ struct { ++ unsigned int video_blank : 24; /* [23:0] */ ++ unsigned int rsv_76 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} video_blank_cfg; ++ ++typedef union { ++ struct { ++ unsigned int reg_tbist_en : 1; /* [0] */ ++ unsigned int reg_tbist_syn_pol : 2; /* [2:1] */ ++ unsigned int reg_tbist_timing_sel : 6; /* [8:3] */ ++ unsigned int reg_tbist_patt_sel : 5; /* [13:9] */ ++ unsigned int rsv_77 : 18; /* [31:14] */ ++ } bits; ++ unsigned int u32; ++} tmds_bist_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int enc_hdmi2_on : 1; /* [0] */ ++ unsigned int enc_scr_on : 1; /* [1] */ ++ unsigned int enc_scr_md : 1; /* [2] */ ++ unsigned int enc_hdmi_val : 1; /* [3] */ ++ unsigned int enc_hdmi_ovr : 1; /* [4] */ ++ unsigned int enc_bypass : 1; /* [5] */ ++ unsigned int enc_ck_div_sel : 2; /* [7:6] */ ++ unsigned int rsv_78 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} hdmi_enc_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int enc_ck_sharp0 : 10; /* [9:0] */ ++ unsigned int enc_ck_sharp1 : 10; /* [19:10] */ ++ unsigned int enc_ck_sharp2 : 10; /* [29:20] */ ++ unsigned int rsv_79 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} enc_ck_sharp; ++ ++typedef struct { ++ volatile tx_pack_fifo_ctrl pack_fifo_ctrl; /* 1800 */ ++ volatile tx_pack_fifo_st pack_fifo_status; /* 1804 */ ++ volatile pclk_refer_cnt pclk_ref_cnt; /* 1808 */ ++ volatile tclk_lower_threshold lower_threshold; /* 180C */ ++ volatile tclk_upper_threshold upper_threshold; /* 1810 */ ++ unsigned int reserved_0[1]; /* 1814 */ ++ volatile avi_pkt_header avi_head; /* 1818 */ ++ volatile avi_sub_pkt0_low avi_pkt0l; /* 181C */ ++ volatile avi_sub_pkt0_high avi_pkt0h; /* 1820 */ ++ volatile avi_sub_pkt1_low avi_pkt1l; /* 1824 */ ++ volatile avi_sub_pkt1_high avi_pkt1h; /* 1828 */ ++ volatile avi_sub_pkt1_low avi_pkt2l; /* 182C */ ++ volatile avi_sub_pkt2_high avi_pkt2h; /* 1830 */ ++ volatile avi_sub_pkt3_low avi_pkt3l; /* 1834 */ ++ volatile avi_sub_pkt3_high avi_pkt3h; /* 1838 */ ++ volatile aif_pkt_header aif_pkt_head; /* 183C */ ++ volatile aif_sub_pkt0_low aif_pkt0l; /* 1840 */ ++ volatile aif_sub_pkt0_high aif_pkt0h; /* 1844 */ ++ volatile aif_sub_pkt1_low aif_pkt1l; /* 1848 */ ++ volatile aif_sub_pkt1_high aif_pkt1h; /* 184C */ ++ volatile aif_sub_pkt2_low aif_pkt2l; /* 1850 */ ++ volatile aif_sub_pkt2_high aif_pkt2h; /* 1854 */ ++ volatile aif_sub_pkt3_low aif_pkt3l; /* 1858 */ ++ volatile aif_sub_pkt3_high aif_pkt3h; /* 185C */ ++ volatile spif_pkt_header spif_pkt_head; /* 1860 */ ++ volatile spif_sub_pkt0_low spif_pkt0l; /* 1864 */ ++ volatile spif_sub_pkt0_high spif_pkt0h; /* 1868 */ ++ volatile spif_sub_pkt1_low spif_pkt1l; /* 186C */ ++ volatile spif_sub_pkt1_high spif_pkt1h; /* 1870 */ ++ volatile spif_sub_pkt2_low spif_pkt2l; /* 1874 */ ++ volatile spif_sub_pkt2_high spif_pkt2h; /* 1878 */ ++ volatile spif_sub_pkt3_low spif_pkt3l; /* 187C */ ++ volatile spif_sub_pkt3_high spif_pkt3h; /* 1880 */ ++ volatile speg_pkt_header mpeg_pkt_head; /* 1884 */ ++ volatile speg_sub_pkt0_low mpeg_pkt0l; /* 1888 */ ++ volatile speg_sub_pkt0_high mpeg_pkt0h; /* 188C */ ++ volatile speg_sub_pkt1_low mpeg_pkt1l; /* 1890 */ ++ volatile mpeg_sub_pkt1_high mpeg_pkt1h; /* 1894 */ ++ volatile mpeg_sub_pkt2_low mpeg_pkt2l; /* 1898 */ ++ volatile mpeg_sub_pkt2_high mpeg_pkt2h; /* 189C */ ++ volatile mpeg_sub_pkt3_low mpeg_pkt3l; /* 18A0 */ ++ volatile mpeg_sub_pkt3_high mpeg_pkt3h; /* 18A4 */ ++ volatile gen_pkt_header gen_pkt_head; /* 18A8 */ ++ volatile gen_sub_pkt0_low gen_pkt0l; /* 18AC */ ++ volatile gen_sub_pkt0_high gen_pkt0h; /* 18B0 */ ++ volatile gen_sub_pkt1_low gen_pkt1l; /* 18B4 */ ++ volatile gen_sub_pkt1_high gen_pkt1h; /* 18B8 */ ++ volatile gen_sub_pkt2_low gen_pkt2l; /* 18BC */ ++ volatile gen_sub_pkt2_high gen_pkt2h; /* 18C0 */ ++ volatile gen_sub_pkt3_low gen_pkt3l; /* 18C4 */ ++ volatile gen_sub_pkt3_high gen_pkt3h; /* 18C8 */ ++ volatile gen2_pkt_header gen2_pkt_head; /* 18CC */ ++ volatile gen2_sub_pkt0_low gen2_pkt0l; /* 18D0 */ ++ volatile gen2_sub_pkt0_high gen2_pkt0h; /* 18D4 */ ++ volatile gen2_sub_pkt1_low gen2_pkt1l; /* 18D8 */ ++ volatile gen2_sub_pkt1_high gen2_pkt1h; /* 18DC */ ++ volatile gen2_sub_pkt2_low gen2_pkt2l; /* 18E0 */ ++ volatile gen2_sub_pkt2_high gen2_pkt2h; /* 18E4 */ ++ volatile gen2_sub_pkt3_low gen2_pkt3l; /* 18E8 */ ++ volatile gen2_sub_pkt3_high gen2_pkt3h; /* 18EC */ ++ volatile gen3_pkt_header gen3_pkt_head; /* 18F0 */ ++ volatile gen3_sub_pkt0_low gen3_pkt0l; /* 18F4 */ ++ volatile gen3_sub_pkt0_high gen3_pkt0h; /* 18F8 */ ++ volatile gen3_sub_pkt1_low gen3_pkt1l; /* 18FC */ ++ volatile gen3_sub_pkt1_high gen3_pkt1h; /* 1900 */ ++ volatile gen3_sub_pkt2_low gen3_pkt2l; /* 1904 */ ++ volatile gen3_sub_pkt2_high gen3_pkt2h; /* 1908 */ ++ volatile gen3_sub_pkt3_low gen3_pkt3l; /* 190C */ ++ volatile gen3_sub_pkt3_high gen3_pkt3h; /* 1910 */ ++ volatile gen4_pkt_header gen4_pkt_head; /* 1914 */ ++ volatile gen4_sub_pkt0_low gen4_pkt0l; /* 1918 */ ++ volatile gen4_sub_pkt0_high gen4_pkt0h; /* 191C */ ++ volatile gen4_sub_pkt1_low gen4_pkt1l; /* 1920 */ ++ volatile gen4_sub_pkt1_high gen4_pkt1h; /* 1924 */ ++ volatile gen4_sub_pkt2_low gen4_pkt2l; /* 1928 */ ++ volatile gen4_sub_pkt2_high gen4_pkt2h; /* 192C */ ++ volatile gen4_sub_pkt3_low gen4_pkt3l; /* 1930 */ ++ volatile gen4_sub_pkt3_high gen4_pkt3h; /* 1934 */ ++ volatile gen5_pkt_header gen5_pkt_head; /* 1938 */ ++ volatile gen5_sub_pkt0_low gen5_pkt0l; /* 193C */ ++ volatile gen5_sub_pkt0_high gen5_pkt0h; /* 1940 */ ++ volatile gen5_sub_pkt1_low gen5_pkt1l; /* 1944 */ ++ volatile gen5_sub_pkt1_high gen5_pkt1h; /* 1948 */ ++ volatile gen5_sub_pkt2_low gen5_pkt2l; /* 194C */ ++ volatile gen5_sub_pkt2_high gen5_pkt2h; /* 1950 */ ++ volatile gen5_sub_pkt3_low gen5_pkt3l; /* 1954 */ ++ volatile gen5_sub_pkt3_high gen5_pkt3h; /* 1958 */ ++ volatile gamut_pkt_header gamut_pkt_head; /* 195C */ ++ volatile gamut_sub_pkt0_low gamut_pkt0l; /* 1960 */ ++ volatile gamut_sub_pkt0_high gamut_pkt0h; /* 1964 */ ++ volatile gamut_sub_pkt1_low gamut_pkt1l; /* 1968 */ ++ volatile gamut_sub_pkt1_high gamut_pkt1h; /* 196C */ ++ volatile gamut_sub_pkt2_low gamut_pkt2l; /* 1970 */ ++ volatile gamut_sub_pkt2_high gamut_pkt2h; /* 1974 */ ++ volatile gamut_sub_pkt3_low gamut_pkt3l; /* 1978 */ ++ volatile gamut_sub_pkt3_high gamut_pkt3h; /* 197C */ ++ volatile vsif_pkt_header vsif_pkt_head; /* 1980 */ ++ volatile vsif_sub_pkt0_low vsif_pkt0l; /* 1984 */ ++ volatile vsif_sub_pkt0_high vsif_pkt0h; /* 1988 */ ++ volatile vsif_sub_pkt1_low vsif_pkt1l; /* 198C */ ++ volatile vsif_sub_pkt1_high vsif_pkt1h; /* 1990 */ ++ volatile vsif_sub_pkt2_low vsif_pkt2l; /* 1994 */ ++ volatile vsif_sub_pkt2_high vsif_pkt2h; /* 1998 */ ++ volatile vsif_sub_pkt3_low vsif_pkt3l; /* 199C */ ++ volatile vsif_sub_pkt3_high vsif_pkt3h; /* 19A0 */ ++ volatile cea_avi_cfg avi_cfg; /* 19A4 */ ++ volatile cea_spf_cfg spf_cfg; /* 19A8 */ ++ volatile cea_aud_cfg aud_cfg; /* 19AC */ ++ volatile cea_mpeg_cfg mpeg_cfg; /* 19B0 */ ++ volatile cea_gen_cfg gen_cfg; /* 19B4 */ ++ volatile cea_cp_cfg cp_cfg; /* 19B8 */ ++ volatile cea_gen2_cfg gen2_cfg; /* 19BC */ ++ volatile cea_gen3_cfg gen3_cfg; /* 19C0 */ ++ volatile cea_gen4_cfg gen4_cfg; /* 19C4 */ ++ volatile cea_gen5_cfg gen5_cfg; /* 19C8 */ ++ volatile cea_gamut_cfg gamut_cfg; /* 19CC */ ++ volatile cea_vsif_cfg vsif_cfg; /* 19D0 */ ++ unsigned int reserved_1[3]; /* 19D4-19DC */ ++ volatile cea_pktf_state pkt_stats; /* 19E0 */ ++ unsigned int reserved_2[9]; /* 19E4-1A04 */ ++ volatile cea_avmixer_config avmixer_cfg; /* 1A08 */ ++ volatile cp_pkt_avmute pkt_avmute; /* 1A0C */ ++ volatile video_blank_cfg vblank_cfg; /* 1A10 */ ++ unsigned int reserved_3[16]; /* 1A14-1A50 */ ++ volatile tmds_bist_ctrl bist_ctrl; /* 1A54 */ ++ unsigned int reserved_4[2]; /* 1A58-1A5C */ ++ volatile hdmi_enc_ctrl enc_ctrl; /* 1A60 */ ++ volatile enc_ck_sharp enc_sharp; /* 1A64 */ ++} tx_hdmi_reg_regs_type; ++ ++int hdmi_reg_tx_hdmi_regs_init(const char *addr); ++int hdmi_reg_tx_hdmi_regs_deinit(void); ++void hdmi_reg_tmds_pack_mode_set(unsigned char tmds_pack_mode); ++void hdmi_reg_avi_pkt_header_hb_set(unsigned char hb0, unsigned char hb1, unsigned char hb2); ++void hdmi_reg_avi_pkt0_low_set(unsigned char avi_pkt0_pb0, unsigned char avi_pkt0_pb1, unsigned char avi_pkt0_pb2, unsigned char avi_pkt0_pb3); ++void hdmi_reg_avi_pkt0_high_set(unsigned char avi_pkt0_pb4, unsigned char avi_pkt0_pb5, unsigned char avi_pkt0_pb6); ++void hdmi_reg_avi_pkt1_low_set(unsigned char avi_pkt1_pb0, unsigned char avi_pkt1_pb1, unsigned char avi_pkt1_pb2, unsigned char avi_pkt1_pb3); ++void hdmi_reg_avi_pkt1_high_set(unsigned char avi_pkt1_pb4, unsigned char avi_pkt1_pb5, unsigned char avi_pkt1_pb6); ++void hdmi_reg_avi_pkt2_low_set(unsigned char avi_pkt2_pb0, unsigned char avi_pkt2_pb1, unsigned char avi_pkt2_pb2, unsigned char avi_pkt2_pb3); ++void hdmi_reg_avi_pkt2_high_set(unsigned char avi_pkt2_pb4, unsigned char avi_pkt2_pb5, unsigned char avi_pkt2_pb6); ++void hdmi_reg_avi_pkt3_low_set(unsigned char avi_pkt3_pb0, unsigned char avi_pkt3_pb1, unsigned char avi_pkt3_pb2, unsigned char avi_pkt3_pb3); ++void hdmi_reg_avi_pkt3_high_set(unsigned char avi_pkt3_pb4, unsigned char avi_pkt3_pb5, unsigned char avi_pkt3_pb6); ++void hdmi_reg_avi_pkt_header_hb_get(avi_pkt_header *pkt_header); ++void hdmi_reg_avi_pkt0_low_get(avi_sub_pkt0_low *sub_pkt0_low); ++void hdmi_reg_avi_pkt0_high_get(avi_sub_pkt0_high *sub_pkt0_high); ++void hdmi_reg_avi_pkt1_low_get(avi_sub_pkt1_low *sub_pkt1_low); ++void hdmi_reg_avi_pkt1_high_get(avi_sub_pkt1_high *sub_pkt1_high); ++void hdmi_reg_avi_pkt2_low_get(avi_sub_pkt2_low *sub_pkt2_low); ++void hdmi_reg_avi_pkt2_high_get(avi_sub_pkt2_high *sub_pkt2_high); ++void hdmi_reg_avi_pkt3_low_get(avi_sub_pkt3_low *sub_pkt3_low); ++void hdmi_reg_avi_pkt3_high_get(avi_sub_pkt3_high *sub_pkt3_high); ++void hdmi_reg_audio_pkt_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2); ++void hdmi_reg_audio_pkt0_low_set(unsigned char avi_pkt0_pb0, unsigned char avi_pkt0_pb1, unsigned char avi_pkt0_pb2, unsigned char avi_pkt0_pb3); ++void hdmi_reg_audio_pkt0_high_set(unsigned char avi_pkt0_pb4, unsigned char avi_pkt0_pb5, unsigned char avi_pkt0_pb6); ++void hdmi_reg_audio_pkt1_low_set(unsigned char avi_pkt1_pb0, unsigned char avi_pkt1_pb1, unsigned char avi_pkt1_pb2, unsigned char avi_pkt1_pb3); ++void hdmi_reg_audio_pkt1_high_set(unsigned char avi_pkt1_pb4, unsigned char avi_pkt1_pb5, unsigned char avi_pkt1_pb6); ++void hdmi_reg_audio_pkt2_low_set(unsigned char avi_pkt2_pb0, unsigned char avi_pkt2_pb1, unsigned char avi_pkt2_pb2, unsigned char avi_pkt2_pb3); ++void hdmi_reg_audio_pkt2_high_set(unsigned char avi_pkt2_pb4, unsigned char avi_pkt2_pb5, unsigned char avi_pkt2_pb6); ++void hdmi_reg_audio_pkt3_low_set(unsigned char avi_pkt3_pb0, unsigned char avi_pkt3_pb1, unsigned char avi_pkt3_pb2, unsigned char avi_pkt3_pb3); ++void hdmi_reg_audio_pkt3_high_set(unsigned char avi_pkt3_pb4, unsigned char avi_pkt3_pb5, unsigned char avi_pkt3_pb6); ++void hdmi_reg_aif_pkt_header_get(aif_pkt_header *pkt_header); ++void hdmi_reg_aif_pkt0_low_get(aif_sub_pkt0_low *sub_pkt0_low); ++void hdmi_reg_aif_pkt0_high_get(aif_sub_pkt0_high *sub_pkt0_high); ++void hdmi_reg_aif_pkt1_low_get(aif_sub_pkt1_low *sub_pkt1_low); ++void hdmi_reg_aif_pkt1_high_get(aif_sub_pkt1_high *sub_pkt1_high); ++void hdmi_reg_aif_pkt2_low_get(aif_sub_pkt2_low *sub_pkt2_low); ++void hdmi_reg_aif_pkt2_high_get(aif_sub_pkt2_high *sub_pkt2_high); ++void hdmi_reg_aif_pkt3_low_get(aif_sub_pkt3_low *sub_pkt3_low); ++void hdmi_reg_aif_pkt3_high_get(aif_sub_pkt3_high *sub_pkt3_high); ++void hdmi_reg_gamut_pkt_header_get(gamut_pkt_header *pkt_header); ++void hdmi_reg_gamut_pkt0_low_get(gamut_sub_pkt0_low *sub_pkt0_low); ++void hdmi_reg_gamut_pkt0_high_get(gamut_sub_pkt0_high *sub_pkt0_high); ++void hdmi_reg_gamut_pkt1_low_get(gamut_sub_pkt1_low *sub_pkt1_low); ++void hdmi_reg_gamut_pkt1_high_get(gamut_sub_pkt1_high *sub_pkt1_high); ++void hdmi_reg_gamut_pkt2_low_get(gamut_sub_pkt2_low *sub_pkt2_low); ++void hdmi_reg_gamut_pkt2_high_get(gamut_sub_pkt2_high *sub_pkt2_high); ++void hdmi_reg_gamut_pkt3_low_get(gamut_sub_pkt3_low *sub_pkt3_low); ++void hdmi_reg_gamut_pkt3_high_get(gamut_sub_pkt3_high *sub_pkt3_high); ++void hdmi_reg_vsif_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2); ++void hdmi_reg_vsif_pkt0_low_set(unsigned char vsif_pkt0_pb0, unsigned char vsif_pkt0_pb1, unsigned char vsif_pkt0_pb2, unsigned char vsif_pkt0_pb3); ++void hdmi_reg_vsif_pkt0_high_set(unsigned char vsif_pkt0_pb4, unsigned char vsif_pkt0_pb5, unsigned char vsif_pkt0_pb6); ++void hdmi_reg_vsif_pkt1_low_set(unsigned char vsif_pkt1_pb0, unsigned char vsif_pkt1_pb1, unsigned char vsif_pkt1_pb2, unsigned char vsif_pkt1_pb3); ++void hdmi_reg_vsif_pkt1_high_set(unsigned char vsif_pkt1_pb4, unsigned char vsif_pkt1_pb5, unsigned char vsif_pkt1_pb6); ++void hdmi_reg_vsif_pkt2_low_set(unsigned char vsif_pkt2_pb0, unsigned char vsif_pkt2_pb1, unsigned char vsif_pkt2_pb2, unsigned char vsif_pkt2_pb3); ++void hdmi_reg_vsif_pkt2_high_set(unsigned char vsif_pkt2_pb4, unsigned char vsif_pkt2_pb5, unsigned char vsif_pkt2_pb6); ++void hdmi_reg_vsif_pkt3_low_set(unsigned char vsif_pkt3_pb0, unsigned char vsif_pkt3_pb1, unsigned char vsif_pkt3_pb2, unsigned char vsif_pkt3_pb3); ++void hdmi_reg_vsif_pkt3_high_set(unsigned char vsif_pkt3_pb4, unsigned char vsif_pkt3_pb5, unsigned char vsif_pkt3_pb6); ++void hdmi_reg_vsif_pkt_header_get(vsif_pkt_header *pkt_header); ++void hdmi_reg_vsif_pkt0_low_get(vsif_sub_pkt0_low *sub_pkt0_low); ++void hdmi_reg_vsif_pkt0_high_get(vsif_sub_pkt0_high *sub_pkt0_high); ++void hdmi_reg_vsif_pkt1_low_get(vsif_sub_pkt1_low *sub_pkt1_low); ++void hdmi_reg_vsif_pkt1_high_get(vsif_sub_pkt1_high *sub_pkt1_high); ++void hdmi_reg_vsif_pkt2_low_get(vsif_sub_pkt2_low *sub_pkt2_low); ++void hdmi_reg_vsif_pkt2_high_get(vsif_sub_pkt2_high *sub_pkt2_high); ++void hdmi_reg_vsif_pkt3_low_get(vsif_sub_pkt3_low *sub_pkt3_low); ++void hdmi_reg_vsif_pkt3_high_get(vsif_sub_pkt3_high *sub_pkt3_high); ++void hdmi_reg_cea_avi_en_set(unsigned char cea_avi_en); ++void hdmi_reg_cea_avi_rpt_en_set(unsigned char cea_avi_rpt_en); ++void hdmi_reg_cea_aud_en_set(unsigned char cea_aud_en); ++void hdmi_reg_cea_aud_rpt_en_set(unsigned char cea_aud_rpt_en); ++void hdmi_reg_cea_cp_en_set(unsigned char cea_cp_en); ++void hdmi_reg_cea_cp_rpt_cnt_set(unsigned char cea_cp_rpt_cnt); ++void hdmi_reg_cea_cp_rpt_en_set(unsigned char cea_cp_rpt_en); ++void hdmi_reg_cea_vsif_en_set(unsigned char cea_vsif_en); ++void hdmi_reg_cea_vsif_rpt_en_set(unsigned char cea_vsif_rpt_en); ++void hdmi_reg_hdmi_mode_set(unsigned char hdmi_mode); ++void hdmi_reg_dc_pkt_en_set(unsigned char dc_pkt_en); ++void hdmi_reg_cp_set_avmute_set(unsigned char cp_set_avmute); ++void hdmi_reg_cp_clr_avmute_set(unsigned char cp_clr_avmute); ++void hdmi_reg_enc_hdmi2_on_set(unsigned char enc_hdmi2_on); ++void hdmi_reg_enc_scr_on_set(unsigned char enc_scr_on); ++void hdmi_reg_enc_bypass_set(unsigned char enc_bypass); ++unsigned char hdmi_reg_tmds_pack_mode_get(void); ++unsigned char hdmi_reg_pclk2tclk_stable_get(void); ++unsigned char hdmi_reg_cea_avi_en_get(void); ++unsigned char hdmi_reg_cea_aud_en_get(void); ++unsigned char hdmi_reg_cea_cp_rpt_en_get(void); ++unsigned char hdmi_reg_cea_gamut_en_get(void); ++unsigned char hdmi_reg_cea_vsif_rpt_en_get(void); ++unsigned char hdmi_reg_hdmi_mode_get(void); ++unsigned char hdmi_reg_dc_pkt_en_get(void); ++unsigned char hdmi_reg_cp_set_avmute_get(void); ++unsigned char hdmi_reg_enc_hdmi2_on_get(void); ++unsigned char hdmi_reg_enc_scr_on_get(void); ++#endif /* HHDMI_REG_TX_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.c +new file mode 100755 +index 000000000..9f145ac1b +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.c +@@ -0,0 +1,593 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#include "hdmi_reg_video_path.h" ++#include "hdmi_product_define.h" ++ ++volatile video_path_reg_regs_type *g_video_path_regs = NULL; ++ ++int hdmi_reg_video_path_regs_init(const char *addr) ++{ ++ ++ g_video_path_regs = (volatile video_path_reg_regs_type *)(addr + HDMI_TX_BASE_ADDR_VIDEO); ++ return 0; ++} ++ ++int hdmi_reg_video_path_regs_deinit(void) ++{ ++ ++ if (g_video_path_regs != NULL) { ++ g_video_path_regs = NULL; ++ } ++ return 0; ++} ++ ++int hdmi_video_path_regs_is_inited(void) ++{ ++ ++ if (g_video_path_regs == NULL) { ++ return -1; ++ } ++ return 0; ++} ++ ++void hdmi_reg_video_blank_en_set(unsigned char reg_video_blank_en) ++{ ++ unsigned int *reg_addr = NULL; ++ video_path_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->vid_path_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_video_blank_en = reg_video_blank_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_video_blank_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_path_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->vid_path_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.reg_video_blank_en; ++} ++ ++void hdmi_reg_solid_pattern_en_set(unsigned char solid_pattern_en) ++{ ++ unsigned int *reg_addr = NULL; ++ pattern_gen_ctrll pattern_gen_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->ptn_gen_ctrl.u32); ++ pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ pattern_gen_ctrl.bits.solid_pattern_en = solid_pattern_en; ++ hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_solid_pattern_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ pattern_gen_ctrll pattern_gen_ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->ptn_gen_ctrl.u32); ++ pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return pattern_gen_ctrl.bits.solid_pattern_en; ++} ++ ++void hdmi_reg_solid_pattern_cr_set(unsigned short solid_pattern_cr) ++{ ++ unsigned int *reg_addr = NULL; ++ solid_pattern_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->solid_ptn_ctrl.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.solid_pattern_cr = solid_pattern_cr; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++void hdmi_reg_solid_pattern_y_set(unsigned short solid_pattern_y) ++{ ++ unsigned int *reg_addr = NULL; ++ solid_pattern_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->solid_ptn_ctrl.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.solid_pattern_y = solid_pattern_y; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++void hdmi_reg_solid_pattern_cb_set(unsigned short solid_pattern_cb) ++{ ++ unsigned int *reg_addr = NULL; ++ solid_pattern_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->solid_ptn_ctrl.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.solid_pattern_cb = solid_pattern_cb; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fdt_status_clear_set(unsigned char fdt_status_clear) ++{ ++ unsigned int *reg_addr = NULL; ++ format_det_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_det_cfg.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.fdt_status_clear = fdt_status_clear; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sync_polarity_force_set(unsigned char sync_polarity_force) ++{ ++ unsigned int *reg_addr = NULL; ++ format_det_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_det_cfg.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.sync_polarity_force = sync_polarity_force; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_vsync_polarity_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_status status; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_status.u32); ++ status.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return status.bits.vsync_polarity; ++} ++ ++unsigned char hdmi_reg_hsync_polarity_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_status status; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_status.u32); ++ status.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return status.bits.hsync_polarity; ++} ++ ++unsigned char hdmi_reg_interlaced_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_status status; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_status.u32); ++ status.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return status.bits.interlaced; ++} ++ ++unsigned short hdmi_reg_hsync_total_cnt_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_hori_res tmp; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_res.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return tmp.bits.hsync_total_cnt; ++} ++ ++unsigned short hdmi_reg_hsync_active_cnt_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_hori_res tmp; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_res.u32); ++ tmp.u32 = hdmi_tx_reg_read(reg_addr); ++ return tmp.bits.hsync_active_cnt; ++} ++ ++unsigned short hdmi_reg_vsync_total_cnt_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_hori_vert_res fdet_vert_res; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_vert_res.u32); ++ fdet_vert_res.u32 = hdmi_tx_reg_read(reg_addr); ++ return fdet_vert_res.bits.vsync_total_cnt; ++} ++ ++unsigned short hdmi_reg_vsync_active_cnt_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ fdet_hori_vert_res fdet_vert_res; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_vert_res.u32); ++ fdet_vert_res.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return fdet_vert_res.bits.vsync_active_cnt; ++} ++ ++unsigned char hdmi_reg_dwsm_vert_bypass_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_dwsm_vert_byp; ++} ++ ++unsigned char hdmi_reg_dwsm_vert_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_dwsm_vert_en; ++} ++ ++unsigned char hdmi_reg_hori_filter_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ ++ video_dwsm_ctrl ctrl; ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.reg_hori_filter_en; ++} ++ ++unsigned char hdmi_reg_dwsm_hori_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_dwsm_hori_en; ++} ++ ++unsigned char hdmi_reg_pxl_div_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ data_align_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_pxl_div_en; ++} ++ ++unsigned char hdmi_reg_demux_420_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ data_align_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_demux_420_en; ++} ++ ++unsigned char hdmi_reg_inver_sync_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_inver_sync; ++} ++ ++unsigned char hdmi_reg_vmux_cr_sel_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_vmux_cr_sel; ++} ++ ++unsigned char hdmi_reg_vmux_cb_sel_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_vmux_cb_sel; ++} ++ ++unsigned char hdmi_reg_vmux_y_sel_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_vmux_y_sel; ++} ++ ++unsigned char hdmi_reg_dither_mode_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ dither_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return config.bits.dither_mode; ++} ++ ++unsigned char hdmi_reg_dither_rnd_bypass_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ dither_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return config.bits.dither_rnd_byp; ++} ++ ++unsigned char hdmi_reg_csc_en_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ multi_csc_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ++ return ctrl.bits.reg_csc_en; ++} ++ ++unsigned char hdmi_reg_csc_mode_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ multi_csc_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ return ctrl.bits.reg_csc_mode; ++} ++ ++void hdmi_reg_dither_mode_set(unsigned char dither_mode) ++{ ++ unsigned int *reg_addr = NULL; ++ dither_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.dither_mode = dither_mode; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dither_rnd_bypass_set(unsigned char dither_rnd_byp) ++{ ++ unsigned int *reg_addr = NULL; ++ dither_config config; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); ++ config.u32 = hdmi_tx_reg_read(reg_addr); ++ config.bits.dither_rnd_byp = dither_rnd_byp; ++ hdmi_tx_reg_write(reg_addr, config.u32); ++ ++ return; ++} ++ ++void hdmi_reg_csc_mode_set(unsigned char reg_csc_mode) ++{ ++ unsigned int *reg_addr = NULL; ++ multi_csc_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_csc_mode = reg_csc_mode; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_csc_saturate_en_set(unsigned char reg_csc_saturate_en) ++{ ++ unsigned int *reg_addr = NULL; ++ multi_csc_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_csc_saturate_en = reg_csc_saturate_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_csc_en_set(unsigned char reg_csc_en) ++{ ++ unsigned int *reg_addr = NULL; ++ multi_csc_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_csc_en = reg_csc_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dwsm_vert_bypass_set(unsigned char reg_dwsm_vert_byp) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_dwsm_vert_byp = reg_dwsm_vert_byp; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dwsm_vert_en_set(unsigned char reg_dwsm_vert_en) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_dwsm_vert_en = reg_dwsm_vert_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_hori_filter_en_set(unsigned char reg_hori_filter_en) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_hori_filter_en = reg_hori_filter_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dwsm_hori_en_set(unsigned char reg_dwsm_hori_en) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dwsm_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_dwsm_hori_en = reg_dwsm_hori_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pxl_div_en_set(unsigned char reg_pxl_div_en) ++{ ++ unsigned int *reg_addr = NULL; ++ data_align_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_pxl_div_en = reg_pxl_div_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_demux_420_en_set(unsigned char reg_demux_420_en) ++{ ++ unsigned int *reg_addr = NULL; ++ data_align_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_demux_420_en = reg_demux_420_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_inver_sync_set(unsigned char reg_inver_sync) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_inver_sync = reg_inver_sync; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_syncmask_en_set(unsigned char reg_syncmask_en) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_syncmask_en = reg_syncmask_en; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vmux_cr_sel_set(unsigned char reg_vmux_cr_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_vmux_cr_sel = reg_vmux_cr_sel; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vmux_cb_sel_set(unsigned char reg_vmux_cb_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_vmux_cb_sel = reg_vmux_cb_sel; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ ++void hdmi_reg_vmux_y_sel_set(unsigned char reg_vmux_y_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ video_dmux_ctrl ctrl; ++ ++ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); ++ ctrl.u32 = hdmi_tx_reg_read(reg_addr); ++ ctrl.bits.reg_vmux_y_sel = reg_vmux_y_sel; ++ hdmi_tx_reg_write(reg_addr, ctrl.u32); ++ ++ return; ++} ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.h +new file mode 100755 +index 000000000..9aef3154f +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.h +@@ -0,0 +1,723 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef HDMI_REG_VIDEO_PATH_H ++#define HDMI_REG_VIDEO_PATH_H ++ ++ ++typedef union { ++ struct { ++ unsigned int reg_timing_gen_en : 1; /* [0] */ ++ unsigned int reg_extmode : 1; /* [1] */ ++ unsigned int reg_timing_sel : 6; /* [7:2] */ ++ unsigned int reg_sync_polarity : 2; /* [9:8] */ ++ unsigned int rsv_0 : 22; /* [31:10] */ ++ } bits; ++ unsigned int u32; ++} timing_gen_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int hsync_total_count : 13; /* [12:0] */ ++ unsigned int hsync_high_to_low_count : 13; /* [25:13] */ ++ unsigned int rsv_1 : 6; /* [31:26] */ ++ } bits; ++ unsigned int u32; ++} hsync_timing_config0; ++ ++typedef union { ++ struct { ++ unsigned int hsync_de_start_count : 13; /* [12:0] */ ++ unsigned int hsync_de_end_count : 13; /* [25:13] */ ++ unsigned int rsv_2 : 6; /* [31:26] */ ++ } bits; ++ unsigned int u32; ++} hsync_timing_config1; ++ ++typedef union { ++ struct { ++ unsigned int hsync_low_to_high_count : 13; /* [12:0] */ ++ unsigned int rsv_3 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} hsync_timing_config2; ++ ++typedef union { ++ struct { ++ unsigned int vsync_total_count : 12; /* [11:0] */ ++ unsigned int vsync_high_to_low_count : 12; /* [23:12] */ ++ unsigned int rsv_4 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsync_timing_config0; ++ ++typedef union { ++ struct { ++ unsigned int vsync_de_start_count : 12; /* [11:0] */ ++ unsigned int vsync_de_end_count : 12; /* [23:12] */ ++ unsigned int rsv_5 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} vsync_timing_config1; ++ ++typedef union { ++ struct { ++ unsigned int vsync_low_to_high_count : 12; /* [11:0] */ ++ unsigned int rsv_6 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} vsync_timing_config2; ++ ++typedef union { ++ struct { ++ unsigned int reg_video_blank_en : 1; /* [0] */ ++ unsigned int rsv_6 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} video_path_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int tpg_enable : 1; /* [0] */ ++ unsigned int video_format : 2; /* [2:1] */ ++ unsigned int solid_pattern_en : 1; /* [3] */ ++ unsigned int colorbar_en : 1; /* [4] */ ++ unsigned int square_pattern_en : 1; /* [5] */ ++ unsigned int mask_pattern_en : 3; /* [8:6] */ ++ unsigned int replace_pattern_en : 3; /* [11:9] */ ++ unsigned int bar_pattern_extmode : 1; /* [12] */ ++ unsigned int cbar_pattern_sel : 2; /* [14:13] */ ++ unsigned int mix_color_en : 1; /* [15] */ ++ unsigned int increase_en : 1; /* [16] */ ++ unsigned int rsv_7 : 15; /* [31:17] */ ++ } bits; ++ unsigned int u32; ++} pattern_gen_ctrll; ++ ++typedef union { ++ struct { ++ unsigned int solid_pattern_cb : 10; /* [9:0] */ ++ unsigned int solid_pattern_y : 10; /* [19:10] */ ++ unsigned int solid_pattern_cr : 10; /* [29:20] */ ++ unsigned int rsv_8 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} solid_pattern_config; ++ ++typedef union { ++ struct { ++ unsigned int mask_pattern_cb : 10; /* [9:0] */ ++ unsigned int mask_pattern_y : 10; /* [19:10] */ ++ unsigned int mask_pattern_cr : 10; /* [29:20] */ ++ unsigned int rsv_9 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} mask_pattern_config; ++ ++typedef union { ++ struct { ++ unsigned int colorbar_width : 12; /* [11:0] */ ++ unsigned int square_height : 12; /* [23:12] */ ++ unsigned int rsv_10 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} bar_ext_config; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a0 : 30; /* [29:0] */ ++ unsigned int rsv_11 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a0; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a1 : 30; /* [29:0] */ ++ unsigned int rsv_12 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a1; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a2 : 30; /* [29:0] */ ++ unsigned int rsv_13 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a2; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a3 : 30; /* [29:0] */ ++ unsigned int rsv_14 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a3; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a4 : 30; /* [29:0] */ ++ unsigned int rsv_15 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a4; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a5 : 30; /* [29:0] */ ++ unsigned int rsv_16 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a5; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a6 : 30; /* [29:0] */ ++ unsigned int rsv_17 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a6; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_a7 : 30; /* [29:0] */ ++ unsigned int rsv_18 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_a7; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b0 : 30; /* [29:0] */ ++ unsigned int rsv_19 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b0; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b1 : 30; /* [29:0] */ ++ unsigned int rsv_20 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b1; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b2 : 30; /* [29:0] */ ++ unsigned int rsv_21 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b2; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b3 : 30; /* [29:0] */ ++ unsigned int rsv_22 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b3; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b4 : 30; /* [29:0] */ ++ unsigned int rsv_23 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b4; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b5 : 30; /* [29:0] */ ++ unsigned int rsv_24 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b5; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b6 : 30; /* [29:0] */ ++ unsigned int rsv_25 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b6; ++ ++typedef union { ++ struct { ++ unsigned int bar_pattern_b7 : 30; /* [29:0] */ ++ unsigned int rsv_26 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} cbar_pattern_b7; ++ ++typedef union { ++ struct { ++ unsigned int sync_polarity_force : 1; /* [0] */ ++ unsigned int hsync_polarity_value : 1; /* [1] */ ++ unsigned int vsync_polarity_value : 1; /* [2] */ ++ unsigned int fdt_status_clear : 1; /* [3] */ ++ unsigned int pixel_cnt_threhold : 4; /* [7:4] */ ++ unsigned int rsv_27 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} format_det_config; ++ ++typedef union { ++ struct { ++ unsigned int interlaced : 1; /* [0] */ ++ unsigned int hsync_polarity : 1; /* [1] */ ++ unsigned int vsync_polarity : 1; /* [2] */ ++ unsigned int rsv_28 : 29; /* [31:3] */ ++ } bits; ++ unsigned int u32; ++} fdet_status; ++ ++typedef union { ++ struct { ++ unsigned int hsync_active_cnt : 13; /* [12:0] */ ++ unsigned int hsync_total_cnt : 13; /* [25:13] */ ++ unsigned int rsv_29 : 6; /* [31:26] */ ++ } bits; ++ unsigned int u32; ++} fdet_hori_res; ++ ++typedef union { ++ struct { ++ unsigned int vsync_active_cnt : 13; /* [12:0] */ ++ unsigned int vsync_total_cnt : 13; /* [25:13] */ ++ unsigned int rsv_30 : 6; /* [31:26] */ ++ } bits; ++ unsigned int u32; ++} fdet_hori_vert_res; ++ ++typedef union { ++ struct { ++ unsigned int dither_rnd_byp : 1; /* [0] */ ++ unsigned int dither_mode : 2; /* [2:1] */ ++ unsigned int dither_rnd_en : 1; /* [3] */ ++ unsigned int dither_spatial_en : 1; /* [4] */ ++ unsigned int dither_spatial_dual : 1; /* [5] */ ++ unsigned int rsv_31 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} dither_config; ++ ++typedef union { ++ struct { ++ unsigned int range_clip_byp : 1; /* [0] */ ++ unsigned int clip_rgb_mode : 1; /* [1] */ ++ unsigned int rsv_32 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} clip_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int clip_y_min : 12; /* [11:0] */ ++ unsigned int clip_y_max : 12; /* [23:12] */ ++ unsigned int rsv_33 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} clip_y_config; ++ ++typedef union { ++ struct { ++ unsigned int clip_c_min : 12; /* [11:0] */ ++ unsigned int clip_c_max : 12; /* [23:12] */ ++ unsigned int rsv_34 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} clip_c_config; ++ ++typedef union { ++ struct { ++ unsigned int auto_trigger_en : 1; /* [0] */ ++ unsigned int soft_trigger_en : 1; /* [1] */ ++ unsigned int show_point_en : 1; /* [2] */ ++ unsigned int rsv_35 : 1; /* [3] */ ++ unsigned int cap_stat_done : 1; /* [4] */ ++ unsigned int cap_stat_busy : 1; /* [5] */ ++ unsigned int cap_stat_error : 1; /* [6] */ ++ unsigned int rsv_36 : 25; /* [31:7] */ ++ } bits; ++ unsigned int u32; ++} pxl_cap_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int cap_pixel_position : 13; /* [12:0] */ ++ unsigned int cap_line_position : 13; /* [25:13] */ ++ unsigned int rsv_37 : 6; /* [31:26] */ ++ } bits; ++ unsigned int u32; ++} pxl_cap_position; ++ ++typedef union { ++ struct { ++ unsigned int capture_y_value : 12; /* [11:0] */ ++ unsigned int rsv_38 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} cap_y_value; ++ ++typedef union { ++ struct { ++ unsigned int capture_cb_value : 12; /* [11:0] */ ++ unsigned int rsv_39 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} cap_cb_value; ++ ++typedef union { ++ struct { ++ unsigned int capture_cr_value : 12; /* [11:0] */ ++ unsigned int rsv_40 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} cap_cr_value; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_en : 1; /* [0] */ ++ unsigned int reg_csc_coef_ext : 1; /* [1] */ ++ unsigned int reg_csc_dither_en : 1; /* [2] */ ++ unsigned int reg_csc_saturate_en : 1; /* [3] */ ++ unsigned int reg_csc_mode : 8; /* [11:4] */ ++ unsigned int rsv_41 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r1c1 : 16; /* [15:0] */ ++ unsigned int rsv_42 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff11; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r1c2 : 16; /* [15:0] */ ++ unsigned int rsv_43 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff12; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r1c3 : 16; /* [15:0] */ ++ unsigned int rsv_44 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff13; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r2c1 : 16; /* [15:0] */ ++ unsigned int rsv_45 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff21; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r2c2 : 16; /* [15:0] */ ++ unsigned int rsv_46 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff22; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r2c3 : 16; /* [15:0] */ ++ unsigned int rsv_47 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff23; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r3c1 : 16; /* [15:0] */ ++ unsigned int rsv_48 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff31; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r3c2 : 16; /* [15:0] */ ++ unsigned int rsv_49 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff32; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_r3c3 : 16; /* [15:0] */ ++ unsigned int rsv_50 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_coeff33; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_inoffset_y : 13; /* [12:0] */ ++ unsigned int rsv_51 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_inoffset_y; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_inoffset_cb : 13; /* [12:0] */ ++ unsigned int rsv_52 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_inoffset_cb; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_inoffset_cr : 13; /* [12:0] */ ++ unsigned int rsv_53 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_inoffset_cr; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_outoffset_y : 13; /* [12:0] */ ++ unsigned int rsv_54 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_outoffset_y; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_outoffset_cb : 13; /* [12:0] */ ++ unsigned int rsv_55 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_outoffset_cb; ++ ++typedef union { ++ struct { ++ unsigned int reg_csc_outoffset_cr : 13; /* [12:0] */ ++ unsigned int rsv_56 : 19; /* [31:13] */ ++ } bits; ++ unsigned int u32; ++} multi_csc_outoffset_cr; ++ ++typedef union { ++ struct { ++ unsigned int reg_dwsm_hori_en : 1; /* [0] */ ++ unsigned int reg_hori_filter_en : 1; /* [1] */ ++ unsigned int reg_dwsm_vert_en : 1; /* [2] */ ++ unsigned int reg_dwsm_vert_byp : 1; /* [3] */ ++ unsigned int reg_vert_cbcr_sel : 1; /* [4] */ ++ unsigned int rsv_57 : 27; /* [31:5] */ ++ } bits; ++ unsigned int u32; ++} video_dwsm_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int reg_demux_420_en : 1; /* [0] */ ++ unsigned int reg_ddr_en : 1; /* [1] */ ++ unsigned int reg_yc_mux_en : 1; /* [2] */ ++ unsigned int reg_blank_replace_en : 1; /* [3] */ ++ unsigned int reg_pixel_rate : 2; /* [5:4] */ ++ unsigned int reg_ddr_polarity : 1; /* [6] */ ++ unsigned int reg_yc_mux_polarity : 1; /* [7] */ ++ unsigned int reg_cbcr_order : 1; /* [8] */ ++ unsigned int reg_demux_cb_or_cr : 1; /* [9] */ ++ unsigned int reg_pxl_div_en : 1; /* [10] */ ++ unsigned int rsv_58 : 21; /* [31:11] */ ++ } bits; ++ unsigned int u32; ++} data_align_ctrl; ++ ++typedef union { ++ struct { ++ unsigned int reg_blank_y : 12; /* [11:0] */ ++ unsigned int rsv_59 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} blank_data_y; ++ ++typedef union { ++ struct { ++ unsigned int reg_blank_cb : 12; /* [11:0] */ ++ unsigned int rsv_60 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} blank_data_cb; ++ ++typedef union { ++ struct { ++ unsigned int reg_blank_cr : 12; /* [11:0] */ ++ unsigned int rsv_61 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} blank_data_cr; ++ ++typedef union { ++ struct { ++ unsigned int reg_vmux_y_sel : 3; /* [2:0] */ ++ unsigned int reg_vmux_cb_sel : 3; /* [5:3] */ ++ unsigned int reg_vmux_cr_sel : 3; /* [8:6] */ ++ unsigned int reg_bitmask_y : 2; /* [10:9] */ ++ unsigned int reg_bitmask_cb : 2; /* [12:11] */ ++ unsigned int reg_bitmask_cr : 2; /* [14:13] */ ++ unsigned int reg_bitrev_en : 3; /* [17:15] */ ++ unsigned int reg_datamask_en : 3; /* [20:18] */ ++ unsigned int reg_syncmask_en : 4; /* [24:21] */ ++ unsigned int reg_inver_sync : 4; /* [28:25] */ ++ unsigned int rsv_62 : 3; /* [31:29] */ ++ } bits; ++ unsigned int u32; ++} video_dmux_ctrl; ++ ++typedef struct { ++ volatile timing_gen_ctrl tim_gen_ctrl; /* 800 */ ++ volatile hsync_timing_config0 hsync_timing_cfg0; /* 804 */ ++ volatile hsync_timing_config1 hsync_timing_cfg1; /* 808 */ ++ volatile hsync_timing_config2 hsync_timing_cfg2; /* 80C */ ++ volatile vsync_timing_config0 vsync_timing_cfg0; /* 810 */ ++ volatile vsync_timing_config1 vsync_timing_cfg1; /* 814 */ ++ volatile vsync_timing_config2 vsync_timing_cfg2; /* 818 */ ++ unsigned int reserved_0[5]; /* 81C-82C */ ++ volatile video_path_ctrl vid_path_ctrl; /* 830 */ ++ unsigned int reserved_1[3]; /* 834-83c */ ++ volatile pattern_gen_ctrll ptn_gen_ctrl; /* 840 */ ++ volatile solid_pattern_config solid_ptn_ctrl; /* 844 */ ++ volatile mask_pattern_config mask_ptn_ctrl; /* 848 */ ++ volatile bar_ext_config bar_ext_cfg; /* 84C */ ++ volatile cbar_pattern_a0 cbar_a0; /* 850 */ ++ volatile cbar_pattern_a1 cbar_a1; /* 854 */ ++ volatile cbar_pattern_a2 cbar_a2; /* 858 */ ++ volatile cbar_pattern_a3 cbar_a3; /* 85C */ ++ volatile cbar_pattern_a4 cbar_a4; /* 860 */ ++ volatile cbar_pattern_a5 cbar_a5; /* 864 */ ++ volatile cbar_pattern_a6 cbar_a6; /* 868 */ ++ volatile cbar_pattern_a7 cbar_a7; /* 86C */ ++ volatile cbar_pattern_b0 cbar_b0; /* 870 */ ++ volatile cbar_pattern_b1 cbar_b1; /* 874 */ ++ volatile cbar_pattern_b2 cbar_b2; /* 878 */ ++ volatile cbar_pattern_b3 cbar_b3; /* 87C */ ++ volatile cbar_pattern_b4 cbar_b4; /* 880 */ ++ volatile cbar_pattern_b5 cbar_b5; /* 884 */ ++ volatile cbar_pattern_b6 cbar_b6; /* 888 */ ++ volatile cbar_pattern_b7 cbar_b7; /* 88C */ ++ unsigned int reserved_2[10]; /* 890-8B4 */ ++ volatile format_det_config fmt_det_cfg; /* 8B8 */ ++ volatile fdet_status fmt_dect_status; /* 8BC */ ++ volatile fdet_hori_res fmt_dect_hori_res; /* 8C0 */ ++ volatile fdet_hori_vert_res fmt_dect_hori_vert_res; /* 8C4 */ ++ unsigned int reserved_3[9]; /* 8C8-8E8 */ ++ volatile dither_config dither_cfg; /* 8EC */ ++ unsigned int reserved_4[2]; /* 8F0-8F4 */ ++ volatile clip_ctrl clip_ctrl; /* 8F8 */ ++ volatile clip_y_config clip_y_cfg; /* 8FC */ ++ volatile clip_c_config clip_c_cfg; /* 900 */ ++ unsigned int reserved_5[2]; /* 904-908 */ ++ volatile pxl_cap_ctrl capture_ctrl; /* 90C */ ++ volatile pxl_cap_position capture_cfg; /* 910 */ ++ volatile cap_y_value pxl_y_capture; /* 914 */ ++ volatile cap_cb_value pxl_cb_capture; /* 918 */ ++ volatile cap_cr_value pxl_cr_capture; /* 91C */ ++ unsigned int reserved_6[5]; /* 920-930 */ ++ volatile multi_csc_ctrl csc_ctrl; /* 934 */ ++ volatile multi_csc_coeff11 csc_coeff11; /* 938 */ ++ volatile multi_csc_coeff12 csc_coeff12; /* 93C */ ++ volatile multi_csc_coeff13 csc_coeff13; /* 940 */ ++ volatile multi_csc_coeff21 csc_coeff21; /* 944 */ ++ volatile multi_csc_coeff22 csc_coeff22; /* 948 */ ++ volatile multi_csc_coeff23 csc_coeff23; /* 94C */ ++ volatile multi_csc_coeff31 csc_coeff31; /* 950 */ ++ volatile multi_csc_coeff32 csc_coeff32; /* 954 */ ++ volatile multi_csc_coeff33 csc_coeff33; /* 958 */ ++ volatile multi_csc_inoffset_y y_in_offset; /* 95C */ ++ volatile multi_csc_inoffset_cb cb_in_offset; /* 960 */ ++ volatile multi_csc_inoffset_cr cr_in_offset; /* 964 */ ++ volatile multi_csc_outoffset_y y_out_offset; /* 968 */ ++ volatile multi_csc_outoffset_cb cb_out_offset; /* 96C */ ++ volatile multi_csc_outoffset_cr cr_out_offset; /* 970 */ ++ unsigned int reserved_7[3]; /* 974-97c */ ++ volatile video_dwsm_ctrl dwsm_ctrl; /* 980 */ ++ unsigned int reserved_8[2]; /* 984-988 */ ++ volatile data_align_ctrl align_ctrl; /* 98C */ ++ volatile blank_data_y blk_data_y; /* 990 */ ++ volatile blank_data_cb blk_data_cb; /* 994 */ ++ volatile blank_data_cr blk_data_cr; /* 998 */ ++ unsigned int reserved_9[3]; /* 99C-9A4 */ ++ volatile video_dmux_ctrl dmux_ctrl; /* 9A8 */ ++} video_path_reg_regs_type; ++ ++int hdmi_reg_video_path_regs_init(const char *addr); ++int hdmi_reg_video_path_regs_deinit(void); ++int hdmi_video_path_regs_is_inited(void); ++void hdmi_reg_video_blank_en_set(unsigned char reg_video_blank_en); ++unsigned char hdmi_reg_video_blank_en_get(void); ++void hdmi_reg_solid_pattern_en_set(unsigned char solid_pattern_en); ++unsigned char hdmi_reg_solid_pattern_en_get(void); ++void hdmi_reg_solid_pattern_cb_set(unsigned short solid_pattern_cb); ++void hdmi_reg_solid_pattern_y_set(unsigned short solid_pattern_y); ++void hdmi_reg_solid_pattern_cr_set(unsigned short solid_pattern_cr); ++void hdmi_reg_sync_polarity_force_set(unsigned char sync_polarity_force); ++void hdmi_reg_fdt_status_clear_set(unsigned char fdt_status_clear); ++unsigned char hdmi_reg_interlaced_get(void); ++unsigned char hdmi_reg_hsync_polarity_get(void); ++unsigned char hdmi_reg_vsync_polarity_get(void); ++unsigned short hdmi_reg_hsync_active_cnt_get(void); ++unsigned short hdmi_reg_hsync_total_cnt_get(void); ++unsigned short hdmi_reg_vsync_active_cnt_get(void); ++unsigned short hdmi_reg_vsync_total_cnt_get(void); ++void hdmi_reg_dither_rnd_bypass_set(unsigned char dither_rnd_byp); ++unsigned char hdmi_reg_dither_rnd_bypass_get(void); ++void hdmi_reg_dither_mode_set(unsigned char dither_mode); ++unsigned char hdmi_reg_dither_mode_get(void); ++void hdmi_reg_csc_en_set(unsigned char reg_csc_en); ++unsigned char hdmi_reg_csc_en_get(void); ++void hdmi_reg_csc_saturate_en_set(unsigned char reg_csc_saturate_en); ++void hdmi_reg_csc_mode_set(unsigned char reg_csc_mode); ++unsigned char hdmi_reg_csc_mode_get(void); ++void hdmi_reg_dwsm_hori_en_set(unsigned char reg_dwsm_hori_en); ++unsigned char hdmi_reg_dwsm_hori_en_get(void); ++void hdmi_reg_hori_filter_en_set(unsigned char reg_hori_filter_en); ++unsigned char hdmi_reg_hori_filter_en_get(void); ++void hdmi_reg_dwsm_vert_en_set(unsigned char reg_dwsm_vert_en); ++unsigned char hdmi_reg_dwsm_vert_en_get(void); ++void hdmi_reg_dwsm_vert_bypass_set(unsigned char reg_dwsm_vert_byp); ++unsigned char hdmi_reg_dwsm_vert_bypass_get(void); ++void hdmi_reg_demux_420_en_set(unsigned char reg_demux_420_en); ++unsigned char hdmi_reg_demux_420_en_get(void); ++void hdmi_reg_pxl_div_en_set(unsigned char reg_pxl_div_en); ++unsigned char hdmi_reg_pxl_div_en_get(void); ++void hdmi_reg_vmux_y_sel_set(unsigned char reg_vmux_y_sel); ++unsigned char hdmi_reg_vmux_y_sel_get(void); ++void hdmi_reg_vmux_cb_sel_set(unsigned char reg_vmux_cb_sel); ++unsigned char hdmi_reg_vmux_cb_sel_get(void); ++void hdmi_reg_vmux_cr_sel_set(unsigned char reg_vmux_cr_sel); ++unsigned char hdmi_reg_vmux_cr_sel_get(void); ++void hdmi_reg_syncmask_en_set(unsigned char reg_syncmask_en); ++void hdmi_reg_inver_sync_set(unsigned char reg_inver_sync); ++unsigned char hdmi_reg_inver_sync_get(void); ++ ++#endif /* HDMI_REG_VIDEO_PATH_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/drv_hdmi_common.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/drv_hdmi_common.h +new file mode 100755 +index 000000000..70ac3dba8 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/drv_hdmi_common.h +@@ -0,0 +1,1342 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef DRV_HDMI_COMMON_H ++#define DRV_HDMI_COMMON_H ++ ++#include "ot_type.h" ++#include "drv_hdmi_infoframe.h" ++#include "hdmi_ext.h" ++#include "securec.h" ++#include "ot_common_hdmi.h" ++ ++ ++#define HDMI_VER_MAJOR 2 ++#define HDMI_VER_MINOR 0 ++#define HDMI_VER_REVISE 0 ++#define HDMI_VER_DATE 20240402 ++#define HDMI_VER_TIMES 0 ++ ++#define make_ver_bit(x) #x ++#define make_macro2str(exp) make_ver_bit(exp) ++#define MAKE_VERSION \ ++ make_macro2str(HDMI_VER_MAJOR) "." \ ++ make_macro2str(HDMI_VER_MINOR) "." \ ++ make_macro2str(HDMI_VER_REVISE) "." \ ++ make_macro2str(HDMI_VER_DATE) "." \ ++ make_macro2str(HDMI_VER_TIMES) ++ ++#define AEN_TX_FFE_LEN 4 ++#define MAX_FRL_RATE 6 ++#define HDMI_FRL_LANE_MAX_NUM 4 ++#define CEA_VIDEO_CODE_MAX 44 ++#define VESA_VIDEO_CODE_MAX 31 ++#define CEA861_F_VIDEO_CODES_MAX_4K 4 ++#define HDMI_INFO_FRAME_MAX_SIZE 31 ++#define SCDC_TMDS_BIT_CLK_RATIO_10X 10 ++#define SCDC_TMDS_BIT_CLK_RATIO_40X 40 ++#define HDMI_DECIMAL 10 ++#define HDMI_HUNDRED 100 ++#define HDMI_THOUSAND 1000 ++#define FMT_PIX_CLK_13400 13400 ++#define FMT_PIX_CLK_74250 74250 ++#define FMT_PIX_CLK_165000 165000 ++#define FMT_PIX_CLK_190000 190000 ++#define FMT_PIX_CLK_297000 297000 ++#define FMT_PIX_CLK_340000 340000 ++#define ZERO_DRMIF_SEND_TIME 2000 /* unit: ms */ ++#define HDRMODE_CHANGE_TIME 500 /* unit: ms */ ++#define HDMI_EDID_BLOCK_SIZE 128 ++#define HDMI_EDID_TOTAL_BLOCKS 4 ++#define HDMI_EDID_SIZE (HDMI_EDID_BLOCK_SIZE * HDMI_EDID_TOTAL_BLOCKS) ++#define HDMI_REGISTER_SIZE 4 ++#define HDMI_EDID_BLOCK_SIZE 128 ++#define HDMI_EDID_MAX_BLOCK_NUM 4 ++#define HDMI_HW_PARAM_LEN 4 ++#define HDMI_EDID_TOTAL_SIZE ((HDMI_EDID_BLOCK_SIZE) * (HDMI_EDID_MAX_BLOCK_NUM)) ++#define hdmi_array_size(a) ((sizeof(a)) / (sizeof(a[0]))) ++#ifdef HDMI_FPGA_SUPPORT ++#define FPGA_SUPPORT TD_TRUE ++#else ++#define FPGA_SUPPORT TD_FALSE ++#endif ++#define DEBUG_MAX_ARGV_NUM 10 ++#define hdmi_unused(x) (x) = (x) ++ ++#define PRT_RED "\033[31;1m" ++#define PRT_GREEN "\033[32;1m" ++#define PRT_CLEAN "\033[0m" ++ ++#define FRL_CTRL_TYPE_COMPRESS_ALL 0x00 ++#define FRL_CTRL_TYPE_COMPRESS_HW 0x01 ++#define FRL_CTRL_TYPE_COMPRESS_NON 0x03 ++#define HDMI_FRL_COMPRESS_DEBUG_MASK 0x4 ++ ++/* AVI InfoFrame Packet byte offset define */ ++#define AVI_OFFSET_TYPE 0 ++#define AVI_OFFSET_VERSION 1 ++#define AVI_OFFSET_LENGTH 2 ++#define AVI_OFFSET_CHECKSUM 3 ++/* ++ * include : ++ * color space ++ * active information present ++ * bar Info data valid ++ * scan Information ++ */ ++#define AVI_OFFSET_PB1 4 ++/* ++ * include : ++ * colorimetry ++ * picture aspect ratio ++ * active format aspect ratio ++ */ ++#define AVI_OFFSET_PB2 5 ++/* ++ * include : ++ * IT content ++ * extended colorimetry ++ * quantization range ++ * non-uniform picture scaling ++ */ ++#define AVI_OFFSET_PB3 6 ++#define AVI_OFFSET_VIC 7 ++/* ++ * include : ++ * YCC quantization range ++ * content type ++ * pixel repetition factor ++ */ ++#define AVI_OFFSET_PB5 8 ++#define AVI_OFFSET_TOP_BAR_LOWER 9 ++#define AVI_OFFSET_TOP_BAR_UPPER 10 ++#define AVI_OFFSET_BOTTOM_BAR_LOWER 11 ++#define AVI_OFFSET_BOTTOM_BAR_UPPER 12 ++#define AVI_OFFSET_LEFT_BAR_LOWER 13 ++#define AVI_OFFSET_LEFT_BAR_UPPER 14 ++#define AVI_OFFSET_RIGHT_BAR_LOWER 15 ++#define AVI_OFFSET_RIGHT_BAR_UPPER 16 ++#define AVI_OFFSET_PB14 17 ++#define AVI_OFFSET_PB15 18 ++#define AVI_OFFSET_PB16 19 ++#define AVI_OFFSET_PB17 20 ++#define AVI_OFFSET_PB18 21 ++#define AVI_OFFSET_PB19 22 ++#define AVI_OFFSET_PB20 23 ++#define AVI_OFFSET_PB21 24 ++#define AVI_OFFSET_PB22 25 ++#define AVI_OFFSET_PB23 26 ++#define AVI_OFFSET_PB24 27 ++#define AVI_OFFSET_PB25 28 ++#define AVI_OFFSET_PB26 29 ++#define AVI_OFFSET_PB27 30 ++#define AVI_FRAME_COLORIMETRY_MASK 0x3 ++#define AVI_FRAME_PIC_ASPECT_MASK 0x3 ++#define AVI_FRAME_ACTIVE_ASPECT_MASK 0xF ++#define AVI_FRAME_EXT_COLORIMETRY_MASK 0x7 ++#define AVI_FRAME_QUANT_RANGE_MASK 0x3 ++#define AVI_FRAME_YCC_QUANT_RANGE_MASK 0x3 ++#define AVI_FRAME_PIXEL_REPET_MASK 0xF ++ ++/* audio infoFrame packet byte offset define */ ++#define AUDIO_OFFSET_TYPE 0 ++#define AUDIO_OFFSET_VERSION 1 ++#define AUDIO_OFFSET_LENGHT 2 ++#define AUDIO_OFFSET_CHECKSUM 3 ++/* ++ * include : ++ * channel count ++ * coding type ++ */ ++#define AUDIO_OFFSET_PB1 4 ++/* ++ * include : ++ * sample size ++ * sample frequency ++ */ ++#define AUDIO_OFFSET_PB2 5 ++#define AUDIO_OFFSET_FORMAT 6 ++#define AUDIO_OFFSET_CA 7 ++/* ++ * include : ++ * level shift value ++ * downmix inhibit ++ * LFE playback level information ++ */ ++#define AUDIO_OFFSET_PB5 8 ++#define AUDIO_OFFSET_PB6 9 ++#define AUDIO_OFFSET_PB7 10 ++#define AUDIO_OFFSET_PB8 11 ++#define AUDIO_OFFSET_PB9 12 ++#define AUDIO_OFFSET_PB10 13 ++#define AUDIO_OFFSET_PB11 14 ++#define AUDIO_OFFSET_PB12 15 ++#define AUDIO_OFFSET_PB13 16 ++#define AUDIO_OFFSET_PB14 17 ++#define AUDIO_OFFSET_PB15 18 ++#define AUDIO_OFFSET_PB16 19 ++#define AUDIO_OFFSET_PB17 20 ++#define AUDIO_OFFSET_PB18 21 ++#define AUDIO_OFFSET_PB19 22 ++#define AUDIO_OFFSET_PB20 23 ++#define AUDIO_OFFSET_PB21 24 ++#define AUDIO_OFFSET_PB22 25 ++#define AUDIO_OFFSET_PB23 26 ++#define AUDIO_OFFSET_PB24 27 ++#define AUDIO_OFFSET_PB25 28 ++#define AUDIO_OFFSET_PB26 29 ++#define AUDIO_OFFSET_PB27 30 ++#define AUDIO_FRAME_CODE_TYPE_MASK 0xF ++ ++/* gdb infoFrame packet byte offset define */ ++#define GDB_OFFSET_HB0 0 ++#define GDB_OFFSET_HB1 1 ++#define GDB_OFFSET_HB2 2 ++#define GDB_OFFSET_CHECKSUM 3 ++#define GDB_OFFSET_PB1 4 ++#define GDB_OFFSET_PB2 5 ++#define GDB_OFFSET_PB3 6 ++#define GDB_OFFSET_PB4 7 ++#define GDB_OFFSET_PB5 8 ++#define GDB_OFFSET_PB6 9 ++#define GDB_OFFSET_PB7 10 ++#define GDB_OFFSET_PB8 11 ++#define GDB_OFFSET_PB9 12 ++#define GDB_OFFSET_PB10 13 ++#define GDB_OFFSET_PB11 14 ++#define GDB_OFFSET_PB12 15 ++#define GDB_OFFSET_PB13 16 ++#define GDB_OFFSET_PB14 17 ++#define GDB_OFFSET_PB15 18 ++#define GDB_OFFSET_PB16 19 ++#define GDB_OFFSET_PB17 20 ++#define GDB_OFFSET_PB18 21 ++#define GDB_OFFSET_PB19 22 ++#define GDB_OFFSET_PB20 23 ++#define GDB_OFFSET_PB21 24 ++#define GDB_OFFSET_PB22 25 ++#define GDB_OFFSET_PB23 26 ++#define GDB_OFFSET_PB24 27 ++#define GDB_OFFSET_PB25 28 ++#define GDB_OFFSET_PB26 29 ++#define GDB_OFFSET_PB27 30 ++ ++/* vendor infoFrame packet byte offset define */ ++#define VENDOR_OFFSET_TYPE 0 ++#define VENDOR_OFFSET_VERSION 1 ++#define VENDOR_OFFSET_LENGHT 2 ++#define VENDOR_OFFSET_CHECSUM 3 ++#define VENDOR_OFFSET_IEEE_LOWER 4 ++#define VENDOR_OFFSET_IEEE_UPPER 5 ++#define VENDOR_OFFSET_IEEE 6 ++#define VENDOR_OFFSET_VIDEO_FMT 7 ++#define VENDOR_OFFSET_VIC 8 ++#define VENDOR_OFFSET_3D_STRUCT 9 ++#define VENDOR_OFFSET_3D_EXT_DATA 10 ++#define VENDOR_OFFSET_PB7 11 ++#define VENDOR_OFFSET_PB8 12 ++#define VENDOR_OFFSET_PB9 13 ++#define VENDOR_OFFSET_PB10 14 ++#define VENDOR_OFFSET_PB11 15 ++#define VENDOR_OFFSET_PB12 16 ++#define VENDOR_OFFSET_PB13 17 ++#define VENDOR_OFFSET_PB14 18 ++#define VENDOR_OFFSET_PB15 19 ++#define VENDOR_OFFSET_PB16 20 ++#define VENDOR_OFFSET_PB17 21 ++#define VENDOR_OFFSET_PB18 22 ++#define VENDOR_OFFSET_PB19 23 ++#define VENDOR_OFFSET_PB20 24 ++#define VENDOR_OFFSET_PB21 25 ++#define VENDOR_OFFSET_PB22 26 ++#define VENDOR_OFFSET_PB23 27 ++#define VENDOR_OFFSET_PB24 28 ++#define VENDOR_OFFSET_PB25 29 ++#define VENDOR_OFFSET_PB26 30 ++#define VENDOR_FARAME_VIDEO_FMT_MASK 0x7 ++#define VENDOR_3D_STRUCT_MASK 0xF ++ ++#define HDMI_BKSV_LEN 5 ++#define HDMI_AKSV_LEN 5 ++ ++#define hdmi_unlock_if_null_return(p, mutex, ret) \ ++ do { \ ++ if ((p) == TD_NULL) { \ ++ hdmi_err("%s is null pointer!\n", #p); \ ++ hdmi_mutex_unlock((mutex)); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_null_return(p, ret) \ ++ do { \ ++ if ((p) == TD_NULL) { \ ++ hdmi_err("%s is null pointer!\n", #p); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_null_return_void(p) \ ++ do { \ ++ if ((p) == TD_NULL) { \ ++ hdmi_err("%s is null pointer!\n", #p); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_null_warn_return(p, ret) \ ++ do { \ ++ if ((p) == TD_NULL) { \ ++ hdmi_warn("%s is null pointer!\n", #p); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_null_warn_return_void(p) \ ++ do { \ ++ if ((p) == TD_NULL) { \ ++ hdmi_warn("%s is null pointer!\n", #p); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_false_return_void(b) \ ++ do { \ ++ if ((b) != TD_TRUE) { \ ++ hdmi_err("%s is FALSE!\n", #b); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_false_return(tmp, ret) \ ++ do { \ ++ if ((tmp) != TD_TRUE) { \ ++ hdmi_err("%s is FALSE!\n", #tmp); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_false_warn_return(tmp, ret) \ ++ do { \ ++ if ((tmp) != TD_TRUE) { \ ++ hdmi_warn("%s is FALSE!\n", #tmp); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_false_warn_return_void(tmp) \ ++ do { \ ++ if ((tmp) != TD_TRUE) { \ ++ hdmi_warn("%s is FALSE!\n", #tmp); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_check_is_change_return(tmp0, tmp1, ret) \ ++ do { \ ++ if ((tmp0) != (tmp1)) { \ ++ hdmi_info("%s change, old(%u)->new(%u) \n", #tmp0, (td_u32)(tmp0), (td_u32)(tmp1)); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_check_max_return(value, max, ret) \ ++ do { \ ++ if ((value) > (max)) { \ ++ hdmi_warn("value %u exceed max!\n", (td_u32)(value)); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_failure_return(tmp, ret) \ ++ do { \ ++ if ((tmp) != TD_SUCCESS) { \ ++ hdmi_err("%s is failure!\n", #tmp); \ ++ return (ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_failure_return_void(tmp) \ ++ do { \ ++ if ((tmp) != TD_SUCCESS) { \ ++ hdmi_err("%s is failure!\n", #tmp); \ ++ return; \ ++ } \ ++ } while (0) ++#define hdmi_if_failure_warn_return_void(tmp) \ ++ do { \ ++ if ((tmp) != TD_SUCCESS) { \ ++ hdmi_warn("%s is failure!\n", #tmp); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_set_bit(var, bit) \ ++ do { \ ++ (var) |= 1 << (bit); \ ++ } while (0) ++ ++#define hdmi_clr_bit(var, bit) \ ++ do { \ ++ (var) &= ~(1 << (bit)); \ ++ } while (0) ++ ++#ifdef HDMI_FPGA_SUPPORT ++#define hdmi_if_fpga_return(ret) \ ++ do { \ ++ if (FPGA_SUPPORT) { \ ++ hdmi_warn("FPGA CFG!\n"); \ ++ return(ret); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_fpga_return_void() \ ++ do { \ ++ if (FPGA_SUPPORT) { \ ++ hdmi_warn("FPGA CFG!\n"); \ ++ return; \ ++ } \ ++ } while (0) ++#else ++#define hdmi_if_fpga_return(ret) ++#define hdmi_if_fpga_return_void() ++#endif ++ ++#define is_bit_set(var, bit) ({ (var) & (0x1 << (bit)) ? TD_TRUE : TD_FALSE; }) ++ ++#define hal_call_ret(ret, func, param...) \ ++ do { \ ++ if (hdmi_dev != TD_NULL && hdmi_dev->hal != TD_NULL && \ ++ hdmi_dev->hal->func != TD_NULL) { \ ++ ret = hdmi_dev->hal->func(param); \ ++ } else { \ ++ ret = OT_ERR_HDMI_NULL_PTR; \ ++ } \ ++ } while (0) ++ ++#define hal_call_void(func, param...) \ ++ do { \ ++ if (hdmi_dev != TD_NULL && hdmi_dev->hal != TD_NULL && \ ++ hdmi_dev->hal->func != TD_NULL) { \ ++ hdmi_dev->hal->func(param); \ ++ } else { \ ++ hdmi_warn("null pointer! \n"); \ ++ } \ ++ } while (0) ++ ++#define hdmi_if_zero_return_void(x) \ ++ do { \ ++ if ((x) == 0) { \ ++ hdmi_err("%s is zero!\n", #x); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_unequal_eok_return(ret, err_code) \ ++ do { \ ++ if ((ret) != EOK) { \ ++ hdmi_err("secure function error:%d\n", (ret)); \ ++ return (err_code); \ ++ } \ ++ } while (0) ++ ++#define hdmi_unlock_unequal_eok_return(ret, mutex, err_code) \ ++ do { \ ++ if ((ret) != EOK) { \ ++ hdmi_err("secure function error:%d\n", (ret)); \ ++ hdmi_mutex_unlock((mutex)); \ ++ return (err_code); \ ++ } \ ++ } while (0) ++ ++#define hdmi_unequal_eok_return_void(ret) \ ++ do { \ ++ if ((ret) != EOK) { \ ++ hdmi_err("secure function error:%d\n", (ret)); \ ++ return; \ ++ } \ ++ } while (0) ++ ++#define hdmi_check_open_return(state) \ ++ do { \ ++ if (!((state) & HDMI_RUN_STATE_OPEN)) { \ ++ hdmi_warn("device not open\n"); \ ++ return OT_ERR_HDMI_DEV_NOT_OPEN; \ ++ } \ ++ } while (0) ++ ++typedef enum { ++ HDMI_DEVICE_ID0, ++ HDMI_DEVICE_ID1, ++ HDMI_DEVICE_ID_BUTT ++} hdmi_device_id; ++ ++#ifdef HDMI_SUPPORT_DUAL_CHANNEL ++#define HDMI_ID_MAX HDMI_DEVICE_ID_BUTT ++#else ++#define HDMI_ID_MAX HDMI_DEVICE_ID1 ++#endif ++ ++typedef enum { ++ HDMI_THREAD_STATE_IDLE, ++ HDMI_THREAD_STATE_RUN, ++ HDMI_THREAD_STATE_STOP ++} hdmi_thread_state; ++ ++typedef enum { ++ HDMI_EVENT_HOTPLUG = 0x10, ++ HDMI_EVENT_HOTUNPLUG, ++ HDMI_EVENT_EDID_FAIL, ++ HDMI_EVENT_RSEN_CONNECT, ++ HDMI_EVENT_RSEN_DISCONNECT, ++ HDMI_EVENT_SCRAMBLE_FAIL, ++ HDMI_EVENT_SCRAMBLE_SUCCESS, ++ HDMI_EVENT_ZERO_DRMIF_TIMEOUT, ++ HDMI_EVENT_SWITCH_TO_HDRMODE_TIMEOUT, ++ HDMI_EVENT_BUTT ++} hdmi_event; ++ ++typedef enum { ++ HDMI_DEBUG_BASE_OSD = 8, ++ HDMI_DEBUG_BASE_DEC = 10, ++ HDMI_DEBUG_BASE_HEX = 16 ++} hdmi_debug_base; ++ ++typedef td_s32 (*hdmi_callback)(td_void *, hdmi_event); ++ ++typedef struct { ++ hdmi_device_id hdmi_id; ++ td_char *argv[DEBUG_MAX_ARGV_NUM]; ++ td_u32 argc; ++ td_u32 remain_len; ++} hdmi_debug_cmd_arg; ++ ++typedef td_s32 (*cmd_func)(const hdmi_debug_cmd_arg *cmd_arg); ++ ++typedef struct { ++ td_char *name; ++ td_char *short_name; ++ cmd_func fn_cmd_func; ++ td_char *comment_help; ++} hdmi_debug_cmd_info; ++ ++typedef struct { ++ td_u32 ddc_reg_cfg; ++ td_u32 approximate_value; ++ td_char *read_value; ++} hdmi_ddc_freq; ++ ++typedef struct { ++ td_bool data_valid; ++ td_s32 len; ++ td_u8 data[HDMI_EDID_TOTAL_SIZE]; ++} hdmi_debug_edid; ++ ++typedef struct { ++ td_void *event_data; ++ hdmi_callback event_callback; ++ td_u32 hdmi_dev_id; ++ td_char *base_addr; ++ td_char *phy_addr; ++} hdmi_hal_init; ++ ++typedef struct { ++ td_u32 cmd; ++ td_s32 (*hdmi_ioctrl_func)(td_void *arg, td_bool user); ++} hdmi_ioctrl_func; ++ ++typedef struct { ++ hdmi_colorimetry colorimetry; ++ hdmi_quant_range quantization; ++ hdmi_pixel_encoding pixel_encoding; ++} hdmi_csc_attr; ++ ++typedef struct { ++ td_u8 edid_valid; ++ td_u32 edid_len; ++ td_u8 edid[HDMI_EDID_SIZE]; ++} hdmi_edid_raw_data; ++ ++typedef enum { ++ HDMI_HDCP_VERSION_NONE, ++ HDMI_HDCP_VERSION_1_4, ++ HDMI_HDCP_VERSION_2_2, ++ HDMI_HDCP_VERSION_BUTT ++} hdmi_hdcp_version; ++ ++typedef struct { ++ td_bool connected; ++ td_bool sink_power_on; ++ td_bool authed; ++ td_u8 bksv[HDMI_BKSV_LEN]; ++ hdmi_hdcp_version hdcp_version; ++} hdmi_status; ++ ++typedef struct { ++ td_u32 i_de_main_clk; ++ td_u32 i_de_main_data; ++ td_u32 i_main_clk; ++ td_u32 i_main_data; ++ td_u32 ft_cap_clk; ++ td_u32 ft_cap_data; ++} hdmi_hw_param; ++ ++typedef struct { ++ hdmi_hw_param hw_param[HDMI_HW_PARAM_LEN]; ++} hdmi_hw_spec; ++ ++typedef struct { ++ hdmi_hw_spec hwspec_user; ++ hdmi_hw_spec hwspec_def; ++ hdmi_hw_param hwparam_cur; ++} hdmi_hwspec; ++ ++typedef enum { ++ HDMI_DEEP_COLOR_24BIT, ++ HDMI_DEEP_COLOR_30BIT, ++ HDMI_DEEP_COLOR_36BIT, ++ HDMI_DEEP_COLOR_48BIT, ++ HDMI_DEEP_COLOR_OFF = 0xff, ++ HDMI_DEEP_COLOR_BUTT ++} hdmi_deep_color; ++ ++typedef enum { ++ HDMI_VIDEO_BITDEPTH_8, ++ HDMI_VIDEO_BITDEPTH_10, ++ HDMI_VIDEO_BITDEPTH_12, ++ HDMI_VIDEO_BITDEPTH_16, ++ HDMI_VIDEO_BITDEPTH_OFF, ++ HDMI_VIDEO_BITDEPTH_BUTT ++} hdmi_video_bit_depth; ++ ++typedef enum { ++ HDMI_HV_SYNC_POL_HPVP, ++ HDMI_HV_SYNC_POL_HPVN, ++ HDMI_HV_SYNC_POL_HNVP, ++ HDMI_HV_SYNC_POL_HNVN, ++ HDMI_HV_SYNC_POL_BUTT ++} hdmi_hvsync_polarity; ++ ++typedef enum { ++ HDMI_PICTURE_NON_UNIFORM_SCALING, ++ HDMI_PICTURE_SCALING_H, ++ HDMI_PICTURE_SCALING_V, ++ HDMI_PICTURE_SCALING_HV ++} hdmi_picture_scaling; ++ ++typedef struct { ++ td_u32 clk_fs; /* VDP setting(in) */ ++ td_u32 tmds_clk; ++ td_u32 hdmi_adapt_pix_clk; /* HDMI adapt setting(out) */ ++ td_u32 pixel_repeat; ++ td_bool v_sync_pol; ++ td_bool h_sync_pol; ++ td_bool de_pol; ++ hdmi_video_timing video_timing; ++ hdmi_3d_mode stereo_mode; ++ hdmi_colorspace in_color_space; ++ hdmi_colormetry colorimetry; ++ hdmi_extended_colormetry extended_colorimetry; ++ hdmi_quantization_range rgb_quantization; ++ hdmi_ycc_quantization_range ycc_quantization; ++ hdmi_picture_aspect picture_aspect; ++ hdmi_active_aspect active_aspect; ++ hdmi_picture_scaling picture_scaling; ++ hdmi_video_bit_depth in_bit_depth; ++ hdmi_disp_format disp_fmt; ++} hdmi_vo_attr; ++ ++typedef enum { ++ HDMI_AUDIO_FORMAT_2CH = 0x2, ++ HDMI_AUDIO_FORMAT_3CH, ++ HDMI_AUDIO_FORMAT_4CH, ++ HDMI_AUDIO_FORMAT_5CH, ++ HDMI_AUDIO_FORMAT_6CH, ++ HDMI_AUDIO_FORMAT_7CH, ++ HDMI_AUDIO_FORMAT_8CH, ++ HDMI_AUDIO_FORMAT_BUTT ++} hdmi_audio_ch; ++ ++typedef enum { ++ HDMI_AUDIO_INTF_I2S, ++ HDMI_AUDIO_INTF_SPDIF, ++ HDMI_AUDIO_INTF_HBRA, ++ HDMI_AUDIO_INTF_BUTT ++} hdmi_audio_interface; ++ ++typedef enum { ++ HDMI_AUDIO_BIT_DEPTH_UNKNOWN, ++ HDMI_AUDIO_BIT_DEPTH_8 = 8, ++ HDMI_AUDIO_BIT_DEPTH_16 = 16, ++ HDMI_AUDIO_BIT_DEPTH_18 = 18, ++ HDMI_AUDIO_BIT_DEPTH_20 = 20, ++ HDMI_AUDIO_BIT_DEPTH_24 = 24, ++ HDMI_AUDIO_BIT_DEPTH_32 = 32, ++ HDMI_AUDIO_BIT_DEPTH_BUTT ++} hdmi_audio_bit_depth; ++ ++typedef enum { ++ HDMI_SAMPLE_RATE_UNKNOWN, ++ HDMI_SAMPLE_RATE_8K = 8000, ++ HDMI_SAMPLE_RATE_11K = 11025, ++ HDMI_SAMPLE_RATE_12K = 12000, ++ HDMI_SAMPLE_RATE_16K = 16000, ++ HDMI_SAMPLE_RATE_22K = 22050, ++ HDMI_SAMPLE_RATE_24K = 24000, ++ HDMI_SAMPLE_RATE_32K = 32000, ++ HDMI_SAMPLE_RATE_44K = 44100, ++ HDMI_SAMPLE_RATE_48K = 48000, ++ HDMI_SAMPLE_RATE_88K = 88200, ++ HDMI_SAMPLE_RATE_96K = 96000, ++ HDMI_SAMPLE_RATE_176K = 176400, ++ HDMI_SAMPLE_RATE_192K = 192000, ++ HDMI_SAMPLE_RATE_768K = 768000, ++ HDMI_SAMPLE_RATE_BUTT ++} hdmi_sample_rate; ++ ++typedef struct { ++ td_bool down_sample; ++ hdmi_sample_rate sample_fs; ++ hdmi_audio_ch channels; ++ hdmi_audio_interface sound_intf; ++ hdmi_audio_bit_depth sample_depth; ++ hdmi_audio_format_code audio_code; ++} hdmi_ao_attr; ++ ++typedef enum { ++ HDMI_TMDS_MODE_NONE, ++ HDMI_TMDS_MODE_DVI, ++ HDMI_TMDS_MODE_HDMI_1_4, ++ HDMI_TMDS_MODE_HDMI_2_0, ++ HDMI_TMDS_MODE_AUTO, ++ HDMI_TMDS_MODE_HDMI_2_1, ++ HDMI_TMDS_MODE_BUTT ++} hdmi_tmds_mode; ++ ++typedef enum { ++ HDMI_HDCP_MODE_AUTO, ++ HDMI_HDCP_MODE_1_4, ++ HDMI_HDCP_MODE_2_2, ++ HDMI_HDCP_MODE_BUTT ++} hdmi_hdcp_mode; ++ ++typedef enum { ++ HDMI_DEFAULT_ACTION_NULL, ++ HDMI_DEFAULT_ACTION_HDMI, ++ HDMI_DEFAULT_ACTION_DVI, ++ HDMI_DEFAULT_ACTION_BUTT ++} hdmi_default_action; ++ ++typedef enum { ++ HDMI_VIDEO_DITHER_12_10, ++ HDMI_VIDEO_DITHER_12_8, ++ HDMI_VIDEO_DITHER_10_8, ++ HDMI_VIDEO_DITHER_DISALBE ++} hdmi_video_dither; ++ ++typedef struct { ++ td_bool enable_hdmi; ++ td_bool enable_video; ++ td_bool enable_audio; ++ hdmi_colorspace out_color_space; ++ hdmi_quantization_range out_csc_quantization; ++ hdmi_deep_color deep_color_mode; ++ td_bool xvycc_mode; ++ td_bool enable_avi_infoframe; ++ td_bool enable_spd_infoframe; ++ td_bool enable_mpeg_infoframe; ++ td_bool enable_aud_infoframe; ++ td_u32 debug_flag; ++ td_bool hdcp_enable; ++ hdmi_default_action hdmi_action; ++ td_bool enable_clr_space_adapt; ++ td_bool enable_deep_clr_adapt; ++ td_bool auth_mode; ++ hdmi_hdcp_mode hdcp_mode; ++} hdmi_app_attr; ++ ++typedef struct { ++ td_bool enable_hdmi; ++ td_bool enable_video; ++ hdmi_disp_format disp_fmt; ++ hdmi_video_timing video_timing; ++ td_u32 pix_clk; ++ hdmi_colorspace in_color_space; ++ hdmi_colorspace out_color_space; ++ hdmi_deep_color deep_color_mode; ++ hdmi_quantization_range out_csc_quantization; ++ td_bool enable_audio; ++ hdmi_sample_rate sample_rate; ++ hdmi_audio_bit_depth bit_depth; ++ td_bool enable_avi_infoframe; ++ td_bool enable_aud_infoframe; ++ hdmi_default_action hdmi_action; ++ td_bool enable_vid_mode_adapt; ++ td_bool enable_deep_clr_adapt; ++ td_bool auth_mode; ++} hdmi_property; ++ ++typedef struct { ++ hdmi_ao_attr ao_attr; ++ hdmi_vo_attr vo_attr; ++ hdmi_app_attr app_attr; ++} hdmi_attr; ++ ++typedef enum { ++ HDMI_TRANSITION_NONE, ++ HDMI_TRANSITION_BOOT_MCE, ++ HDMI_TRANSITION_MCE_APP, ++ HDMI_TRANSITION_BOOT_APP = 0x4 ++} hdmi_transition_state; ++ ++typedef enum { ++ HDMI_RUN_STATE_NONE, ++ HDMI_RUN_STATE_INIT, ++ HDMI_RUN_STATE_OPEN, ++ HDMI_RUN_STATE_START = 0x4, ++ HDMI_RUN_STATE_STOP = 0x8, ++ HDMI_RUN_STATE_CLOSE = 0x10, ++ HDMI_RUN_STATE_DEINIT = 0x20 ++} hdmi_run_state; ++ ++typedef struct { ++ td_u16 length; ++ td_u8 *list; ++ td_u8 *list_start; ++} hdmi_hdcp_ksv_list; ++ ++typedef struct { ++ td_bool tx_hdmi_14; ++ td_bool tx_hdmi_20; ++ td_bool tx_hdmi_21; ++ td_bool tx_hdcp_14; ++ td_bool tx_hdcp_22; ++ td_bool tx_rgb444; ++ td_bool tx_ycbcr444; ++ td_bool tx_ycbcr422; ++ td_bool tx_ycbcr420; ++ td_bool tx_deep_clr10_bit; ++ td_bool tx_deep_clr12_bit; ++ td_bool tx_deep_clr16_bit; ++ td_bool tx_rgb_ycbcr444; ++ td_bool tx_ycbcr444_422; ++ td_bool tx_ycbcr422_420; ++ td_bool tx_ycbcr420_422; ++ td_bool tx_ycbcr422_444; ++ td_bool tx_ycbcr444_rgb; ++ td_bool tx_scdc; ++ td_u32 tx_max_tmds_clk; ++ td_u32 tx_max_frl_rate; ++} hdmi_tx_capability_data; ++ ++typedef enum { ++ HDMI_CONV_STD_BT_709, ++ HDMI_CONV_STD_BT_601, ++ HDMI_CONV_STD_BT_2020_NON_CONST_LUMINOUS, ++ HDMI_CONV_STD_BT_2020_CONST_LUMINOUS, ++ HDMI_CONV_STD_BUTT ++} hdmi_conversion_stb; ++ ++typedef struct { ++ hdmi_video_timing timing; ++ td_u32 pixel_clk; ++ td_u32 tmds_clk; ++ td_bool v_sync_pol; ++ td_bool h_sync_pol; ++ td_bool de_pol; ++ hdmi_conversion_stb conv_std; ++ hdmi_quantization_range quantization; ++ hdmi_colorspace in_color_space; ++ hdmi_colorspace out_color_space; ++ hdmi_deep_color deep_color; ++ hdmi_video_bit_depth in_bit_depth; ++ hdmi_quantization_range out_csc_quantization; ++ td_bool emi_enable; ++} hdmi_video_config; ++ ++typedef struct { ++ td_bool enable_audio; ++ td_bool down_sample; ++ td_u32 tmds_clk; ++ td_u32 pixel_repeat; ++ hdmi_sample_rate sample_fs; ++ hdmi_audio_ch layout; ++ hdmi_audio_interface sound_intf; ++ hdmi_audio_bit_depth sample_depth; ++} hdmi_audio_config; ++ ++typedef enum { ++ HDMI_FRL_MODE_TMDS, ++ HDMI_FRL_MODE_FRL, ++ HDMI_FRL_MODE_BUTT ++} hdmi_frl_mode; ++ ++typedef struct { ++ hdmi_sample_rate sample_rate; ++ hdmi_frl_mode hdmi_mode; ++ td_u8 frl_rate; ++ td_u32 pixel_clk; ++} hdmi_audio_ncts; ++ ++typedef struct { ++ td_bool phy_oe; ++ td_bool phy_power_on; ++ hdmi_video_bit_depth deep_color; ++} hdmi_phy_status; ++ ++typedef struct { ++ td_bool sw_emi_enable; ++ td_bool hw_emi_enable; ++ td_bool debug_enable; ++} hdmi_emi_status; ++ ++typedef struct { ++ td_bool video_mute; ++ td_bool ycbcr2rgb; ++ td_bool rgb2ycbcr; ++ td_bool ycbcr444_422; ++ td_bool ycbcr422_420; ++ td_bool ycbcr420_422; ++ td_bool ycbcr422_444; ++ td_bool in420_ydemux; ++ td_bool out420_ydemux; ++ hdmi_video_dither dither; ++ td_bool v_sync_pol; ++ td_bool h_sync_pol; ++ td_bool sync_pol; ++ td_bool de_pol; ++ td_bool swap_hs_cs; ++ hdmi_colorspace in_color_space; ++ hdmi_colorspace out_color_space; ++ hdmi_video_bit_depth out_bit_depth; ++ hdmi_hvsync_polarity hv_sync_pol; ++ hdmi_quantization_range out_csc_quantization; ++ /* detect timing */ ++ td_bool sync_sw_enable; ++ td_bool vsync_polarity; /* when sync_sw_enable==0,indicates hw;or ,indicates sw */ ++ td_bool hsync_polarity; /* when sync_sw_enable==0,indicates hw;or ,indicates sw */ ++ td_bool progressive; ++ td_u32 hsync_total; ++ td_u32 hactive_cnt; ++ td_u32 vsync_total; ++ td_u32 vactive_cnt; ++} hdmi_video_status; ++ ++typedef struct { ++ td_bool hdcp14_support; ++ td_bool hdcp22_support; ++} hdmi_hdcp_capability; ++ ++typedef struct { ++ td_bool audio_mute; ++ td_bool audio_enable; ++ td_bool down_sample; ++ hdmi_sample_rate sample_fs; ++ hdmi_audio_ch layout; ++ hdmi_audio_interface sound_intf; ++ hdmi_audio_bit_depth sample_depth; ++ td_u32 ref_n; ++ td_u32 reg_n; ++ td_u32 ref_cts; ++ td_u32 reg_cts; ++} hdmi_audio_status; ++ ++typedef struct { ++ td_bool hotplug; ++ td_bool rsen; ++ td_bool avmute; ++ hdmi_tmds_mode tmds_mode; ++} hdmi_common_status; ++ ++typedef struct { ++ td_bool source_scramble_on; ++ td_bool sink_scramble_on; ++ td_u8 tmds_bit_clk_ratio; ++ td_bool sink_read_quest; ++ /* in unit of ms.for [0,200], force to default 200; or, set the value cfg(>200). */ ++ td_u32 scramble_timeout; ++ /* in unit of ms, range[20,200). for [0,20] or >=200, force to default 20; or, set the value cfg[20,200). */ ++ td_u32 scramble_interval; ++} hdmi_scdc_status; ++ ++typedef struct { ++ td_bool avi_enable; ++ td_bool audio_enable; ++ td_bool vsif_enable; ++ td_bool spd_enable; ++ td_bool mpeg_enable; ++ td_bool gbd_enable; ++ td_u8 avi[HDMI_INFO_FRAME_MAX_SIZE]; ++ td_u8 audio[HDMI_INFO_FRAME_MAX_SIZE]; ++ td_u8 vsif[HDMI_INFO_FRAME_MAX_SIZE]; ++ td_u8 spd[HDMI_INFO_FRAME_MAX_SIZE]; ++ td_u8 mpeg[HDMI_INFO_FRAME_MAX_SIZE]; ++ td_u8 gdb[HDMI_INFO_FRAME_MAX_SIZE]; ++} hdmi_infoframe_status; ++ ++typedef struct { ++ td_bool hdcp22_enable; ++ td_bool hdcp14_enable; ++ td_bool repeater_on; ++ td_u8 bksv[HDMI_BKSV_LEN]; ++ td_u8 aksv[HDMI_AKSV_LEN]; ++ td_u8 hdcp_status; ++} hdmi_hdcp_status; ++ ++typedef enum { ++ FRL_WORK_MODE_NONE, ++ FRL_WORK_MODE_3L3G, ++ FRL_WORK_MODE_3L6G, ++ FRL_WORK_MODE_4L6G, ++ FRL_WORK_MODE_4L8G, ++ FRL_WORK_MODE_4L10G, ++ FRL_WORK_MODE_4L12G, ++ FRL_WORK_MODE_BUTT ++} hdmi_work_mode; ++ ++typedef struct { ++ td_bool frl_start; ++ td_bool work_en; ++ hdmi_work_mode work_mode; ++} hdmi_frl_status; ++ ++typedef enum { ++ FRL_TXFFE_MODE_0, ++ FRL_TXFFE_MODE_1, ++ FRL_TXFFE_MODE_2, ++ FRL_TXFFE_MODE_3, ++ FRL_TXFFE_MODE_BUTT ++} hdmi_txfff_mode; ++ ++typedef struct { ++ hdmi_common_status common_status; ++ hdmi_phy_status phy_status; ++ hdmi_video_status video_status; ++ hdmi_audio_status audio_status; ++ hdmi_infoframe_status info_frame_status; ++ hdmi_hdcp_status hdcp_status; ++ hdmi_hwspec phy_hwspec; ++ hdmi_frl_status frl_status; ++} hdmi_hardware_status; ++ ++typedef struct { ++ td_u32 max_tmds_character_rate; ++ td_bool scdc_present; ++ td_bool rr_capable; ++ td_bool lte340_mcsc_scramble; ++ td_bool _3d_osd_disparity; ++ td_bool dual_view; ++ td_bool independent_view; ++ td_bool dc30bit420; ++ td_bool dc36bit420; ++ td_bool dc48bit420; ++ td_bool scdc_enable; ++} hdmi_scdc_config; ++ ++typedef struct { ++ td_u32 mute_delay; /* delay for avmute */ ++ td_u32 fmt_delay; /* delay for setformat */ ++ td_bool force_fmt_delay; /* force setformat delay mode */ ++ td_bool force_mute_delay; /* force avmute delay mode */ ++} hdmi_delay; ++ ++typedef enum { ++ HDMI_VIDEO_UNKNOWN, ++ HDMI_VIDEO_PROGRESSIVE, ++ HDMI_VIDEO_INTERLACE, ++ HDMI_VIDEO_BUTT ++} hdmi_video_format_type; ++ ++typedef struct { ++ hdmi_video_code_vic video_code; ++ td_u32 pixclk; ++ td_u32 rate; ++ td_u32 hactive; ++ td_u32 vactive; ++ td_u32 hblank; ++ td_u32 vblank; ++ td_u32 hfront; ++ td_u32 hsync; ++ td_u32 hback; ++ td_u32 vfront; ++ td_u32 vsync; ++ td_u32 vback; ++ hdmi_picture_aspect aspect_ratio; ++ hdmi_video_timing timing; ++ hdmi_video_format_type pi_type; ++ td_char *fmt_str; ++} hdmi_video_def; ++ ++typedef struct { ++ hdmi_vsif_vic hdmi_vic; ++ hdmi_video_code_vic equivalent_video_code; ++ td_u32 pixclk; ++ td_u32 rate; ++ td_u32 hactive; ++ td_u32 vactive; ++ hdmi_picture_aspect aspect_ratio; ++ hdmi_video_timing timing; ++ hdmi_video_format_type pi_type; ++ td_char *fmt_str; ++} hdmi_video_4k_def; ++ ++typedef struct { ++ td_u32 attach_in_time; ++ td_u32 attach_out_time; ++ td_u32 de_attach_in_time; ++ td_u32 de_attach_out_time; ++ td_u32 preformat_in_time; ++ td_u32 preformat_out_time; ++ td_u32 setformat_in_time; ++ td_u32 setformat_out_time; ++ td_u32 suspend_in_time; ++ td_u32 suspend_out_time; ++ td_u32 resume_in_time; ++ td_u32 resume_out_time; ++ td_u32 event_thread_cycle_time; ++} hdmi_intf_status; ++ ++typedef struct { ++ td_bool black_enable; ++ td_u8 in_color_space; ++ td_u8 in_bit_depth; ++ td_u8 in_quantization; ++} hdmi_black_frame_info; ++ ++typedef struct { ++ td_u32 stop_delay; ++ hdmi_intf_status intf_status; ++} hdmi_debug; ++ ++typedef enum { ++ HDMI_TIMER_ZERO_DRMIF, ++ HDMI_TIMER_SDR_TO_HDR10, ++ HDMI_TIMER_TYPE_BUTT ++} hdmi_timer_type; ++ ++typedef struct { ++ td_bool mute_pkg_en; ++ td_bool mute_set; ++ td_bool mute_clr; ++ td_bool mute_rpt_en; ++ td_u32 rpt_cnt; ++} hdmi_avmute_cfg; ++ ++typedef enum { ++ HDMI_FRL_SCDC_TYPE_SINK_VERSION, ++ HDMI_FRL_SCDC_TYPE_SOURCE_VERSION, ++ HDMI_FRL_SCDC_TYPE_UPDATE_FLAGS, ++ HDMI_FRL_SCDC_TYPE_STATUS_FLAGS, ++ HDMI_FRL_SCDC_TYPE_CONFIG, ++ HDMI_FRL_SCDC_TYPE_TXFFE_REQ, ++ HDMI_FRL_FLAGS_TYPE_BUTT ++} hdmi_frl_scdc_type; ++ ++typedef enum { ++ HDMI_FRL_TRAIN_PATTERN_NONE, ++ HDMI_FRL_TRAIN_PATTERN_LP1, ++ HDMI_FRL_TRAIN_PATTERN_LP2, ++ HDMI_FRL_TRAIN_PATTERN_LP3, ++ HDMI_FRL_TRAIN_PATTERN_LP4, ++ HDMI_FRL_TRAIN_PATTERN_LP5, ++ HDMI_FRL_TRAIN_PATTERN_LP6, ++ HDMI_FRL_TRAIN_PATTERN_LP7, ++ HDMI_FRL_TRAIN_PATTERN_LP8, ++ HDMI_FRL_TRAIN_PATTERN_RESERVED, ++ HDMI_FRL_TRAIN_PATTERN_0E = 0xE, ++ HDMI_FRL_TRAIN_PATTERN_0F = 0xF, ++ HDMI_FRL_TRAIN_PATTERN_BUTT ++} hdmi_frl_train_pattern; ++ ++typedef enum { ++ HDMI_FRL_TRAIN_NONE, ++ HDMI_FRL_TRAIN_FAIL, ++ HDMI_FRL_TRAIN_SUCCESS, ++ HDMI_FRL_TRAIN_BUSY, ++ HDMI_FRL_TRAIN_BUTT ++} hdmi_frl_train_status; ++ ++typedef enum { ++ HDMI_FRL_TRAIN_FAIL_NORMAL, ++ HDMI_FRL_TRAIN_FAIL_FLTTIMEOUT, ++ HDMI_FRL_TRAIN_FAIL_FLTSTEPTIMEOUT, ++ HDMI_FRL_TRAIN_FAIL_RATECHANGE, ++ HDMI_FRL_TRAIN_FAIL_FFECHANGE, ++ HDMI_FRL_TRAIN_FAIL_BUTT ++} hdmi_frl_train_fail_code; ++ ++typedef enum { ++ HDMI_FRL_TRAIN_SEL_SW, ++ HDMI_FRL_TRAIN_SEL_HW, ++ HDMI_FRL_TRAIN_SEL_BUTT ++} hdmi_frl_train_sel; ++ ++typedef enum { ++ FRL_DEBUG_RATE, ++ FRL_DEBUG_SW_TRAIN_SEL, ++ FRL_DEBUG_LTP_PATTERN, ++ FRL_DEBUG_SELECT_CHANNEL, ++ FRL_DEBUG_LTS3_INTERVAL, ++ FRL_DEBUG_LTS3_TIMEOUT, ++ FRL_DEBUG_TRAINING_BREAK, ++ FRL_DEBUG_LM_TABLE_GET, ++ FRL_DEBUG_CTRL_TYPE_CONFIG, ++ FRL_DEBUG_BUTT ++} frl_debug_cmd; ++ ++typedef enum { ++ FRL_SW_TRAIN_DELAY, ++ FRL_SW_TRAIN_TIMER, ++ FRL_SW_TRAIN_BUTT ++} frl_sw_train_mode; ++ ++typedef enum { ++ FRL_CHL_SEL_NORMAL, ++ FRL_CHL_SEL_RX_TMDS, ++ FRL_CHL_SEL_BUTT ++} frl_channel_sel; ++ ++typedef struct { ++ hdmi_frl_train_status frl_train_status; ++ hdmi_frl_train_pattern train_pattern[HDMI_FRL_LANE_MAX_NUM]; ++ hdmi_frl_train_fail_code train_fail_res; ++} hdmi_frl_train; ++ ++typedef enum { ++ HDMI_FRL_MACH_MODE_STEP, ++ HDMI_FRL_MACH_MODE_TIMEOUT, ++ HDMI_FRL_MACH_MODE_BUTT ++} hdmi_frl_mach_mode; ++ ++typedef struct { ++ td_bool frl_no_timeout; ++ td_u8 frl_rate; ++ td_u8 ffe_levels; ++ td_u32 train_timeout; ++ hdmi_frl_mach_mode mach_mode; ++ frl_sw_train_mode sw_train_mode; ++ td_u8 ctl_type_config; ++} hdmi_frl_train_config; ++ ++typedef struct { ++ frl_debug_cmd debug_cmd; ++ td_u8 rate; ++ td_u8 ltp; ++ td_u8 lane_idx; ++ td_u8 training_break; ++ frl_sw_train_mode sw_train_mode; ++ frl_channel_sel channel_sel; ++ td_u32 lts3_interval; ++ td_u32 lts3_timeout; ++ td_u8 crtl_type_config; ++ td_u8 avi_send_by_gen5; ++} frl_debug; ++ ++typedef enum { ++ SCDC_CMD_SET_SOURCE_VER, ++ SCDC_CMD_GET_SOURCE_VER, ++ SCDC_CMD_GET_SINK_VER, ++ SCDC_CMD_SET_FLT_UPDATE, ++ SCDC_CMD_GET_FLT_UPDATE, ++ SCDC_CMD_SET_FLT_UPDATE_TRIM, ++ SCDC_CMD_GET_FLT_UPDATE_TRIM, ++ SCDC_CMD_SET_FRL_START, ++ SCDC_CMD_GET_FRL_START, ++ SCDC_CMD_SET_CONFIG1, ++ SCDC_CMD_GET_CONFIG1, ++ SCDC_CMD_GET_TEST_CONFIG, ++ SCDC_CMD_GET_FLT_READY, ++ SCDC_CMD_GET_LTP_REQ, ++ SCDC_CMD_BUTT ++} scdc_cmd; ++ ++typedef struct { ++ td_u8 frl_rate; ++ td_u8 ffe_levels; ++} scdc_config1; ++ ++typedef struct { ++ td_bool pre_shoot_only; ++ td_bool de_emphasis_only; ++ td_bool no_ffe; ++ td_bool flt_no_timeout; ++ td_bool dsc_frl_max; ++ td_bool frl_max; ++} scdc_test_config; ++ ++typedef struct { ++ td_u8 ln0_ltp; ++ td_u8 ln1_ltp; ++ td_u8 ln2_ltp; ++ td_u8 ln3_ltp; ++} scdc_ltp_req; ++ ++typedef enum { ++ HDMI_PHY_MODE_CFG_TMDS, ++ HDMI_PHY_MODE_CFG_FRL, ++ HDMI_PHY_MODE_CFG_TXFFE ++} hdmi_phy_mode_cfg; ++ ++typedef enum { ++ HDMI_TRACE_LEN_0, /* 1.0 inch */ ++ HDMI_TRACE_LEN_1, /* 1.5 inch */ ++ HDMI_TRACE_LEN_2, /* 2.0 inch */ ++ HDMI_TRACE_LEN_3, /* 2.5 inch */ ++ HDMI_TRACE_LEN_4, /* 3.0 inch */ ++ HDMI_TRACE_LEN_5, /* 3.5 inch */ ++ HDMI_TRACE_LEN_6, /* 4.0 inch */ ++ HDMI_TRACE_LEN_7, /* 4.5 inch */ ++ HDMI_TRACE_LEN_8, /* 5.0 inch */ ++ HDMI_TRACE_DEFAULT, /* default config */ ++ HDMI_TRACE_BUTT ++} hdmi_trace_len; ++ ++typedef struct { ++ td_bool emi_en; ++ hdmi_trace_len trace_len; ++} hdmi_mode_param; ++ ++typedef struct { ++ td_u32 pixel_clk; ++ td_u32 tmds_clk; /* in khz */ ++ td_bool emi_enable; ++ hdmi_deep_color deep_color; /* deep color(color depth) */ ++ hdmi_phy_mode_cfg mode_cfg; /* tmds/frl/tx ffe */ ++ hdmi_trace_len trace_len; ++ hdmi_colorspace color_space; ++ hdmi_work_mode rate; /* lane and rate */ ++ hdmi_txfff_mode aen_tx_ffe[AEN_TX_FFE_LEN]; /* tx ffe */ ++} hdmi_phy_cfg; ++ ++hdmi_video_code_vic drv_hdmi_vic_search(hdmi_video_timing, hdmi_picture_aspect, td_bool); ++ ++td_void hdmi_reg_write(volatile td_u32 *reg_addr, td_u32 value); ++ ++td_u32 hdmi_reg_read(volatile td_u32 *reg_addr); ++ ++td_u32 drv_hdmi_vic_to_index(td_u32 vic); ++ ++hdmi_video_timing drv_hdmi_video_timing_get(hdmi_video_code_vic vic, hdmi_picture_aspect aspect); ++ ++hdmi_video_timing drv_hdmi_vsif_video_timing_get(hdmi_vsif_vic vic); ++ ++hdmi_video_4k_def *drv_hdmi_video_codes_4k_get(td_u32 cnt); ++ ++hdmi_video_def *drv_hdmi_comm_format_param_get(hdmi_video_code_vic vic); ++ ++#endif /* DRV_HDMI_COMMON_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/gfbg_reg.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/gfbg_reg.h +new file mode 100755 +index 000000000..b760b4a0e +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/gfbg_reg.h +@@ -0,0 +1,18438 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2019-2019. All rights reserved. ++ * Description: gfbg reg ++ */ ++ ++#ifndef GFBG_REG_H ++#define GFBG_REG_H ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif ++/* Define the union u_voctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 23; /* [22..0] */ ++ unsigned int g3_ck_gt_en : 1; /* [23] */ ++ unsigned int v2_ck_gt_en : 1; /* [24] */ ++ unsigned int wbc_dhd_ck_gt_en : 1; /* [25] */ ++ unsigned int g1_ck_gt_en : 1; /* [26] */ ++ unsigned int g0_ck_gt_en : 1; /* [27] */ ++ unsigned int v1_ck_gt_en : 1; /* [28] */ ++ unsigned int v0_ck_gt_en : 1; /* [29] */ ++ unsigned int chk_sum_en : 1; /* [30] */ ++ unsigned int vo_ck_gt_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_voctrl; ++ ++/* Define the union u_vointsta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_int : 1; /* [0] */ ++ unsigned int dhd0vtthd2_int : 1; /* [1] */ ++ unsigned int dhd0vtthd3_int : 1; /* [2] */ ++ unsigned int dhd0uf_int : 1; /* [3] */ ++ unsigned int dhd1vtthd1_int : 1; /* [4] */ ++ unsigned int dhd1vtthd2_int : 1; /* [5] */ ++ unsigned int dhd1vtthd3_int : 1; /* [6] */ ++ unsigned int dhd1uf_int : 1; /* [7] */ ++ unsigned int dsdvtthd1_int : 1; /* [8] */ ++ unsigned int dsdvtthd2_int : 1; /* [9] */ ++ unsigned int dsdvtthd3_int : 1; /* [10] */ ++ unsigned int dsduf_int : 1; /* [11] */ ++ unsigned int b0_err_int : 1; /* [12] */ ++ unsigned int b1_err_int : 1; /* [13] */ ++ unsigned int b2_err_int : 1; /* [14] */ ++ unsigned int wbc_dhd_over_int : 1; /* [15] */ ++ unsigned int vdac0_int : 1; /* [16] */ ++ unsigned int vdac1_int : 1; /* [17] */ ++ unsigned int vdac2_int : 1; /* [18] */ ++ unsigned int vdac3_int : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vointsta; ++ ++/* Define the union u_vomskintsta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_clr : 1; /* [0] */ ++ unsigned int dhd0vtthd2_clr : 1; /* [1] */ ++ unsigned int dhd0vtthd3_clr : 1; /* [2] */ ++ unsigned int dhd0uf_clr : 1; /* [3] */ ++ unsigned int dhd1vtthd1_clr : 1; /* [4] */ ++ unsigned int dhd1vtthd2_clr : 1; /* [5] */ ++ unsigned int dhd1vtthd3_clr : 1; /* [6] */ ++ unsigned int dhd1uf_clr : 1; /* [7] */ ++ unsigned int dsdvtthd1_clr : 1; /* [8] */ ++ unsigned int dsdvtthd2_clr : 1; /* [9] */ ++ unsigned int dsdvtthd3_clr : 1; /* [10] */ ++ unsigned int dsduf_clr : 1; /* [11] */ ++ unsigned int b0_err_clr : 1; /* [12] */ ++ unsigned int b1_err_clr : 1; /* [13] */ ++ unsigned int b2_err_clr : 1; /* [14] */ ++ unsigned int wbc_dhd_over_clr : 1; /* [15] */ ++ unsigned int vdac0_clr : 1; /* [16] */ ++ unsigned int vdac1_clr : 1; /* [17] */ ++ unsigned int vdac2_clr : 1; /* [18] */ ++ unsigned int vdac3_clr : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vomskintsta; ++ ++/* Define the union u_vointmsk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ ++ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ ++ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ ++ unsigned int dhd0uf_intmask : 1; /* [3] */ ++ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ ++ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ ++ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ ++ unsigned int dhd1uf_intmask : 1; /* [7] */ ++ unsigned int dsdvtthd1_intmask : 1; /* [8] */ ++ unsigned int dsdvtthd2_intmask : 1; /* [9] */ ++ unsigned int dsdvtthd3_intmask : 1; /* [10] */ ++ unsigned int dsduf_intmask : 1; /* [11] */ ++ unsigned int b0_err_intmask : 1; /* [12] */ ++ unsigned int b1_err_intmask : 1; /* [13] */ ++ unsigned int b2_err_intmask : 1; /* [14] */ ++ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ ++ unsigned int vdac0_intmask : 1; /* [16] */ ++ unsigned int vdac1_intmask : 1; /* [17] */ ++ unsigned int vdac2_intmask : 1; /* [18] */ ++ unsigned int vdac3_intmask : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vointmsk; ++ ++/* Define the union u_vodebug */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rm_en_chn : 4; /* [3..0] */ ++ unsigned int dhd0_ff_info : 2; /* [5..4] */ ++ unsigned int dhd1_ff_info : 2; /* [7..6] */ ++ unsigned int dsd0_ff_info : 2; /* [9..8] */ ++ unsigned int bfm_vga_en : 1; /* [10] */ ++ unsigned int bfm_cvbs_en : 1; /* [11] */ ++ unsigned int bfm_lcd_en : 1; /* [12] */ ++ unsigned int bfm_bt1120_en : 1; /* [13] */ ++ unsigned int wbc2_ff_info : 2; /* [15..14] */ ++ unsigned int wbc_mode : 4; /* [19..16] */ ++ unsigned int node_num : 4; /* [23..20] */ ++ unsigned int wbc_cmp_mode : 2; /* [25..24] */ ++ unsigned int bfm_mode : 3; /* [28..26] */ ++ unsigned int bfm_clk_sel : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vodebug; ++ ++/* Define the union u_vointsta1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_int : 1; /* [0] */ ++ unsigned int dhd0vtthd2_int : 1; /* [1] */ ++ unsigned int dhd0vtthd3_int : 1; /* [2] */ ++ unsigned int dhd0uf_int : 1; /* [3] */ ++ unsigned int dhd1vtthd1_int : 1; /* [4] */ ++ unsigned int dhd1vtthd2_int : 1; /* [5] */ ++ unsigned int dhd1vtthd3_int : 1; /* [6] */ ++ unsigned int dhd1uf_int : 1; /* [7] */ ++ unsigned int dsdvtthd1_int : 1; /* [8] */ ++ unsigned int dsdvtthd2_int : 1; /* [9] */ ++ unsigned int dsdvtthd3_int : 1; /* [10] */ ++ unsigned int dsduf_int : 1; /* [11] */ ++ unsigned int b0_err_int : 1; /* [12] */ ++ unsigned int b1_err_int : 1; /* [13] */ ++ unsigned int b2_err_int : 1; /* [14] */ ++ unsigned int wbc_dhd_over_int : 1; /* [15] */ ++ unsigned int vdac0_int : 1; /* [16] */ ++ unsigned int vdac1_int : 1; /* [17] */ ++ unsigned int vdac2_int : 1; /* [18] */ ++ unsigned int vdac3_int : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vointsta1; ++ ++/* Define the union u_vomskintsta1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_clr : 1; /* [0] */ ++ unsigned int dhd0vtthd2_clr : 1; /* [1] */ ++ unsigned int dhd0vtthd3_clr : 1; /* [2] */ ++ unsigned int dhd0uf_clr : 1; /* [3] */ ++ unsigned int dhd1vtthd1_clr : 1; /* [4] */ ++ unsigned int dhd1vtthd2_clr : 1; /* [5] */ ++ unsigned int dhd1vtthd3_clr : 1; /* [6] */ ++ unsigned int dhd1uf_clr : 1; /* [7] */ ++ unsigned int dsdvtthd1_clr : 1; /* [8] */ ++ unsigned int dsdvtthd2_clr : 1; /* [9] */ ++ unsigned int dsdvtthd3_clr : 1; /* [10] */ ++ unsigned int dsduf_clr : 1; /* [11] */ ++ unsigned int b0_err_clr : 1; /* [12] */ ++ unsigned int b1_err_clr : 1; /* [13] */ ++ unsigned int b2_err_clr : 1; /* [14] */ ++ unsigned int wbc_dhd_over_clr : 1; /* [15] */ ++ unsigned int vdac0_clr : 1; /* [16] */ ++ unsigned int vdac1_clr : 1; /* [17] */ ++ unsigned int vdac2_clr : 1; /* [18] */ ++ unsigned int vdac3_clr : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vomskintsta1; ++ ++/* Define the union u_vointmsk1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ ++ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ ++ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ ++ unsigned int dhd0uf_intmask : 1; /* [3] */ ++ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ ++ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ ++ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ ++ unsigned int dhd1uf_intmask : 1; /* [7] */ ++ unsigned int dsdvtthd1_intmask : 1; /* [8] */ ++ unsigned int dsdvtthd2_intmask : 1; /* [9] */ ++ unsigned int dsdvtthd3_intmask : 1; /* [10] */ ++ unsigned int dsduf_intmask : 1; /* [11] */ ++ unsigned int b0_err_intmask : 1; /* [12] */ ++ unsigned int b1_err_intmask : 1; /* [13] */ ++ unsigned int b2_err_intmask : 1; /* [14] */ ++ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ ++ unsigned int vdac0_intmask : 1; /* [16] */ ++ unsigned int vdac1_intmask : 1; /* [17] */ ++ unsigned int vdac2_intmask : 1; /* [18] */ ++ unsigned int vdac3_intmask : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vointmsk1; ++ ++/* Define the union u_volowpower_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rfs_ema : 3; /* [2..0] */ ++ unsigned int rfs_emaw : 2; /* [4..3] */ ++ unsigned int ret1n : 1; /* [5] */ ++ unsigned int rft_emaa : 3; /* [8..6] */ ++ unsigned int rft_emab : 3; /* [11..9] */ ++ unsigned int rfs_colldisn : 1; /* [12] */ ++ unsigned int rft_emasa : 1; /* [13] */ ++ unsigned int rftuhd_ema : 3; /* [16..14] */ ++ unsigned int rftuhd_emaw : 2; /* [18..17] */ ++ unsigned int rftuhd_emas : 1; /* [19] */ ++ unsigned int rftuhd_emap : 1; /* [20] */ ++ unsigned int rftuhd_stov : 1; /* [21] */ ++ unsigned int rftuhd_stovab : 1; /* [22] */ ++ unsigned int rfs_wabl : 1; /* [23] */ ++ unsigned int rfs_wablm : 2; /* [25..24] */ ++ unsigned int ras_ema : 3; /* [28..26] */ ++ unsigned int ras_emaw : 2; /* [30..29] */ ++ unsigned int ras_stov : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_volowpower_ctrl; ++ ++/* Define the union u_voufsta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_uf_sta : 1; /* [0] */ ++ unsigned int v1_uf_sta : 1; /* [1] */ ++ unsigned int reserved_0 : 1; /* [2] */ ++ unsigned int v3_uf_sta : 1; /* [3] */ ++ unsigned int reserved_1 : 4; /* [7..4] */ ++ unsigned int g0_uf_sta : 1; /* [8] */ ++ unsigned int g1_uf_sta : 1; /* [9] */ ++ unsigned int g2_uf_sta : 1; /* [10] */ ++ unsigned int g3_uf_sta : 1; /* [11] */ ++ unsigned int g4_uf_sta : 1; /* [12] */ ++ unsigned int reserved_2 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_voufsta; ++ ++/* Define the union u_voufclr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_uf_clr : 1; /* [0] */ ++ unsigned int v1_uf_clr : 1; /* [1] */ ++ unsigned int reserved_0 : 1; /* [2] */ ++ unsigned int v3_uf_clr : 1; /* [3] */ ++ unsigned int reserved_1 : 4; /* [7..4] */ ++ unsigned int g0_uf_clr : 1; /* [8] */ ++ unsigned int g1_uf_clr : 1; /* [9] */ ++ unsigned int g2_uf_clr : 1; /* [10] */ ++ unsigned int g3_uf_clr : 1; /* [11] */ ++ unsigned int g4_uf_clr : 1; /* [12] */ ++ unsigned int reserved_2 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_voufclr; ++ ++/* Define the union u_vointproc_tim */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vointproc_time : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vointproc_tim; ++ ++/* Define the union u_volowpower_ctrl1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rftf_rct : 2; /* [1..0] */ ++ unsigned int rftf_kp : 3; /* [4..2] */ ++ unsigned int rft_wtsel : 2; /* [6..5] */ ++ unsigned int rft_rtsel : 2; /* [8..7] */ ++ unsigned int rft_mtsel : 2; /* [10..9] */ ++ unsigned int rasshds_wtsel : 2; /* [12..11] */ ++ unsigned int rasshds_rtsel : 2; /* [14..13] */ ++ unsigned int rasshdm_wtsel : 2; /* [16..15] */ ++ unsigned int rasshdm_rtsel : 2; /* [18..17] */ ++ unsigned int rashds_wtsel : 2; /* [20..19] */ ++ unsigned int rashds_rtsel : 2; /* [22..21] */ ++ unsigned int rashdm_wtsel : 2; /* [24..23] */ ++ unsigned int rashdm_rtsel : 2; /* [26..25] */ ++ unsigned int ras_wtsel : 2; /* [28..27] */ ++ unsigned int ras_rtsel : 2; /* [30..29] */ ++ unsigned int ras_emas : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_volowpower_ctrl1; ++ ++/* Define the union u_vofpgadef */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_hdr_v_def : 1; /* [0] */ ++ unsigned int ot_hdr_g_def : 1; /* [1] */ ++ unsigned int ot_hdr_wd_def : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vofpgadef; ++ ++/* Define the union u_volowpower_ctrl2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int s14_rfshd_rm : 4; /* [3..0] */ ++ unsigned int s14_rfshs_rm : 4; /* [7..4] */ ++ unsigned int s14_rasehd_rm : 4; /* [11..8] */ ++ unsigned int s14_rashd_rm : 4; /* [15..12] */ ++ unsigned int s14_rfshd_rme : 1; /* [16] */ ++ unsigned int s14_rfshs_rme : 1; /* [17] */ ++ unsigned int s14_rasehd_rme : 1; /* [18] */ ++ unsigned int s14_rashd_rme : 1; /* [19] */ ++ unsigned int s14_rfthd_rma : 4; /* [23..20] */ ++ unsigned int s14_rfthd_rmb : 4; /* [27..24] */ ++ unsigned int s14_rfthd_rmea : 1; /* [28] */ ++ unsigned int s14_rfthd_rmeb : 1; /* [29] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_volowpower_ctrl2; ++ ++/* Define the union u_volowpower_ctrl3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int s14_rom_rm : 4; /* [3..0] */ ++ unsigned int s14_rom_rme : 1; /* [4] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_volowpower_ctrl3; ++ ++/* Define the union u_vomux_dac */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dac0_sel : 4; /* [3..0] */ ++ unsigned int dac1_sel : 4; /* [7..4] */ ++ unsigned int dac2_sel : 4; /* [11..8] */ ++ unsigned int dac3_sel : 4; /* [15..12] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vomux_dac; ++ ++/* Define the union u_vomux_testsync */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int test_dv : 1; /* [0] */ ++ unsigned int test_hsync : 1; /* [1] */ ++ unsigned int test_vsync : 1; /* [2] */ ++ unsigned int test_field : 1; /* [3] */ ++ unsigned int reserved_0 : 27; /* [30..4] */ ++ unsigned int vo_test_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vomux_testsync; ++ ++/* Define the union u_vomux_testdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int test_data : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vomux_testdata; ++ ++/* Define the union u_vo_dac_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dac_reg_rev : 16; /* [15..0] */ ++ unsigned int enctr : 4; /* [19..16] */ ++ unsigned int enextref : 1; /* [20] */ ++ unsigned int pdchopper : 1; /* [21] */ ++ unsigned int envbg : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac_ctrl; ++ ++/* Define the union u_vo_dac_otp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dac_otp_reg : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac_otp; ++ ++/* Define the union u_vo_dac0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac0_ctrl; ++ ++/* Define the union u_vo_dac1_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac1_ctrl; ++ ++/* Define the union u_vo_dac2_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac2_ctrl; ++ ++/* Define the union u_vo_dac3_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac3_ctrl; ++ ++/* Define the union u_vo_dac_stat0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cableout0 : 1; /* [0] */ ++ unsigned int cableout1 : 1; /* [1] */ ++ unsigned int cableout2 : 1; /* [2] */ ++ unsigned int cableout3 : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_dac_stat0; ++ ++/* Define the union u_cbm_bkg1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cbm_bkgcr1 : 10; /* [9..0] */ ++ unsigned int cbm_bkgcb1 : 10; /* [19..10] */ ++ unsigned int cbm_bkgy1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_cbm_bkg1; ++ ++/* Define the union u_cbm_mix1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int mixer_prio4 : 4; /* [19..16] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_cbm_mix1; ++ ++/* Define the union u_wbc_bmp_thd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_bmp_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_bmp_thd; ++ ++/* Define the union u_cbm_bkg2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cbm_bkgcr2 : 10; /* [9..0] */ ++ unsigned int cbm_bkgcb2 : 10; /* [19..10] */ ++ unsigned int cbm_bkgy2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_cbm_bkg2; ++ ++/* Define the union u_cbm_mix2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int mixer_prio4 : 4; /* [19..16] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_cbm_mix2; ++ ++/* Define the union u_hc_bmp_thd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hc_bmp_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hc_bmp_thd; ++ ++/* Define the union u_cbm_bkg3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cbm_bkgcr3 : 10; /* [9..0] */ ++ unsigned int cbm_bkgcb3 : 10; /* [19..10] */ ++ unsigned int cbm_bkgy3 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_cbm_bkg3; ++ ++/* Define the union u_cbm_mix3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_cbm_mix3; ++ ++/* Define the union u_mixv0_bkg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_bkgcr : 10; /* [9..0] */ ++ unsigned int mixer_bkgcb : 10; /* [19..10] */ ++ unsigned int mixer_bkgy : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mixv0_bkg; ++ ++/* Define the union u_mixv0_mix */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mixv0_mix; ++ ++/* Define the union u_mixg0_bkg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_bkgcr : 10; /* [9..0] */ ++ unsigned int mixer_bkgcb : 10; /* [19..10] */ ++ unsigned int mixer_bkgy : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mixg0_bkg; ++ ++/* Define the union u_mixg0_bkalpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mixg0_bkalpha; ++ ++/* Define the union u_mixg0_mix */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mixg0_mix; ++typedef union { ++ struct { ++ unsigned int v2_link : 2; /* [1..0] */ ++ unsigned int g3_link : 2; /* [3..2] */ ++ unsigned int g2_link : 2; /* borrow 2 bits from reserved for complie */ ++ unsigned int g4_link : 2; /* borrow 2 bits from reserved for complie */ ++ unsigned int reserved : 24; /* [31..8] */ ++ } bits; ++ unsigned int u32; ++} u_link_ctrl; ++ ++/* Define the union u_vpss_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vpss_en : 1; /* [0] */ ++ unsigned int chk_sum_en : 1; /* [1] */ ++ unsigned int dei_en : 1; /* [2] */ ++ unsigned int mcdi_en : 1; /* [3] */ ++ unsigned int nx2_vc1_en : 1; /* [4] */ ++ unsigned int rgme_en : 1; /* [5] */ ++ unsigned int meds_en : 1; /* [6] */ ++ unsigned int hsp_en : 1; /* [7] */ ++ unsigned int snr_en : 1; /* [8] */ ++ unsigned int tnr_en : 1; /* [9] */ ++ unsigned int rfr_en : 1; /* [10] */ ++ unsigned int ifmd_en : 1; /* [11] */ ++ unsigned int igbm_en : 1; /* [12] */ ++ unsigned int cue_en : 1; /* [13] */ ++ unsigned int scd_en : 1; /* [14] */ ++ unsigned int blk_det_en : 1; /* [15] */ ++ unsigned int reserved_0 : 7; /* [22..16] */ ++ unsigned int vpss_node_init : 1; /* [23] */ ++ unsigned int ram_bank : 4; /* [27..24] */ ++ unsigned int dei_debug_en : 1; /* [28] */ ++ unsigned int dei_repeat_mode : 1; /* [29] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vpss_ctrl; ++ ++/* Define the union u_vpss_miscellaneous */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 4; /* [3..0] */ ++ unsigned int reserved_1 : 4; /* [7..4] */ ++ unsigned int reserved_2 : 16; /* [23..8] */ ++ unsigned int ck_gt_en : 1; /* [24] */ ++ unsigned int ck_gt_en_calc : 1; /* [25] */ ++ unsigned int reserved_3 : 2; /* [27..26] */ ++ unsigned int reserved_4 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vpss_miscellaneous; ++ ++/* Define the union u_vpss_ftconfig */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int node_rst_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vpss_ftconfig; ++ ++/* Define the union u_para_up_vhd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_up_vhd_chn00 : 1; /* [0] */ ++ unsigned int para_up_vhd_chn01 : 1; /* [1] */ ++ unsigned int para_up_vhd_chn02 : 1; /* [2] */ ++ unsigned int para_up_vhd_chn03 : 1; /* [3] */ ++ unsigned int para_up_vhd_chn04 : 1; /* [4] */ ++ unsigned int para_up_vhd_chn05 : 1; /* [5] */ ++ unsigned int para_up_vhd_chn06 : 1; /* [6] */ ++ unsigned int para_up_vhd_chn07 : 1; /* [7] */ ++ unsigned int para_up_vhd_chn08 : 1; /* [8] */ ++ unsigned int para_up_vhd_chn09 : 1; /* [9] */ ++ unsigned int para_up_vhd_chn10 : 1; /* [10] */ ++ unsigned int para_up_vhd_chn11 : 1; /* [11] */ ++ unsigned int para_up_vhd_chn12 : 1; /* [12] */ ++ unsigned int para_up_vhd_chn13 : 1; /* [13] */ ++ unsigned int para_up_vhd_chn14 : 1; /* [14] */ ++ unsigned int para_up_vhd_chn15 : 1; /* [15] */ ++ unsigned int para_up_vhd_chn16 : 1; /* [16] */ ++ unsigned int para_up_vhd_chn17 : 1; /* [17] */ ++ unsigned int para_up_vhd_chn18 : 1; /* [18] */ ++ unsigned int para_up_vhd_chn19 : 1; /* [19] */ ++ unsigned int para_up_vhd_chn20 : 1; /* [20] */ ++ unsigned int para_up_vhd_chn21 : 1; /* [21] */ ++ unsigned int para_up_vhd_chn22 : 1; /* [22] */ ++ unsigned int para_up_vhd_chn23 : 1; /* [23] */ ++ unsigned int para_up_vhd_chn24 : 1; /* [24] */ ++ unsigned int para_up_vhd_chn25 : 1; /* [25] */ ++ unsigned int para_up_vhd_chn26 : 1; /* [26] */ ++ unsigned int para_up_vhd_chn27 : 1; /* [27] */ ++ unsigned int para_up_vhd_chn28 : 1; /* [28] */ ++ unsigned int para_up_vhd_chn29 : 1; /* [29] */ ++ unsigned int para_up_vhd_chn30 : 1; /* [30] */ ++ unsigned int para_up_vhd_chn31 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_para_up_vhd; ++ ++/* Define the union u_para_up_vsd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_up_vsd_chn00 : 1; /* [0] */ ++ unsigned int para_up_vsd_chn01 : 1; /* [1] */ ++ unsigned int para_up_vsd_chn02 : 1; /* [2] */ ++ unsigned int para_up_vsd_chn03 : 1; /* [3] */ ++ unsigned int para_up_vsd_chn04 : 1; /* [4] */ ++ unsigned int para_up_vsd_chn05 : 1; /* [5] */ ++ unsigned int para_up_vsd_chn06 : 1; /* [6] */ ++ unsigned int para_up_vsd_chn07 : 1; /* [7] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_para_up_vsd; ++ ++/* Define the union u_para_conflict_clr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_conflict_clr_hd : 1; /* [0] */ ++ unsigned int para_conflict_clr_sd : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_para_conflict_clr; ++ ++/* Define the union u_para_conflict_sta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_conflict_hd : 1; /* [0] */ ++ unsigned int para_conflict_sd : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_para_conflict_sta; ++ ++/* Define the union u_v0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ctrl; ++ ++/* Define the union u_v0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_upd; ++ ++/* Define the union u_v0_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_0reso_read; ++ ++/* Define the union u_v0_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ireso; ++ ++/* Define the union u_v0_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_dfpos; ++ ++/* Define the union u_v0_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_dlpos; ++ ++/* Define the union u_v0_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_vfpos; ++ ++/* Define the union u_v0_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_vlpos; ++ ++/* Define the union u_v0_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_bk; ++ ++/* Define the union u_v0_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_alpha; ++ ++/* Define the union u_v0_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mute_bk; ++ ++/* Define the union u_v0_rimwidth */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_width : 5; /* [4..0] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_rimwidth; ++ ++/* Define the union u_v0_rimcol0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_v0 : 10; /* [9..0] */ ++ unsigned int v0_rim_u0 : 10; /* [19..10] */ ++ unsigned int v0_rim_y0 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_rimcol0; ++ ++/* Define the union u_v0_rimcol1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_v1 : 10; /* [9..0] */ ++ unsigned int v0_rim_u1 : 10; /* [19..10] */ ++ unsigned int v0_rim_y1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_rimcol1; ++ ++/* Define the union u_v0_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_ctrl; ++ ++/* Define the union u_v0_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef00; ++ ++/* Define the union u_v0_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef01; ++ ++/* Define the union u_v0_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef02; ++ ++/* Define the union u_v0_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef10; ++ ++/* Define the union u_v0_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef11; ++ ++/* Define the union u_v0_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef12; ++ ++/* Define the union u_v0_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef20; ++ ++/* Define the union u_v0_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef21; ++ ++/* Define the union u_v0_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_coef22; ++ ++/* Define the union u_v0_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_scale; ++ ++/* Define the union u_v0_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_idc0; ++ ++/* Define the union u_v0_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_idc1; ++ ++/* Define the union u_v0_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_idc2; ++ ++/* Define the union u_v0_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_odc0; ++ ++/* Define the union u_v0_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_odc1; ++ ++/* Define the union u_v0_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_odc2; ++ ++/* Define the union u_v0_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_min_y; ++ ++/* Define the union u_v0_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_min_c; ++ ++/* Define the union u_v0_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_max_y; ++ ++/* Define the union u_v0_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_max_c; ++ ++/* Define the union u_v0_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef00; ++ ++/* Define the union u_v0_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef01; ++ ++/* Define the union u_v0_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef02; ++ ++/* Define the union u_v0_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef10; ++ ++/* Define the union u_v0_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef11; ++ ++/* Define the union u_v0_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef12; ++ ++/* Define the union u_v0_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef20; ++ ++/* Define the union u_v0_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef21; ++ ++/* Define the union u_v0_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_coef22; ++ ++/* Define the union u_v0_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_scale; ++ ++/* Define the union u_v0_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_idc0; ++ ++/* Define the union u_v0_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_idc1; ++ ++/* Define the union u_v0_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_idc2; ++ ++/* Define the union u_v0_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_odc0; ++ ++/* Define the union u_v0_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_odc1; ++ ++/* Define the union u_v0_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_odc2; ++ ++/* Define the union u_v0_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_min_y; ++ ++/* Define the union u_v0_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_min_c; ++ ++/* Define the union u_v0_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_max_y; ++ ++/* Define the union u_v0_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc2_max_c; ++ ++/* Define the union u_v0_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_v0_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_ot_pp_csc_ink_pos; ++ ++/* Define the union u_v0_zme_hinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int hzme_ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hinfo; ++ ++/* Define the union u_v0_zme_hsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int chfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int non_lnr_en : 1; /* [27] */ ++ unsigned int chmid_en : 1; /* [28] */ ++ unsigned int lhmid_en : 1; /* [29] */ ++ unsigned int chfir_en : 1; /* [30] */ ++ unsigned int lhfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hsp; ++ ++/* Define the union u_v0_zme_hloffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hloffset; ++ ++/* Define the union u_v0_zme_hcoffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hcoffset; ++ ++/* Define the union u_v0_zme_hzone0delta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int zone0_delta : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hzone0delta; ++ ++/* Define the union u_v0_zme_hzone2delta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int zone2_delta : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hzone2delta; ++ ++/* Define the union u_v0_zme_hzoneend */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int zone0_end : 12; /* [11..0] */ ++ unsigned int zone1_end : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hzoneend; ++ ++/* Define the union u_v0_zme_hl_shootctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hl_coring : 8; /* [7..0] */ ++ unsigned int hl_gain : 6; /* [13..8] */ ++ unsigned int hl_coringadj_en : 1; /* [14] */ ++ unsigned int hl_flatdect_mode : 1; /* [15] */ ++ unsigned int hl_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int hl_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hl_shootctrl; ++ ++/* Define the union u_v0_zme_hc_shootctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hc_coring : 8; /* [7..0] */ ++ unsigned int hc_gain : 6; /* [13..8] */ ++ unsigned int hc_coringadj_en : 1; /* [14] */ ++ unsigned int hc_flatdect_mode : 1; /* [15] */ ++ unsigned int hc_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int hc_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hc_shootctrl; ++ ++/* Define the union u_v0_zme_hcoef_ren */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_hf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hcoef_ren; ++ ++/* Define the union u_v0_zme_hcoef_rdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_hcoef_rdata; ++ ++/* Define the union u_v0_zme_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vinfo; ++ ++/* Define the union u_v0_zme_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int graphdet_en : 1; /* [16] */ ++ unsigned int reserved_0 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int vfir_1tap_en : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int lvmid_en : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int lvfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vsp; ++ ++/* Define the union u_v0_zme_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int vluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_voffset; ++ ++/* Define the union u_v0_zme_vboffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int vbluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vboffset; ++ ++/* Define the union u_v0_zme_vl_shootctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vl_coring : 8; /* [7..0] */ ++ unsigned int vl_gain : 6; /* [13..8] */ ++ unsigned int vl_coringadj_en : 1; /* [14] */ ++ unsigned int vl_flatdect_mode : 1; /* [15] */ ++ unsigned int vl_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int vl_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vl_shootctrl; ++ ++/* Define the union u_v0_zme_vc_shootctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vc_coring : 8; /* [7..0] */ ++ unsigned int vc_gain : 6; /* [13..8] */ ++ unsigned int vc_coringadj_en : 1; /* [14] */ ++ unsigned int vc_flatdect_mode : 1; /* [15] */ ++ unsigned int vc_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int vc_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vc_shootctrl; ++ ++/* Define the union u_v0_zme_vcoef_ren */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_vf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vcoef_ren; ++ ++/* Define the union u_v0_zme_vcoef_rdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_zme_vcoef_rdata; ++ ++/* Define the union u_v0_hfir_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_hfir_ctrl; ++ ++/* Define the union u_v0_hfircoef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_hfircoef01; ++ ++/* Define the union u_v0_hfircoef23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_hfircoef23; ++ ++/* Define the union u_v0_hfircoef45 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_hfircoef45; ++ ++/* Define the union u_v0_hfircoef67 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_hfircoef67; ++ ++/* Define the union u_v1_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ctrl; ++ ++/* Define the union u_v1_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_upd; ++ ++/* Define the union u_v1_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_0reso_read; ++ ++/* Define the union u_v1_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ireso; ++ ++/* Define the union u_v1_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_dfpos; ++ ++/* Define the union u_v1_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_dlpos; ++ ++/* Define the union u_v1_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_vfpos; ++ ++/* Define the union u_v1_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_vlpos; ++ ++/* Define the union u_v1_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_bk; ++ ++/* Define the union u_v1_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_alpha; ++ ++/* Define the union u_v1_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mute_bk; ++ ++/* Define the union u_v1_rimwidth */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_width : 5; /* [4..0] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_rimwidth; ++ ++/* Define the union u_v1_rimcol0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_v0 : 10; /* [9..0] */ ++ unsigned int v0_rim_u0 : 10; /* [19..10] */ ++ unsigned int v0_rim_y0 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_rimcol0; ++ ++/* Define the union u_v1_rimcol1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_v1 : 10; /* [9..0] */ ++ unsigned int v0_rim_u1 : 10; /* [19..10] */ ++ unsigned int v0_rim_y1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_rimcol1; ++ ++/* Define the union u_v1_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_ctrl; ++ ++/* Define the union u_v1_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef00; ++ ++/* Define the union u_v1_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef01; ++ ++/* Define the union u_v1_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef02; ++ ++/* Define the union u_v1_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef10; ++ ++/* Define the union u_v1_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef11; ++ ++/* Define the union u_v1_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef12; ++ ++/* Define the union u_v1_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef20; ++ ++/* Define the union u_v1_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef21; ++ ++/* Define the union u_v1_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_coef22; ++ ++/* Define the union u_v1_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_scale; ++ ++/* Define the union u_v1_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_idc0; ++ ++/* Define the union u_v1_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_idc1; ++ ++/* Define the union u_v1_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_idc2; ++ ++/* Define the union u_v1_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_odc0; ++ ++/* Define the union u_v1_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_odc1; ++ ++/* Define the union u_v1_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_odc2; ++ ++/* Define the union u_v1_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_min_y; ++ ++/* Define the union u_v1_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_min_c; ++ ++/* Define the union u_v1_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_max_y; ++ ++/* Define the union u_v1_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_max_c; ++ ++/* Define the union u_v1_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef00; ++ ++/* Define the union u_v1_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef01; ++ ++/* Define the union u_v1_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef02; ++ ++/* Define the union u_v1_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef10; ++ ++/* Define the union u_v1_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef11; ++ ++/* Define the union u_v1_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef12; ++ ++/* Define the union u_v1_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef20; ++ ++/* Define the union u_v1_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef21; ++ ++/* Define the union u_v1_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_coef22; ++ ++/* Define the union u_v1_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_scale; ++ ++/* Define the union u_v1_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_idc0; ++ ++/* Define the union u_v1_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_idc1; ++ ++/* Define the union u_v1_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_idc2; ++ ++/* Define the union u_v1_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_odc0; ++ ++/* Define the union u_v1_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_odc1; ++ ++/* Define the union u_v1_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_odc2; ++ ++/* Define the union u_v1_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_min_y; ++ ++/* Define the union u_v1_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_min_c; ++ ++/* Define the union u_v1_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_max_y; ++ ++/* Define the union u_v1_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc2_max_c; ++ ++/* Define the union u_v1_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_v1_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_ot_pp_csc_ink_pos; ++ ++/* Define the union u_v1_cvfir_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_vinfo; ++ ++/* Define the union u_v1_cvfir_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_vsp; ++ ++/* Define the union u_v1_cvfir_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_voffset; ++ ++/* Define the union u_v1_cvfir_vboffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_vboffset; ++ ++/* Define the union u_v1_cvfir_vcoef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_vcoef0; ++ ++/* Define the union u_v1_cvfir_vcoef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_vcoef1; ++ ++/* Define the union u_v1_cvfir_vcoef2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_cvfir_vcoef2; ++ ++/* Define the union u_v1_hfir_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_hfir_ctrl; ++ ++/* Define the union u_v1_hfircoef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_hfircoef01; ++ ++/* Define the union u_v1_hfircoef23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_hfircoef23; ++ ++/* Define the union u_v1_hfircoef45 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_hfircoef45; ++ ++/* Define the union u_v1_hfircoef67 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_hfircoef67; ++ ++/* Define the union u_v2_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ctrl; ++ ++/* Define the union u_v2_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_upd; ++ ++/* Define the union u_v2_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_0reso_read; ++ ++/* Define the union u_v2_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ireso; ++ ++/* Define the union u_v2_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_dfpos; ++ ++/* Define the union u_v2_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_dlpos; ++ ++/* Define the union u_v2_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_vfpos; ++ ++/* Define the union u_v2_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_vlpos; ++ ++/* Define the union u_v2_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_bk; ++ ++/* Define the union u_v2_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_alpha; ++ ++/* Define the union u_v2_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_mute_bk; ++ ++/* Define the union u_v2_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_ctrl; ++ ++/* Define the union u_v2_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef00; ++ ++/* Define the union u_v2_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef01; ++ ++/* Define the union u_v2_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef02; ++ ++/* Define the union u_v2_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef10; ++ ++/* Define the union u_v2_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef11; ++ ++/* Define the union u_v2_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef12; ++ ++/* Define the union u_v2_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef20; ++ ++/* Define the union u_v2_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef21; ++ ++/* Define the union u_v2_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_coef22; ++ ++/* Define the union u_v2_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_scale; ++ ++/* Define the union u_v2_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_idc0; ++ ++/* Define the union u_v2_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_idc1; ++ ++/* Define the union u_v2_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_idc2; ++ ++/* Define the union u_v2_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_odc0; ++ ++/* Define the union u_v2_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_odc1; ++ ++/* Define the union u_v2_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_odc2; ++ ++/* Define the union u_v2_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_min_y; ++ ++/* Define the union u_v2_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_min_c; ++ ++/* Define the union u_v2_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_max_y; ++ ++/* Define the union u_v2_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_max_c; ++ ++/* Define the union u_v2_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef00; ++ ++/* Define the union u_v2_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef01; ++ ++/* Define the union u_v2_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef02; ++ ++/* Define the union u_v2_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef10; ++ ++/* Define the union u_v2_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef11; ++ ++/* Define the union u_v2_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef12; ++ ++/* Define the union u_v2_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef20; ++ ++/* Define the union u_v2_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef21; ++ ++/* Define the union u_v2_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_coef22; ++ ++/* Define the union u_v2_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_scale; ++ ++/* Define the union u_v2_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_idc0; ++ ++/* Define the union u_v2_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_idc1; ++ ++/* Define the union u_v2_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_idc2; ++ ++/* Define the union u_v2_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_odc0; ++ ++/* Define the union u_v2_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_odc1; ++ ++/* Define the union u_v2_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_odc2; ++ ++/* Define the union u_v2_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_min_y; ++ ++/* Define the union u_v2_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_min_c; ++ ++/* Define the union u_v2_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_max_y; ++ ++/* Define the union u_v2_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc2_max_c; ++ ++/* Define the union u_v2_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_v2_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_ot_pp_csc_ink_pos; ++ ++/* Define the union u_v2_cvfir_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_vinfo; ++ ++/* Define the union u_v2_cvfir_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_vsp; ++ ++/* Define the union u_v2_cvfir_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_voffset; ++ ++/* Define the union u_v2_cvfir_vboffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_vboffset; ++ ++/* Define the union u_v2_cvfir_vcoef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_vcoef0; ++ ++/* Define the union u_v2_cvfir_vcoef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_vcoef1; ++ ++/* Define the union u_v2_cvfir_vcoef2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_cvfir_vcoef2; ++ ++/* Define the union u_v2_hfir_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_hfir_ctrl; ++ ++/* Define the union u_v2_hfircoef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_hfircoef01; ++ ++/* Define the union u_v2_hfircoef23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_hfircoef23; ++ ++/* Define the union u_v2_hfircoef45 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_hfircoef45; ++ ++/* Define the union u_v2_hfircoef67 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_hfircoef67; ++ ++/* Define the union u_v3_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ctrl; ++ ++/* Define the union u_v3_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_upd; ++ ++/* Define the union u_v3_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_0reso_read; ++ ++/* Define the union u_v3_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ireso; ++ ++/* Define the union u_v3_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_dfpos; ++ ++/* Define the union u_v3_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_dlpos; ++ ++/* Define the union u_v3_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_vfpos; ++ ++/* Define the union u_v3_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_vlpos; ++ ++/* Define the union u_v3_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_bk; ++ ++/* Define the union u_v3_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_alpha; ++ ++/* Define the union u_v3_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_mute_bk; ++ ++/* Define the union u_v3_rimwidth */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_width : 5; /* [4..0] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_rimwidth; ++ ++/* Define the union u_v3_rimcol0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_v0 : 10; /* [9..0] */ ++ unsigned int v0_rim_u0 : 10; /* [19..10] */ ++ unsigned int v0_rim_y0 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_rimcol0; ++ ++/* Define the union u_v3_rimcol1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int v0_rim_v1 : 10; /* [9..0] */ ++ unsigned int v0_rim_u1 : 10; /* [19..10] */ ++ unsigned int v0_rim_y1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_rimcol1; ++ ++/* Define the union u_v3_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_ctrl; ++ ++/* Define the union u_v3_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef00; ++ ++/* Define the union u_v3_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef01; ++ ++/* Define the union u_v3_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef02; ++ ++/* Define the union u_v3_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef10; ++ ++/* Define the union u_v3_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef11; ++ ++/* Define the union u_v3_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef12; ++ ++/* Define the union u_v3_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef20; ++ ++/* Define the union u_v3_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef21; ++ ++/* Define the union u_v3_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_coef22; ++ ++/* Define the union u_v3_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_scale; ++ ++/* Define the union u_v3_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_idc0; ++ ++/* Define the union u_v3_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_idc1; ++ ++/* Define the union u_v3_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_idc2; ++ ++/* Define the union u_v3_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_odc0; ++ ++/* Define the union u_v3_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_odc1; ++ ++/* Define the union u_v3_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_odc2; ++ ++/* Define the union u_v3_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_min_y; ++ ++/* Define the union u_v3_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_min_c; ++ ++/* Define the union u_v3_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_max_y; ++ ++/* Define the union u_v3_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_max_c; ++ ++/* Define the union u_v3_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef00; ++ ++/* Define the union u_v3_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef01; ++ ++/* Define the union u_v3_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef02; ++ ++/* Define the union u_v3_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef10; ++ ++/* Define the union u_v3_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef11; ++ ++/* Define the union u_v3_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef12; ++ ++/* Define the union u_v3_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef20; ++ ++/* Define the union u_v3_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef21; ++ ++/* Define the union u_v3_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_coef22; ++ ++/* Define the union u_v3_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_scale; ++ ++/* Define the union u_v3_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_idc0; ++ ++/* Define the union u_v3_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_idc1; ++ ++/* Define the union u_v3_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_idc2; ++ ++/* Define the union u_v3_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_odc0; ++ ++/* Define the union u_v3_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_odc1; ++ ++/* Define the union u_v3_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_odc2; ++ ++/* Define the union u_v3_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_min_y; ++ ++/* Define the union u_v3_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_min_c; ++ ++/* Define the union u_v3_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_max_y; ++ ++/* Define the union u_v3_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc2_max_c; ++ ++/* Define the union u_v3_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_v3_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_ot_pp_csc_ink_pos; ++ ++/* Define the union u_v3_hfir_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_hfir_ctrl; ++ ++/* Define the union u_v3_hfircoef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_hfircoef01; ++ ++/* Define the union u_v3_hfircoef23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_hfircoef23; ++ ++/* Define the union u_v3_hfircoef45 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_hfircoef45; ++ ++/* Define the union u_v3_hfircoef67 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v3_hfircoef67; ++ ++/* Define the union u_vp0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_upd; ++ ++/* Define the union u_vp0_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_ireso; ++ ++/* Define the union u_vp0_lbox_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_lbox_ctrl; ++ ++/* Define the union u_vp0_galpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_galpha; ++ ++/* Define the union u_vp0_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 12; /* [11..0] */ ++ unsigned int disp_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_dfpos; ++ ++/* Define the union u_vp0_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 12; /* [11..0] */ ++ unsigned int disp_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_dlpos; ++ ++/* Define the union u_vp0_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 12; /* [11..0] */ ++ unsigned int video_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_vfpos; ++ ++/* Define the union u_vp0_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 12; /* [11..0] */ ++ unsigned int video_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_vlpos; ++ ++/* Define the union u_vp0_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_bk; ++ ++/* Define the union u_vp0_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_alpha; ++ ++/* Define the union u_vp0_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vp0_mute_bk; ++ ++/* Define the union u_g0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g0_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ctrl; ++ ++/* Define the union u_g0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_upd; ++ ++/* Define the union u_g0_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_0reso_read; ++ ++/* Define the union u_g0_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ireso; ++ ++/* Define the union u_g0_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_dfpos; ++ ++/* Define the union u_g0_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_dlpos; ++ ++/* Define the union u_g0_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_vfpos; ++ ++/* Define the union u_g0_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_vlpos; ++ ++/* Define the union u_g0_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_bk; ++ ++/* Define the union u_g0_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_alpha; ++ ++/* Define the union u_g0_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_mute_bk; ++ ++/* Define the union u_g0_lbox_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_lbox_ctrl; ++ ++/* Define the union u_g0_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_ctrl; ++ ++/* Define the union u_g0_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef00; ++ ++/* Define the union u_g0_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef01; ++ ++/* Define the union u_g0_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef02; ++ ++/* Define the union u_g0_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef10; ++ ++/* Define the union u_g0_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef11; ++ ++/* Define the union u_g0_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef12; ++ ++/* Define the union u_g0_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef20; ++ ++/* Define the union u_g0_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef21; ++ ++/* Define the union u_g0_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_coef22; ++ ++/* Define the union u_g0_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_scale; ++ ++/* Define the union u_g0_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_idc0; ++ ++/* Define the union u_g0_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_idc1; ++ ++/* Define the union u_g0_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_idc2; ++ ++/* Define the union u_g0_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_odc0; ++ ++/* Define the union u_g0_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_odc1; ++ ++/* Define the union u_g0_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_odc2; ++ ++/* Define the union u_g0_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_min_y; ++ ++/* Define the union u_g0_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_min_c; ++ ++/* Define the union u_g0_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_max_y; ++ ++/* Define the union u_g0_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_max_c; ++ ++/* Define the union u_g0_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef00; ++ ++/* Define the union u_g0_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef01; ++ ++/* Define the union u_g0_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef02; ++ ++/* Define the union u_g0_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef10; ++ ++/* Define the union u_g0_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef11; ++ ++/* Define the union u_g0_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef12; ++ ++/* Define the union u_g0_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef20; ++ ++/* Define the union u_g0_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef21; ++ ++/* Define the union u_g0_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_coef22; ++ ++/* Define the union u_g0_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_scale; ++ ++/* Define the union u_g0_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_idc0; ++ ++/* Define the union u_g0_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_idc1; ++ ++/* Define the union u_g0_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_idc2; ++ ++/* Define the union u_g0_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_odc0; ++ ++/* Define the union u_g0_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_odc1; ++ ++/* Define the union u_g0_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_odc2; ++ ++/* Define the union u_g0_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_min_y; ++ ++/* Define the union u_g0_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_min_c; ++ ++/* Define the union u_g0_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_max_y; ++ ++/* Define the union u_g0_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc2_max_c; ++ ++/* Define the union u_g0_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_g0_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_ot_pp_csc_ink_pos; ++ ++/* Define the union u_g0_dof_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int dof_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_dof_ctrl; ++ ++/* Define the union u_g0_dof_step */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int left_step : 8; /* [7..0] */ ++ unsigned int right_step : 8; /* [15..8] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_dof_step; ++ ++/* Define the union u_g0_dof_bkg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dof_bk_cr : 10; /* [9..0] */ ++ unsigned int dof_bk_cb : 10; /* [19..10] */ ++ unsigned int dof_bk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_dof_bkg; ++ ++/* Define the union u_g0_dof_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dof_bk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_dof_alpha; ++ ++/* Define the union u_g0_zme_hinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_hinfo; ++ ++/* Define the union u_g0_zme_hsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int ahfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int chfir_mid_en : 1; /* [28] */ ++ unsigned int lhfir_mid_en : 1; /* [29] */ ++ unsigned int ahfir_mid_en : 1; /* [30] */ ++ unsigned int hfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_hsp; ++ ++/* Define the union u_g0_zme_hloffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_hloffset; ++ ++/* Define the union u_g0_zme_hcoffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_hcoffset; ++ ++/* Define the union u_g0_zme_coef_ren */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int apb_g0_vf_lren : 1; /* [1] */ ++ unsigned int reserved_1 : 1; /* [2] */ ++ unsigned int apb_g0_hf_lren : 1; /* [3] */ ++ unsigned int reserved_2 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_coef_ren; ++ ++/* Define the union u_g0_zme_coef_rdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_coef_rdata; ++ ++/* Define the union u_g0_zme_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int reserved_0 : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_vinfo; ++ ++/* Define the union u_g0_zme_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 9; /* [24..16] */ ++ unsigned int vafir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int reserved_1 : 1; /* [27] */ ++ unsigned int cvfir_mid_en : 1; /* [28] */ ++ unsigned int lvfir_mid_en : 1; /* [29] */ ++ unsigned int avfir_mid_en : 1; /* [30] */ ++ unsigned int vfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_vsp; ++ ++/* Define the union u_g0_zme_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbtm_offset : 16; /* [15..0] */ ++ unsigned int vtp_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g0_zme_voffset; ++ ++/* Define the union u_g1_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ctrl; ++ ++/* Define the union u_g1_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_upd; ++ ++/* Define the union u_g1_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_0reso_read; ++ ++/* Define the union u_g1_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ireso; ++ ++/* Define the union u_g1_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_dfpos; ++ ++/* Define the union u_g1_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_dlpos; ++ ++/* Define the union u_g1_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_vfpos; ++ ++/* Define the union u_g1_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_vlpos; ++ ++/* Define the union u_g1_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_bk; ++ ++/* Define the union u_g1_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_alpha; ++ ++/* Define the union u_g1_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_mute_bk; ++ ++/* Define the union u_g1_lbox_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_lbox_ctrl; ++ ++/* Define the union u_g1_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_ctrl; ++ ++/* Define the union u_g1_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef00; ++ ++/* Define the union u_g1_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef01; ++ ++/* Define the union u_g1_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef02; ++ ++/* Define the union u_g1_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef10; ++ ++/* Define the union u_g1_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef11; ++ ++/* Define the union u_g1_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef12; ++ ++/* Define the union u_g1_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef20; ++ ++/* Define the union u_g1_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef21; ++ ++/* Define the union u_g1_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_coef22; ++ ++/* Define the union u_g1_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_scale; ++ ++/* Define the union u_g1_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_idc0; ++ ++/* Define the union u_g1_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_idc1; ++ ++/* Define the union u_g1_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_idc2; ++ ++/* Define the union u_g1_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_odc0; ++ ++/* Define the union u_g1_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_odc1; ++ ++/* Define the union u_g1_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_odc2; ++ ++/* Define the union u_g1_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_min_y; ++ ++/* Define the union u_g1_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_min_c; ++ ++/* Define the union u_g1_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_max_y; ++ ++/* Define the union u_g1_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_max_c; ++ ++/* Define the union u_g1_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef00; ++ ++/* Define the union u_g1_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef01; ++ ++/* Define the union u_g1_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef02; ++ ++/* Define the union u_g1_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef10; ++ ++/* Define the union u_g1_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef11; ++ ++/* Define the union u_g1_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef12; ++ ++/* Define the union u_g1_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef20; ++ ++/* Define the union u_g1_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef21; ++ ++/* Define the union u_g1_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_coef22; ++ ++/* Define the union u_g1_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_scale; ++ ++/* Define the union u_g1_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_idc0; ++ ++/* Define the union u_g1_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_idc1; ++ ++/* Define the union u_g1_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_idc2; ++ ++/* Define the union u_g1_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_odc0; ++ ++/* Define the union u_g1_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_odc1; ++ ++/* Define the union u_g1_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_odc2; ++ ++/* Define the union u_g1_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_min_y; ++ ++/* Define the union u_g1_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_min_c; ++ ++/* Define the union u_g1_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_max_y; ++ ++/* Define the union u_g1_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc2_max_c; ++ ++/* Define the union u_g1_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_g1_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_ot_pp_csc_ink_pos; ++ ++/* Define the union u_g1_zme_hinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_hinfo; ++ ++/* Define the union u_g1_zme_hsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int ahfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int chfir_mid_en : 1; /* [28] */ ++ unsigned int lhfir_mid_en : 1; /* [29] */ ++ unsigned int ahfir_mid_en : 1; /* [30] */ ++ unsigned int hfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_hsp; ++ ++/* Define the union u_g1_zme_hloffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_hloffset; ++ ++/* Define the union u_g1_zme_hcoffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_hcoffset; ++ ++/* Define the union u_g1_zme_coef_ren */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int apb_g1_vf_lren : 1; /* [1] */ ++ unsigned int reserved_1 : 1; /* [2] */ ++ unsigned int apb_g1_hf_lren : 1; /* [3] */ ++ unsigned int reserved_2 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_coef_ren; ++ ++/* Define the union u_g1_zme_coef_rdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_coef_rdata; ++ ++/* Define the union u_g1_zme_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int reserved_0 : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_vinfo; ++ ++/* Define the union u_g1_zme_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 9; /* [24..16] */ ++ unsigned int vafir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int reserved_1 : 1; /* [27] */ ++ unsigned int cvfir_mid_en : 1; /* [28] */ ++ unsigned int lvfir_mid_en : 1; /* [29] */ ++ unsigned int avfir_mid_en : 1; /* [30] */ ++ unsigned int vfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_vsp; ++ ++/* Define the union u_g1_zme_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbtm_offset : 16; /* [15..0] */ ++ unsigned int vtp_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_zme_voffset; ++ ++/* Define the union u_g2_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ctrl; ++ ++/* Define the union u_g2_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_upd; ++ ++/* Define the union u_g2_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_0reso_read; ++ ++/* Define the union u_g2_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ireso; ++ ++/* Define the union u_g2_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_dfpos; ++ ++/* Define the union u_g2_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_dlpos; ++ ++/* Define the union u_g2_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_vfpos; ++ ++/* Define the union u_g2_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_vlpos; ++ ++/* Define the union u_g2_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_bk; ++ ++/* Define the union u_g2_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_alpha; ++ ++/* Define the union u_g2_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_mute_bk; ++ ++/* Define the union u_g2_lbox_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_lbox_ctrl; ++ ++/* Define the union u_g2_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_ctrl; ++ ++/* Define the union u_g2_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef00; ++ ++/* Define the union u_g2_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef01; ++ ++/* Define the union u_g2_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef02; ++ ++/* Define the union u_g2_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef10; ++ ++/* Define the union u_g2_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef11; ++ ++/* Define the union u_g2_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef12; ++ ++/* Define the union u_g2_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef20; ++ ++/* Define the union u_g2_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef21; ++ ++/* Define the union u_g2_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_coef22; ++ ++/* Define the union u_g2_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_scale; ++ ++/* Define the union u_g2_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_idc0; ++ ++/* Define the union u_g2_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_idc1; ++ ++/* Define the union u_g2_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_idc2; ++ ++/* Define the union u_g2_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_odc0; ++ ++/* Define the union u_g2_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_odc1; ++ ++/* Define the union u_g2_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_odc2; ++ ++/* Define the union u_g2_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_min_y; ++ ++/* Define the union u_g2_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_min_c; ++ ++/* Define the union u_g2_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_max_y; ++ ++/* Define the union u_g2_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_max_c; ++ ++/* Define the union u_g2_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef00; ++ ++/* Define the union u_g2_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef01; ++ ++/* Define the union u_g2_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef02; ++ ++/* Define the union u_g2_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef10; ++ ++/* Define the union u_g2_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef11; ++ ++/* Define the union u_g2_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef12; ++ ++/* Define the union u_g2_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef20; ++ ++/* Define the union u_g2_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef21; ++ ++/* Define the union u_g2_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_coef22; ++ ++/* Define the union u_g2_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_scale; ++ ++/* Define the union u_g2_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_idc0; ++ ++/* Define the union u_g2_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_idc1; ++ ++/* Define the union u_g2_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_idc2; ++ ++/* Define the union u_g2_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_odc0; ++ ++/* Define the union u_g2_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_odc1; ++ ++/* Define the union u_g2_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_odc2; ++ ++/* Define the union u_g2_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_min_y; ++ ++/* Define the union u_g2_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_min_c; ++ ++/* Define the union u_g2_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_max_y; ++ ++/* Define the union u_g2_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc2_max_c; ++ ++/* Define the union u_g2_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_g2_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g2_ot_pp_csc_ink_pos; ++ ++/* Define the union u_g3_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ctrl; ++ ++/* Define the union u_g3_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_upd; ++ ++/* Define the union u_g3_0reso_read */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_0reso_read; ++ ++/* Define the union u_g3_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ireso; ++ ++/* Define the union u_g3_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_dfpos; ++ ++/* Define the union u_g3_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_dlpos; ++ ++/* Define the union u_g3_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_vfpos; ++ ++/* Define the union u_g3_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_vlpos; ++ ++/* Define the union u_g3_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_bk; ++ ++/* Define the union u_g3_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_alpha; ++ ++/* Define the union u_g3_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_mute_bk; ++ ++/* Define the union u_g3_lbox_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_lbox_ctrl; ++ ++/* Define the union u_g3_ot_pp_csc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_ctrl; ++ ++/* Define the union u_g3_ot_pp_csc_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef00; ++ ++/* Define the union u_g3_ot_pp_csc_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef01; ++ ++/* Define the union u_g3_ot_pp_csc_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef02; ++ ++/* Define the union u_g3_ot_pp_csc_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef10; ++ ++/* Define the union u_g3_ot_pp_csc_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef11; ++ ++/* Define the union u_g3_ot_pp_csc_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef12; ++ ++/* Define the union u_g3_ot_pp_csc_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef20; ++ ++/* Define the union u_g3_ot_pp_csc_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef21; ++ ++/* Define the union u_g3_ot_pp_csc_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_coef22; ++ ++/* Define the union u_g3_ot_pp_csc_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_scale; ++ ++/* Define the union u_g3_ot_pp_csc_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_idc0; ++ ++/* Define the union u_g3_ot_pp_csc_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_idc1; ++ ++/* Define the union u_g3_ot_pp_csc_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_idc2; ++ ++/* Define the union u_g3_ot_pp_csc_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_odc0; ++ ++/* Define the union u_g3_ot_pp_csc_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_odc1; ++ ++/* Define the union u_g3_ot_pp_csc_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_odc2; ++ ++/* Define the union u_g3_ot_pp_csc_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_min_y; ++ ++/* Define the union u_g3_ot_pp_csc_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_min_c; ++ ++/* Define the union u_g3_ot_pp_csc_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_max_y; ++ ++/* Define the union u_g3_ot_pp_csc_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_max_c; ++ ++/* Define the union u_g3_ot_pp_csc2_coef00 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef00; ++ ++/* Define the union u_g3_ot_pp_csc2_coef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef01; ++ ++/* Define the union u_g3_ot_pp_csc2_coef02 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef02; ++ ++/* Define the union u_g3_ot_pp_csc2_coef10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef10; ++ ++/* Define the union u_g3_ot_pp_csc2_coef11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef11; ++ ++/* Define the union u_g3_ot_pp_csc2_coef12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef12; ++ ++/* Define the union u_g3_ot_pp_csc2_coef20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef20; ++ ++/* Define the union u_g3_ot_pp_csc2_coef21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef21; ++ ++/* Define the union u_g3_ot_pp_csc2_coef22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_coef22; ++ ++/* Define the union u_g3_ot_pp_csc2_scale */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_scale; ++ ++/* Define the union u_g3_ot_pp_csc2_idc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_idc0; ++ ++/* Define the union u_g3_ot_pp_csc2_idc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_idc1; ++ ++/* Define the union u_g3_ot_pp_csc2_idc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_idc2; ++ ++/* Define the union u_g3_ot_pp_csc2_odc0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_odc0; ++ ++/* Define the union u_g3_ot_pp_csc2_odc1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_odc1; ++ ++/* Define the union u_g3_ot_pp_csc2_odc2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_odc2; ++ ++/* Define the union u_g3_ot_pp_csc2_min_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_min_y; ++ ++/* Define the union u_g3_ot_pp_csc2_min_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_min_c; ++ ++/* Define the union u_g3_ot_pp_csc2_max_y */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_max_y; ++ ++/* Define the union u_g3_ot_pp_csc2_max_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc2_max_c; ++ ++/* Define the union u_g3_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_ink_ctrl; ++ ++/* Define the union u_g3_ot_pp_csc_ink_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_ot_pp_csc_ink_pos; ++ ++/* define the union reg_osb_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_v : 10; /* [9..0] */ ++ unsigned int osb_bk_u : 10; /* [19..10] */ ++ unsigned int osb_bk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int osb_mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_osb_mute_bk; ++ ++/* define the union reg_osb_bk_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_osb_bk_alpha; ++ ++/* define the union reg_osb_coef_rd_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_osb_coef_rd_en; ++ ++/* Define the union u_gp0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_upd; ++ ++/* Define the union u_gp0_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_ireso; ++ ++/* Define the union u_gp0_lbox_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_lbox_ctrl; ++ ++/* Define the union u_gp0_galpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_galpha; ++ ++/* Define the union u_gp0_dfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 12; /* [11..0] */ ++ unsigned int disp_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_dfpos; ++ ++/* Define the union u_gp0_dlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 12; /* [11..0] */ ++ unsigned int disp_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_dlpos; ++ ++/* Define the union u_gp0_vfpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 12; /* [11..0] */ ++ unsigned int video_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_vfpos; ++ ++/* Define the union u_gp0_vlpos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 12; /* [11..0] */ ++ unsigned int video_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_vlpos; ++ ++/* Define the union u_gp0_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_bk; ++ ++/* Define the union u_gp0_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_alpha; ++ ++/* Define the union u_gp0_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_mute_bk; ++ ++/* Define the union u_gp0_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_idc; ++ ++/* Define the union u_gp0_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_odc; ++ ++/* Define the union u_gp0_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_iodc; ++ ++/* Define the union u_gp0_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_p0; ++ ++/* Define the union u_gp0_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_p1; ++ ++/* Define the union u_gp0_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_p2; ++ ++/* Define the union u_gp0_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_p3; ++ ++/* Define the union u_gp0_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gp0_csc_p4; ++ ++/* Define the union u_wbc_g0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int auto_stop_en : 1; /* [10] */ ++ unsigned int reserved_0 : 15; /* [25..11] */ ++ unsigned int format_out : 2; /* [27..26] */ ++ unsigned int reserved_1 : 3; /* [30..28] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_ctrl; ++ ++/* Define the union u_wbc_g0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_upd; ++ ++/* Define the union u_wbc_g0_cmp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cmp_lossy_en : 1; /* [0] */ ++ unsigned int reserved_0 : 3; /* [3..1] */ ++ unsigned int cmp_drr : 4; /* [7..4] */ ++ unsigned int reserved_1 : 23; /* [30..8] */ ++ unsigned int cmp_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_cmp; ++ ++/* Define the union u_wbc_g0_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbcstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_stride; ++ ++/* Define the union u_wbc_g0_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_oreso; ++ ++/* Define the union u_wbc_g0_fcrop */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wfcrop : 12; /* [11..0] */ ++ unsigned int hfcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_fcrop; ++ ++/* Define the union u_wbc_g0_lcrop */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wlcrop : 12; /* [11..0] */ ++ unsigned int hlcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_g0_lcrop; ++ ++/* Define the union u_wbc_gp0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int auto_stop_en : 1; /* [10] */ ++ unsigned int reserved_0 : 1; /* [11] */ ++ unsigned int wbc_vtthd_mode : 1; /* [12] */ ++ unsigned int reserved_1 : 5; /* [17..13] */ ++ unsigned int three_d_mode : 2; /* [19..18] */ ++ unsigned int reserved_2 : 3; /* [22..20] */ ++ unsigned int flip_en : 1; /* [23] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int mode_out : 2; /* [29..28] */ ++ unsigned int reserved_3 : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_ctrl; ++ ++/* Define the union u_wbc_gp0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_upd; ++ ++/* Define the union u_wbc_gp0_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbclstride : 16; /* [15..0] */ ++ unsigned int wbccstride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_stride; ++ ++/* Define the union u_wbc_gp0_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_oreso; ++ ++/* Define the union u_wbc_gp0_fcrop */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wfcrop : 12; /* [11..0] */ ++ unsigned int hfcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_fcrop; ++ ++/* Define the union u_wbc_gp0_lcrop */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wlcrop : 12; /* [11..0] */ ++ unsigned int hlcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_lcrop; ++ ++/* Define the union u_wbc_gp0_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int dither_round : 1; /* [29] */ ++ unsigned int dither_mode : 1; /* [30] */ ++ unsigned int dither_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_dither_ctrl; ++ ++/* Define the union u_wbc_gp0_dither_coef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_coef0 : 8; /* [7..0] */ ++ unsigned int dither_coef1 : 8; /* [15..8] */ ++ unsigned int dither_coef2 : 8; /* [23..16] */ ++ unsigned int dither_coef3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_dither_coef0; ++ ++/* Define the union u_wbc_gp0_dither_coef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_coef4 : 8; /* [7..0] */ ++ unsigned int dither_coef5 : 8; /* [15..8] */ ++ unsigned int dither_coef6 : 8; /* [23..16] */ ++ unsigned int dither_coef7 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_dither_coef1; ++ ++/* Define the union u_wbc_gp0_hpzme */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int hpzme_mode : 1; /* [29] */ ++ unsigned int hpzme_mid_en : 1; /* [30] */ ++ unsigned int hpzme_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_gp0_hpzme; ++ ++/* Define the union u_wbc_me_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 10; /* [19..10] */ ++ unsigned int ofl_master : 1; /* [20] */ ++ unsigned int reserved_1 : 2; /* [22..21] */ ++ unsigned int mad_data_mode : 1; /* [23] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int reserved_2 : 1; /* [28] */ ++ unsigned int c_wbc_en : 1; /* [29] */ ++ unsigned int reserved_3 : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_ctrl; ++ ++/* Define the union u_wbc_me_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_upd; ++ ++/* Define the union u_wbc_me_wlen_sel */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wlen_sel : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_wlen_sel; ++ ++/* Define the union u_wbc_me_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbclstride : 16; /* [15..0] */ ++ unsigned int wbccstride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_stride; ++ ++/* Define the union u_wbc_me_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_oreso; ++ ++/* Define the union u_wbc_me_smmu_bypass */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int l_bypass : 1; /* [0] */ ++ unsigned int c_bypass : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_smmu_bypass; ++ ++/* Define the union u_wbc_me_paraup */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_hlcoef_upd : 1; /* [0] */ ++ unsigned int wbc_hccoef_upd : 1; /* [1] */ ++ unsigned int wbc_vlcoef_upd : 1; /* [2] */ ++ unsigned int wbc_vccoef_upd : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_paraup; ++ ++/* Define the union u_wbc_me_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int dither_round : 1; /* [29] */ ++ unsigned int dither_mode : 1; /* [30] */ ++ unsigned int dither_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_dither_ctrl; ++ ++/* Define the union u_wbc_me_dither_coef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_coef0 : 8; /* [7..0] */ ++ unsigned int dither_coef1 : 8; /* [15..8] */ ++ unsigned int dither_coef2 : 8; /* [23..16] */ ++ unsigned int dither_coef3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_dither_coef0; ++ ++/* Define the union u_wbc_me_dither_coef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_coef4 : 8; /* [7..0] */ ++ unsigned int dither_coef5 : 8; /* [15..8] */ ++ unsigned int dither_coef6 : 8; /* [23..16] */ ++ unsigned int dither_coef7 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_dither_coef1; ++ ++/* Define the union u_wbc_me_zme_hsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int hchfir_en : 1; /* [25] */ ++ unsigned int hlfir_en : 1; /* [26] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int hchmid_en : 1; /* [28] */ ++ unsigned int hlmid_en : 1; /* [29] */ ++ unsigned int hchmsc_en : 1; /* [30] */ ++ unsigned int hlmsc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_hsp; ++ ++/* Define the union u_wbc_me_zme_hloffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hor_loffset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_hloffset; ++ ++/* Define the union u_wbc_me_zme_hcoffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hor_coffset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_hcoffset; ++ ++/* Define the union u_wbc_me_zme_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 19; /* [18..0] */ ++ unsigned int zme_in_fmt : 2; /* [20..19] */ ++ unsigned int zme_out_fmt : 2; /* [22..21] */ ++ unsigned int vchfir_en : 1; /* [23] */ ++ unsigned int vlfir_en : 1; /* [24] */ ++ unsigned int reserved_1 : 3; /* [27..25] */ ++ unsigned int vchmid_en : 1; /* [28] */ ++ unsigned int vlmid_en : 1; /* [29] */ ++ unsigned int vchmsc_en : 1; /* [30] */ ++ unsigned int vlmsc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_vsp; ++ ++/* Define the union u_wbc_me_zme_vsr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_vsr; ++ ++/* Define the union u_wbc_me_zme_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int vluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_voffset; ++ ++/* Define the union u_wbc_me_zme_vboffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int vbluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_me_zme_vboffset; ++ ++/* Define the union u_wbc_fi_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 3; /* [12..10] */ ++ unsigned int addr_mode : 1; /* [13] */ ++ unsigned int fsize_mode : 1; /* [14] */ ++ unsigned int tnr_nrds_en : 1; /* [15] */ ++ unsigned int reserved_1 : 4; /* [19..16] */ ++ unsigned int ofl_master : 1; /* [20] */ ++ unsigned int data_width : 1; /* [21] */ ++ unsigned int reserved_2 : 2; /* [23..22] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int reserved_3 : 2; /* [29..28] */ ++ unsigned int cmp_en : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_ctrl; ++ ++/* Define the union u_wbc_fi_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_upd; ++ ++/* Define the union u_wbc_fi_wlen_sel */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wlen_sel : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_wlen_sel; ++ ++/* Define the union u_wbc_fi_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbclstride : 16; /* [15..0] */ ++ unsigned int wbccstride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_stride; ++ ++/* Define the union u_wbc_fi_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_oreso; ++ ++/* Define the union u_wbc_fi_smmu_bypass */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int l_bypass : 1; /* [0] */ ++ unsigned int c_bypass : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_smmu_bypass; ++ ++/* Define the union u_wbc_fi_frame_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_size : 23; /* [22..0] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_frame_size; ++ ++/* Define the union u_wbc_fi_hcds */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int hchfir_en : 1; /* [29] */ ++ unsigned int hchmid_en : 1; /* [30] */ ++ unsigned int hcds_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_hcds; ++ ++/* Define the union u_wbc_fi_hcds_coef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int coef1 : 10; /* [19..10] */ ++ unsigned int coef2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_hcds_coef0; ++ ++/* Define the union u_wbc_fi_hcds_coef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef3 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_hcds_coef1; ++ ++/* Define the union u_wbc_fi_cmp_mb */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mb_bits : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_mb; ++ ++/* Define the union u_wbc_fi_cmp_max_min */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int min_bits_cnt : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int max_bits_cnt : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_max_min; ++ ++/* Define the union u_wbc_fi_cmp_adj_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int adj_sad_thr : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int adj_sad_bit_thr : 8; /* [23..16] */ ++ unsigned int adj_spec_bit_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_adj_thr; ++ ++/* Define the union u_wbc_fi_cmp_big_grad */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int big_grad_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int big_grad_num_thr : 5; /* [12..8] */ ++ unsigned int reserved_1 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_big_grad; ++ ++/* Define the union u_wbc_fi_cmp_blk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smth_thr : 6; /* [5..0] */ ++ unsigned int reserved_0 : 2; /* [7..6] */ ++ unsigned int blk_comp_thr : 3; /* [10..8] */ ++ unsigned int reserved_1 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_blk; ++ ++/* Define the union u_wbc_fi_cmp_graphic_judge */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int graphic_en : 1; /* [0] */ ++ unsigned int reserved_0 : 15; /* [15..1] */ ++ unsigned int video_sad_thr : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_graphic_judge; ++ ++/* Define the union u_wbc_fi_cmp_rc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int sadbits_ngain : 3; /* [2..0] */ ++ unsigned int reserved_0 : 5; /* [7..3] */ ++ unsigned int rc_smth_gain : 3; /* [10..8] */ ++ unsigned int reserved_1 : 5; /* [15..11] */ ++ unsigned int max_trow_bits : 6; /* [21..16] */ ++ unsigned int reserved_2 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_rc; ++ ++/* Define the union u_wbc_fi_cmp_frame_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_size : 21; /* [20..0] */ ++ unsigned int reserved_0 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_fi_cmp_frame_size; ++ ++/* Define the union u_wbc_cmp_glb_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int is_lossless : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int dw_mode : 1; /* [2] */ ++ unsigned int sep_cmp_en : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_glb_info; ++ ++/* Define the union u_wbc_cmp_framesize */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_width : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int frame_height : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_framesize; ++ ++/* Define the union u_wbc_cmp_rc_cfg0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mb_bits_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int min_mb_bits_y : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg0; ++ ++/* Define the union u_wbc_cmp_rc_cfg2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_qp_y : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int sad_bits_ngain : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int rc_smth_ngain : 3; /* [18..16] */ ++ unsigned int reserved_2 : 5; /* [23..19] */ ++ unsigned int max_trow_bits : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg2; ++ ++/* Define the union u_wbc_cmp_rc_cfg3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_sad_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int min_sad_thr : 7; /* [22..16] */ ++ unsigned int reserved_1 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg3; ++ ++/* Define the union u_wbc_cmp_rc_cfg4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smth_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int still_thr : 7; /* [14..8] */ ++ unsigned int reserved_1 : 1; /* [15] */ ++ unsigned int big_grad_thr : 10; /* [25..16] */ ++ unsigned int reserved_2 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg4; ++ ++/* Define the union u_wbc_cmp_rc_cfg5 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smth_pix_num_thr : 6; /* [5..0] */ ++ unsigned int reserved_0 : 2; /* [7..6] */ ++ unsigned int still_pix_num_thr : 6; /* [13..8] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_2 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg5; ++ ++/* Define the union u_wbc_cmp_rc_cfg6 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int noise_sad : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int pix_diff_thr : 9; /* [24..16] */ ++ unsigned int reserved_1 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg6; ++ ++/* Define the union u_wbc_cmp_rc_cfg7 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg7; ++ ++/* Define the union u_wbc_cmp_rc_cfg8 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr_y : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr_y : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr_y : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr_y : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg8; ++ ++/* Define the union u_wbc_cmp_rc_cfg10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int est_err_gain : 5; /* [4..0] */ ++ unsigned int reserved_0 : 11; /* [15..5] */ ++ unsigned int max_est_err_level : 9; /* [24..16] */ ++ unsigned int max_vbv_buf_loss_thr : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_rc_cfg10; ++ ++/* Define the union u_wbc_cmp_outsize0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_size0_reg : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_outsize0; ++ ++/* Define the union u_wbc_cmp_max_row */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_size1_reg : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_max_row; ++ ++/* Define the union u_wbc_bmp_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 10; /* [19..10] */ ++ unsigned int ofl_master : 1; /* [20] */ ++ unsigned int data_width : 1; /* [21] */ ++ unsigned int reserved_1 : 2; /* [23..22] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int reserved_2 : 3; /* [30..28] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_bmp_ctrl; ++ ++/* Define the union u_wbc_bmp_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_bmp_upd; ++ ++/* Define the union u_wbc_bmp_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_bmp_oreso; ++ ++/* Define the union u_wbc_bmp_sum */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bmp_sum : 25; /* [24..0] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_bmp_sum; ++ ++/* Define the union u_wbc_dhd0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int p2i_en : 1; /* [0] */ ++ unsigned int root_path : 2; /* [2..1] */ ++ unsigned int reserved_0 : 19; /* [21..3] */ ++ unsigned int mode_out : 2; /* [23..22] */ ++ unsigned int three_d_mode : 2; /* [25..24] */ ++ unsigned int auto_stop_en : 1; /* [26] */ ++ unsigned int wbc_vtthd_mode : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_dhd0_ctrl; ++ ++/* Define the union u_wbc_dhd0_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_dhd0_upd; ++ ++/* Define the union u_wbc_dhd0_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_dhd0_oreso; ++ ++/* Define the union u_wd_hpzme_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_en : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hpzme_ctrl; ++ ++/* Define the union u_wd_hpzmecoef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hpzmecoef01; ++ ++/* Define the union u_wd_hpzmecoef23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hpzmecoef23; ++ ++/* Define the union u_wd_hpzmecoef45 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hpzmecoef45; ++ ++/* Define the union u_wd_hpzmecoef67 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hpzmecoef67; ++ ++/* Define the union u_wd_hcds_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_en : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hcds_ctrl; ++ ++/* Define the union u_wd_hcdscoef01 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hcdscoef01; ++ ++/* Define the union u_wd_hcdscoef23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hcdscoef23; ++ ++/* Define the union u_wd_hcdscoef45 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hcdscoef45; ++ ++/* Define the union u_wd_hcdscoef67 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_hcdscoef67; ++ ++/* Define the union u_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_ctrl; ++ ++/* Define the union u_dither_sed_y0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_y0; ++ ++/* Define the union u_dither_sed_u0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_u0; ++ ++/* Define the union u_dither_sed_v0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_v0; ++ ++/* Define the union u_dither_sed_w0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_w0; ++ ++/* Define the union u_dither_sed_y1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_y1; ++ ++/* Define the union u_dither_sed_u1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_u1; ++ ++/* Define the union u_dither_sed_v1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_v1; ++ ++/* Define the union u_dither_sed_w1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_w1; ++ ++/* Define the union u_dither_sed_y2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_y2; ++ ++/* Define the union u_dither_sed_u2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_u2; ++ ++/* Define the union u_dither_sed_v2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_v2; ++ ++/* Define the union u_dither_sed_w2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_w2; ++ ++/* Define the union u_dither_sed_y3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_y3; ++ ++/* Define the union u_dither_sed_u3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_u3; ++ ++/* Define the union u_dither_sed_v3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_v3; ++ ++/* Define the union u_dither_sed_w3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_sed_w3; ++ ++/* Define the union u_dither_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dither_thr; ++ ++/* Define the union u_wd_zme_hinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int hzme_ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hinfo; ++ ++/* Define the union u_wd_zme_hsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int chfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int non_lnr_en : 1; /* [27] */ ++ unsigned int chmid_en : 1; /* [28] */ ++ unsigned int lhmid_en : 1; /* [29] */ ++ unsigned int chfir_en : 1; /* [30] */ ++ unsigned int lhfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hsp; ++ ++/* Define the union u_wd_zme_hloffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hloffset; ++ ++/* Define the union u_wd_zme_hcoffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hcoffset; ++ ++/* Define the union u_wd_zme_hcoef_ren */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_hf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hcoef_ren; ++ ++/* Define the union u_wd_zme_hcoef_rdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hcoef_rdata; ++ ++/* Define the union u_wd_zme_hdraw */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hdraw_mode : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hdraw; ++ ++/* Define the union u_wd_zme_hratio */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hratio : 27; /* [26..0] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_hratio; ++ ++/* Define the union u_wd_zme_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vinfo; ++ ++/* Define the union u_wd_zme_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 16; /* [15..0] */ ++ unsigned int graphdet_en : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int vfir_1tap_en : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int lvmid_en : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int lvfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vsp; ++ ++/* Define the union u_wd_zme_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int vluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_voffset; ++ ++/* Define the union u_wd_zme_vboffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int vbluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vboffset; ++ ++/* Define the union u_wd_zme_vcoef_ren */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_vf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vcoef_ren; ++ ++/* Define the union u_wd_zme_vcoef_rdata */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vcoef_rdata; ++ ++/* Define the union u_wd_zme_vdraw */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vdraw_mode : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vdraw; ++ ++/* Define the union u_wd_zme_vratio */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 19; /* [18..0] */ ++ unsigned int reserved_0 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wd_zme_vratio; ++ ++/* Define the union u_dhd0_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int disp_mode : 3; /* [3..1] */ ++ unsigned int iop : 1; /* [4] */ ++ unsigned int intf_ivs : 1; /* [5] */ ++ unsigned int intf_ihs : 1; /* [6] */ ++ unsigned int intf_idv : 1; /* [7] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int hdmi420c_sel : 1; /* [9] */ ++ unsigned int hdmi420_en : 1; /* [10] */ ++ unsigned int uf_offline_en : 1; /* [11] */ ++ unsigned int reserved_1 : 2; /* [13..12] */ ++ unsigned int hdmi_mode : 1; /* [14] */ ++ unsigned int twochn_debug : 1; /* [15] */ ++ unsigned int twochn_en : 1; /* [16] */ ++ unsigned int reserved_2 : 1; /* [17] */ ++ unsigned int cbar_mode : 1; /* [18] */ ++ unsigned int sin_en : 1; /* [19] */ ++ unsigned int fpga_lmt_width : 7; /* [26..20] */ ++ unsigned int fpga_lmt_en : 1; /* [27] */ ++ unsigned int p2i_en : 1; /* [28] */ ++ unsigned int cbar_sel : 1; /* [29] */ ++ unsigned int cbar_en : 1; /* [30] */ ++ unsigned int intf_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ctrl; ++ ++/* Define the union u_dhd0_vsync1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vact : 16; /* [15..0] */ ++ unsigned int vbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vsync1; ++ ++/* Define the union u_dhd0_vsync2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vsync2; ++ ++/* Define the union u_dhd0_hsync1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hact : 16; /* [15..0] */ ++ unsigned int hbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_hsync1; ++ ++/* Define the union u_dhd0_hsync2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfb : 16; /* [15..0] */ ++ unsigned int hmid : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_hsync2; ++ ++/* Define the union u_dhd0_vplus1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bvact : 16; /* [15..0] */ ++ unsigned int bvbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vplus1; ++ ++/* Define the union u_dhd0_vplus2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bvfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vplus2; ++ ++/* Define the union u_dhd0_pwr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hpw : 16; /* [15..0] */ ++ unsigned int vpw : 8; /* [23..16] */ ++ unsigned int reserved_0 : 3; /* [26..24] */ ++ unsigned int multichn_en : 2; /* [28..27] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_pwr; ++ ++/* Define the union u_dhd0_vtthd3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vtmgthd3 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd3_mode : 1; /* [15] */ ++ unsigned int vtmgthd4 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd4_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vtthd3; ++ ++/* Define the union u_dhd0_vtthd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vtmgthd1 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd1_mode : 1; /* [15] */ ++ unsigned int vtmgthd2 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd2_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vtthd; ++ ++/* Define the union u_dhd0_parathd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int dfs_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_parathd; ++ ++/* Define the union u_dhd0_precharge_thd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tcon_precharge_thd : 17; /* [16..0] */ ++ unsigned int reserved_0 : 3; /* [19..17] */ ++ unsigned int vsync_te_mode : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_precharge_thd; ++ ++/* Define the union u_dhd0_start_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int start_pos : 8; /* [7..0] */ ++ unsigned int timing_start_pos : 8; /* [15..8] */ ++ unsigned int fi_start_pos : 4; /* [19..16] */ ++ unsigned int req_start_pos : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_start_pos; ++ ++/* Define the union u_dhd0_start_pos1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_start_pos1 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_start_pos1; ++ ++/* Define the union u_dhd0_paraup */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int paraup_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_paraup; ++ ++/* Define the union u_dhd0_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lcd_dv_inv : 1; /* [0] */ ++ unsigned int lcd_hs_inv : 1; /* [1] */ ++ unsigned int lcd_vs_inv : 1; /* [2] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int vga_dv_inv : 1; /* [4] */ ++ unsigned int vga_hs_inv : 1; /* [5] */ ++ unsigned int vga_vs_inv : 1; /* [6] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int hdmi_dv_inv : 1; /* [8] */ ++ unsigned int hdmi_hs_inv : 1; /* [9] */ ++ unsigned int hdmi_vs_inv : 1; /* [10] */ ++ unsigned int hdmi_f_inv : 1; /* [11] */ ++ unsigned int date_dv_inv : 1; /* [12] */ ++ unsigned int date_hs_inv : 1; /* [13] */ ++ unsigned int date_vs_inv : 1; /* [14] */ ++ unsigned int date_f_inv : 1; /* [15] */ ++ unsigned int reserved_2 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_sync_inv; ++ ++/* Define the union u_dhd0_clk_dv_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int intf_clk_mux : 1; /* [0] */ ++ unsigned int intf_dv_mux : 1; /* [1] */ ++ unsigned int no_active_area_pos : 16; /* [17..2] */ ++ unsigned int reserved_0 : 14; /* [31..18] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_clk_dv_ctrl; ++ ++/* Define the union u_dhd0_rgb_fix_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fix_b : 10; /* [9..0] */ ++ unsigned int fix_g : 10; /* [19..10] */ ++ unsigned int fix_r : 10; /* [29..20] */ ++ unsigned int rgb_fix_mux : 1; /* [30] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_rgb_fix_ctrl; ++ ++/* Define the union u_dhd0_lockcfg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int measure_en : 1; /* [0] */ ++ unsigned int lock_cnt_en : 1; /* [1] */ ++ unsigned int vdp_measure_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_lockcfg; ++ ++/* Define the union u_dhd0_intf_chksum_high1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int r0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_intf_chksum_high1; ++ ++/* Define the union u_dhd0_intf_chksum_high2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int r1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_intf_chksum_high2; ++ ++/* Define the union u_dhd0_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vback_blank : 1; /* [0] */ ++ unsigned int vblank : 1; /* [1] */ ++ unsigned int bottom_field : 1; /* [2] */ ++ unsigned int vcnt : 13; /* [15..3] */ ++ unsigned int count_int : 8; /* [23..16] */ ++ unsigned int dhd_even : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_state; ++ ++/* Define the union u_dhd0_uf_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ud_first_cnt : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int start_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_uf_state; ++ ++/* Define the union u_vo_mux */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mipi_sel : 4; /* [3..0] */ ++ unsigned int lcd_sel : 4; /* [7..4] */ ++ unsigned int bt_sel : 4; /* [11..8] */ ++ unsigned int sddate_sel : 4; /* [15..12] */ ++ unsigned int hdmi_sel : 4; /* [19..16] */ ++ unsigned int hdmi1_sel : 4; /* [23..20] */ ++ unsigned int vga_sel : 4; /* [27..24] */ ++ unsigned int digital_sel : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_mux; ++ ++/* Define the union u_vo_mux_sync */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int sync_dv : 1; /* [0] */ ++ unsigned int sync_hsync : 1; /* [1] */ ++ unsigned int sync_vsync : 1; /* [2] */ ++ unsigned int sync_field : 1; /* [3] */ ++ unsigned int reserved_0 : 27; /* [30..4] */ ++ unsigned int sync_test_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_mux_sync; ++ ++/* Define the union u_vo_mux_data */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vomux_data : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vo_mux_data; ++ ++/* Define the union u_dhd0_vsync_te_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vsync_te_start_sta : 8; /* [7..0] */ ++ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ ++ unsigned int vsync_te_end_sta : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vsync_te_state; ++ ++/* Define the union u_dhd0_vsync_te_state1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vsync_te_vfb : 16; /* [15..0] */ ++ unsigned int vsync_te_width : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_vsync_te_state1; ++ ++/* Define the union u_dhd0_ccdoimgmod */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int img_mode : 7; /* [6..0] */ ++ unsigned int img_right : 1; /* [7] */ ++ unsigned int img_id : 2; /* [9..8] */ ++ unsigned int slave_mode : 1; /* [10] */ ++ unsigned int ccd_en : 1; /* [11] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int vbi_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ccdoimgmod; ++ ++/* Define the union u_dhd0_ccdoposmskh */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int p32_en : 1; /* [0] */ ++ unsigned int p33_en : 1; /* [1] */ ++ unsigned int p34_en : 1; /* [2] */ ++ unsigned int p35_en : 1; /* [3] */ ++ unsigned int p36_en : 1; /* [4] */ ++ unsigned int p37_en : 1; /* [5] */ ++ unsigned int p38_en : 1; /* [6] */ ++ unsigned int p39_en : 1; /* [7] */ ++ unsigned int p40_en : 1; /* [8] */ ++ unsigned int p41_en : 1; /* [9] */ ++ unsigned int p42_en : 1; /* [10] */ ++ unsigned int p43_en : 1; /* [11] */ ++ unsigned int p44_en : 1; /* [12] */ ++ unsigned int p45_en : 1; /* [13] */ ++ unsigned int p46_en : 1; /* [14] */ ++ unsigned int p47_en : 1; /* [15] */ ++ unsigned int p48_en : 1; /* [16] */ ++ unsigned int p49_en : 1; /* [17] */ ++ unsigned int p50_en : 1; /* [18] */ ++ unsigned int p51_en : 1; /* [19] */ ++ unsigned int p52_en : 1; /* [20] */ ++ unsigned int p53_en : 1; /* [21] */ ++ unsigned int p54_en : 1; /* [22] */ ++ unsigned int p55_en : 1; /* [23] */ ++ unsigned int p56_en : 1; /* [24] */ ++ unsigned int p57_en : 1; /* [25] */ ++ unsigned int p58_en : 1; /* [26] */ ++ unsigned int p59_en : 1; /* [27] */ ++ unsigned int p60_en : 1; /* [28] */ ++ unsigned int p61_en : 1; /* [29] */ ++ unsigned int p62_en : 1; /* [30] */ ++ unsigned int p63_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ccdoposmskh; ++ ++/* Define the union u_dhd0_ccdoposmskl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int p0_en : 1; /* [0] */ ++ unsigned int p1_en : 1; /* [1] */ ++ unsigned int p2_en : 1; /* [2] */ ++ unsigned int p3_en : 1; /* [3] */ ++ unsigned int p4_en : 1; /* [4] */ ++ unsigned int p5_en : 1; /* [5] */ ++ unsigned int p6_en : 1; /* [6] */ ++ unsigned int p7_en : 1; /* [7] */ ++ unsigned int p8_en : 1; /* [8] */ ++ unsigned int p9_en : 1; /* [9] */ ++ unsigned int p10_en : 1; /* [10] */ ++ unsigned int p11_en : 1; /* [11] */ ++ unsigned int p12_en : 1; /* [12] */ ++ unsigned int p13_en : 1; /* [13] */ ++ unsigned int p14_en : 1; /* [14] */ ++ unsigned int p15_en : 1; /* [15] */ ++ unsigned int p16_en : 1; /* [16] */ ++ unsigned int p17_en : 1; /* [17] */ ++ unsigned int p18_en : 1; /* [18] */ ++ unsigned int p19_en : 1; /* [19] */ ++ unsigned int p20_en : 1; /* [20] */ ++ unsigned int p21_en : 1; /* [21] */ ++ unsigned int p22_en : 1; /* [22] */ ++ unsigned int p23_en : 1; /* [23] */ ++ unsigned int p24_en : 1; /* [24] */ ++ unsigned int p25_en : 1; /* [25] */ ++ unsigned int p26_en : 1; /* [26] */ ++ unsigned int p27_en : 1; /* [27] */ ++ unsigned int p28_en : 1; /* [28] */ ++ unsigned int p29_en : 1; /* [29] */ ++ unsigned int p30_en : 1; /* [30] */ ++ unsigned int p31_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ccdoposmskl; ++ ++/* Define the union u_dhd0_dacdet1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vdac_det_high : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int det_line : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_dacdet1; ++ ++/* Define the union u_dhd0_dacdet2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int det_pixel_sta : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int det_pixel_wid : 11; /* [26..16] */ ++ unsigned int reserved_1 : 4; /* [30..27] */ ++ unsigned int vdac_det_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_dacdet2; ++ ++/* Define the union u_dhd0_ccd_info1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int img_mode : 7; /* [6..0] */ ++ unsigned int img_right : 1; /* [7] */ ++ unsigned int img_id : 2; /* [9..8] */ ++ unsigned int reserved_0 : 1; /* [10] */ ++ unsigned int ccd_en : 1; /* [11] */ ++ unsigned int reserved_1 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ccd_info1; ++ ++/* Define the union u_dhd0_ccd_info2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int p32_en : 1; /* [0] */ ++ unsigned int p33_en : 1; /* [1] */ ++ unsigned int p34_en : 1; /* [2] */ ++ unsigned int p35_en : 1; /* [3] */ ++ unsigned int p36_en : 1; /* [4] */ ++ unsigned int p37_en : 1; /* [5] */ ++ unsigned int p38_en : 1; /* [6] */ ++ unsigned int p39_en : 1; /* [7] */ ++ unsigned int p40_en : 1; /* [8] */ ++ unsigned int p41_en : 1; /* [9] */ ++ unsigned int p42_en : 1; /* [10] */ ++ unsigned int p43_en : 1; /* [11] */ ++ unsigned int p44_en : 1; /* [12] */ ++ unsigned int p45_en : 1; /* [13] */ ++ unsigned int p46_en : 1; /* [14] */ ++ unsigned int p47_en : 1; /* [15] */ ++ unsigned int p48_en : 1; /* [16] */ ++ unsigned int p49_en : 1; /* [17] */ ++ unsigned int p50_en : 1; /* [18] */ ++ unsigned int p51_en : 1; /* [19] */ ++ unsigned int p52_en : 1; /* [20] */ ++ unsigned int p53_en : 1; /* [21] */ ++ unsigned int p54_en : 1; /* [22] */ ++ unsigned int p55_en : 1; /* [23] */ ++ unsigned int p56_en : 1; /* [24] */ ++ unsigned int p57_en : 1; /* [25] */ ++ unsigned int p58_en : 1; /* [26] */ ++ unsigned int p59_en : 1; /* [27] */ ++ unsigned int p60_en : 1; /* [28] */ ++ unsigned int p61_en : 1; /* [29] */ ++ unsigned int p62_en : 1; /* [30] */ ++ unsigned int p63_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ccd_info2; ++ ++/* Define the union u_dhd0_ccd_info3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int p0_en : 1; /* [0] */ ++ unsigned int p1_en : 1; /* [1] */ ++ unsigned int p2_en : 1; /* [2] */ ++ unsigned int p3_en : 1; /* [3] */ ++ unsigned int p4_en : 1; /* [4] */ ++ unsigned int p5_en : 1; /* [5] */ ++ unsigned int p6_en : 1; /* [6] */ ++ unsigned int p7_en : 1; /* [7] */ ++ unsigned int p8_en : 1; /* [8] */ ++ unsigned int p9_en : 1; /* [9] */ ++ unsigned int p10_en : 1; /* [10] */ ++ unsigned int p11_en : 1; /* [11] */ ++ unsigned int p12_en : 1; /* [12] */ ++ unsigned int p13_en : 1; /* [13] */ ++ unsigned int p14_en : 1; /* [14] */ ++ unsigned int p15_en : 1; /* [15] */ ++ unsigned int p16_en : 1; /* [16] */ ++ unsigned int p17_en : 1; /* [17] */ ++ unsigned int p18_en : 1; /* [18] */ ++ unsigned int p19_en : 1; /* [19] */ ++ unsigned int p20_en : 1; /* [20] */ ++ unsigned int p21_en : 1; /* [21] */ ++ unsigned int p22_en : 1; /* [22] */ ++ unsigned int p23_en : 1; /* [23] */ ++ unsigned int p24_en : 1; /* [24] */ ++ unsigned int p25_en : 1; /* [25] */ ++ unsigned int p26_en : 1; /* [26] */ ++ unsigned int p27_en : 1; /* [27] */ ++ unsigned int p28_en : 1; /* [28] */ ++ unsigned int p29_en : 1; /* [29] */ ++ unsigned int p30_en : 1; /* [30] */ ++ unsigned int p31_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd0_ccd_info3; ++ ++/* Define the union u_intf_hdmi_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int hdmi_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_hdmi_ctrl; ++ ++/* Define the union u_intf_hdmi_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_hdmi_upd; ++ ++/* Define the union u_intf_hdmi_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_hdmi_sync_inv; ++ ++/* Define the union u_hdmi_intf_chksum_high */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int r0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_intf_chksum_high; ++ ++/* Define the union u_hdmi_intf1_chksum_high */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int r1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_intf1_chksum_high; ++ ++/* Define the union u_hdmi_hfir_coef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_hfir_coef0; ++ ++/* Define the union u_hdmi_hfir_coef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_hfir_coef1; ++ ++/* Define the union u_hdmi_hfir_coef2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_hfir_coef2; ++ ++/* Define the union u_hdmi_hfir_coef3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_hfir_coef3; ++ ++/* Define the union u_hdmi_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_idc; ++ ++/* Define the union u_hdmi_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_odc; ++ ++/* Define the union u_hdmi_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_iodc; ++ ++/* Define the union u_hdmi_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_p0; ++ ++/* Define the union u_hdmi_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_p1; ++ ++/* Define the union u_hdmi_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_p2; ++ ++/* Define the union u_hdmi_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_p3; ++ ++/* Define the union u_hdmi_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi_csc_p4; ++ ++/* Define the union u_intf_mipi_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_mipi_ctrl; ++ ++/* Define the union u_intf_mipi_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_mipi_upd; ++ ++/* Define the union u_intf_mipi_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_mipi_sync_inv; ++ ++/* Define the union u_mipi_intf_chksum_high */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int b0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int r0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mipi_intf_chksum_high; ++ ++/* Define the union u_mipi_intf1_chksum_high */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int b1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int r1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mipi_intf1_chksum_high; ++ ++/* Define the union u_mipi_hfir_coef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mipi_hfir_coef0; ++ ++/* Define the union u_mipi_hfir_coef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mipi_hfir_coef1; ++ ++/* Define the union u_mipi_hfir_coef2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mipi_hfir_coef2; ++ ++/* Define the union u_mipi_hfir_coef3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mipi_hfir_coef3; ++ ++/* Define the union u_intf_bt_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 16; /* [15..0] */ ++ unsigned int data_width : 1; /* [16] */ ++ unsigned int bit_inv : 1; /* [17] */ ++ unsigned int uv_mode : 1; /* [18] */ ++ unsigned int yc_mode : 1; /* [19] */ ++ unsigned int reserved_1 : 10; /* [29..20] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_bt_ctrl; ++ ++/* Define the union u_intf_bt_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_bt_upd; ++ ++/* Define the union u_intf_bt_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_bt_sync_inv; ++ ++/* Define the union u_bt_clip0_l */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int clip_cl0 : 10; /* [9..0] */ ++ unsigned int clip_cl1 : 10; /* [19..10] */ ++ unsigned int clip_cl2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int clip_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_clip0_l; ++ ++/* Define the union u_bt_clip0_h */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int clip_ch0 : 10; /* [9..0] */ ++ unsigned int clip_ch1 : 10; /* [19..10] */ ++ unsigned int clip_ch2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_clip0_h; ++ ++/* Define the union u_bt_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_ctrl; ++ ++/* Define the union u_bt_dither_sed_y0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_y0; ++ ++/* Define the union u_bt_dither_sed_u0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_u0; ++ ++/* Define the union u_bt_dither_sed_v0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_v0; ++ ++/* Define the union u_bt_dither_sed_w0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_w0; ++ ++/* Define the union u_bt_dither_sed_y1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_y1; ++ ++/* Define the union u_bt_dither_sed_u1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_u1; ++ ++/* Define the union u_bt_dither_sed_v1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_v1; ++ ++/* Define the union u_bt_dither_sed_w1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_w1; ++ ++/* Define the union u_bt_dither_sed_y2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_y2; ++ ++/* Define the union u_bt_dither_sed_u2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_u2; ++ ++/* Define the union u_bt_dither_sed_v2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_v2; ++ ++/* Define the union u_bt_dither_sed_w2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_w2; ++ ++/* Define the union u_bt_dither_sed_y3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_y3; ++ ++/* Define the union u_bt_dither_sed_u3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_u3; ++ ++/* Define the union u_bt_dither_sed_v3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_v3; ++ ++/* Define the union u_bt_dither_sed_w3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_sed_w3; ++ ++/* Define the union u_bt_dither_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_bt_dither_thr; ++ ++/* Define the union u_intf_lcd_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 20; /* [19..0] */ ++ unsigned int lcd_format : 4; /* [23..20] */ ++ unsigned int lcd_bit_inv : 1; /* [24] */ ++ unsigned int lcd_comp_order : 1; /* [25] */ ++ unsigned int lcd_serial_perd : 1; /* [26] */ ++ unsigned int reserved_1 : 3; /* [29..27] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_lcd_ctrl; ++ ++/* Define the union u_intf_lcd_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_lcd_upd; ++ ++/* Define the union u_intf_lcd_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_lcd_sync_inv; ++ ++/* Define the union u_lcd_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_ctrl; ++ ++/* Define the union u_lcd_dither_sed_y0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_y0; ++ ++/* Define the union u_lcd_dither_sed_u0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_u0; ++ ++/* Define the union u_lcd_dither_sed_v0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_v0; ++ ++/* Define the union u_lcd_dither_sed_w0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_w0; ++ ++/* Define the union u_lcd_dither_sed_y1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_y1; ++ ++/* Define the union u_lcd_dither_sed_u1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_u1; ++ ++/* Define the union u_lcd_dither_sed_v1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_v1; ++ ++/* Define the union u_lcd_dither_sed_w1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_w1; ++ ++/* Define the union u_lcd_dither_sed_y2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_y2; ++ ++/* Define the union u_lcd_dither_sed_u2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_u2; ++ ++/* Define the union u_lcd_dither_sed_v2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_v2; ++ ++/* Define the union u_lcd_dither_sed_w2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_w2; ++ ++/* Define the union u_lcd_dither_sed_y3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_y3; ++ ++/* Define the union u_lcd_dither_sed_u3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_u3; ++ ++/* Define the union u_lcd_dither_sed_v3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_v3; ++ ++/* Define the union u_lcd_dither_sed_w3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_sed_w3; ++ ++/* Define the union u_lcd_dither_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_lcd_dither_thr; ++ ++/* Define the union u_intf_hdmi1_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int hdmi_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_hdmi1_ctrl; ++ ++/* Define the union u_intf_hdmi1_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_hdmi1_upd; ++ ++/* Define the union u_intf_hdmi1_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_hdmi1_sync_inv; ++ ++/* Define the union u_hdmi1_intf_chksum_high */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int r0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi1_intf_chksum_high; ++ ++/* Define the union u_hdmi1_intf1_chksum_high */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int r1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi1_intf1_chksum_high; ++ ++/* Define the union u_hdmi1_hfir_coef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi1_hfir_coef0; ++ ++/* Define the union u_hdmi1_hfir_coef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi1_hfir_coef1; ++ ++/* Define the union u_hdmi1_hfir_coef2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi1_hfir_coef2; ++ ++/* Define the union u_hdmi1_hfir_coef3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_hdmi1_hfir_coef3; ++ ++/* Define the union u_intf_vga_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 24; /* [23..0] */ ++ unsigned int yc_mode : 1; /* [24] */ ++ unsigned int lcd_parallel_mode : 1; /* [25] */ ++ unsigned int lcd_data_inv : 1; /* [26] */ ++ unsigned int lcd_parallel_order : 1; /* [27] */ ++ unsigned int lcd_serial_perd : 1; /* [28] */ ++ unsigned int lcd_serial_mode : 1; /* [29] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_vga_ctrl; ++ ++/* Define the union u_intf_vga_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_vga_upd; ++ ++/* Define the union u_intf_vga_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_vga_sync_inv; ++ ++/* Define the union u_vga_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_idc; ++ ++/* Define the union u_vga_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_odc; ++ ++/* Define the union u_vga_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_iodc; ++ ++/* Define the union u_vga_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_p0; ++ ++/* Define the union u_vga_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_p1; ++ ++/* Define the union u_vga_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_p2; ++ ++/* Define the union u_vga_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_p3; ++ ++/* Define the union u_vga_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_csc_p4; ++ ++/* Define the union u_vga_hspcfg0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_tmp0 : 8; /* [7..0] */ ++ unsigned int hsp_hf0_tmp1 : 8; /* [15..8] */ ++ unsigned int hsp_hf0_tmp2 : 8; /* [23..16] */ ++ unsigned int hsp_hf0_tmp3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg0; ++ ++/* Define the union u_vga_hspcfg1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_coring : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int hsp_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg1; ++ ++/* Define the union u_vga_hspcfg5 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_gainpos : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int hsp_hf0_gainneg : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg5; ++ ++/* Define the union u_vga_hspcfg6 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_overth : 8; /* [7..0] */ ++ unsigned int hsp_hf0_underth : 8; /* [15..8] */ ++ unsigned int hsp_hf0_mixratio : 8; /* [23..16] */ ++ unsigned int reserved_0 : 4; /* [27..24] */ ++ unsigned int hsp_hf0_winsize : 3; /* [30..28] */ ++ unsigned int hsp_hf0_adpshoot_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg6; ++ ++/* Define the union u_vga_hspcfg7 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_tmp0 : 8; /* [7..0] */ ++ unsigned int hsp_hf1_tmp1 : 8; /* [15..8] */ ++ unsigned int hsp_hf1_tmp2 : 8; /* [23..16] */ ++ unsigned int hsp_hf1_tmp3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg7; ++ ++/* Define the union u_vga_hspcfg8 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_coring : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg8; ++ ++/* Define the union u_vga_hspcfg12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_gainpos : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int hsp_hf1_gainneg : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg12; ++ ++/* Define the union u_vga_hspcfg13 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_overth : 8; /* [7..0] */ ++ unsigned int hsp_hf1_underth : 8; /* [15..8] */ ++ unsigned int hsp_hf1_mixratio : 8; /* [23..16] */ ++ unsigned int reserved_0 : 4; /* [27..24] */ ++ unsigned int hsp_hf1_winsize : 3; /* [30..28] */ ++ unsigned int hsp_hf1_adpshoot_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg13; ++ ++/* Define the union u_vga_hspcfg14 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_cdti_gain : 8; /* [7..0] */ ++ unsigned int hsp_ldti_gain : 8; /* [15..8] */ ++ unsigned int hsp_lti_ratio : 8; /* [23..16] */ ++ unsigned int hsp_hf_shootdiv : 3; /* [26..24] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int hsp_ctih_en : 1; /* [28] */ ++ unsigned int hsp_ltih_en : 1; /* [29] */ ++ unsigned int hsp_h1_en : 1; /* [30] */ ++ unsigned int hsp_h0_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg14; ++ ++/* Define the union u_vga_hspcfg15 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hsp_glb_underth : 9; /* [8..0] */ ++ unsigned int reserved_0 : 1; /* [9] */ ++ unsigned int hsp_glb_overth : 9; /* [18..10] */ ++ unsigned int reserved_1 : 1; /* [19] */ ++ unsigned int hsp_peak_ratio : 8; /* [27..20] */ ++ unsigned int reserved_2 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vga_hspcfg15; ++ ++/* Define the union u_intf_date_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 23; /* [22..0] */ ++ unsigned int uv_mode : 1; /* [23] */ ++ unsigned int yc_mode : 1; /* [24] */ ++ unsigned int lcd_parallel_mode : 1; /* [25] */ ++ unsigned int lcd_data_inv : 1; /* [26] */ ++ unsigned int lcd_parallel_order : 1; /* [27] */ ++ unsigned int lcd_serial_perd : 1; /* [28] */ ++ unsigned int lcd_serial_mode : 1; /* [29] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_date_ctrl; ++ ++/* Define the union u_intf_date_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_date_upd; ++ ++/* Define the union u_intf_date_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf_date_sync_inv; ++ ++/* Define the union u_date_clip0_l */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int clip_cl0 : 10; /* [9..0] */ ++ unsigned int clip_cl1 : 10; /* [19..10] */ ++ unsigned int clip_cl2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int clip_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_clip0_l; ++ ++/* Define the union u_date_clip0_h */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int clip_ch0 : 10; /* [9..0] */ ++ unsigned int clip_ch1 : 10; /* [19..10] */ ++ unsigned int clip_ch2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_clip0_h; ++ ++/* Define the union u_intf0_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_ctrl; ++ ++/* Define the union u_intf0_dither_sed_y0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_y0; ++ ++/* Define the union u_intf0_dither_sed_u0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_u0; ++ ++/* Define the union u_intf0_dither_sed_v0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_v0; ++ ++/* Define the union u_intf0_dither_sed_w0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_w0; ++ ++/* Define the union u_intf0_dither_sed_y1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_y1; ++ ++/* Define the union u_intf0_dither_sed_u1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_u1; ++ ++/* Define the union u_intf0_dither_sed_v1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_v1; ++ ++/* Define the union u_intf0_dither_sed_w1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_w1; ++ ++/* Define the union u_intf0_dither_sed_y2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_y2; ++ ++/* Define the union u_intf0_dither_sed_u2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_u2; ++ ++/* Define the union u_intf0_dither_sed_v2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_v2; ++ ++/* Define the union u_intf0_dither_sed_w2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_w2; ++ ++/* Define the union u_intf0_dither_sed_y3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_y3; ++ ++/* Define the union u_intf0_dither_sed_u3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_u3; ++ ++/* Define the union u_intf0_dither_sed_v3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_v3; ++ ++/* Define the union u_intf0_dither_sed_w3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_sed_w3; ++ ++/* Define the union u_intf0_dither_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf0_dither_thr; ++ ++/* Define the union u_dhd1_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int disp_mode : 3; /* [3..1] */ ++ unsigned int iop : 1; /* [4] */ ++ unsigned int intf_ivs : 1; /* [5] */ ++ unsigned int intf_ihs : 1; /* [6] */ ++ unsigned int intf_idv : 1; /* [7] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int hdmi420c_sel : 1; /* [9] */ ++ unsigned int hdmi420_en : 1; /* [10] */ ++ unsigned int uf_offline_en : 1; /* [11] */ ++ unsigned int reserved_1 : 2; /* [13..12] */ ++ unsigned int hdmi_mode : 1; /* [14] */ ++ unsigned int twochn_debug : 1; /* [15] */ ++ unsigned int twochn_en : 1; /* [16] */ ++ unsigned int reserved_2 : 1; /* [17] */ ++ unsigned int cbar_mode : 1; /* [18] */ ++ unsigned int sin_en : 1; /* [19] */ ++ unsigned int fpga_lmt_width : 7; /* [26..20] */ ++ unsigned int fpga_lmt_en : 1; /* [27] */ ++ unsigned int p2i_en : 1; /* [28] */ ++ unsigned int cbar_sel : 1; /* [29] */ ++ unsigned int cbar_en : 1; /* [30] */ ++ unsigned int intf_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_ctrl; ++ ++/* Define the union u_dhd1_vsync1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vact : 16; /* [15..0] */ ++ unsigned int vbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vsync1; ++ ++/* Define the union u_dhd1_vsync2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vsync2; ++ ++/* Define the union u_dhd1_hsync1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hact : 16; /* [15..0] */ ++ unsigned int hbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_hsync1; ++ ++/* Define the union u_dhd1_hsync2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfb : 16; /* [15..0] */ ++ unsigned int hmid : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_hsync2; ++ ++/* Define the union u_dhd1_vplus1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bvact : 16; /* [15..0] */ ++ unsigned int bvbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vplus1; ++ ++/* Define the union u_dhd1_vplus2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bvfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vplus2; ++ ++/* Define the union u_dhd1_pwr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hpw : 16; /* [15..0] */ ++ unsigned int vpw : 8; /* [23..16] */ ++ unsigned int reserved_0 : 3; /* [26..24] */ ++ unsigned int multichn_en : 2; /* [28..27] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_pwr; ++ ++/* Define the union u_dhd1_vtthd3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vtmgthd3 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd3_mode : 1; /* [15] */ ++ unsigned int vtmgthd4 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd4_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vtthd3; ++ ++/* Define the union u_dhd1_vtthd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vtmgthd1 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd1_mode : 1; /* [15] */ ++ unsigned int vtmgthd2 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd2_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vtthd; ++ ++/* Define the union u_dhd1_parathd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int dfs_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_parathd; ++ ++/* Define the union u_dhd1_precharge_thd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tcon_precharge_thd : 17; /* [16..0] */ ++ unsigned int reserved_0 : 3; /* [19..17] */ ++ unsigned int vsync_te_mode : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_precharge_thd; ++ ++/* Define the union u_dhd1_start_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int start_pos : 8; /* [7..0] */ ++ unsigned int timing_start_pos : 8; /* [15..8] */ ++ unsigned int fi_start_pos : 4; /* [19..16] */ ++ unsigned int req_start_pos : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_start_pos; ++ ++/* Define the union u_dhd1_start_pos1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_start_pos1 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_start_pos1; ++ ++/* Define the union u_dhd1_paraup */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int paraup_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_paraup; ++ ++/* Define the union u_dhd1_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lcd_dv_inv : 1; /* [0] */ ++ unsigned int lcd_hs_inv : 1; /* [1] */ ++ unsigned int lcd_vs_inv : 1; /* [2] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int vga_dv_inv : 1; /* [4] */ ++ unsigned int vga_hs_inv : 1; /* [5] */ ++ unsigned int vga_vs_inv : 1; /* [6] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int hdmi_dv_inv : 1; /* [8] */ ++ unsigned int hdmi_hs_inv : 1; /* [9] */ ++ unsigned int hdmi_vs_inv : 1; /* [10] */ ++ unsigned int hdmi_f_inv : 1; /* [11] */ ++ unsigned int date_dv_inv : 1; /* [12] */ ++ unsigned int date_hs_inv : 1; /* [13] */ ++ unsigned int date_vs_inv : 1; /* [14] */ ++ unsigned int date_f_inv : 1; /* [15] */ ++ unsigned int reserved_2 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_sync_inv; ++ ++/* Define the union u_dhd1_clk_dv_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int intf_clk_mux : 1; /* [0] */ ++ unsigned int intf_dv_mux : 1; /* [1] */ ++ unsigned int no_active_area_pos : 16; /* [17..2] */ ++ unsigned int reserved_0 : 14; /* [31..18] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_clk_dv_ctrl; ++ ++/* Define the union u_dhd1_rgb_fix_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fix_b : 10; /* [9..0] */ ++ unsigned int fix_g : 10; /* [19..10] */ ++ unsigned int fix_r : 10; /* [29..20] */ ++ unsigned int rgb_fix_mux : 1; /* [30] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_rgb_fix_ctrl; ++ ++/* Define the union u_dhd1_lockcfg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int measure_en : 1; /* [0] */ ++ unsigned int lock_cnt_en : 1; /* [1] */ ++ unsigned int vdp_measure_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_lockcfg; ++ ++/* Define the union u_dhd1_intf_chksum_high1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int y0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_intf_chksum_high1; ++ ++/* Define the union u_dhd1_intf_chksum_high2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int y1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_intf_chksum_high2; ++ ++/* Define the union u_dhd1_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vback_blank : 1; /* [0] */ ++ unsigned int vblank : 1; /* [1] */ ++ unsigned int bottom_field : 1; /* [2] */ ++ unsigned int vcnt : 13; /* [15..3] */ ++ unsigned int count_int : 8; /* [23..16] */ ++ unsigned int dhd_even : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_state; ++ ++/* Define the union u_dhd1_uf_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ud_first_cnt : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int start_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_uf_state; ++ ++/* Define the union u_dhd1_vsync_te_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vsync_te_start_sta : 8; /* [7..0] */ ++ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ ++ unsigned int vsync_te_end_sta : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vsync_te_state; ++ ++/* Define the union u_dhd1_vsync_te_state1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vsync_te_vfb : 16; /* [15..0] */ ++ unsigned int vsync_te_width : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd1_vsync_te_state1; ++ ++/* Define the union u_intf1_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_ctrl; ++ ++/* Define the union u_intf1_dither_sed_y0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_y0; ++ ++/* Define the union u_intf1_dither_sed_u0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_u0; ++ ++/* Define the union u_intf1_dither_sed_v0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_v0; ++ ++/* Define the union u_intf1_dither_sed_w0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_w0; ++ ++/* Define the union u_intf1_dither_sed_y1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_y1; ++ ++/* Define the union u_intf1_dither_sed_u1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_u1; ++ ++/* Define the union u_intf1_dither_sed_v1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_v1; ++ ++/* Define the union u_intf1_dither_sed_w1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_w1; ++ ++/* Define the union u_intf1_dither_sed_y2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_y2; ++ ++/* Define the union u_intf1_dither_sed_u2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_u2; ++ ++/* Define the union u_intf1_dither_sed_v2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_v2; ++ ++/* Define the union u_intf1_dither_sed_w2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_w2; ++ ++/* Define the union u_intf1_dither_sed_y3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_y3; ++ ++/* Define the union u_intf1_dither_sed_u3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_u3; ++ ++/* Define the union u_intf1_dither_sed_v3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_v3; ++ ++/* Define the union u_intf1_dither_sed_w3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_sed_w3; ++ ++/* Define the union u_intf1_dither_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf1_dither_thr; ++ ++/* Define the union u_dhd2_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int disp_mode : 3; /* [3..1] */ ++ unsigned int iop : 1; /* [4] */ ++ unsigned int intf_ivs : 1; /* [5] */ ++ unsigned int intf_ihs : 1; /* [6] */ ++ unsigned int intf_idv : 1; /* [7] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int hdmi420c_sel : 1; /* [9] */ ++ unsigned int hdmi420_en : 1; /* [10] */ ++ unsigned int uf_offline_en : 1; /* [11] */ ++ unsigned int reserved_1 : 2; /* [13..12] */ ++ unsigned int hdmi_mode : 1; /* [14] */ ++ unsigned int twochn_debug : 1; /* [15] */ ++ unsigned int twochn_en : 1; /* [16] */ ++ unsigned int reserved_2 : 1; /* [17] */ ++ unsigned int cbar_mode : 1; /* [18] */ ++ unsigned int sin_en : 1; /* [19] */ ++ unsigned int fpga_lmt_width : 7; /* [26..20] */ ++ unsigned int fpga_lmt_en : 1; /* [27] */ ++ unsigned int p2i_en : 1; /* [28] */ ++ unsigned int cbar_sel : 1; /* [29] */ ++ unsigned int cbar_en : 1; /* [30] */ ++ unsigned int intf_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_ctrl; ++ ++/* Define the union u_dhd2_vsync1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vact : 16; /* [15..0] */ ++ unsigned int vbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vsync1; ++ ++/* Define the union u_dhd2_vsync2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vsync2; ++ ++/* Define the union u_dhd2_hsync1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hact : 16; /* [15..0] */ ++ unsigned int hbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_hsync1; ++ ++/* Define the union u_dhd2_hsync2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hfb : 16; /* [15..0] */ ++ unsigned int hmid : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_hsync2; ++ ++/* Define the union u_dhd2_vplus1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bvact : 16; /* [15..0] */ ++ unsigned int bvbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vplus1; ++ ++/* Define the union u_dhd2_vplus2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bvfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vplus2; ++ ++/* Define the union u_dhd2_pwr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int hpw : 16; /* [15..0] */ ++ unsigned int vpw : 8; /* [23..16] */ ++ unsigned int reserved_0 : 3; /* [26..24] */ ++ unsigned int multichn_en : 2; /* [28..27] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_pwr; ++ ++/* Define the union u_dhd2_vtthd3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vtmgthd3 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd3_mode : 1; /* [15] */ ++ unsigned int vtmgthd4 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd4_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vtthd3; ++ ++/* Define the union u_dhd2_vtthd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vtmgthd1 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd1_mode : 1; /* [15] */ ++ unsigned int vtmgthd2 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd2_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vtthd; ++ ++/* Define the union u_dhd2_parathd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int dfs_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_parathd; ++ ++/* Define the union u_dhd2_precharge_thd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tcon_precharge_thd : 17; /* [16..0] */ ++ unsigned int reserved_0 : 3; /* [19..17] */ ++ unsigned int vsync_te_mode : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_precharge_thd; ++ ++/* Define the union u_dhd2_start_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int start_pos : 8; /* [7..0] */ ++ unsigned int timing_start_pos : 8; /* [15..8] */ ++ unsigned int fi_start_pos : 4; /* [19..16] */ ++ unsigned int req_start_pos : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_start_pos; ++ ++/* Define the union u_dhd2_start_pos1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_start_pos1 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_start_pos1; ++ ++/* Define the union u_dhd2_paraup */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int paraup_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_paraup; ++ ++/* Define the union u_dhd2_sync_inv */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lcd_dv_inv : 1; /* [0] */ ++ unsigned int lcd_hs_inv : 1; /* [1] */ ++ unsigned int lcd_vs_inv : 1; /* [2] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int vga_dv_inv : 1; /* [4] */ ++ unsigned int vga_hs_inv : 1; /* [5] */ ++ unsigned int vga_vs_inv : 1; /* [6] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int hdmi_dv_inv : 1; /* [8] */ ++ unsigned int hdmi_hs_inv : 1; /* [9] */ ++ unsigned int hdmi_vs_inv : 1; /* [10] */ ++ unsigned int hdmi_f_inv : 1; /* [11] */ ++ unsigned int date_dv_inv : 1; /* [12] */ ++ unsigned int date_hs_inv : 1; /* [13] */ ++ unsigned int date_vs_inv : 1; /* [14] */ ++ unsigned int date_f_inv : 1; /* [15] */ ++ unsigned int reserved_2 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_sync_inv; ++ ++/* Define the union u_dhd2_clk_dv_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int intf_clk_mux : 1; /* [0] */ ++ unsigned int intf_dv_mux : 1; /* [1] */ ++ unsigned int no_active_area_pos : 16; /* [17..2] */ ++ unsigned int reserved_0 : 14; /* [31..18] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_clk_dv_ctrl; ++ ++/* Define the union u_dhd2_rgb_fix_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fix_b : 10; /* [9..0] */ ++ unsigned int fix_g : 10; /* [19..10] */ ++ unsigned int fix_r : 10; /* [29..20] */ ++ unsigned int rgb_fix_mux : 1; /* [30] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_rgb_fix_ctrl; ++ ++/* Define the union u_dhd2_lockcfg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int measure_en : 1; /* [0] */ ++ unsigned int lock_cnt_en : 1; /* [1] */ ++ unsigned int vdp_measure_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_lockcfg; ++ ++/* Define the union u_dhd2_intf_chksum_high1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int y0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_intf_chksum_high1; ++ ++/* Define the union u_dhd2_intf_chksum_high2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int y1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_intf_chksum_high2; ++ ++/* Define the union u_dhd2_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vback_blank : 1; /* [0] */ ++ unsigned int vblank : 1; /* [1] */ ++ unsigned int bottom_field : 1; /* [2] */ ++ unsigned int vcnt : 13; /* [15..3] */ ++ unsigned int count_int : 8; /* [23..16] */ ++ unsigned int dhd_even : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_state; ++ ++/* Define the union u_dhd2_uf_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ud_first_cnt : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int start_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_uf_state; ++ ++/* Define the union u_dhd2_vsync_te_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vsync_te_start_sta : 8; /* [7..0] */ ++ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ ++ unsigned int vsync_te_end_sta : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vsync_te_state; ++ ++/* Define the union u_dhd2_vsync_te_state1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vsync_te_vfb : 16; /* [15..0] */ ++ unsigned int vsync_te_width : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_dhd2_vsync_te_state1; ++ ++/* Define the union u_intf2_dither_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_ctrl; ++ ++/* Define the union u_intf2_dither_sed_y0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_y0; ++ ++/* Define the union u_intf2_dither_sed_u0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_u0; ++ ++/* Define the union u_intf2_dither_sed_v0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_v0; ++ ++/* Define the union u_intf2_dither_sed_w0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_w0; ++ ++/* Define the union u_intf2_dither_sed_y1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_y1; ++ ++/* Define the union u_intf2_dither_sed_u1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_u1; ++ ++/* Define the union u_intf2_dither_sed_v1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_v1; ++ ++/* Define the union u_intf2_dither_sed_w1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_w1; ++ ++/* Define the union u_intf2_dither_sed_y2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_y2; ++ ++/* Define the union u_intf2_dither_sed_u2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_u2; ++ ++/* Define the union u_intf2_dither_sed_v2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_v2; ++ ++/* Define the union u_intf2_dither_sed_w2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_w2; ++ ++/* Define the union u_intf2_dither_sed_y3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_y3; ++ ++/* Define the union u_intf2_dither_sed_u3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_u3; ++ ++/* Define the union u_intf2_dither_sed_v3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_v3; ++ ++/* Define the union u_intf2_dither_sed_w3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_sed_w3; ++ ++/* Define the union u_intf2_dither_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_intf2_dither_thr; ++ ++/* Define the union u_date_coeff0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt_seq : 1; /* [0] */ ++ unsigned int chgain_en : 1; /* [1] */ ++ unsigned int sylp_en : 1; /* [2] */ ++ unsigned int chlp_en : 1; /* [3] */ ++ unsigned int oversam2_en : 1; /* [4] */ ++ unsigned int lunt_en : 1; /* [5] */ ++ unsigned int oversam_en : 2; /* [7..6] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int luma_dl : 4; /* [12..9] */ ++ unsigned int agc_amp_sel : 1; /* [13] */ ++ unsigned int length_sel : 1; /* [14] */ ++ unsigned int sync_mode_scart : 1; /* [15] */ ++ unsigned int sync_mode_sel : 2; /* [17..16] */ ++ unsigned int style_sel : 4; /* [21..18] */ ++ unsigned int fm_sel : 1; /* [22] */ ++ unsigned int vbi_lpf_en : 1; /* [23] */ ++ unsigned int rgb_en : 1; /* [24] */ ++ unsigned int scanline : 1; /* [25] */ ++ unsigned int pbpr_lpf_en : 1; /* [26] */ ++ unsigned int pal_half_en : 1; /* [27] */ ++ unsigned int reserved_1 : 1; /* [28] */ ++ unsigned int dis_ire : 1; /* [29] */ ++ unsigned int clpf_sel : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff0; ++ ++/* Define the union u_date_coeff1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dac_test : 10; /* [9..0] */ ++ unsigned int date_test_mode : 2; /* [11..10] */ ++ unsigned int date_test_en : 1; /* [12] */ ++ unsigned int amp_outside : 10; /* [22..13] */ ++ unsigned int c_limit_en : 1; /* [23] */ ++ unsigned int cc_seq : 1; /* [24] */ ++ unsigned int cgms_seq : 1; /* [25] */ ++ unsigned int vps_seq : 1; /* [26] */ ++ unsigned int wss_seq : 1; /* [27] */ ++ unsigned int cvbs_limit_en : 1; /* [28] */ ++ unsigned int c_gain : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff1; ++ ++/* Define the union u_date_coeff3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef03 : 26; /* [25..0] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff3; ++ ++/* Define the union u_date_coeff4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef04 : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff4; ++ ++/* Define the union u_date_coeff5 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef05 : 29; /* [28..0] */ ++ unsigned int reserved_0 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff5; ++ ++/* Define the union u_date_coeff6 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int coef06_1 : 23; /* [22..0] */ ++ unsigned int reserved_0 : 8; /* [30..23] */ ++ unsigned int coef06_0 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff6; ++ ++/* Define the union u_date_coeff7 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt07_enf2 : 1; /* [0] */ ++ unsigned int tt08_enf2 : 1; /* [1] */ ++ unsigned int tt09_enf2 : 1; /* [2] */ ++ unsigned int tt10_enf2 : 1; /* [3] */ ++ unsigned int tt11_enf2 : 1; /* [4] */ ++ unsigned int tt12_enf2 : 1; /* [5] */ ++ unsigned int tt13_enf2 : 1; /* [6] */ ++ unsigned int tt14_enf2 : 1; /* [7] */ ++ unsigned int tt15_enf2 : 1; /* [8] */ ++ unsigned int tt16_enf2 : 1; /* [9] */ ++ unsigned int tt17_enf2 : 1; /* [10] */ ++ unsigned int tt18_enf2 : 1; /* [11] */ ++ unsigned int tt19_enf2 : 1; /* [12] */ ++ unsigned int tt20_enf2 : 1; /* [13] */ ++ unsigned int tt21_enf2 : 1; /* [14] */ ++ unsigned int tt22_enf2 : 1; /* [15] */ ++ unsigned int tt07_enf1 : 1; /* [16] */ ++ unsigned int tt08_enf1 : 1; /* [17] */ ++ unsigned int tt09_enf1 : 1; /* [18] */ ++ unsigned int tt10_enf1 : 1; /* [19] */ ++ unsigned int tt11_enf1 : 1; /* [20] */ ++ unsigned int tt12_enf1 : 1; /* [21] */ ++ unsigned int tt13_enf1 : 1; /* [22] */ ++ unsigned int tt14_enf1 : 1; /* [23] */ ++ unsigned int tt15_enf1 : 1; /* [24] */ ++ unsigned int tt16_enf1 : 1; /* [25] */ ++ unsigned int tt17_enf1 : 1; /* [26] */ ++ unsigned int tt18_enf1 : 1; /* [27] */ ++ unsigned int tt19_enf1 : 1; /* [28] */ ++ unsigned int tt20_enf1 : 1; /* [29] */ ++ unsigned int tt21_enf1 : 1; /* [30] */ ++ unsigned int tt22_enf1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff7; ++ ++/* Define the union u_date_coeff10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt_pktoff : 8; /* [7..0] */ ++ unsigned int tt_mode : 2; /* [9..8] */ ++ unsigned int tt_highest : 1; /* [10] */ ++ unsigned int full_page : 1; /* [11] */ ++ unsigned int nabts_100ire : 1; /* [12] */ ++ unsigned int reserved_0 : 18; /* [30..13] */ ++ unsigned int tt_ready : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff10; ++ ++/* Define the union u_date_coeff11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int date_clf2 : 10; /* [9..0] */ ++ unsigned int date_clf1 : 10; /* [19..10] */ ++ unsigned int cc_enf2 : 1; /* [20] */ ++ unsigned int cc_enf1 : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff11; ++ ++/* Define the union u_date_coeff12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cc_f2data : 16; /* [15..0] */ ++ unsigned int cc_f1data : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff12; ++ ++/* Define the union u_date_coeff13 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cg_f1data : 20; /* [19..0] */ ++ unsigned int cg_enf2 : 1; /* [20] */ ++ unsigned int cg_enf1 : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff13; ++ ++/* Define the union u_date_coeff14 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cg_f2data : 20; /* [19..0] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff14; ++ ++/* Define the union u_date_coeff15 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wss_data : 14; /* [13..0] */ ++ unsigned int wss_en : 1; /* [14] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff15; ++ ++/* Define the union u_date_coeff16 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vps_data : 24; /* [23..0] */ ++ unsigned int vps_en : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff16; ++ ++/* Define the union u_date_coeff19 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vps_data : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff19; ++ ++/* Define the union u_date_coeff20 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt05_enf2 : 1; /* [0] */ ++ unsigned int tt06_enf2 : 1; /* [1] */ ++ unsigned int tt06_enf1 : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff20; ++ ++/* Define the union u_date_coeff21 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dac0_in_sel : 3; /* [2..0] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int dac1_in_sel : 3; /* [6..4] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int dac2_in_sel : 3; /* [10..8] */ ++ unsigned int reserved_2 : 1; /* [11] */ ++ unsigned int dac3_in_sel : 3; /* [14..12] */ ++ unsigned int reserved_3 : 1; /* [15] */ ++ unsigned int dac4_in_sel : 3; /* [18..16] */ ++ unsigned int reserved_4 : 1; /* [19] */ ++ unsigned int dac5_in_sel : 3; /* [22..20] */ ++ unsigned int reserved_5 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff21; ++ ++/* Define the union u_date_coeff22 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int video_phase_delta : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff22; ++ ++/* Define the union u_date_coeff23 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dac0_out_dly : 3; /* [2..0] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int dac1_out_dly : 3; /* [6..4] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int dac2_out_dly : 3; /* [10..8] */ ++ unsigned int reserved_2 : 1; /* [11] */ ++ unsigned int dac3_out_dly : 3; /* [14..12] */ ++ unsigned int reserved_3 : 1; /* [15] */ ++ unsigned int dac4_out_dly : 3; /* [18..16] */ ++ unsigned int reserved_4 : 1; /* [19] */ ++ unsigned int dac5_out_dly : 3; /* [22..20] */ ++ unsigned int reserved_5 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff23; ++ ++/* Define the union u_date_coeff25 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_n_coef : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int x_n_1_coef : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff25; ++ ++/* Define the union u_date_coeff26 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int x_n_1_coef : 13; /* [12..0] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff26; ++ ++/* Define the union u_date_coeff27 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int y_n_coef : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int y_n_1_coef : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff27; ++ ++/* Define the union u_date_coeff28 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int pixel_begin1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int pixel_begin2 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff28; ++ ++/* Define the union u_date_coeff29 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int pixel_end : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff29; ++ ++/* Define the union u_date_coeff30 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int g_secam : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff30; ++ ++/* Define the union u_date_isrmask */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt_mask : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_isrmask; ++ ++/* Define the union u_date_isrstate */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt_status : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_isrstate; ++ ++/* Define the union u_date_isr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tt_int : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_isr; ++ ++/* Define the union u_date_coeff37 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fir_y1_coeff0 : 8; /* [7..0] */ ++ unsigned int fir_y1_coeff1 : 8; /* [15..8] */ ++ unsigned int fir_y1_coeff2 : 8; /* [23..16] */ ++ unsigned int fir_y1_coeff3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff37; ++ ++/* Define the union u_date_coeff38 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fir_y2_coeff0 : 16; /* [15..0] */ ++ unsigned int fir_y2_coeff1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff38; ++ ++/* Define the union u_date_coeff39 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fir_y2_coeff2 : 16; /* [15..0] */ ++ unsigned int fir_y2_coeff3 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff39; ++ ++/* Define the union u_date_coeff40 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fir_c1_coeff0 : 8; /* [7..0] */ ++ unsigned int fir_c1_coeff1 : 8; /* [15..8] */ ++ unsigned int fir_c1_coeff2 : 8; /* [23..16] */ ++ unsigned int fir_c1_coeff3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff40; ++ ++/* Define the union u_date_coeff41 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fir_c2_coeff0 : 16; /* [15..0] */ ++ unsigned int fir_c2_coeff1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff41; ++ ++/* Define the union u_date_coeff42 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int fir_c2_coeff2 : 16; /* [15..0] */ ++ unsigned int fir_c2_coeff3 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff42; ++ ++/* Define the union u_date_dacdet1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vdac_det_high : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int det_line : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_dacdet1; ++ ++/* Define the union u_date_dacdet2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int det_pixel_sta : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int det_pixel_wid : 11; /* [26..16] */ ++ unsigned int reserved_1 : 4; /* [30..27] */ ++ unsigned int vdac_det_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_dacdet2; ++ ++/* Define the union u_date_coeff50 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff50; ++ ++/* Define the union u_date_coeff51 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff51; ++ ++/* Define the union u_date_coeff52 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff52; ++ ++/* Define the union u_date_coeff53 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff53; ++ ++/* Define the union u_date_coeff54 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff54; ++ ++/* Define the union u_date_coeff55 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_date_coeff55; ++ ++/* Define the union u_mac_outstanding */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mstr0_routstanding : 4; /* [3..0] */ ++ unsigned int mstr0_woutstanding : 4; /* [7..4] */ ++ unsigned int mstr1_routstanding : 4; /* [11..8] */ ++ unsigned int mstr1_woutstanding : 4; /* [15..12] */ ++ unsigned int mstr2_routstanding : 4; /* [19..16] */ ++ unsigned int mstr2_woutstanding : 4; /* [23..20] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_outstanding; ++ ++/* Define the union u_mac_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int split_mode : 4; /* [3..0] */ ++ unsigned int arb_mode : 4; /* [7..4] */ ++ unsigned int mid_enable : 1; /* [8] */ ++ unsigned int reserved_0 : 3; /* [11..9] */ ++ unsigned int wport_sel : 4; /* [15..12] */ ++ unsigned int reserved_1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_ctrl; ++ ++/* Define the union u_mac_rchn_prio */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_prio : 1; /* [0] */ ++ unsigned int v0l_prio : 1; /* [1] */ ++ unsigned int v0c_prio : 1; /* [2] */ ++ unsigned int v0lh_prio : 1; /* [3] */ ++ unsigned int v0ch_prio : 1; /* [4] */ ++ unsigned int v1l_prio : 1; /* [5] */ ++ unsigned int v1c_prio : 1; /* [6] */ ++ unsigned int v1lh_prio : 1; /* [7] */ ++ unsigned int v1ch_prio : 1; /* [8] */ ++ unsigned int g0ar_prio : 1; /* [9] */ ++ unsigned int g0gb_prio : 1; /* [10] */ ++ unsigned int g1ar_prio : 1; /* [11] */ ++ unsigned int g1gb_prio : 1; /* [12] */ ++ unsigned int v2l_prio : 1; /* [13] */ ++ unsigned int v2c_prio : 1; /* [14] */ ++ unsigned int v2lh_prio : 1; /* [15] */ ++ unsigned int v2ch_prio : 1; /* [16] */ ++ unsigned int g3ar_prio : 1; /* [17] */ ++ unsigned int g3gb_prio : 1; /* [18] */ ++ unsigned int reserved_0 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_rchn_prio; ++ ++/* Define the union u_mac_wchn_prio */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbcl_prio : 1; /* [0] */ ++ unsigned int wbcc_prio : 1; /* [1] */ ++ unsigned int wbclh_prio : 1; /* [2] */ ++ unsigned int wbcch_prio : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_wchn_prio; ++ ++/* Define the union u_mac_rchn_sel0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int para_sel : 2; /* [1..0] */ ++ unsigned int v0l_sel : 2; /* [3..2] */ ++ unsigned int v0c_sel : 2; /* [5..4] */ ++ unsigned int v0lh_sel : 2; /* [7..6] */ ++ unsigned int v0ch_sel : 2; /* [9..8] */ ++ unsigned int v1l_sel : 2; /* [11..10] */ ++ unsigned int v1c_sel : 2; /* [13..12] */ ++ unsigned int v1lh_sel : 2; /* [15..14] */ ++ unsigned int v1ch_sel : 2; /* [17..16] */ ++ unsigned int g0ar_sel : 2; /* [19..18] */ ++ unsigned int g0gb_sel : 2; /* [21..20] */ ++ unsigned int g1ar_sel : 2; /* [23..22] */ ++ unsigned int g1gb_sel : 2; /* [25..24] */ ++ unsigned int v2_sel : 2; /* [27..26] */ ++ unsigned int g3_sel : 2; /* [29..28] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_rchn_sel0; ++ ++/* Define the union u_mac_wchn_sel0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbcl_sel : 2; /* [1..0] */ ++ unsigned int wbcc_sel : 2; /* [3..2] */ ++ unsigned int wbclh_sel : 2; /* [5..4] */ ++ unsigned int wbcch_sel : 2; /* [7..6] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_wchn_sel0; ++ ++/* Define the union u_mac_bus_err_clr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int bus_error_clr : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_bus_err_clr; ++ ++/* Define the union u_mac_bus_err */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mst0_r_error : 1; /* [0] */ ++ unsigned int mst0_w_error : 1; /* [1] */ ++ unsigned int mst1_r_error : 1; /* [2] */ ++ unsigned int mst1_w_error : 1; /* [3] */ ++ unsigned int mst2_r_error : 1; /* [4] */ ++ unsigned int mst2_w_error : 1; /* [5] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_bus_err; ++ ++/* Define the union u_mac_debug_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int axi_det_enable : 1; /* [0] */ ++ unsigned int reserved_0 : 3; /* [3..1] */ ++ unsigned int fifo_det_mode : 4; /* [7..4] */ ++ unsigned int reserved_1 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_debug_ctrl; ++ ++/* Define the union u_mac_debug_clr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int axi_det_clr : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_mac_debug_clr; ++ ++/* Define the union u_vid_read_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int chm_rmode : 3; /* [2..0] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int lm_rmode : 3; /* [6..4] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int chm_draw_mode : 2; /* [9..8] */ ++ unsigned int lm_draw_mode : 2; /* [11..10] */ ++ unsigned int flip_en : 1; /* [12] */ ++ unsigned int chm_copy_en : 1; /* [13] */ ++ unsigned int reserved_2 : 2; /* [15..14] */ ++ unsigned int mute_en : 1; /* [16] */ ++ unsigned int mute_req_en : 1; /* [17] */ ++ unsigned int vicap_mute_en : 1; /* [18] */ ++ unsigned int mrg_enable : 1; /* [19] */ ++ unsigned int mrg_mute_mode : 1; /* [20] */ ++ unsigned int fdr_ck_gt_en : 1; /* [21] */ ++ unsigned int reserved_3 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_read_ctrl; ++ ++/* Define the union u_vid_mac_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_ctrl : 2; /* [1..0] */ ++ unsigned int req_len : 2; /* [3..2] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int ofl_master : 1; /* [8] */ ++ unsigned int reserved_1 : 22; /* [30..9] */ ++ unsigned int pre_rd_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_mac_ctrl; ++ ++/* Define the union u_vid_out_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int draw_pixel_mode : 3; /* [2..0] */ ++ unsigned int draw_pixel_en : 1; /* [3] */ ++ unsigned int uv_order_en : 1; /* [4] */ ++ unsigned int single_port_mode : 1; /* [5] */ ++ unsigned int testpattern_en : 1; /* [6] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_out_ctrl; ++ ++/* Define the union u_vid_mute_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_mute_alpha; ++ ++/* Define the union u_vid_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_mute_bk; ++ ++/* Define the union u_vid_src_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int data_type : 3; /* [2..0] */ ++ unsigned int data_fmt : 2; /* [4..3] */ ++ unsigned int reserved_0 : 3; /* [7..5] */ ++ unsigned int data_width : 2; /* [9..8] */ ++ unsigned int reserved_1 : 2; /* [11..10] */ ++ unsigned int field_type : 1; /* [12] */ ++ unsigned int reserved_2 : 3; /* [15..13] */ ++ unsigned int disp_mode : 4; /* [19..16] */ ++ unsigned int dcmp_en : 2; /* [21..20] */ ++ unsigned int reserved_3 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_src_info; ++ ++/* Define the union u_vid_src_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int src_w : 16; /* [15..0] */ ++ unsigned int src_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_src_reso; ++ ++/* Define the union u_vid_src_crop */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int src_crop_x : 16; /* [15..0] */ ++ unsigned int src_crop_y : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_src_crop; ++ ++/* Define the union u_vid_in_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ireso_w : 16; /* [15..0] */ ++ unsigned int ireso_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_in_reso; ++ ++/* Define the union u_vid_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lm_stride : 16; /* [15..0] */ ++ unsigned int chm_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_stride; ++ ++/* Define the union u_vid_2bit_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lm_tile_stride : 16; /* [15..0] */ ++ unsigned int chm_tile_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_2bit_stride; ++ ++/* Define the union u_vid_head_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lm_head_stride : 16; /* [15..0] */ ++ unsigned int chm_head_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_head_stride; ++ ++/* Define the union u_vid_smmu_bypass */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lm_bypass_2d : 1; /* [0] */ ++ unsigned int chm_bypass_2d : 1; /* [1] */ ++ unsigned int lm_bypass_3d : 1; /* [2] */ ++ unsigned int chm_bypass_3d : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_smmu_bypass; ++ ++/* Define the union u_vid_testpat_cfg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tp_speed : 10; /* [9..0] */ ++ unsigned int reserved_0 : 2; /* [11..10] */ ++ unsigned int tp_line_w : 1; /* [12] */ ++ unsigned int tp_color_mode : 1; /* [13] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int tp_mode : 2; /* [17..16] */ ++ unsigned int reserved_2 : 14; /* [31..18] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_testpat_cfg; ++ ++/* Define the union u_vid_testpat_seed */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tp_seed : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_testpat_seed; ++ ++/* Define the union u_vid_dcmp_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int c_is_lossless : 1; /* [0] */ ++ unsigned int l_is_lossless : 1; /* [1] */ ++ unsigned int c_cmp_mode : 1; /* [2] */ ++ unsigned int l_cmp_mode : 1; /* [3] */ ++ unsigned int c_cmp_rate : 2; /* [5..4] */ ++ unsigned int l_cmp_rate : 2; /* [7..6] */ ++ unsigned int mem_mode : 1; /* [8] */ ++ unsigned int reserved_0 : 23; /* [31..9] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vid_dcmp_ctrl; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_glb_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int is_lossless : 1; /* [1] */ ++ unsigned int cmp_mode : 1; /* [2] */ ++ unsigned int max_mb_qp_y : 3; /* [5..3] */ ++ unsigned int reserved_0 : 10; /* [15..6] */ ++ unsigned int max_mb_qp_c : 3; /* [18..16] */ ++ unsigned int seg_en : 1; /* [19] */ ++ unsigned int bit_depth : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_glb_info; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_frame_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_height : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_width : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_frame_size; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_error_sta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dcmp_error : 1; /* [0] */ ++ unsigned int forgive : 1; /* [1] */ ++ unsigned int consume : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_error_sta; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_glb_info_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int is_lossless : 1; /* [1] */ ++ unsigned int cmp_mode : 1; /* [2] */ ++ unsigned int max_mb_qp_y : 3; /* [5..3] */ ++ unsigned int reserved_0 : 10; /* [15..6] */ ++ unsigned int max_mb_qp_c : 3; /* [18..16] */ ++ unsigned int seg_en : 1; /* [19] */ ++ unsigned int bit_depth : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_glb_info_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_frame_size_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_height : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_width : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_frame_size_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_dcmp_error_sta_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dcmp_error : 1; /* [0] */ ++ unsigned int forgive : 1; /* [1] */ ++ unsigned int consume : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_dcmp_error_sta_c; ++ ++/* Define the union u_gfx_read_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int read_mode : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int draw_mode : 2; /* [5..4] */ ++ unsigned int reserved_1 : 2; /* [7..6] */ ++ unsigned int flip_en : 1; /* [8] */ ++ unsigned int reserved_2 : 1; /* [9] */ ++ unsigned int mute_en : 1; /* [10] */ ++ unsigned int mute_req_en : 1; /* [11] */ ++ unsigned int fdr_ck_gt_en : 1; /* [12] */ ++ unsigned int reserved_3 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_read_ctrl; ++ ++/* Define the union u_gfx_mac_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_ctrl : 2; /* [1..0] */ ++ unsigned int req_len : 2; /* [3..2] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int ofl_master : 1; /* [8] */ ++ unsigned int dcmp_thd_close : 1; /* [9] */ ++ unsigned int dcmp_mute_ctrl : 1; /* [10] */ ++ unsigned int reserved_1 : 13; /* [23..11] */ ++ unsigned int req_ld_mode : 2; /* [25..24] */ ++ unsigned int reserved_2 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_mac_ctrl; ++ ++/* Define the union u_gfx_out_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int palpha_range : 1; /* [0] */ ++ unsigned int palpha_en : 1; /* [1] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int key_mode : 1; /* [4] */ ++ unsigned int enable : 1; /* [5] */ ++ unsigned int reserved_1 : 2; /* [7..6] */ ++ unsigned int bitext : 2; /* [9..8] */ ++ unsigned int premulti_en : 1; /* [10] */ ++ unsigned int testpattern_en : 1; /* [11] */ ++ unsigned int reserved_2 : 20; /* [31..12] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_out_ctrl; ++ ++/* Define the union u_gfx_mute_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_mute_alpha; ++ ++/* Define the union u_gfx_mute_bk */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_mute_bk; ++ ++/* Define the union u_gfx_smmu_bypass */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smmu_bypass_2d : 1; /* [0] */ ++ unsigned int smmu_bypass_3d : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_smmu_bypass; ++ ++/* Define the union u_gfx_1555_alpha */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int alpha_0 : 8; /* [7..0] */ ++ unsigned int alpha_1 : 8; /* [15..8] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_1555_alpha; ++ ++/* Define the union u_gfx_src_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ifmt : 8; /* [7..0] */ ++ unsigned int reserved_0 : 8; /* [15..8] */ ++ unsigned int disp_mode : 4; /* [19..16] */ ++ unsigned int dcmp_en : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_src_info; ++ ++/* Define the union u_gfx_src_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int src_w : 16; /* [15..0] */ ++ unsigned int src_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_src_reso; ++ ++/* Define the union u_gfx_src_crop */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int src_crop_x : 16; /* [15..0] */ ++ unsigned int src_crop_y : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_src_crop; ++ ++/* Define the union u_gfx_ireso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ireso_w : 16; /* [15..0] */ ++ unsigned int ireso_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ireso; ++ ++/* Define the union u_gfx_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int surface_stride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_stride; ++ ++/* Define the union u_gfx_ckey_max */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int key_b_max : 8; /* [7..0] */ ++ unsigned int key_g_max : 8; /* [15..8] */ ++ unsigned int key_r_max : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ckey_max; ++ ++/* Define the union u_gfx_ckey_min */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int key_b_min : 8; /* [7..0] */ ++ unsigned int key_g_min : 8; /* [15..8] */ ++ unsigned int key_r_min : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ckey_min; ++ ++/* Define the union u_gfx_ckey_mask */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int key_b_msk : 8; /* [7..0] */ ++ unsigned int key_g_msk : 8; /* [15..8] */ ++ unsigned int key_r_msk : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ckey_mask; ++ ++/* Define the union u_gfx_testpat_cfg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tp_speed : 10; /* [9..0] */ ++ unsigned int reserved_0 : 2; /* [11..10] */ ++ unsigned int tp_line_w : 1; /* [12] */ ++ unsigned int tp_color_mode : 1; /* [13] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int tp_mode : 2; /* [17..16] */ ++ unsigned int reserved_2 : 14; /* [31..18] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_testpat_cfg; ++ ++/* Define the union u_gfx_testpat_seed */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int tp_seed : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_testpat_seed; ++ ++/* Define the union u_gfx_ld_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hw_mute_clr : 1; /* [1] */ ++ unsigned int ld_mute_en : 1; /* [2] */ ++ unsigned int ld_err_mute_en : 1; /* [3] */ ++ unsigned int reserved_1 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ld_ctrl; ++ ++/* Define the union u_gfx_ld_smute_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved : 31; /* [30..0] */ ++ unsigned int sw_mute_clr : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ld_smute_ctrl; ++ ++/* Define the union u_gfx_ld_err_sta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ld_err_clr : 1; /* [0] */ ++ unsigned int reserved : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_ld_err_sta; ++ ++ ++ ++ ++/* define the union reg_vdp_v3r2_line_osd_dcmp_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int conv_en : 1; /* [2] */ ++ unsigned int is_lossless : 1; /* [3] */ ++ unsigned int osd_mode : 2; /* [5..4] */ ++ unsigned int max_mb_qp : 3; /* [8..6] */ ++ unsigned int excess_err_mask : 1; /* [9] */ ++ unsigned int rw_reg_add : 6; /* [15..10] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_line_osd_dcmp_glb_info; ++ ++/* define the union reg_vdp_v3r2_line_osd_dcmp_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_height : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_line_osd_dcmp_frame_size; ++ ++/* define the union reg_vdp_v3r2_line_osd_dcmp_error_sta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dcmp_error : 1; /* [0] */ ++ unsigned int o_pix_forgive : 1; /* [1] */ ++ unsigned int o_pix_consume : 1; /* [2] */ ++ unsigned int o_mb_qp_error : 1; /* [3] */ ++ unsigned int o_dcmp_excess_err : 1; /* [4] */ ++ unsigned int o_dcmp_err_add : 5; /* [9..5] */ ++ unsigned int o_dcmp_debug : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_line_osd_dcmp_error_sta; ++ ++ ++/* Define the union u_wbc_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 4; /* [3..0] */ ++ unsigned int data_width : 1; /* [4] */ ++ unsigned int reserved_1 : 3; /* [7..5] */ ++ unsigned int uv_order : 1; /* [8] */ ++ unsigned int flip_en : 1; /* [9] */ ++ unsigned int align_mode : 1; /* [10] */ ++ unsigned int reserved_2 : 3; /* [13..11] */ ++ unsigned int cap_ck_gt_en : 1; /* [14] */ ++ unsigned int reserved_3 : 14; /* [28..15] */ ++ unsigned int wbc_cmp_en : 1; /* [29] */ ++ unsigned int reserved_4 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_ctrl; ++ ++/* Define the union u_wbc_mac_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 2; /* [11..10] */ ++ unsigned int wbc_len : 2; /* [13..12] */ ++ unsigned int reserved_1 : 18; /* [31..14] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_mac_ctrl; ++ ++/* Define the union u_wbc_smmu_bypass */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int l_bypass : 1; /* [0] */ ++ unsigned int c_bypass : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_smmu_bypass; ++ ++/* Define the union u_wbc_lowdlyctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wb_per_line_num : 12; /* [11..0] */ ++ unsigned int partfns_line_num : 12; /* [23..12] */ ++ unsigned int reserved_0 : 6; /* [29..24] */ ++ unsigned int lowdly_test : 1; /* [30] */ ++ unsigned int lowdly_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_lowdlyctrl; ++ ++/* Define the union u_wbc_lowdlysta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int part_finish : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_lowdlysta; ++ ++/* Define the union u_wbc_ystride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_ystride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_ystride; ++ ++/* Define the union u_wbc_cstride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_cstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cstride; ++ ++/* Define the union u_wbc_ynstride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_ynstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_ynstride; ++ ++/* Define the union u_wbc_cnstride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_cnstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cnstride; ++ ++/* Define the union u_wbc_sta */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_l_busy : 1; /* [0] */ ++ unsigned int wbc_c_busy : 1; /* [1] */ ++ unsigned int wbc_lh_busy : 1; /* [2] */ ++ unsigned int wbc_ch_busy : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_sta; ++ ++/* Define the union u_wbc_line_num */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int wbc_l_linenum : 16; /* [15..0] */ ++ unsigned int wbc_c_linenum : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_line_num; ++ ++/* Define the union u_wbc_cap_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cap_width : 16; /* [15..0] */ ++ unsigned int cap_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cap_reso; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_glb_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int is_lossless : 1; /* [2] */ ++ unsigned int chroma_en : 1; /* [3] */ ++ unsigned int esl_qp : 3; /* [6..4] */ ++ unsigned int bit_depth : 1; /* [7] */ ++ unsigned int mirror_en : 1; /* [8] */ ++ unsigned int seg_en : 1; /* [9] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_glb_info; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_frame_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_width : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_height : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_frame_size; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int big_grad_thr : 8; /* [7..0] */ ++ unsigned int diff_thr : 8; /* [15..8] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg0; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg1; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int buffer_init_bits : 16; /* [15..0] */ ++ unsigned int buffer_size : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg12; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg13 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int budget_mb_bits : 10; /* [9..0] */ ++ unsigned int budget_mb_bits_last : 10; /* [19..10] */ ++ unsigned int min_mb_bits : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg13; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg16 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smooth_status_thr : 4; /* [3..0] */ ++ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ ++ unsigned int max_mb_qp : 3; /* [14..12] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg16; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_glb_st */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_left_bits_buffer : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_glb_st; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_glb_info_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int is_lossless : 1; /* [2] */ ++ unsigned int chroma_en : 1; /* [3] */ ++ unsigned int esl_qp : 3; /* [6..4] */ ++ unsigned int bit_depth : 1; /* [7] */ ++ unsigned int mirror_en : 1; /* [8] */ ++ unsigned int seg_en : 1; /* [9] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_glb_info_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_frame_size_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_width : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_height : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_frame_size_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg0_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int big_grad_thr : 8; /* [7..0] */ ++ unsigned int diff_thr : 8; /* [15..8] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg0_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg1_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg1_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg12_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int buffer_init_bits : 16; /* [15..0] */ ++ unsigned int buffer_size : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg12_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg13_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int budget_mb_bits : 10; /* [9..0] */ ++ unsigned int budget_mb_bits_last : 10; /* [19..10] */ ++ unsigned int min_mb_bits : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg13_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg16_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smooth_status_thr : 4; /* [3..0] */ ++ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ ++ unsigned int max_mb_qp : 3; /* [14..12] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_rc_cfg16_c; ++ ++/* Define the union u_vdp_v3r2_lineseg_cmp_glb_st_c */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_left_bits_buffer : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_vdp_v3r2_lineseg_cmp_glb_st_c; ++ ++/* Define the union u_wbc_cmp_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 17; /* [26..10] */ ++ unsigned int mem_mode : 1; /* [27] */ ++ unsigned int data_width : 1; /* [28] */ ++ unsigned int reserved_1 : 1; /* [29] */ ++ unsigned int l_cmp_en : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_ctrl; ++ ++/* Define the union u_wbc_cmp_upd */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_upd; ++ ++/* Define the union u_wbc_cmp_height */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int c_max_height : 13; /* [12..0] */ ++ unsigned int l_max_height : 13; /* [25..13] */ ++ unsigned int addr_mode : 1; /* [26] */ ++ unsigned int fsize_mode : 1; /* [27] */ ++ unsigned int rgb_cmp_mode : 2; /* [29..28] */ ++ unsigned int pause_mode : 1; /* [30] */ ++ unsigned int buffer_mode : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_height; ++ ++/* Define the union u_wbc_cmp_oreso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_cmp_oreso; ++ ++/* Define the union u_wbc_od_state */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int addr_err : 1; /* [0] */ ++ unsigned int he_addr_err0 : 1; /* [1] */ ++ unsigned int he_addr_err1 : 1; /* [2] */ ++ unsigned int he_addr_err2 : 1; /* [3] */ ++ unsigned int w_addr_err : 1; /* [4] */ ++ unsigned int he_fsize_err0 : 1; /* [5] */ ++ unsigned int he_fsize_err1 : 1; /* [6] */ ++ unsigned int he_fsize_err2 : 1; /* [7] */ ++ unsigned int w_fsize_err : 1; /* [8] */ ++ unsigned int he_fsize_war0 : 1; /* [9] */ ++ unsigned int he_fsize_war1 : 1; /* [10] */ ++ unsigned int he_fsize_war2 : 1; /* [11] */ ++ unsigned int w_fsize_war : 1; /* [12] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_wbc_od_state; ++ ++/* Define the union u_od_pic_osd_glb_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int is_lossless : 1; /* [0] */ ++ unsigned int is_lossless_a : 1; /* [1] */ ++ unsigned int cmp_mode : 1; /* [2] */ ++ unsigned int source_mode : 3; /* [5..3] */ ++ unsigned int part_cmp_en : 1; /* [6] */ ++ unsigned int top_pred_en : 1; /* [7] */ ++ unsigned int graphic_en : 1; /* [8] */ ++ unsigned int reserved_0 : 23; /* [31..9] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_glb_info; ++ ++/* Define the union u_od_pic_osd_frame_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_width : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int frame_height : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_frame_size; ++ ++/* Define the union u_od_pic_osd_rc_cfg0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mb_bits : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int min_mb_bits : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg0; ++ ++/* Define the union u_od_pic_osd_rc_cfg1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_qp : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int sad_bits_gain : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int rc_smth_ngain : 3; /* [18..16] */ ++ unsigned int reserved_2 : 5; /* [23..19] */ ++ unsigned int max_trow_bits : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg1; ++ ++/* Define the union u_od_pic_osd_rc_cfg2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_sad_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int min_sad_thr : 7; /* [22..16] */ ++ unsigned int reserved_1 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg2; ++ ++/* Define the union u_od_pic_osd_rc_cfg3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smth_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int still_thr : 7; /* [14..8] */ ++ unsigned int reserved_1 : 1; /* [15] */ ++ unsigned int big_grad_thr : 10; /* [25..16] */ ++ unsigned int reserved_2 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg3; ++ ++/* Define the union u_od_pic_osd_rc_cfg4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int smth_pix_num_thr : 6; /* [5..0] */ ++ unsigned int reserved_0 : 2; /* [7..6] */ ++ unsigned int still_pix_num_thr : 6; /* [13..8] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_2 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg4; ++ ++/* Define the union u_od_pic_osd_rc_cfg5 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int noise_sad : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int pix_diff_thr : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg5; ++ ++/* Define the union u_od_pic_osd_rc_cfg6 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg6; ++ ++/* Define the union u_od_pic_osd_rc_cfg7 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg7; ++ ++/* Define the union u_od_pic_osd_rc_cfg8 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int est_err_gain : 5; /* [4..0] */ ++ unsigned int reserved_0 : 11; /* [15..5] */ ++ unsigned int max_est_err_level : 9; /* [24..16] */ ++ unsigned int reserved_1 : 7; /* [31..25] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg8; ++ ++/* Define the union u_od_pic_osd_rc_cfg9 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 16; /* [15..0] */ ++ unsigned int vbv_buf_loss1_thr : 7; /* [22..16] */ ++ unsigned int reserved_1 : 1; /* [23] */ ++ unsigned int vbv_buf_loss2_thr : 7; /* [30..24] */ ++ unsigned int reserved_2 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg9; ++ ++/* Define the union u_od_pic_osd_rc_cfg10 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int qp_thr0 : 3; /* [2..0] */ ++ unsigned int reserved_0 : 5; /* [7..3] */ ++ unsigned int qp_thr1 : 3; /* [10..8] */ ++ unsigned int reserved_1 : 5; /* [15..11] */ ++ unsigned int qp_thr2 : 3; /* [18..16] */ ++ unsigned int reserved_2 : 13; /* [31..19] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg10; ++ ++/* Define the union u_od_pic_osd_rc_cfg11 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int grph_bias_bit_thr0 : 8; /* [7..0] */ ++ unsigned int grph_bias_bit_thr1 : 8; /* [15..8] */ ++ unsigned int grph_ideal_bit_thr : 10; /* [25..16] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg11; ++ ++/* Define the union u_od_pic_osd_rc_cfg12 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int force_rc_en : 1; /* [0] */ ++ unsigned int reserved_0 : 7; /* [7..1] */ ++ unsigned int forcerc_bits_diff_thr : 8; /* [15..8] */ ++ unsigned int reserved_1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg12; ++ ++/* Define the union u_od_pic_osd_rc_cfg13 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int maxdiff_ctrl_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg13; ++ ++/* Define the union u_od_pic_osd_rc_cfg14 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mb_bits_cap : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int init_buf_bits_cap : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg14; ++ ++/* Define the union u_od_pic_osd_rc_cfg15 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int lfw_mb_len : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int cmplx_sad_thr : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int err_thr0 : 4; /* [19..16] */ ++ unsigned int reserved_2 : 4; /* [23..20] */ ++ unsigned int err_thr1 : 4; /* [27..24] */ ++ unsigned int reserved_3 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg15; ++ ++/* Define the union u_od_pic_osd_rc_cfg16 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int sim_num_thr : 3; /* [2..0] */ ++ unsigned int reserved_0 : 5; /* [7..3] */ ++ unsigned int sum_y_err_thr : 7; /* [14..8] */ ++ unsigned int reserved_1 : 1; /* [15] */ ++ unsigned int sum_c_err_thr : 7; /* [22..16] */ ++ unsigned int reserved_2 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg16; ++ ++/* Define the union u_od_pic_osd_rc_cfg17 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cpmlx_sad_thr_y : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int smpl_sad_thr_c : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int smpl_sumsad_thr_y : 8; /* [23..16] */ ++ unsigned int smpl_sumsad_thr_c : 8; /* [31..24] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg17; ++ ++/* Define the union u_od_pic_osd_rc_cfg18 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int future_sad_y_thr0 : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int future_sad_c_thr0 : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int future_sad_y_thr1 : 4; /* [19..16] */ ++ unsigned int reserved_2 : 4; /* [23..20] */ ++ unsigned int future_sad_c_thr1 : 4; /* [27..24] */ ++ unsigned int reserved_3 : 4; /* [31..28] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg18; ++ ++/* Define the union u_od_pic_osd_rc_cfg19 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cmplx_sumsad_thr_y : 8; /* [7..0] */ ++ unsigned int cmplx_sumsad_thr_c : 8; /* [15..8] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_rc_cfg19; ++ ++/* Define the union u_od_pic_osd_stat_thr */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_gap_bw_row_len_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_stat_thr; ++ ++/* Define the union u_od_pic_osd_pcmp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int pcmp_start_hpos : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int pcmp_end_hpos : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_pcmp; ++ ++/* Define the union u_od_pic_osd_bs_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_size_reg : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_bs_size; ++ ++/* Define the union u_od_pic_osd_worst_row */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_frm_row_len : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_worst_row; ++ ++/* Define the union u_od_pic_osd_best_row */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int min_frm_row_len : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_best_row; ++ ++/* Define the union u_od_pic_osd_stat_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int max_gap_bw_row_len_cnt : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_od_pic_osd_stat_info; ++ ++/* Define the union u_v0_mrg_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ ++ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ ++ unsigned int reserved_0 : 12; /* [19..8] */ ++ unsigned int mrg_edge_en : 1; /* [20] */ ++ unsigned int reserved_1 : 4; /* [24..21] */ ++ unsigned int mrg_edge_typ : 1; /* [25] */ ++ unsigned int reserved_2 : 2; /* [27..26] */ ++ unsigned int mrg_crop_en : 1; /* [28] */ ++ unsigned int mrg_dcmp_en : 1; /* [29] */ ++ unsigned int mrg_mute_en : 1; /* [30] */ ++ unsigned int mrg_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_ctrl; ++ ++/* Define the union u_v0_mrg_disp_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_xpos : 16; /* [15..0] */ ++ unsigned int mrg_ypos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_disp_pos; ++ ++/* Define the union u_v0_mrg_disp_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_width : 16; /* [15..0] */ ++ unsigned int mrg_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_disp_reso; ++ ++/* Define the union u_v0_mrg_src_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_src_width : 16; /* [15..0] */ ++ unsigned int mrg_src_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_src_reso; ++ ++/* Define the union u_v0_mrg_src_offset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_src_hoffset : 16; /* [15..0] */ ++ unsigned int mrg_src_voffset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_src_offset; ++ ++/* Define the union u_v0_mrg_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_c_stride : 16; /* [15..0] */ ++ unsigned int mrg_y_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_stride; ++ ++/* Define the union u_v0_mrg_hstride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_ch_stride : 16; /* [15..0] */ ++ unsigned int mrg_yh_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_hstride; ++ ++/* Define the union u_v0_mrg_read_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rd_region : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_read_ctrl; ++ ++/* Define the union u_v0_mrg_read_en */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_mrg_read_en; ++ ++/* Define the union u_v1_mrg_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ ++ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ ++ unsigned int reserved_0 : 12; /* [19..8] */ ++ unsigned int mrg_edge_en : 1; /* [20] */ ++ unsigned int reserved_1 : 4; /* [24..21] */ ++ unsigned int mrg_edge_typ : 1; /* [25] */ ++ unsigned int reserved_2 : 2; /* [27..26] */ ++ unsigned int mrg_crop_en : 1; /* [28] */ ++ unsigned int mrg_dcmp_en : 1; /* [29] */ ++ unsigned int mrg_mute_en : 1; /* [30] */ ++ unsigned int mrg_en : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_ctrl; ++ ++/* Define the union u_v1_mrg_disp_pos */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_xpos : 16; /* [15..0] */ ++ unsigned int mrg_ypos : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_disp_pos; ++ ++/* Define the union u_v1_mrg_disp_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_width : 16; /* [15..0] */ ++ unsigned int mrg_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_disp_reso; ++ ++/* Define the union u_v1_mrg_src_reso */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_src_width : 16; /* [15..0] */ ++ unsigned int mrg_src_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_src_reso; ++ ++/* Define the union u_v1_mrg_src_offset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_src_hoffset : 16; /* [15..0] */ ++ unsigned int mrg_src_voffset : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_src_offset; ++ ++/* Define the union u_v1_mrg_stride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_c_stride : 16; /* [15..0] */ ++ unsigned int mrg_y_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_stride; ++ ++/* Define the union u_v1_mrg_hstride */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int mrg_ch_stride : 16; /* [15..0] */ ++ unsigned int mrg_yh_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_hstride; ++ ++/* Define the union u_v1_mrg_read_ctrl */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rd_region : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_read_ctrl; ++ ++/* Define the union u_v1_mrg_read_en */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_mrg_read_en; ++ ++/* define the union reg_osb_ctrl1_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mode_0 : 2; /* [1..0] */ ++ unsigned int thick_w_0 : 6; /* [7..2] */ ++ unsigned int arm_w_0 : 8; /* [15..8] */ ++ unsigned int edge_v_0 : 4; /* [19..16] */ ++ unsigned int edge_reg_0 : 4; /* [23..20] */ ++ unsigned int edge_y_0 : 4; /* [27..24] */ ++ unsigned int edge_alpha_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_osb_ctrl1_box_0; ++ ++/* define the union reg_osb_ctrl2_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int hend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_osb_ctrl2_box_0; ++ ++/* define the union reg_osb_ctrl3_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int vend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} u_osb_ctrl3_box_0; ++ ++/* Define the union u_v1_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_idc; ++ ++/* Define the union u_v1_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_odc; ++ ++/* Define the union u_v1_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_iodc; ++ ++/* Define the union u_v1_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_p0; ++ ++/* Define the union u_v1_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_p1; ++ ++/* Define the union u_v1_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_p2; ++ ++/* Define the union u_v1_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_p3; ++ ++/* Define the union u_v1_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc_p4; ++ ++/* Define the union u_v1_csc1_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_idc; ++ ++/* Define the union u_v1_csc1_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_odc; ++ ++/* Define the union u_v1_csc1_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_iodc; ++ ++/* Define the union u_v1_csc1_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_p0; ++ ++/* Define the union u_v1_csc1_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_p1; ++ ++/* Define the union u_v1_csc1_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_p2; ++ ++/* Define the union u_v1_csc1_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_p3; ++ ++/* Define the union u_v1_csc1_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v1_csc1_p4; ++ ++/* Define the union u_v2_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_idc; ++ ++/* Define the union u_v2_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_odc; ++ ++/* Define the union u_v2_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_iodc; ++ ++/* Define the union u_v2_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_p0; ++ ++/* Define the union u_v2_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_p1; ++ ++/* Define the union u_v2_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_p2; ++ ++/* Define the union u_v2_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_p3; ++ ++/* Define the union u_v2_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc_p4; ++ ++/* Define the union u_v2_csc1_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_idc; ++ ++/* Define the union u_v2_csc1_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_odc; ++ ++/* Define the union u_v2_csc1_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_iodc; ++ ++/* Define the union u_v2_csc1_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_p0; ++ ++/* Define the union u_v2_csc1_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_p1; ++ ++/* Define the union u_v2_csc1_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_p2; ++ ++/* Define the union u_v2_csc1_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_p3; ++ ++/* Define the union u_v2_csc1_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v2_csc1_p4; ++ ++/* Define the union u_g1_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_idc; ++ ++/* Define the union u_g1_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_odc; ++ ++/* Define the union u_g1_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_iodc; ++ ++/* Define the union u_g1_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_p0; ++ ++/* Define the union u_g1_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_p1; ++ ++/* Define the union u_g1_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_p2; ++ ++/* Define the union u_g1_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_p3; ++ ++/* Define the union u_g1_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc_p4; ++ ++/* Define the union u_g1_csc1_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_idc; ++ ++/* Define the union u_g1_csc1_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_odc; ++ ++/* Define the union u_g1_csc1_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_iodc; ++ ++/* Define the union u_g1_csc1_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_p0; ++ ++/* Define the union u_g1_csc1_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_p1; ++ ++/* Define the union u_g1_csc1_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_p2; ++ ++/* Define the union u_g1_csc1_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_p3; ++ ++/* Define the union u_g1_csc1_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g1_csc1_p4; ++ ++/* Define the union u_g3_csc_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_idc; ++ ++/* Define the union u_g3_csc_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_odc; ++ ++/* Define the union u_g3_csc_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_iodc; ++ ++/* Define the union u_g3_csc_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_p0; ++ ++/* Define the union u_g3_csc_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_p1; ++ ++/* Define the union u_g3_csc_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_p2; ++ ++/* Define the union u_g3_csc_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_p3; ++ ++/* Define the union u_g3_csc_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc_p4; ++ ++/* Define the union u_g3_csc1_idc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_idc; ++ ++/* Define the union u_g3_csc1_odc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_odc; ++ ++/* Define the union u_g3_csc1_iodc */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_iodc; ++ ++/* Define the union u_g3_csc1_p0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_p0; ++ ++/* Define the union u_g3_csc1_p1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_p1; ++ ++/* Define the union u_g3_csc1_p2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_p2; ++ ++/* Define the union u_g3_csc1_p3 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_p3; ++ ++/* Define the union u_g3_csc1_p4 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_g3_csc1_p4; ++ ++/* Define the union u_v0_cvfir_vinfo */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_vinfo; ++ ++/* Define the union u_v0_cvfir_vsp */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_vsp; ++ ++/* Define the union u_v0_cvfir_voffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_voffset; ++ ++/* Define the union u_v0_cvfir_vboffset */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_vboffset; ++ ++/* Define the union u_v0_cvfir_vcoef0 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_vcoef0; ++ ++/* Define the union u_v0_cvfir_vcoef1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_vcoef1; ++ ++/* Define the union u_v0_cvfir_vcoef2 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_v0_cvfir_vcoef2; ++ ++/* Define the union u_gfx_osd_glb_info */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int dcmp_en : 1; /* [0] */ ++ unsigned int is_lossless : 1; /* [1] */ ++ unsigned int is_lossless_a : 1; /* [2] */ ++ unsigned int cmp_mode : 1; /* [3] */ ++ unsigned int source_mode : 3; /* [6..4] */ ++ unsigned int tpred_en : 1; /* [7] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_osd_glb_info; ++ ++/* Define the union u_gfx_osd_frame_size */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int frame_width : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int frame_height : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_osd_frame_size; ++ ++/* Define the union u_gfx_osd_dbg_reg */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 30; /* [29..0] */ ++ unsigned int dcmp_err0 : 1; /* [30] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_osd_dbg_reg; ++ ++/* Define the union u_gfx_osd_dbg_reg1 */ ++typedef union { ++ /* Define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 30; /* [29..0] */ ++ unsigned int dcmp_err1 : 1; /* [30] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* Define an unsigned member */ ++ unsigned int u32; ++} u_gfx_osd_dbg_reg1; ++ ++/* Define the global struct */ ++typedef struct { ++ volatile u_voctrl voctrl; /* 0x0 */ ++ volatile u_vointsta vointsta; /* 0x4 */ ++ volatile u_vomskintsta vomskintsta; /* 0x8 */ ++ volatile u_vointmsk vointmsk; /* 0xc */ ++ volatile u_vodebug vodebug; /* 0x10 */ ++ volatile u_vointsta1 vointsta1; /* 0x14 */ ++ volatile u_vomskintsta1 vomskintsta1; /* 0x18 */ ++ volatile u_vointmsk1 vointmsk1; /* 0x1c */ ++ volatile unsigned int vdpversion1; /* 0x20 */ ++ volatile unsigned int vdpversion2; /* 0x24 */ ++ volatile u_volowpower_ctrl volowpower_ctrl; /* 0x28 */ ++ volatile u_voufsta voufsta; /* 0x2c */ ++ volatile u_voufclr voufclr; /* 0x30 */ ++ volatile u_vointproc_tim vointproc_tim; /* 0x34 */ ++ volatile unsigned int vofpgatest; /* 0x38 */ ++ volatile unsigned int reserved_0[3]; /* 0x3c~0x44 */ ++ volatile u_volowpower_ctrl1 volowpower_ctrl1; /* 0x48 */ ++ volatile u_vofpgadef vofpgadef; /* 0x4c */ ++ volatile u_volowpower_ctrl2 volowpower_ctrl2; /* 0x50 */ ++ volatile u_volowpower_ctrl3 volowpower_ctrl3; /* 0x54 */ ++ volatile unsigned int reserved_1[43]; /* 43:0x58~0x100 */ ++ volatile u_vomux_dac vomux_dac; /* 0x104 */ ++ volatile u_vomux_testsync vomux_testsync; /* 0x108 */ ++ volatile u_vomux_testdata vomux_testdata; /* 0x10c */ ++ volatile unsigned int reserved_2[4]; /* 4:0x110~0x11c */ ++ volatile u_vo_dac_ctrl vo_dac_ctrl; /* 0x120 */ ++ volatile u_vo_dac_otp vo_dac_otp; /* 0x124 */ ++ volatile unsigned int reserved_3[2]; /* 2:0x128~0x12c */ ++ volatile u_vo_dac0_ctrl vo_dac0_ctrl; /* 0x130 */ ++ volatile u_vo_dac1_ctrl vo_dac1_ctrl; /* 0x134 */ ++ volatile u_vo_dac2_ctrl vo_dac2_ctrl; /* 0x138 */ ++ volatile u_vo_dac3_ctrl vo_dac3_ctrl; /* 0x13c */ ++ volatile u_vo_dac_stat0 vo_dac_stat0; /* 0x140 */ ++ volatile unsigned int reserved_4[111]; /* 111:0x144~0x2fc */ ++ volatile u_cbm_bkg1 cbm_bkg1; /* 0x300 */ ++ volatile unsigned int reserved_5; /* 0x304 */ ++ volatile u_cbm_mix1 cbm_mix1; /* 0x308 */ ++ volatile unsigned int reserved_6[14]; /* 14:0x30c~0x340 */ ++ volatile u_wbc_bmp_thd wbc_bmp_thd; /* 0x344 */ ++ volatile unsigned int reserved_7[2]; /* 2:0x348~0x34c */ ++ volatile unsigned int cbm1_lay0_debug; /* 0x350 */ ++ volatile unsigned int cbm1_lay1_debug; /* 0x354 */ ++ volatile unsigned int cbm1_lay2_debug; /* 0x358 */ ++ volatile unsigned int cbm1_lay3_debug; /* 0x35c */ ++ volatile unsigned int cbm1_lay4_debug; /* 0x360 */ ++ volatile unsigned int cbm1_lay0_last_debug; /* 0x364 */ ++ volatile unsigned int cbm1_lay1_last_debug; /* 0x368 */ ++ volatile unsigned int cbm1_lay2_last_debug; /* 0x36c */ ++ volatile unsigned int cbm1_lay3_last_debug; /* 0x370 */ ++ volatile unsigned int cbm1_lay4_last_debug; /* 0x374 */ ++ volatile unsigned int reserved_8[2]; /* 2:0x378~0x37c */ ++ volatile u_cbm_bkg2 cbm_bkg2; /* 0x380 */ ++ volatile unsigned int reserved_9; /* 0x384 */ ++ volatile u_cbm_mix2 cbm_mix2; /* 0x388 */ ++ volatile unsigned int reserved_10[14]; /* 14:0x38c~0x3c0 */ ++ volatile u_hc_bmp_thd hc_bmp_thd; /* 0x3c4 */ ++ volatile unsigned int reserved_11[2]; /* 2:0x3c8~0x3cc */ ++ volatile unsigned int cbm2_lay0_debug; /* 0x3d0 */ ++ volatile unsigned int cbm2_lay1_debug; /* 0x3d4 */ ++ volatile unsigned int cbm2_lay2_debug; /* 0x3d8 */ ++ volatile unsigned int cbm2_lay3_debug; /* 0x3dc */ ++ volatile unsigned int cbm2_lay4_debug; /* 0x3e0 */ ++ volatile unsigned int cbm2_lay0_last_debug; /* 0x3e4 */ ++ volatile unsigned int cbm2_lay1_last_debug; /* 0x3e8 */ ++ volatile unsigned int cbm2_lay2_last_debug; /* 0x3ec */ ++ volatile unsigned int cbm2_lay3_last_debug; /* 0x3f0 */ ++ volatile unsigned int cbm2_lay4_last_debug; /* 0x3f4 */ ++ volatile unsigned int reserved_12[2]; /* 2:0x3f8~0x3fc */ ++ volatile u_cbm_bkg3 cbm_bkg3; /* 0x400 */ ++ volatile unsigned int reserved_13; /* 0x404 */ ++ volatile u_cbm_mix3 cbm_mix3; /* 0x408 */ ++ volatile unsigned int reserved_14[17]; /* 17:0x40c~0x44c */ ++ volatile unsigned int cbm3_lay0_debug; /* 0x450 */ ++ volatile unsigned int cbm3_lay1_debug; /* 0x454 */ ++ volatile unsigned int cbm3_lay2_debug; /* 0x458 */ ++ volatile unsigned int cbm3_lay3_debug; /* 0x45c */ ++ volatile unsigned int cbm3_lay4_debug; /* 0x460 */ ++ volatile unsigned int cbm3_lay0_last_debug; /* 0x464 */ ++ volatile unsigned int cbm3_lay1_last_debug; /* 0x468 */ ++ volatile unsigned int cbm3_lay2_last_debug; /* 0x46c */ ++ volatile unsigned int cbm3_lay3_last_debug; /* 0x470 */ ++ volatile unsigned int cbm3_lay4_last_debug; /* 0x474 */ ++ volatile unsigned int reserved_15[98]; /* 98:0x478~0x5fc */ ++ volatile u_mixv0_bkg mixv0_bkg; /* 0x600 */ ++ volatile unsigned int reserved_16; /* 0x604 */ ++ volatile u_mixv0_mix mixv0_mix; /* 0x608 */ ++ volatile unsigned int reserved_17[189]; /* 189:0x60c~0x8fc */ ++ volatile u_mixg0_bkg mixg0_bkg; /* 0x900 */ ++ volatile u_mixg0_bkalpha mixg0_bkalpha; /* 0x904 */ ++ volatile u_mixg0_mix mixg0_mix; /* 0x908 */ ++ volatile unsigned int reserved_18[189]; /* 189:0x90c~0xbfc */ ++ volatile u_link_ctrl link_ctrl; /* 0xc00 */ ++ volatile unsigned int reserved_19[63]; /* 63:0xc04~0xcfc */ ++ volatile u_vpss_ctrl vpss_ctrl; /* 0xd00 */ ++ volatile u_vpss_miscellaneous vpss_miscellaneous; /* 0xd04 */ ++ volatile u_vpss_ftconfig vpss_ftconfig; /* 0xd08 */ ++ volatile unsigned int reserved_20[5]; /* 5:0xd0c~0xd1c */ ++ volatile unsigned int vpss_version; /* 0xd20 */ ++ volatile unsigned int vpss_debug0; /* 0xd24 */ ++ volatile unsigned int vpss_debug1; /* 0xd28 */ ++ volatile unsigned int vpss_debug2; /* 0xd2c */ ++ volatile unsigned int vpss_debug3; /* 0xd30 */ ++ volatile unsigned int vpss_debug4; /* 0xd34 */ ++ volatile unsigned int vpss_debug5; /* 0xd38 */ ++ volatile unsigned int vpss_debug6; /* 0xd3c */ ++ volatile unsigned int reserved_21[48]; /* 48:0xd40~0xdfc */ ++ volatile unsigned int para_haddr_vhd_chn00; /* 0xe00 */ ++ volatile unsigned int para_addr_vhd_chn00; /* 0xe04 */ ++ volatile unsigned int para_haddr_vhd_chn01; /* 0xe08 */ ++ volatile unsigned int para_addr_vhd_chn01; /* 0xe0c */ ++ volatile unsigned int para_haddr_vhd_chn02; /* 0xe10 */ ++ volatile unsigned int para_addr_vhd_chn02; /* 0xe14 */ ++ volatile unsigned int para_haddr_vhd_chn03; /* 0xe18 */ ++ volatile unsigned int para_addr_vhd_chn03; /* 0xe1c */ ++ volatile unsigned int para_haddr_vhd_chn04; /* 0xe20 */ ++ volatile unsigned int para_addr_vhd_chn04; /* 0xe24 */ ++ volatile unsigned int para_haddr_vhd_chn05; /* 0xe28 */ ++ volatile unsigned int para_addr_vhd_chn05; /* 0xe2c */ ++ volatile unsigned int para_haddr_vhd_chn06; /* 0xe30 */ ++ volatile unsigned int para_addr_vhd_chn06; /* 0xe34 */ ++ volatile unsigned int para_haddr_vhd_chn07; /* 0xe38 */ ++ volatile unsigned int para_addr_vhd_chn07; /* 0xe3c */ ++ volatile unsigned int para_haddr_vhd_chn08; /* 0xe40 */ ++ volatile unsigned int para_addr_vhd_chn08; /* 0xe44 */ ++ volatile unsigned int para_haddr_vhd_chn09; /* 0xe48 */ ++ volatile unsigned int para_addr_vhd_chn09; /* 0xe4c */ ++ volatile unsigned int para_haddr_vhd_chn10; /* 0xe50 */ ++ volatile unsigned int para_addr_vhd_chn10; /* 0xe54 */ ++ volatile unsigned int para_haddr_vhd_chn11; /* 0xe58 */ ++ volatile unsigned int para_addr_vhd_chn11; /* 0xe5c */ ++ volatile unsigned int para_haddr_vhd_chn12; /* 0xe60 */ ++ volatile unsigned int para_addr_vhd_chn12; /* 0xe64 */ ++ volatile unsigned int para_haddr_vhd_chn13; /* 0xe68 */ ++ volatile unsigned int para_addr_vhd_chn13; /* 0xe6c */ ++ volatile unsigned int para_haddr_vhd_chn14; /* 0xe70 */ ++ volatile unsigned int para_addr_vhd_chn14; /* 0xe74 */ ++ volatile unsigned int para_haddr_vhd_chn15; /* 0xe78 */ ++ volatile unsigned int para_addr_vhd_chn15; /* 0xe7c */ ++ volatile unsigned int para_haddr_vhd_chn16; /* 0xe80 */ ++ volatile unsigned int para_addr_vhd_chn16; /* 0xe84 */ ++ volatile unsigned int para_haddr_vhd_chn17; /* 0xe88 */ ++ volatile unsigned int para_addr_vhd_chn17; /* 0xe8c */ ++ volatile unsigned int para_haddr_vhd_chn18; /* 0xe90 */ ++ volatile unsigned int para_addr_vhd_chn18; /* 0xe94 */ ++ volatile unsigned int para_haddr_vhd_chn19; /* 0xe98 */ ++ volatile unsigned int para_addr_vhd_chn19; /* 0xe9c */ ++ volatile unsigned int para_haddr_vhd_chn20; /* 0xea0 */ ++ volatile unsigned int para_addr_vhd_chn20; /* 0xea4 */ ++ volatile unsigned int para_haddr_vhd_chn21; /* 0xea8 */ ++ volatile unsigned int para_addr_vhd_chn21; /* 0xeac */ ++ volatile unsigned int para_haddr_vhd_chn22; /* 0xeb0 */ ++ volatile unsigned int para_addr_vhd_chn22; /* 0xeb4 */ ++ volatile unsigned int para_haddr_vhd_chn23; /* 0xeb8 */ ++ volatile unsigned int para_addr_vhd_chn23; /* 0xebc */ ++ volatile unsigned int para_haddr_vhd_chn24; /* 0xec0 */ ++ volatile unsigned int para_addr_vhd_chn24; /* 0xec4 */ ++ volatile unsigned int para_haddr_vhd_chn25; /* 0xec8 */ ++ volatile unsigned int para_addr_vhd_chn25; /* 0xecc */ ++ volatile unsigned int para_haddr_vhd_chn26; /* 0xed0 */ ++ volatile unsigned int para_addr_vhd_chn26; /* 0xed4 */ ++ volatile unsigned int para_haddr_vhd_chn27; /* 0xed8 */ ++ volatile unsigned int para_addr_vhd_chn27; /* 0xedc */ ++ volatile unsigned int para_haddr_vhd_chn28; /* 0xee0 */ ++ volatile unsigned int para_addr_vhd_chn28; /* 0xee4 */ ++ volatile unsigned int para_haddr_vhd_chn29; /* 0xee8 */ ++ volatile unsigned int para_addr_vhd_chn29; /* 0xeec */ ++ volatile unsigned int para_haddr_vhd_chn30; /* 0xef0 */ ++ volatile unsigned int para_addr_vhd_chn30; /* 0xef4 */ ++ volatile unsigned int para_haddr_vhd_chn31; /* 0xef8 */ ++ volatile unsigned int para_addr_vhd_chn31; /* 0xefc */ ++ volatile u_para_up_vhd para_up_vhd; /* 0xf00 */ ++ volatile unsigned int para_haddr_vsd_chn00; /* 0xf04 */ ++ volatile unsigned int para_addr_vsd_chn00; /* 0xf08 */ ++ volatile unsigned int para_haddr_vsd_chn01; /* 0xf0c */ ++ volatile unsigned int para_addr_vsd_chn01; /* 0xf10 */ ++ volatile unsigned int para_haddr_vsd_chn02; /* 0xf14 */ ++ volatile unsigned int para_addr_vsd_chn02; /* 0xf18 */ ++ volatile unsigned int para_haddr_vsd_chn03; /* 0xf1c */ ++ volatile unsigned int para_addr_vsd_chn03; /* 0xf20 */ ++ volatile unsigned int para_haddr_vsd_chn04; /* 0xf24 */ ++ volatile unsigned int para_addr_vsd_chn04; /* 0xf28 */ ++ volatile unsigned int para_haddr_vsd_chn05; /* 0xf2c */ ++ volatile unsigned int para_addr_vsd_chn05; /* 0xf30 */ ++ volatile unsigned int para_haddr_vsd_chn06; /* 0xf34 */ ++ volatile unsigned int para_addr_vsd_chn06; /* 0xf38 */ ++ volatile unsigned int para_haddr_vsd_chn07; /* 0xf3c */ ++ volatile unsigned int para_addr_vsd_chn07; /* 0xf40 */ ++ volatile u_para_up_vsd para_up_vsd; /* 0xf44 */ ++ volatile u_para_conflict_clr para_conflict_clr; /* 0xf48 */ ++ volatile u_para_conflict_sta para_conflict_sta; /* 0xf4c */ ++ volatile unsigned int reserved_22[44]; /* 44:0xf50~0xffc */ ++ volatile u_v0_ctrl v0_ctrl; /* 0x1000 */ ++ volatile u_v0_upd v0_upd; /* 0x1004 */ ++ volatile u_v0_0reso_read v0_0reso_read; /* 0x1008 */ ++ volatile unsigned int reserved_23; /* 0x100c */ ++ volatile u_v0_ireso v0_ireso; /* 0x1010 */ ++ volatile unsigned int reserved_24[27]; /* 27:0x1014~0x107c */ ++ volatile u_v0_dfpos v0_dfpos; /* 0x1080 */ ++ volatile u_v0_dlpos v0_dlpos; /* 0x1084 */ ++ volatile u_v0_vfpos v0_vfpos; /* 0x1088 */ ++ volatile u_v0_vlpos v0_vlpos; /* 0x108c */ ++ volatile u_v0_bk v0_bk; /* 0x1090 */ ++ volatile u_v0_alpha v0_alpha; /* 0x1094 */ ++ volatile u_v0_mute_bk v0_mute_bk; /* 0x1098 */ ++ volatile unsigned int reserved_25; /* 0x109c */ ++ volatile u_v0_rimwidth v0_rimwidth; /* 0x10a0 */ ++ volatile u_v0_rimcol0 v0_rimcol0; /* 0x10a4 */ ++ volatile u_v0_rimcol1 v0_rimcol1; /* 0x10a8 */ ++ volatile unsigned int reserved_26[85]; /* 85:0x10ac~0x11fc */ ++ volatile u_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; /* 0x1200 */ ++ volatile u_v0_ot_pp_csc_coef00 v0_ot_pp_csc_coef00; /* 0x1204 */ ++ volatile u_v0_ot_pp_csc_coef01 v0_ot_pp_csc_coef01; /* 0x1208 */ ++ volatile u_v0_ot_pp_csc_coef02 v0_ot_pp_csc_coef02; /* 0x120c */ ++ volatile u_v0_ot_pp_csc_coef10 v0_ot_pp_csc_coef10; /* 0x1210 */ ++ volatile u_v0_ot_pp_csc_coef11 v0_ot_pp_csc_coef11; /* 0x1214 */ ++ volatile u_v0_ot_pp_csc_coef12 v0_ot_pp_csc_coef12; /* 0x1218 */ ++ volatile u_v0_ot_pp_csc_coef20 v0_ot_pp_csc_coef20; /* 0x121c */ ++ volatile u_v0_ot_pp_csc_coef21 v0_ot_pp_csc_coef21; /* 0x1220 */ ++ volatile u_v0_ot_pp_csc_coef22 v0_ot_pp_csc_coef22; /* 0x1224 */ ++ volatile u_v0_ot_pp_csc_scale v0_ot_pp_csc_scale; /* 0x1228 */ ++ volatile u_v0_ot_pp_csc_idc0 v0_ot_pp_csc_idc0; /* 0x122c */ ++ volatile u_v0_ot_pp_csc_idc1 v0_ot_pp_csc_idc1; /* 0x1230 */ ++ volatile u_v0_ot_pp_csc_idc2 v0_ot_pp_csc_idc2; /* 0x1234 */ ++ volatile u_v0_ot_pp_csc_odc0 v0_ot_pp_csc_odc0; /* 0x1238 */ ++ volatile u_v0_ot_pp_csc_odc1 v0_ot_pp_csc_odc1; /* 0x123c */ ++ volatile u_v0_ot_pp_csc_odc2 v0_ot_pp_csc_odc2; /* 0x1240 */ ++ volatile u_v0_ot_pp_csc_min_y v0_ot_pp_csc_min_y; /* 0x1244 */ ++ volatile u_v0_ot_pp_csc_min_c v0_ot_pp_csc_min_c; /* 0x1248 */ ++ volatile u_v0_ot_pp_csc_max_y v0_ot_pp_csc_max_y; /* 0x124c */ ++ volatile u_v0_ot_pp_csc_max_c v0_ot_pp_csc_max_c; /* 0x1250 */ ++ volatile u_v0_ot_pp_csc2_coef00 v0_ot_pp_csc2_coef00; /* 0x1254 */ ++ volatile u_v0_ot_pp_csc2_coef01 v0_ot_pp_csc2_coef01; /* 0x1258 */ ++ volatile u_v0_ot_pp_csc2_coef02 v0_ot_pp_csc2_coef02; /* 0x125c */ ++ volatile u_v0_ot_pp_csc2_coef10 v0_ot_pp_csc2_coef10; /* 0x1260 */ ++ volatile u_v0_ot_pp_csc2_coef11 v0_ot_pp_csc2_coef11; /* 0x1264 */ ++ volatile u_v0_ot_pp_csc2_coef12 v0_ot_pp_csc2_coef12; /* 0x1268 */ ++ volatile u_v0_ot_pp_csc2_coef20 v0_ot_pp_csc2_coef20; /* 0x126c */ ++ volatile u_v0_ot_pp_csc2_coef21 v0_ot_pp_csc2_coef21; /* 0x1270 */ ++ volatile u_v0_ot_pp_csc2_coef22 v0_ot_pp_csc2_coef22; /* 0x1274 */ ++ volatile u_v0_ot_pp_csc2_scale v0_ot_pp_csc2_scale; /* 0x1278 */ ++ volatile u_v0_ot_pp_csc2_idc0 v0_ot_pp_csc2_idc0; /* 0x127c */ ++ volatile u_v0_ot_pp_csc2_idc1 v0_ot_pp_csc2_idc1; /* 0x1280 */ ++ volatile u_v0_ot_pp_csc2_idc2 v0_ot_pp_csc2_idc2; /* 0x1284 */ ++ volatile u_v0_ot_pp_csc2_odc0 v0_ot_pp_csc2_odc0; /* 0x1288 */ ++ volatile u_v0_ot_pp_csc2_odc1 v0_ot_pp_csc2_odc1; /* 0x128c */ ++ volatile u_v0_ot_pp_csc2_odc2 v0_ot_pp_csc2_odc2; /* 0x1290 */ ++ volatile u_v0_ot_pp_csc2_min_y v0_ot_pp_csc2_min_y; /* 0x1294 */ ++ volatile u_v0_ot_pp_csc2_min_c v0_ot_pp_csc2_min_c; /* 0x1298 */ ++ volatile u_v0_ot_pp_csc2_max_y v0_ot_pp_csc2_max_y; /* 0x129c */ ++ volatile u_v0_ot_pp_csc2_max_c v0_ot_pp_csc2_max_c; /* 0x12a0 */ ++ volatile unsigned int reserved_27[19]; /* 19:0x12a4~0x12ec */ ++ volatile u_v0_ot_pp_csc_ink_ctrl v0_ot_pp_csc_ink_ctrl; /* 0x12f0 */ ++ volatile u_v0_ot_pp_csc_ink_pos v0_ot_pp_csc_ink_pos; /* 0x12f4 */ ++ volatile unsigned int v0_ot_pp_csc_ink_data; /* 0x12f8 */ ++ volatile unsigned int v0_ot_pp_csc_ink_data2; /* 0x12fc */ ++ volatile u_v0_zme_hinfo v0_zme_hinfo; /* 0x1300 */ ++ volatile u_v0_zme_hsp v0_zme_hsp; /* 0x1304 */ ++ volatile u_v0_zme_hloffset v0_zme_hloffset; /* 0x1308 */ ++ volatile u_v0_zme_hcoffset v0_zme_hcoffset; /* 0x130c */ ++ volatile u_v0_zme_hzone0delta v0_zme_hzone0delta; /* 0x1310 */ ++ volatile u_v0_zme_hzone2delta v0_zme_hzone2delta; /* 0x1314 */ ++ volatile u_v0_zme_hzoneend v0_zme_hzoneend; /* 0x1318 */ ++ volatile u_v0_zme_hl_shootctrl v0_zme_hl_shootctrl; /* 0x131c */ ++ volatile u_v0_zme_hc_shootctrl v0_zme_hc_shootctrl; /* 0x1320 */ ++ volatile u_v0_zme_hcoef_ren v0_zme_hcoef_ren; /* 0x1324 */ ++ volatile u_v0_zme_hcoef_rdata v0_zme_hcoef_rdata; /* 0x1328 */ ++ volatile unsigned int reserved_28[53]; /* 53:0x132c~0x13fc */ ++ volatile u_v0_zme_vinfo v0_zme_vinfo; /* 0x1400 */ ++ volatile u_v0_zme_vsp v0_zme_vsp; /* 0x1404 */ ++ volatile u_v0_zme_voffset v0_zme_voffset; /* 0x1408 */ ++ volatile u_v0_zme_vboffset v0_zme_vboffset; /* 0x140c */ ++ volatile unsigned int reserved_29[3]; /* 3:0x1410~0x1418 */ ++ volatile u_v0_zme_vl_shootctrl v0_zme_vl_shootctrl; /* 0x141c */ ++ volatile u_v0_zme_vc_shootctrl v0_zme_vc_shootctrl; /* 0x1420 */ ++ volatile u_v0_zme_vcoef_ren v0_zme_vcoef_ren; /* 0x1424 */ ++ volatile u_v0_zme_vcoef_rdata v0_zme_vcoef_rdata; /* 0x1428 */ ++ volatile unsigned int reserved_30[53]; /* 53:0x142c~0x14fc */ ++ volatile u_v0_hfir_ctrl v0_hfir_ctrl; /* 0x1500 */ ++ volatile u_v0_hfircoef01 v0_hfircoef01; /* 0x1504 */ ++ volatile u_v0_hfircoef23 v0_hfircoef23; /* 0x1508 */ ++ volatile u_v0_hfircoef45 v0_hfircoef45; /* 0x150c */ ++ volatile u_v0_hfircoef67 v0_hfircoef67; /* 0x1510 */ ++ volatile unsigned int reserved_31[699]; /* 699:0x1514~0x1ffc */ ++ volatile u_v1_ctrl v1_ctrl; /* 0x2000 */ ++ volatile u_v1_upd v1_upd; /* 0x2004 */ ++ volatile u_v1_0reso_read v1_0reso_read; /* 0x2008 */ ++ volatile unsigned int reserved_32; /* 0x200c */ ++ volatile u_v1_ireso v1_ireso; /* 0x2010 */ ++ volatile unsigned int reserved_33[27]; /* 27:0x2014~0x207c */ ++ volatile u_v1_dfpos v1_dfpos; /* 0x2080 */ ++ volatile u_v1_dlpos v1_dlpos; /* 0x2084 */ ++ volatile u_v1_vfpos v1_vfpos; /* 0x2088 */ ++ volatile u_v1_vlpos v1_vlpos; /* 0x208c */ ++ volatile u_v1_bk v1_bk; /* 0x2090 */ ++ volatile u_v1_alpha v1_alpha; /* 0x2094 */ ++ volatile u_v1_mute_bk v1_mute_bk; /* 0x2098 */ ++ volatile unsigned int reserved_34; /* 0x209c */ ++ volatile u_v1_rimwidth v1_rimwidth; /* 0x20a0 */ ++ volatile u_v1_rimcol0 v1_rimcol0; /* 0x20a4 */ ++ volatile u_v1_rimcol1 v1_rimcol1; /* 0x20a8 */ ++ volatile unsigned int reserved_35[85]; /* 85:0x20ac~0x21fc */ ++ volatile u_v1_ot_pp_csc_ctrl v1_ot_pp_csc_ctrl; /* 0x2200 */ ++ volatile u_v1_ot_pp_csc_coef00 v1_ot_pp_csc_coef00; /* 0x2204 */ ++ volatile u_v1_ot_pp_csc_coef01 v1_ot_pp_csc_coef01; /* 0x2208 */ ++ volatile u_v1_ot_pp_csc_coef02 v1_ot_pp_csc_coef02; /* 0x220c */ ++ volatile u_v1_ot_pp_csc_coef10 v1_ot_pp_csc_coef10; /* 0x2210 */ ++ volatile u_v1_ot_pp_csc_coef11 v1_ot_pp_csc_coef11; /* 0x2214 */ ++ volatile u_v1_ot_pp_csc_coef12 v1_ot_pp_csc_coef12; /* 0x2218 */ ++ volatile u_v1_ot_pp_csc_coef20 v1_ot_pp_csc_coef20; /* 0x221c */ ++ volatile u_v1_ot_pp_csc_coef21 v1_ot_pp_csc_coef21; /* 0x2220 */ ++ volatile u_v1_ot_pp_csc_coef22 v1_ot_pp_csc_coef22; /* 0x2224 */ ++ volatile u_v1_ot_pp_csc_scale v1_ot_pp_csc_scale; /* 0x2228 */ ++ volatile u_v1_ot_pp_csc_idc0 v1_ot_pp_csc_idc0; /* 0x222c */ ++ volatile u_v1_ot_pp_csc_idc1 v1_ot_pp_csc_idc1; /* 0x2230 */ ++ volatile u_v1_ot_pp_csc_idc2 v1_ot_pp_csc_idc2; /* 0x2234 */ ++ volatile u_v1_ot_pp_csc_odc0 v1_ot_pp_csc_odc0; /* 0x2238 */ ++ volatile u_v1_ot_pp_csc_odc1 v1_ot_pp_csc_odc1; /* 0x223c */ ++ volatile u_v1_ot_pp_csc_odc2 v1_ot_pp_csc_odc2; /* 0x2240 */ ++ volatile u_v1_ot_pp_csc_min_y v1_ot_pp_csc_min_y; /* 0x2244 */ ++ volatile u_v1_ot_pp_csc_min_c v1_ot_pp_csc_min_c; /* 0x2248 */ ++ volatile u_v1_ot_pp_csc_max_y v1_ot_pp_csc_max_y; /* 0x224c */ ++ volatile u_v1_ot_pp_csc_max_c v1_ot_pp_csc_max_c; /* 0x2250 */ ++ volatile u_v1_ot_pp_csc2_coef00 v1_ot_pp_csc2_coef00; /* 0x2254 */ ++ volatile u_v1_ot_pp_csc2_coef01 v1_ot_pp_csc2_coef01; /* 0x2258 */ ++ volatile u_v1_ot_pp_csc2_coef02 v1_ot_pp_csc2_coef02; /* 0x225c */ ++ volatile u_v1_ot_pp_csc2_coef10 v1_ot_pp_csc2_coef10; /* 0x2260 */ ++ volatile u_v1_ot_pp_csc2_coef11 v1_ot_pp_csc2_coef11; /* 0x2264 */ ++ volatile u_v1_ot_pp_csc2_coef12 v1_ot_pp_csc2_coef12; /* 0x2268 */ ++ volatile u_v1_ot_pp_csc2_coef20 v1_ot_pp_csc2_coef20; /* 0x226c */ ++ volatile u_v1_ot_pp_csc2_coef21 v1_ot_pp_csc2_coef21; /* 0x2270 */ ++ volatile u_v1_ot_pp_csc2_coef22 v1_ot_pp_csc2_coef22; /* 0x2274 */ ++ volatile u_v1_ot_pp_csc2_scale v1_ot_pp_csc2_scale; /* 0x2278 */ ++ volatile u_v1_ot_pp_csc2_idc0 v1_ot_pp_csc2_idc0; /* 0x227c */ ++ volatile u_v1_ot_pp_csc2_idc1 v1_ot_pp_csc2_idc1; /* 0x2280 */ ++ volatile u_v1_ot_pp_csc2_idc2 v1_ot_pp_csc2_idc2; /* 0x2284 */ ++ volatile u_v1_ot_pp_csc2_odc0 v1_ot_pp_csc2_odc0; /* 0x2288 */ ++ volatile u_v1_ot_pp_csc2_odc1 v1_ot_pp_csc2_odc1; /* 0x228c */ ++ volatile u_v1_ot_pp_csc2_odc2 v1_ot_pp_csc2_odc2; /* 0x2290 */ ++ volatile u_v1_ot_pp_csc2_min_y v1_ot_pp_csc2_min_y; /* 0x2294 */ ++ volatile u_v1_ot_pp_csc2_min_c v1_ot_pp_csc2_min_c; /* 0x2298 */ ++ volatile u_v1_ot_pp_csc2_max_y v1_ot_pp_csc2_max_y; /* 0x229c */ ++ volatile u_v1_ot_pp_csc2_max_c v1_ot_pp_csc2_max_c; /* 0x22a0 */ ++ volatile unsigned int reserved_36[19]; /* 19:0x22a4~0x22ec */ ++ volatile u_v1_ot_pp_csc_ink_ctrl v1_ot_pp_csc_ink_ctrl; /* 0x22f0 */ ++ volatile u_v1_ot_pp_csc_ink_pos v1_ot_pp_csc_ink_pos; /* 0x22f4 */ ++ volatile unsigned int v1_ot_pp_csc_ink_data; /* 0x22f8 */ ++ volatile unsigned int v1_ot_pp_csc_ink_data2; /* 0x22fc */ ++ volatile unsigned int reserved_37[64]; /* 64:0x2300~0x23fc */ ++ volatile u_v1_cvfir_vinfo v1_cvfir_vinfo; /* 0x2400 */ ++ volatile u_v1_cvfir_vsp v1_cvfir_vsp; /* 0x2404 */ ++ volatile u_v1_cvfir_voffset v1_cvfir_voffset; /* 0x2408 */ ++ volatile u_v1_cvfir_vboffset v1_cvfir_vboffset; /* 0x240c */ ++ volatile unsigned int reserved_38[8]; /* 8:0x2410~0x242c */ ++ volatile u_v1_cvfir_vcoef0 v1_cvfir_vcoef0; /* 0x2430 */ ++ volatile u_v1_cvfir_vcoef1 v1_cvfir_vcoef1; /* 0x2434 */ ++ volatile u_v1_cvfir_vcoef2 v1_cvfir_vcoef2; /* 0x2438 */ ++ volatile unsigned int reserved_39[49]; /* 49:0x243c~0x24fc */ ++ volatile u_v1_hfir_ctrl v1_hfir_ctrl; /* 0x2500 */ ++ volatile u_v1_hfircoef01 v1_hfircoef01; /* 0x2504 */ ++ volatile u_v1_hfircoef23 v1_hfircoef23; /* 0x2508 */ ++ volatile u_v1_hfircoef45 v1_hfircoef45; /* 0x250c */ ++ volatile u_v1_hfircoef67 v1_hfircoef67; /* 0x2510 */ ++ volatile unsigned int reserved_40[699]; /* 699:0x2514~0x2ffc */ ++ volatile u_v2_ctrl v2_ctrl; /* 0x3000 */ ++ volatile u_v2_upd v2_upd; /* 0x3004 */ ++ volatile u_v2_0reso_read v2_0reso_read; /* 0x3008 */ ++ volatile unsigned int reserved_41; /* 0x300c */ ++ volatile u_v2_ireso v2_ireso; /* 0x3010 */ ++ volatile unsigned int reserved_42[27]; /* 27:0x3014~0x307c */ ++ volatile u_v2_dfpos v2_dfpos; /* 0x3080 */ ++ volatile u_v2_dlpos v2_dlpos; /* 0x3084 */ ++ volatile u_v2_vfpos v2_vfpos; /* 0x3088 */ ++ volatile u_v2_vlpos v2_vlpos; /* 0x308c */ ++ volatile u_v2_bk v2_bk; /* 0x3090 */ ++ volatile u_v2_alpha v2_alpha; /* 0x3094 */ ++ volatile u_v2_mute_bk v2_mute_bk; /* 0x3098 */ ++ volatile unsigned int reserved_43[89]; /* 89:0x309c~0x31fc */ ++ volatile u_v2_ot_pp_csc_ctrl v2_ot_pp_csc_ctrl; /* 0x3200 */ ++ volatile u_v2_ot_pp_csc_coef00 v2_ot_pp_csc_coef00; /* 0x3204 */ ++ volatile u_v2_ot_pp_csc_coef01 v2_ot_pp_csc_coef01; /* 0x3208 */ ++ volatile u_v2_ot_pp_csc_coef02 v2_ot_pp_csc_coef02; /* 0x320c */ ++ volatile u_v2_ot_pp_csc_coef10 v2_ot_pp_csc_coef10; /* 0x3210 */ ++ volatile u_v2_ot_pp_csc_coef11 v2_ot_pp_csc_coef11; /* 0x3214 */ ++ volatile u_v2_ot_pp_csc_coef12 v2_ot_pp_csc_coef12; /* 0x3218 */ ++ volatile u_v2_ot_pp_csc_coef20 v2_ot_pp_csc_coef20; /* 0x321c */ ++ volatile u_v2_ot_pp_csc_coef21 v2_ot_pp_csc_coef21; /* 0x3220 */ ++ volatile u_v2_ot_pp_csc_coef22 v2_ot_pp_csc_coef22; /* 0x3224 */ ++ volatile u_v2_ot_pp_csc_scale v2_ot_pp_csc_scale; /* 0x3228 */ ++ volatile u_v2_ot_pp_csc_idc0 v2_ot_pp_csc_idc0; /* 0x322c */ ++ volatile u_v2_ot_pp_csc_idc1 v2_ot_pp_csc_idc1; /* 0x3230 */ ++ volatile u_v2_ot_pp_csc_idc2 v2_ot_pp_csc_idc2; /* 0x3234 */ ++ volatile u_v2_ot_pp_csc_odc0 v2_ot_pp_csc_odc0; /* 0x3238 */ ++ volatile u_v2_ot_pp_csc_odc1 v2_ot_pp_csc_odc1; /* 0x323c */ ++ volatile u_v2_ot_pp_csc_odc2 v2_ot_pp_csc_odc2; /* 0x3240 */ ++ volatile u_v2_ot_pp_csc_min_y v2_ot_pp_csc_min_y; /* 0x3244 */ ++ volatile u_v2_ot_pp_csc_min_c v2_ot_pp_csc_min_c; /* 0x3248 */ ++ volatile u_v2_ot_pp_csc_max_y v2_ot_pp_csc_max_y; /* 0x324c */ ++ volatile u_v2_ot_pp_csc_max_c v2_ot_pp_csc_max_c; /* 0x3250 */ ++ volatile u_v2_ot_pp_csc2_coef00 v2_ot_pp_csc2_coef00; /* 0x3254 */ ++ volatile u_v2_ot_pp_csc2_coef01 v2_ot_pp_csc2_coef01; /* 0x3258 */ ++ volatile u_v2_ot_pp_csc2_coef02 v2_ot_pp_csc2_coef02; /* 0x325c */ ++ volatile u_v2_ot_pp_csc2_coef10 v2_ot_pp_csc2_coef10; /* 0x3260 */ ++ volatile u_v2_ot_pp_csc2_coef11 v2_ot_pp_csc2_coef11; /* 0x3264 */ ++ volatile u_v2_ot_pp_csc2_coef12 v2_ot_pp_csc2_coef12; /* 0x3268 */ ++ volatile u_v2_ot_pp_csc2_coef20 v2_ot_pp_csc2_coef20; /* 0x326c */ ++ volatile u_v2_ot_pp_csc2_coef21 v2_ot_pp_csc2_coef21; /* 0x3270 */ ++ volatile u_v2_ot_pp_csc2_coef22 v2_ot_pp_csc2_coef22; /* 0x3274 */ ++ volatile u_v2_ot_pp_csc2_scale v2_ot_pp_csc2_scale; /* 0x3278 */ ++ volatile u_v2_ot_pp_csc2_idc0 v2_ot_pp_csc2_idc0; /* 0x327c */ ++ volatile u_v2_ot_pp_csc2_idc1 v2_ot_pp_csc2_idc1; /* 0x3280 */ ++ volatile u_v2_ot_pp_csc2_idc2 v2_ot_pp_csc2_idc2; /* 0x3284 */ ++ volatile u_v2_ot_pp_csc2_odc0 v2_ot_pp_csc2_odc0; /* 0x3288 */ ++ volatile u_v2_ot_pp_csc2_odc1 v2_ot_pp_csc2_odc1; /* 0x328c */ ++ volatile u_v2_ot_pp_csc2_odc2 v2_ot_pp_csc2_odc2; /* 0x3290 */ ++ volatile u_v2_ot_pp_csc2_min_y v2_ot_pp_csc2_min_y; /* 0x3294 */ ++ volatile u_v2_ot_pp_csc2_min_c v2_ot_pp_csc2_min_c; /* 0x3298 */ ++ volatile u_v2_ot_pp_csc2_max_y v2_ot_pp_csc2_max_y; /* 0x329c */ ++ volatile u_v2_ot_pp_csc2_max_c v2_ot_pp_csc2_max_c; /* 0x32a0 */ ++ volatile unsigned int reserved_44[19]; /* 19:0x32a4~0x32ec */ ++ volatile u_v2_ot_pp_csc_ink_ctrl v2_ot_pp_csc_ink_ctrl; /* 0x32f0 */ ++ volatile u_v2_ot_pp_csc_ink_pos v2_ot_pp_csc_ink_pos; /* 0x32f4 */ ++ volatile unsigned int v2_ot_pp_csc_ink_data; /* 0x32f8 */ ++ volatile unsigned int v2_ot_pp_csc_ink_data2; /* 0x32fc */ ++ volatile unsigned int reserved_45[64]; /* 64:0x3300~0x33fc */ ++ volatile u_v2_cvfir_vinfo v2_cvfir_vinfo; /* 0x3400 */ ++ volatile u_v2_cvfir_vsp v2_cvfir_vsp; /* 0x3404 */ ++ volatile u_v2_cvfir_voffset v2_cvfir_voffset; /* 0x3408 */ ++ volatile u_v2_cvfir_vboffset v2_cvfir_vboffset; /* 0x340c */ ++ volatile unsigned int reserved_46[8]; /* 8:0x3410~0x342c */ ++ volatile u_v2_cvfir_vcoef0 v2_cvfir_vcoef0; /* 0x3430 */ ++ volatile u_v2_cvfir_vcoef1 v2_cvfir_vcoef1; /* 0x3434 */ ++ volatile u_v2_cvfir_vcoef2 v2_cvfir_vcoef2; /* 0x3438 */ ++ volatile unsigned int reserved_47[49]; /* 49:0x343c~0x34fc */ ++ volatile u_v2_hfir_ctrl v2_hfir_ctrl; /* 0x3500 */ ++ volatile u_v2_hfircoef01 v2_hfircoef01; /* 0x3504 */ ++ volatile u_v2_hfircoef23 v2_hfircoef23; /* 0x3508 */ ++ volatile u_v2_hfircoef45 v2_hfircoef45; /* 0x350c */ ++ volatile u_v2_hfircoef67 v2_hfircoef67; /* 0x3510 */ ++ volatile unsigned int reserved_48[699]; /* 699:0x3514~0x3ffc */ ++ volatile u_v3_ctrl v3_ctrl; /* 0x4000 */ ++ volatile u_v3_upd v3_upd; /* 0x4004 */ ++ volatile u_v3_0reso_read v3_0reso_read; /* 0x4008 */ ++ volatile unsigned int reserved_49; /* 0x400c */ ++ volatile u_v3_ireso v3_ireso; /* 0x4010 */ ++ volatile unsigned int reserved_50[27]; /* 27:0x4014~0x407c */ ++ volatile u_v3_dfpos v3_dfpos; /* 0x4080 */ ++ volatile u_v3_dlpos v3_dlpos; /* 0x4084 */ ++ volatile u_v3_vfpos v3_vfpos; /* 0x4088 */ ++ volatile u_v3_vlpos v3_vlpos; /* 0x408c */ ++ volatile u_v3_bk v3_bk; /* 0x4090 */ ++ volatile u_v3_alpha v3_alpha; /* 0x4094 */ ++ volatile u_v3_mute_bk v3_mute_bk; /* 0x4098 */ ++ volatile unsigned int reserved_51; /* 0x409c */ ++ volatile u_v3_rimwidth v3_rimwidth; /* 0x40a0 */ ++ volatile u_v3_rimcol0 v3_rimcol0; /* 0x40a4 */ ++ volatile u_v3_rimcol1 v3_rimcol1; /* 0x40a8 */ ++ volatile unsigned int reserved_52[85]; /* 85:0x40ac~0x41fc */ ++ volatile u_v3_ot_pp_csc_ctrl v3_ot_pp_csc_ctrl; /* 0x4200 */ ++ volatile u_v3_ot_pp_csc_coef00 v3_ot_pp_csc_coef00; /* 0x4204 */ ++ volatile u_v3_ot_pp_csc_coef01 v3_ot_pp_csc_coef01; /* 0x4208 */ ++ volatile u_v3_ot_pp_csc_coef02 v3_ot_pp_csc_coef02; /* 0x420c */ ++ volatile u_v3_ot_pp_csc_coef10 v3_ot_pp_csc_coef10; /* 0x4210 */ ++ volatile u_v3_ot_pp_csc_coef11 v3_ot_pp_csc_coef11; /* 0x4214 */ ++ volatile u_v3_ot_pp_csc_coef12 v3_ot_pp_csc_coef12; /* 0x4218 */ ++ volatile u_v3_ot_pp_csc_coef20 v3_ot_pp_csc_coef20; /* 0x421c */ ++ volatile u_v3_ot_pp_csc_coef21 v3_ot_pp_csc_coef21; /* 0x4220 */ ++ volatile u_v3_ot_pp_csc_coef22 v3_ot_pp_csc_coef22; /* 0x4224 */ ++ volatile u_v3_ot_pp_csc_scale v3_ot_pp_csc_scale; /* 0x4228 */ ++ volatile u_v3_ot_pp_csc_idc0 v3_ot_pp_csc_idc0; /* 0x422c */ ++ volatile u_v3_ot_pp_csc_idc1 v3_ot_pp_csc_idc1; /* 0x4230 */ ++ volatile u_v3_ot_pp_csc_idc2 v3_ot_pp_csc_idc2; /* 0x4234 */ ++ volatile u_v3_ot_pp_csc_odc0 v3_ot_pp_csc_odc0; /* 0x4238 */ ++ volatile u_v3_ot_pp_csc_odc1 v3_ot_pp_csc_odc1; /* 0x423c */ ++ volatile u_v3_ot_pp_csc_odc2 v3_ot_pp_csc_odc2; /* 0x4240 */ ++ volatile u_v3_ot_pp_csc_min_y v3_ot_pp_csc_min_y; /* 0x4244 */ ++ volatile u_v3_ot_pp_csc_min_c v3_ot_pp_csc_min_c; /* 0x4248 */ ++ volatile u_v3_ot_pp_csc_max_y v3_ot_pp_csc_max_y; /* 0x424c */ ++ volatile u_v3_ot_pp_csc_max_c v3_ot_pp_csc_max_c; /* 0x4250 */ ++ volatile u_v3_ot_pp_csc2_coef00 v3_ot_pp_csc2_coef00; /* 0x4254 */ ++ volatile u_v3_ot_pp_csc2_coef01 v3_ot_pp_csc2_coef01; /* 0x4258 */ ++ volatile u_v3_ot_pp_csc2_coef02 v3_ot_pp_csc2_coef02; /* 0x425c */ ++ volatile u_v3_ot_pp_csc2_coef10 v3_ot_pp_csc2_coef10; /* 0x4260 */ ++ volatile u_v3_ot_pp_csc2_coef11 v3_ot_pp_csc2_coef11; /* 0x4264 */ ++ volatile u_v3_ot_pp_csc2_coef12 v3_ot_pp_csc2_coef12; /* 0x4268 */ ++ volatile u_v3_ot_pp_csc2_coef20 v3_ot_pp_csc2_coef20; /* 0x426c */ ++ volatile u_v3_ot_pp_csc2_coef21 v3_ot_pp_csc2_coef21; /* 0x4270 */ ++ volatile u_v3_ot_pp_csc2_coef22 v3_ot_pp_csc2_coef22; /* 0x4274 */ ++ volatile u_v3_ot_pp_csc2_scale v3_ot_pp_csc2_scale; /* 0x4278 */ ++ volatile u_v3_ot_pp_csc2_idc0 v3_ot_pp_csc2_idc0; /* 0x427c */ ++ volatile u_v3_ot_pp_csc2_idc1 v3_ot_pp_csc2_idc1; /* 0x4280 */ ++ volatile u_v3_ot_pp_csc2_idc2 v3_ot_pp_csc2_idc2; /* 0x4284 */ ++ volatile u_v3_ot_pp_csc2_odc0 v3_ot_pp_csc2_odc0; /* 0x4288 */ ++ volatile u_v3_ot_pp_csc2_odc1 v3_ot_pp_csc2_odc1; /* 0x428c */ ++ volatile u_v3_ot_pp_csc2_odc2 v3_ot_pp_csc2_odc2; /* 0x4290 */ ++ volatile u_v3_ot_pp_csc2_min_y v3_ot_pp_csc2_min_y; /* 0x4294 */ ++ volatile u_v3_ot_pp_csc2_min_c v3_ot_pp_csc2_min_c; /* 0x4298 */ ++ volatile u_v3_ot_pp_csc2_max_y v3_ot_pp_csc2_max_y; /* 0x429c */ ++ volatile u_v3_ot_pp_csc2_max_c v3_ot_pp_csc2_max_c; /* 0x42a0 */ ++ volatile unsigned int reserved_53[19]; /* 19:0x42a4~0x42ec */ ++ volatile u_v3_ot_pp_csc_ink_ctrl v3_ot_pp_csc_ink_ctrl; /* 0x42f0 */ ++ volatile u_v3_ot_pp_csc_ink_pos v3_ot_pp_csc_ink_pos; /* 0x42f4 */ ++ volatile unsigned int v3_ot_pp_csc_ink_data; /* 0x42f8 */ ++ volatile unsigned int v3_ot_pp_csc_ink_data2; /* 0x42fc */ ++ volatile unsigned int reserved_54[128]; /* 128:0x4300~0x44fc */ ++ volatile u_v3_hfir_ctrl v3_hfir_ctrl; /* 0x4500 */ ++ volatile u_v3_hfircoef01 v3_hfircoef01; /* 0x4504 */ ++ volatile u_v3_hfircoef23 v3_hfircoef23; /* 0x4508 */ ++ volatile u_v3_hfircoef45 v3_hfircoef45; /* 0x450c */ ++ volatile u_v3_hfircoef67 v3_hfircoef67; /* 0x4510 */ ++ volatile unsigned int reserved_55[1211]; /* 1211:0x4514~0x57fc */ ++ volatile unsigned int vp0_ctrl; /* 0x5800 */ ++ volatile u_vp0_upd vp0_upd; /* 0x5804 */ ++ volatile u_vp0_ireso vp0_ireso; /* 0x5808 */ ++ volatile unsigned int reserved_56[29]; /* 29:0x580c~0x587c */ ++ volatile u_vp0_lbox_ctrl vp0_lbox_ctrl; /* 0x5880 */ ++ volatile u_vp0_galpha vp0_galpha; /* 0x5884 */ ++ volatile u_vp0_dfpos vp0_dfpos; /* 0x5888 */ ++ volatile u_vp0_dlpos vp0_dlpos; /* 0x588c */ ++ volatile u_vp0_vfpos vp0_vfpos; /* 0x5890 */ ++ volatile u_vp0_vlpos vp0_vlpos; /* 0x5894 */ ++ volatile u_vp0_bk vp0_bk; /* 0x5898 */ ++ volatile u_vp0_alpha vp0_alpha; /* 0x589c */ ++ volatile u_vp0_mute_bk vp0_mute_bk; /* 0x58a0 */ ++ volatile unsigned int reserved_57[1495]; /* 1495:0x58a4~0x6ffc */ ++ volatile u_g0_ctrl g0_ctrl; /* 0x7000 */ ++ volatile u_g0_upd g0_upd; /* 0x7004 */ ++ volatile unsigned int g0_galpha_sum; /* 0x7008 */ ++ volatile u_g0_0reso_read g0_0reso_read; /* 0x700c */ ++ volatile u_g0_ireso g0_ireso; /* 0x7010 */ ++ volatile unsigned int reserved_58[27]; /* 27:0x7014~0x707c */ ++ volatile u_g0_dfpos g0_dfpos; /* 0x7080 */ ++ volatile u_g0_dlpos g0_dlpos; /* 0x7084 */ ++ volatile u_g0_vfpos g0_vfpos; /* 0x7088 */ ++ volatile u_g0_vlpos g0_vlpos; /* 0x708c */ ++ volatile u_g0_bk g0_bk; /* 0x7090 */ ++ volatile u_g0_alpha g0_alpha; /* 0x7094 */ ++ volatile u_g0_mute_bk g0_mute_bk; /* 0x7098 */ ++ volatile u_g0_lbox_ctrl g0_lbox_ctrl; /* 0x709c */ ++ volatile unsigned int reserved_59[24]; /* 24:0x70a0~0x70fc */ ++ volatile u_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; /* 0x7100 */ ++ volatile u_g0_ot_pp_csc_coef00 g0_ot_pp_csc_coef00; /* 0x7104 */ ++ volatile u_g0_ot_pp_csc_coef01 g0_ot_pp_csc_coef01; /* 0x7108 */ ++ volatile u_g0_ot_pp_csc_coef02 g0_ot_pp_csc_coef02; /* 0x710c */ ++ volatile u_g0_ot_pp_csc_coef10 g0_ot_pp_csc_coef10; /* 0x7110 */ ++ volatile u_g0_ot_pp_csc_coef11 g0_ot_pp_csc_coef11; /* 0x7114 */ ++ volatile u_g0_ot_pp_csc_coef12 g0_ot_pp_csc_coef12; /* 0x7118 */ ++ volatile u_g0_ot_pp_csc_coef20 g0_ot_pp_csc_coef20; /* 0x711c */ ++ volatile u_g0_ot_pp_csc_coef21 g0_ot_pp_csc_coef21; /* 0x7120 */ ++ volatile u_g0_ot_pp_csc_coef22 g0_ot_pp_csc_coef22; /* 0x7124 */ ++ volatile u_g0_ot_pp_csc_scale g0_ot_pp_csc_scale; /* 0x7128 */ ++ volatile u_g0_ot_pp_csc_idc0 g0_ot_pp_csc_idc0; /* 0x712c */ ++ volatile u_g0_ot_pp_csc_idc1 g0_ot_pp_csc_idc1; /* 0x7130 */ ++ volatile u_g0_ot_pp_csc_idc2 g0_ot_pp_csc_idc2; /* 0x7134 */ ++ volatile u_g0_ot_pp_csc_odc0 g0_ot_pp_csc_odc0; /* 0x7138 */ ++ volatile u_g0_ot_pp_csc_odc1 g0_ot_pp_csc_odc1; /* 0x713c */ ++ volatile u_g0_ot_pp_csc_odc2 g0_ot_pp_csc_odc2; /* 0x7140 */ ++ volatile u_g0_ot_pp_csc_min_y g0_ot_pp_csc_min_y; /* 0x7144 */ ++ volatile u_g0_ot_pp_csc_min_c g0_ot_pp_csc_min_c; /* 0x7148 */ ++ volatile u_g0_ot_pp_csc_max_y g0_ot_pp_csc_max_y; /* 0x714c */ ++ volatile u_g0_ot_pp_csc_max_c g0_ot_pp_csc_max_c; /* 0x7150 */ ++ volatile u_g0_ot_pp_csc2_coef00 g0_ot_pp_csc2_coef00; /* 0x7154 */ ++ volatile u_g0_ot_pp_csc2_coef01 g0_ot_pp_csc2_coef01; /* 0x7158 */ ++ volatile u_g0_ot_pp_csc2_coef02 g0_ot_pp_csc2_coef02; /* 0x715c */ ++ volatile u_g0_ot_pp_csc2_coef10 g0_ot_pp_csc2_coef10; /* 0x7160 */ ++ volatile u_g0_ot_pp_csc2_coef11 g0_ot_pp_csc2_coef11; /* 0x7164 */ ++ volatile u_g0_ot_pp_csc2_coef12 g0_ot_pp_csc2_coef12; /* 0x7168 */ ++ volatile u_g0_ot_pp_csc2_coef20 g0_ot_pp_csc2_coef20; /* 0x716c */ ++ volatile u_g0_ot_pp_csc2_coef21 g0_ot_pp_csc2_coef21; /* 0x7170 */ ++ volatile u_g0_ot_pp_csc2_coef22 g0_ot_pp_csc2_coef22; /* 0x7174 */ ++ volatile u_g0_ot_pp_csc2_scale g0_ot_pp_csc2_scale; /* 0x7178 */ ++ volatile u_g0_ot_pp_csc2_idc0 g0_ot_pp_csc2_idc0; /* 0x717c */ ++ volatile u_g0_ot_pp_csc2_idc1 g0_ot_pp_csc2_idc1; /* 0x7180 */ ++ volatile u_g0_ot_pp_csc2_idc2 g0_ot_pp_csc2_idc2; /* 0x7184 */ ++ volatile u_g0_ot_pp_csc2_odc0 g0_ot_pp_csc2_odc0; /* 0x7188 */ ++ volatile u_g0_ot_pp_csc2_odc1 g0_ot_pp_csc2_odc1; /* 0x718c */ ++ volatile u_g0_ot_pp_csc2_odc2 g0_ot_pp_csc2_odc2; /* 0x7190 */ ++ volatile u_g0_ot_pp_csc2_min_y g0_ot_pp_csc2_min_y; /* 0x7194 */ ++ volatile u_g0_ot_pp_csc2_min_c g0_ot_pp_csc2_min_c; /* 0x7198 */ ++ volatile u_g0_ot_pp_csc2_max_y g0_ot_pp_csc2_max_y; /* 0x719c */ ++ volatile u_g0_ot_pp_csc2_max_c g0_ot_pp_csc2_max_c; /* 0x71a0 */ ++ volatile unsigned int reserved_60[19]; /* 19:0x71a4~0x71ec */ ++ volatile u_g0_ot_pp_csc_ink_ctrl g0_ot_pp_csc_ink_ctrl; /* 0x71f0 */ ++ volatile u_g0_ot_pp_csc_ink_pos g0_ot_pp_csc_ink_pos; /* 0x71f4 */ ++ volatile unsigned int g0_ot_pp_csc_ink_data; /* 0x71f8 */ ++ volatile unsigned int g0_ot_pp_csc_ink_data2; /* 0x71fc */ ++ volatile u_g0_dof_ctrl g0_dof_ctrl; /* 0x7200 */ ++ volatile u_g0_dof_step g0_dof_step; /* 0x7204 */ ++ volatile u_g0_dof_bkg g0_dof_bkg; /* 0x7208 */ ++ volatile u_g0_dof_alpha g0_dof_alpha; /* 0x720c */ ++ volatile unsigned int reserved_61[60]; /* 60:0x7210~0x72fc */ ++ volatile u_g0_zme_hinfo g0_zme_hinfo; /* 0x7300 */ ++ volatile u_g0_zme_hsp g0_zme_hsp; /* 0x7304 */ ++ volatile u_g0_zme_hloffset g0_zme_hloffset; /* 0x7308 */ ++ volatile u_g0_zme_hcoffset g0_zme_hcoffset; /* 0x730c */ ++ volatile unsigned int reserved_62[5]; /* 5:0x7310~0x7320 */ ++ volatile u_g0_zme_coef_ren g0_zme_coef_ren; /* 0x7324 */ ++ volatile u_g0_zme_coef_rdata g0_zme_coef_rdata; /* 0x7328 */ ++ volatile unsigned int reserved_63[21]; /* 21:0x732c~0x737c */ ++ volatile u_g0_zme_vinfo g0_zme_vinfo; /* 0x7380 */ ++ volatile u_g0_zme_vsp g0_zme_vsp; /* 0x7384 */ ++ volatile u_g0_zme_voffset g0_zme_voffset; /* 0x7388 */ ++ volatile unsigned int reserved_64[285]; /* 285:0x738c~0x77fc */ ++ volatile u_g1_ctrl g1_ctrl; /* 0x7800 */ ++ volatile u_g1_upd g1_upd; /* 0x7804 */ ++ volatile unsigned int g1_galpha_sum; /* 0x7808 */ ++ volatile u_g1_0reso_read g1_0reso_read; /* 0x780c */ ++ volatile u_g1_ireso g1_ireso; /* 0x7810 */ ++ volatile unsigned int reserved_65[27]; /* 27:0x7814~0x787c */ ++ volatile u_g1_dfpos g1_dfpos; /* 0x7880 */ ++ volatile u_g1_dlpos g1_dlpos; /* 0x7884 */ ++ volatile u_g1_vfpos g1_vfpos; /* 0x7888 */ ++ volatile u_g1_vlpos g1_vlpos; /* 0x788c */ ++ volatile u_g1_bk g1_bk; /* 0x7890 */ ++ volatile u_g1_alpha g1_alpha; /* 0x7894 */ ++ volatile u_g1_mute_bk g1_mute_bk; /* 0x7898 */ ++ volatile u_g1_lbox_ctrl g1_lbox_ctrl; /* 0x789c */ ++ volatile unsigned int reserved_66[24]; /* 24:0x78a0~0x78fc */ ++ volatile u_g1_ot_pp_csc_ctrl g1_ot_pp_csc_ctrl; /* 0x7900 */ ++ volatile u_g1_ot_pp_csc_coef00 g1_ot_pp_csc_coef00; /* 0x7904 */ ++ volatile u_g1_ot_pp_csc_coef01 g1_ot_pp_csc_coef01; /* 0x7908 */ ++ volatile u_g1_ot_pp_csc_coef02 g1_ot_pp_csc_coef02; /* 0x790c */ ++ volatile u_g1_ot_pp_csc_coef10 g1_ot_pp_csc_coef10; /* 0x7910 */ ++ volatile u_g1_ot_pp_csc_coef11 g1_ot_pp_csc_coef11; /* 0x7914 */ ++ volatile u_g1_ot_pp_csc_coef12 g1_ot_pp_csc_coef12; /* 0x7918 */ ++ volatile u_g1_ot_pp_csc_coef20 g1_ot_pp_csc_coef20; /* 0x791c */ ++ volatile u_g1_ot_pp_csc_coef21 g1_ot_pp_csc_coef21; /* 0x7920 */ ++ volatile u_g1_ot_pp_csc_coef22 g1_ot_pp_csc_coef22; /* 0x7924 */ ++ volatile u_g1_ot_pp_csc_scale g1_ot_pp_csc_scale; /* 0x7928 */ ++ volatile u_g1_ot_pp_csc_idc0 g1_ot_pp_csc_idc0; /* 0x792c */ ++ volatile u_g1_ot_pp_csc_idc1 g1_ot_pp_csc_idc1; /* 0x7930 */ ++ volatile u_g1_ot_pp_csc_idc2 g1_ot_pp_csc_idc2; /* 0x7934 */ ++ volatile u_g1_ot_pp_csc_odc0 g1_ot_pp_csc_odc0; /* 0x7938 */ ++ volatile u_g1_ot_pp_csc_odc1 g1_ot_pp_csc_odc1; /* 0x793c */ ++ volatile u_g1_ot_pp_csc_odc2 g1_ot_pp_csc_odc2; /* 0x7940 */ ++ volatile u_g1_ot_pp_csc_min_y g1_ot_pp_csc_min_y; /* 0x7944 */ ++ volatile u_g1_ot_pp_csc_min_c g1_ot_pp_csc_min_c; /* 0x7948 */ ++ volatile u_g1_ot_pp_csc_max_y g1_ot_pp_csc_max_y; /* 0x794c */ ++ volatile u_g1_ot_pp_csc_max_c g1_ot_pp_csc_max_c; /* 0x7950 */ ++ volatile u_g1_ot_pp_csc2_coef00 g1_ot_pp_csc2_coef00; /* 0x7954 */ ++ volatile u_g1_ot_pp_csc2_coef01 g1_ot_pp_csc2_coef01; /* 0x7958 */ ++ volatile u_g1_ot_pp_csc2_coef02 g1_ot_pp_csc2_coef02; /* 0x795c */ ++ volatile u_g1_ot_pp_csc2_coef10 g1_ot_pp_csc2_coef10; /* 0x7960 */ ++ volatile u_g1_ot_pp_csc2_coef11 g1_ot_pp_csc2_coef11; /* 0x7964 */ ++ volatile u_g1_ot_pp_csc2_coef12 g1_ot_pp_csc2_coef12; /* 0x7968 */ ++ volatile u_g1_ot_pp_csc2_coef20 g1_ot_pp_csc2_coef20; /* 0x796c */ ++ volatile u_g1_ot_pp_csc2_coef21 g1_ot_pp_csc2_coef21; /* 0x7970 */ ++ volatile u_g1_ot_pp_csc2_coef22 g1_ot_pp_csc2_coef22; /* 0x7974 */ ++ volatile u_g1_ot_pp_csc2_scale g1_ot_pp_csc2_scale; /* 0x7978 */ ++ volatile u_g1_ot_pp_csc2_idc0 g1_ot_pp_csc2_idc0; /* 0x797c */ ++ volatile u_g1_ot_pp_csc2_idc1 g1_ot_pp_csc2_idc1; /* 0x7980 */ ++ volatile u_g1_ot_pp_csc2_idc2 g1_ot_pp_csc2_idc2; /* 0x7984 */ ++ volatile u_g1_ot_pp_csc2_odc0 g1_ot_pp_csc2_odc0; /* 0x7988 */ ++ volatile u_g1_ot_pp_csc2_odc1 g1_ot_pp_csc2_odc1; /* 0x798c */ ++ volatile u_g1_ot_pp_csc2_odc2 g1_ot_pp_csc2_odc2; /* 0x7990 */ ++ volatile u_g1_ot_pp_csc2_min_y g1_ot_pp_csc2_min_y; /* 0x7994 */ ++ volatile u_g1_ot_pp_csc2_min_c g1_ot_pp_csc2_min_c; /* 0x7998 */ ++ volatile u_g1_ot_pp_csc2_max_y g1_ot_pp_csc2_max_y; /* 0x799c */ ++ volatile u_g1_ot_pp_csc2_max_c g1_ot_pp_csc2_max_c; /* 0x79a0 */ ++ volatile unsigned int reserved_67[19]; /* 19:0x79a4~0x79ec */ ++ volatile u_g1_ot_pp_csc_ink_ctrl g1_ot_pp_csc_ink_ctrl; /* 0x79f0 */ ++ volatile u_g1_ot_pp_csc_ink_pos g1_ot_pp_csc_ink_pos; /* 0x79f4 */ ++ volatile unsigned int g1_ot_pp_csc_ink_data; /* 0x79f8 */ ++ volatile unsigned int g1_ot_pp_csc_ink_data2; /* 0x79fc */ ++ volatile unsigned int reserved_68[64]; /* 64:0x7a00~0x7afc */ ++ volatile u_g1_zme_hinfo g1_zme_hinfo; /* 0x7b00 */ ++ volatile u_g1_zme_hsp g1_zme_hsp; /* 0x7b04 */ ++ volatile u_g1_zme_hloffset g1_zme_hloffset; /* 0x7b08 */ ++ volatile u_g1_zme_hcoffset g1_zme_hcoffset; /* 0x7b0c */ ++ volatile unsigned int reserved_69[5]; /* 5:0x7b10~0x7b20 */ ++ volatile u_g1_zme_coef_ren g1_zme_coef_ren; /* 0x7b24 */ ++ volatile u_g1_zme_coef_rdata g1_zme_coef_rdata; /* 0x7b28 */ ++ volatile unsigned int reserved_70[21]; /* 21:0x7b2c~0x7b7c */ ++ volatile u_g1_zme_vinfo g1_zme_vinfo; /* 0x7b80 */ ++ volatile u_g1_zme_vsp g1_zme_vsp; /* 0x7b84 */ ++ volatile u_g1_zme_voffset g1_zme_voffset; /* 0x7b88 */ ++ volatile unsigned int reserved_71[285]; /* 285:0x7b8c~0x7ffc */ ++ volatile u_g2_ctrl g2_ctrl; /* 0x8000 */ ++ volatile u_g2_upd g2_upd; /* 0x8004 */ ++ volatile unsigned int g2_galpha_sum; /* 0x8008 */ ++ volatile u_g2_0reso_read g2_0reso_read; /* 0x800c */ ++ volatile u_g2_ireso g2_ireso; /* 0x8010 */ ++ volatile unsigned int reserved_72[27]; /* 27:0x8014~0x807c */ ++ volatile u_g2_dfpos g2_dfpos; /* 0x8080 */ ++ volatile u_g2_dlpos g2_dlpos; /* 0x8084 */ ++ volatile u_g2_vfpos g2_vfpos; /* 0x8088 */ ++ volatile u_g2_vlpos g2_vlpos; /* 0x808c */ ++ volatile u_g2_bk g2_bk; /* 0x8090 */ ++ volatile u_g2_alpha g2_alpha; /* 0x8094 */ ++ volatile u_g2_mute_bk g2_mute_bk; /* 0x8098 */ ++ volatile u_g2_lbox_ctrl g2_lbox_ctrl; /* 0x809c */ ++ volatile unsigned int reserved_73[24]; /* 24:0x80a0~0x80fc */ ++ volatile u_g2_ot_pp_csc_ctrl g2_ot_pp_csc_ctrl; /* 0x8100 */ ++ volatile u_g2_ot_pp_csc_coef00 g2_ot_pp_csc_coef00; /* 0x8104 */ ++ volatile u_g2_ot_pp_csc_coef01 g2_ot_pp_csc_coef01; /* 0x8108 */ ++ volatile u_g2_ot_pp_csc_coef02 g2_ot_pp_csc_coef02; /* 0x810c */ ++ volatile u_g2_ot_pp_csc_coef10 g2_ot_pp_csc_coef10; /* 0x8110 */ ++ volatile u_g2_ot_pp_csc_coef11 g2_ot_pp_csc_coef11; /* 0x8114 */ ++ volatile u_g2_ot_pp_csc_coef12 g2_ot_pp_csc_coef12; /* 0x8118 */ ++ volatile u_g2_ot_pp_csc_coef20 g2_ot_pp_csc_coef20; /* 0x811c */ ++ volatile u_g2_ot_pp_csc_coef21 g2_ot_pp_csc_coef21; /* 0x8120 */ ++ volatile u_g2_ot_pp_csc_coef22 g2_ot_pp_csc_coef22; /* 0x8124 */ ++ volatile u_g2_ot_pp_csc_scale g2_ot_pp_csc_scale; /* 0x8128 */ ++ volatile u_g2_ot_pp_csc_idc0 g2_ot_pp_csc_idc0; /* 0x812c */ ++ volatile u_g2_ot_pp_csc_idc1 g2_ot_pp_csc_idc1; /* 0x8130 */ ++ volatile u_g2_ot_pp_csc_idc2 g2_ot_pp_csc_idc2; /* 0x8134 */ ++ volatile u_g2_ot_pp_csc_odc0 g2_ot_pp_csc_odc0; /* 0x8138 */ ++ volatile u_g2_ot_pp_csc_odc1 g2_ot_pp_csc_odc1; /* 0x813c */ ++ volatile u_g2_ot_pp_csc_odc2 g2_ot_pp_csc_odc2; /* 0x8140 */ ++ volatile u_g2_ot_pp_csc_min_y g2_ot_pp_csc_min_y; /* 0x8144 */ ++ volatile u_g2_ot_pp_csc_min_c g2_ot_pp_csc_min_c; /* 0x8148 */ ++ volatile u_g2_ot_pp_csc_max_y g2_ot_pp_csc_max_y; /* 0x814c */ ++ volatile u_g2_ot_pp_csc_max_c g2_ot_pp_csc_max_c; /* 0x8150 */ ++ volatile u_g2_ot_pp_csc2_coef00 g2_ot_pp_csc2_coef00; /* 0x8154 */ ++ volatile u_g2_ot_pp_csc2_coef01 g2_ot_pp_csc2_coef01; /* 0x8158 */ ++ volatile u_g2_ot_pp_csc2_coef02 g2_ot_pp_csc2_coef02; /* 0x815c */ ++ volatile u_g2_ot_pp_csc2_coef10 g2_ot_pp_csc2_coef10; /* 0x8160 */ ++ volatile u_g2_ot_pp_csc2_coef11 g2_ot_pp_csc2_coef11; /* 0x8164 */ ++ volatile u_g2_ot_pp_csc2_coef12 g2_ot_pp_csc2_coef12; /* 0x8168 */ ++ volatile u_g2_ot_pp_csc2_coef20 g2_ot_pp_csc2_coef20; /* 0x816c */ ++ volatile u_g2_ot_pp_csc2_coef21 g2_ot_pp_csc2_coef21; /* 0x8170 */ ++ volatile u_g2_ot_pp_csc2_coef22 g2_ot_pp_csc2_coef22; /* 0x8174 */ ++ volatile u_g2_ot_pp_csc2_scale g2_ot_pp_csc2_scale; /* 0x8178 */ ++ volatile u_g2_ot_pp_csc2_idc0 g2_ot_pp_csc2_idc0; /* 0x817c */ ++ volatile u_g2_ot_pp_csc2_idc1 g2_ot_pp_csc2_idc1; /* 0x8180 */ ++ volatile u_g2_ot_pp_csc2_idc2 g2_ot_pp_csc2_idc2; /* 0x8184 */ ++ volatile u_g2_ot_pp_csc2_odc0 g2_ot_pp_csc2_odc0; /* 0x8188 */ ++ volatile u_g2_ot_pp_csc2_odc1 g2_ot_pp_csc2_odc1; /* 0x818c */ ++ volatile u_g2_ot_pp_csc2_odc2 g2_ot_pp_csc2_odc2; /* 0x8190 */ ++ volatile u_g2_ot_pp_csc2_min_y g2_ot_pp_csc2_min_y; /* 0x8194 */ ++ volatile u_g2_ot_pp_csc2_min_c g2_ot_pp_csc2_min_c; /* 0x8198 */ ++ volatile u_g2_ot_pp_csc2_max_y g2_ot_pp_csc2_max_y; /* 0x819c */ ++ volatile u_g2_ot_pp_csc2_max_c g2_ot_pp_csc2_max_c; /* 0x81a0 */ ++ volatile unsigned int reserved_74[19]; /* 19:0x81a4~0x81ec */ ++ volatile u_g2_ot_pp_csc_ink_ctrl g2_ot_pp_csc_ink_ctrl; /* 0x81f0 */ ++ volatile u_g2_ot_pp_csc_ink_pos g2_ot_pp_csc_ink_pos; /* 0x81f4 */ ++ volatile unsigned int g2_ot_pp_csc_ink_data; /* 0x81f8 */ ++ volatile unsigned int g2_ot_pp_csc_ink_data2; /* 0x81fc */ ++ volatile unsigned int reserved_75[384]; /* 384:0x8200~0x87fc */ ++ volatile u_g3_ctrl g3_ctrl; /* 0x8800 */ ++ volatile u_g3_upd g3_upd; /* 0x8804 */ ++ volatile unsigned int g3_galpha_sum; /* 0x8808 */ ++ volatile u_g3_0reso_read g3_0reso_read; /* 0x880c */ ++ volatile u_g3_ireso g3_ireso; /* 0x8810 */ ++ volatile unsigned int reserved_76[27]; /* 27:0x8814~0x887c */ ++ volatile u_g3_dfpos g3_dfpos; /* 0x8880 */ ++ volatile u_g3_dlpos g3_dlpos; /* 0x8884 */ ++ volatile u_g3_vfpos g3_vfpos; /* 0x8888 */ ++ volatile u_g3_vlpos g3_vlpos; /* 0x888c */ ++ volatile u_g3_bk g3_bk; /* 0x8890 */ ++ volatile u_g3_alpha g3_alpha; /* 0x8894 */ ++ volatile u_g3_mute_bk g3_mute_bk; /* 0x8898 */ ++ volatile u_g3_lbox_ctrl g3_lbox_ctrl; /* 0x889c */ ++ volatile unsigned int reserved_77[24]; /* 24:0x88a0~0x88fc */ ++ volatile u_g3_ot_pp_csc_ctrl g3_ot_pp_csc_ctrl; /* 0x8900 */ ++ volatile u_g3_ot_pp_csc_coef00 g3_ot_pp_csc_coef00; /* 0x8904 */ ++ volatile u_g3_ot_pp_csc_coef01 g3_ot_pp_csc_coef01; /* 0x8908 */ ++ volatile u_g3_ot_pp_csc_coef02 g3_ot_pp_csc_coef02; /* 0x890c */ ++ volatile u_g3_ot_pp_csc_coef10 g3_ot_pp_csc_coef10; /* 0x8910 */ ++ volatile u_g3_ot_pp_csc_coef11 g3_ot_pp_csc_coef11; /* 0x8914 */ ++ volatile u_g3_ot_pp_csc_coef12 g3_ot_pp_csc_coef12; /* 0x8918 */ ++ volatile u_g3_ot_pp_csc_coef20 g3_ot_pp_csc_coef20; /* 0x891c */ ++ volatile u_g3_ot_pp_csc_coef21 g3_ot_pp_csc_coef21; /* 0x8920 */ ++ volatile u_g3_ot_pp_csc_coef22 g3_ot_pp_csc_coef22; /* 0x8924 */ ++ volatile u_g3_ot_pp_csc_scale g3_ot_pp_csc_scale; /* 0x8928 */ ++ volatile u_g3_ot_pp_csc_idc0 g3_ot_pp_csc_idc0; /* 0x892c */ ++ volatile u_g3_ot_pp_csc_idc1 g3_ot_pp_csc_idc1; /* 0x8930 */ ++ volatile u_g3_ot_pp_csc_idc2 g3_ot_pp_csc_idc2; /* 0x8934 */ ++ volatile u_g3_ot_pp_csc_odc0 g3_ot_pp_csc_odc0; /* 0x8938 */ ++ volatile u_g3_ot_pp_csc_odc1 g3_ot_pp_csc_odc1; /* 0x893c */ ++ volatile u_g3_ot_pp_csc_odc2 g3_ot_pp_csc_odc2; /* 0x8940 */ ++ volatile u_g3_ot_pp_csc_min_y g3_ot_pp_csc_min_y; /* 0x8944 */ ++ volatile u_g3_ot_pp_csc_min_c g3_ot_pp_csc_min_c; /* 0x8948 */ ++ volatile u_g3_ot_pp_csc_max_y g3_ot_pp_csc_max_y; /* 0x894c */ ++ volatile u_g3_ot_pp_csc_max_c g3_ot_pp_csc_max_c; /* 0x8950 */ ++ volatile u_g3_ot_pp_csc2_coef00 g3_ot_pp_csc2_coef00; /* 0x8954 */ ++ volatile u_g3_ot_pp_csc2_coef01 g3_ot_pp_csc2_coef01; /* 0x8958 */ ++ volatile u_g3_ot_pp_csc2_coef02 g3_ot_pp_csc2_coef02; /* 0x895c */ ++ volatile u_g3_ot_pp_csc2_coef10 g3_ot_pp_csc2_coef10; /* 0x8960 */ ++ volatile u_g3_ot_pp_csc2_coef11 g3_ot_pp_csc2_coef11; /* 0x8964 */ ++ volatile u_g3_ot_pp_csc2_coef12 g3_ot_pp_csc2_coef12; /* 0x8968 */ ++ volatile u_g3_ot_pp_csc2_coef20 g3_ot_pp_csc2_coef20; /* 0x896c */ ++ volatile u_g3_ot_pp_csc2_coef21 g3_ot_pp_csc2_coef21; /* 0x8970 */ ++ volatile u_g3_ot_pp_csc2_coef22 g3_ot_pp_csc2_coef22; /* 0x8974 */ ++ volatile u_g3_ot_pp_csc2_scale g3_ot_pp_csc2_scale; /* 0x8978 */ ++ volatile u_g3_ot_pp_csc2_idc0 g3_ot_pp_csc2_idc0; /* 0x897c */ ++ volatile u_g3_ot_pp_csc2_idc1 g3_ot_pp_csc2_idc1; /* 0x8980 */ ++ volatile u_g3_ot_pp_csc2_idc2 g3_ot_pp_csc2_idc2; /* 0x8984 */ ++ volatile u_g3_ot_pp_csc2_odc0 g3_ot_pp_csc2_odc0; /* 0x8988 */ ++ volatile u_g3_ot_pp_csc2_odc1 g3_ot_pp_csc2_odc1; /* 0x898c */ ++ volatile u_g3_ot_pp_csc2_odc2 g3_ot_pp_csc2_odc2; /* 0x8990 */ ++ volatile u_g3_ot_pp_csc2_min_y g3_ot_pp_csc2_min_y; /* 0x8994 */ ++ volatile u_g3_ot_pp_csc2_min_c g3_ot_pp_csc2_min_c; /* 0x8998 */ ++ volatile u_g3_ot_pp_csc2_max_y g3_ot_pp_csc2_max_y; /* 0x899c */ ++ volatile u_g3_ot_pp_csc2_max_c g3_ot_pp_csc2_max_c; /* 0x89a0 */ ++ volatile unsigned int reserved_78[19]; /* 19:0x89a4~0x89ec */ ++ volatile u_g3_ot_pp_csc_ink_ctrl g3_ot_pp_csc_ink_ctrl; /* 0x89f0 */ ++ volatile u_g3_ot_pp_csc_ink_pos g3_ot_pp_csc_ink_pos; /* 0x89f4 */ ++ volatile unsigned int g3_ot_pp_csc_ink_data; /* 0x89f8 */ ++ volatile unsigned int g3_ot_pp_csc_ink_data2; /* 0x89fc */ ++ volatile u_osb_mute_bk osb_mute_bk; /* 0x8a00 */ ++ volatile u_osb_bk_alpha osb_bk_alpha; /* 0x8a04 */ ++ volatile u_osb_coef_rd_en osb_coef_rd_en; /* 0x8a08 */ ++ volatile unsigned int osb_coef_rd_addr; /* 0x8a0c */ ++ volatile unsigned int reserved_79[892]; /* 892:0x8a10~0x97fc 892 regs */ ++ volatile unsigned int gp0_ctrl; /* 0x9800 */ ++ volatile u_gp0_upd gp0_upd; /* 0x9804 */ ++ volatile u_gp0_ireso gp0_ireso; /* 0x9808 */ ++ volatile unsigned int reserved_80[29]; /* 29:0x980c~0x987c */ ++ volatile u_gp0_lbox_ctrl gp0_lbox_ctrl; /* 0x9880 */ ++ volatile u_gp0_galpha gp0_galpha; /* 0x9884 */ ++ volatile unsigned int gp0_galpha_sum; /* 0x9888 */ ++ volatile u_gp0_dfpos gp0_dfpos; /* 0x988c */ ++ volatile u_gp0_dlpos gp0_dlpos; /* 0x9890 */ ++ volatile u_gp0_vfpos gp0_vfpos; /* 0x9894 */ ++ volatile u_gp0_vlpos gp0_vlpos; /* 0x9898 */ ++ volatile u_gp0_bk gp0_bk; /* 0x989c */ ++ volatile u_gp0_alpha gp0_alpha; /* 0x98a0 */ ++ volatile u_gp0_mute_bk gp0_mute_bk; /* 0x98a4 */ ++ volatile unsigned int reserved_81[22]; /* 22:0x98a8~0x98fc */ ++ volatile u_gp0_csc_idc gp0_csc_idc; /* 0x9900 */ ++ volatile u_gp0_csc_odc gp0_csc_odc; /* 0x9904 */ ++ volatile u_gp0_csc_iodc gp0_csc_iodc; /* 0x9908 */ ++ volatile u_gp0_csc_p0 gp0_csc_p0; /* 0x990c */ ++ volatile u_gp0_csc_p1 gp0_csc_p1; /* 0x9910 */ ++ volatile u_gp0_csc_p2 gp0_csc_p2; /* 0x9914 */ ++ volatile u_gp0_csc_p3 gp0_csc_p3; /* 0x9918 */ ++ volatile u_gp0_csc_p4 gp0_csc_p4; /* 0x991c */ ++ volatile unsigned int reserved_82[1464]; /* 1464:0x9920~0xaffc */ ++ volatile u_wbc_g0_ctrl wbc_g0_ctrl; /* 0xb000 */ ++ volatile u_wbc_g0_upd wbc_g0_upd; /* 0xb004 */ ++ volatile u_wbc_g0_cmp wbc_g0_cmp; /* 0xb008 */ ++ volatile unsigned int reserved_83; /* 0xb00c */ ++ volatile unsigned int wbc_g0_ar_addr; /* 0xb010 */ ++ volatile unsigned int wbc_g0_gb_addr; /* 0xb014 */ ++ volatile u_wbc_g0_stride wbc_g0_stride; /* 0xb018 */ ++ volatile unsigned int wbc_g0_offset; /* 0xb01c */ ++ volatile u_wbc_g0_oreso wbc_g0_oreso; /* 0xb020 */ ++ volatile u_wbc_g0_fcrop wbc_g0_fcrop; /* 0xb024 */ ++ volatile u_wbc_g0_lcrop wbc_g0_lcrop; /* 0xb028 */ ++ volatile unsigned int reserved_84[501]; /* 501:0xb02c~0xb7fc */ ++ volatile u_wbc_gp0_ctrl wbc_gp0_ctrl; /* 0xb800 */ ++ volatile u_wbc_gp0_upd wbc_gp0_upd; /* 0xb804 */ ++ volatile unsigned int reserved_85[2]; /* 2:0xb808~0xb80c */ ++ volatile unsigned int wbc_gp0_yaddr; /* 0xb810 */ ++ volatile unsigned int wbc_gp0_caddr; /* 0xb814 */ ++ volatile u_wbc_gp0_stride wbc_gp0_stride; /* 0xb818 */ ++ volatile unsigned int reserved_86; /* 0xb81c */ ++ volatile u_wbc_gp0_oreso wbc_gp0_oreso; /* 0xb820 */ ++ volatile u_wbc_gp0_fcrop wbc_gp0_fcrop; /* 0xb824 */ ++ volatile u_wbc_gp0_lcrop wbc_gp0_lcrop; /* 0xb828 */ ++ volatile unsigned int reserved_87[53]; /* 53:0xb82c~0xb8fc */ ++ volatile u_wbc_gp0_dither_ctrl wbc_gp0_dither_ctrl; /* 0xb900 */ ++ volatile u_wbc_gp0_dither_coef0 wbc_gp0_dither_coef0; /* 0xb904 */ ++ volatile u_wbc_gp0_dither_coef1 wbc_gp0_dither_coef1; /* 0xb908 */ ++ volatile unsigned int reserved_88[17]; /* 17:0xb90c~0xb94c */ ++ volatile u_wbc_gp0_hpzme wbc_gp0_hpzme; /* 0xb950 */ ++ volatile unsigned int reserved_89[43]; /* 43:0xb954~0xb9fc */ ++ volatile u_wbc_me_ctrl wbc_me_ctrl; /* 0xba00 */ ++ volatile u_wbc_me_upd wbc_me_upd; /* 0xba04 */ ++ volatile u_wbc_me_wlen_sel wbc_me_wlen_sel; /* 0xba08 */ ++ volatile unsigned int reserved_90; /* 0xba0c */ ++ volatile unsigned int wbc_me_yaddr; /* 0xba10 */ ++ volatile unsigned int wbc_me_caddr; /* 0xba14 */ ++ volatile u_wbc_me_stride wbc_me_stride; /* 0xba18 */ ++ volatile unsigned int reserved_91; /* 0xba1c */ ++ volatile u_wbc_me_oreso wbc_me_oreso; /* 0xba20 */ ++ volatile unsigned int reserved_92[2]; /* 2:0xba24~0xba28 */ ++ volatile u_wbc_me_smmu_bypass wbc_me_smmu_bypass; /* 0xba2c */ ++ volatile unsigned int reserved_93[4]; /* 4:0xba30~0xba3c */ ++ volatile u_wbc_me_paraup wbc_me_paraup; /* 0xba40 */ ++ volatile unsigned int reserved_94[3]; /* 3:0xba44~0xba4c */ ++ volatile unsigned int wbc_me_hlcoefad; /* 0xba50 */ ++ volatile unsigned int wbc_me_hccoefad; /* 0xba54 */ ++ volatile unsigned int wbc_me_vlcoefad; /* 0xba58 */ ++ volatile unsigned int wbc_me_vccoefad; /* 0xba5c */ ++ volatile unsigned int reserved_95[36]; /* 36:0xba60~0xbaec */ ++ volatile unsigned int wbc_me_checksum_y; /* 0xbaf0 */ ++ volatile unsigned int wbc_me_checksum_c; /* 0xbaf4 */ ++ volatile unsigned int reserved_96[2]; /* 2:0xbaf8~0xbafc */ ++ volatile u_wbc_me_dither_ctrl wbc_me_dither_ctrl; /* 0xbb00 */ ++ volatile u_wbc_me_dither_coef0 wbc_me_dither_coef0; /* 0xbb04 */ ++ volatile u_wbc_me_dither_coef1 wbc_me_dither_coef1; /* 0xbb08 */ ++ volatile unsigned int reserved_97[109]; /* 109:0xbb0c~0xbcbc */ ++ volatile u_wbc_me_zme_hsp wbc_me_zme_hsp; /* 0xbcc0 */ ++ volatile u_wbc_me_zme_hloffset wbc_me_zme_hloffset; /* 0xbcc4 */ ++ volatile u_wbc_me_zme_hcoffset wbc_me_zme_hcoffset; /* 0xbcc8 */ ++ volatile unsigned int reserved_98[3]; /* 3:0xbccc~0xbcd4 */ ++ volatile u_wbc_me_zme_vsp wbc_me_zme_vsp; /* 0xbcd8 */ ++ volatile u_wbc_me_zme_vsr wbc_me_zme_vsr; /* 0xbcdc */ ++ volatile u_wbc_me_zme_voffset wbc_me_zme_voffset; /* 0xbce0 */ ++ volatile u_wbc_me_zme_vboffset wbc_me_zme_vboffset; /* 0xbce4 */ ++ volatile unsigned int reserved_99[6]; /* 6:0xbce8~0xbcfc */ ++ volatile u_wbc_fi_ctrl wbc_fi_ctrl; /* 0xbd00 */ ++ volatile u_wbc_fi_upd wbc_fi_upd; /* 0xbd04 */ ++ volatile u_wbc_fi_wlen_sel wbc_fi_wlen_sel; /* 0xbd08 */ ++ volatile unsigned int reserved_100; /* 0xbd0c */ ++ volatile unsigned int wbc_fi_yaddr; /* 0xbd10 */ ++ volatile unsigned int wbc_fi_caddr; /* 0xbd14 */ ++ volatile u_wbc_fi_stride wbc_fi_stride; /* 0xbd18 */ ++ volatile unsigned int reserved_101; /* 0xbd1c */ ++ volatile u_wbc_fi_oreso wbc_fi_oreso; /* 0xbd20 */ ++ volatile unsigned int reserved_102[2]; /* 2:0xbd24~0xbd28 */ ++ volatile u_wbc_fi_smmu_bypass wbc_fi_smmu_bypass; /* 0xbd2c */ ++ volatile unsigned int reserved_103[5]; /* 5:0xbd30~0xbd40 */ ++ volatile u_wbc_fi_frame_size wbc_fi_frame_size; /* 0xbd44 */ ++ volatile unsigned int wbc_fi_y_raddr; /* 0xbd48 */ ++ volatile unsigned int wbc_fi_c_raddr; /* 0xbd4c */ ++ volatile unsigned int reserved_104[40]; /* 40:0xbd50~0xbdec */ ++ volatile unsigned int wbc_fi_checksum_y; /* 0xbdf0 */ ++ volatile unsigned int wbc_fi_checksum_c; /* 0xbdf4 */ ++ volatile unsigned int reserved_105[6]; /* 6:0xbdf8~0xbe0c */ ++ volatile u_wbc_fi_hcds wbc_fi_hcds; /* 0xbe10 */ ++ volatile u_wbc_fi_hcds_coef0 wbc_fi_hcds_coef0; /* 0xbe14 */ ++ volatile u_wbc_fi_hcds_coef1 wbc_fi_hcds_coef1; /* 0xbe18 */ ++ volatile unsigned int reserved_106; /* 0xbe1c */ ++ volatile u_wbc_fi_cmp_mb wbc_fi_cmp_mb; /* 0xbe20 */ ++ volatile u_wbc_fi_cmp_max_min wbc_fi_cmp_max_min; /* 0xbe24 */ ++ volatile u_wbc_fi_cmp_adj_thr wbc_fi_cmp_adj_thr; /* 0xbe28 */ ++ volatile u_wbc_fi_cmp_big_grad wbc_fi_cmp_big_grad; /* 0xbe2c */ ++ volatile u_wbc_fi_cmp_blk wbc_fi_cmp_blk; /* 0xbe30 */ ++ volatile u_wbc_fi_cmp_graphic_judge wbc_fi_cmp_graphic_judge; /* 0xbe34 */ ++ volatile u_wbc_fi_cmp_rc wbc_fi_cmp_rc; /* 0xbe38 */ ++ volatile u_wbc_fi_cmp_frame_size wbc_fi_cmp_frame_size; /* 0xbe3c */ ++ volatile unsigned int reserved_107[48]; /* 48:0xbe40~0xbefc */ ++ volatile u_wbc_cmp_glb_info wbc_cmp_glb_info; /* 0xbf00 */ ++ volatile u_wbc_cmp_framesize wbc_cmp_framesize; /* 0xbf04 */ ++ volatile u_wbc_cmp_rc_cfg0 wbc_cmp_rc_cfg0; /* 0xbf08 */ ++ volatile u_wbc_cmp_rc_cfg2 wbc_cmp_rc_cfg2; /* 0xbf0c */ ++ volatile u_wbc_cmp_rc_cfg3 wbc_cmp_rc_cfg3; /* 0xbf10 */ ++ volatile u_wbc_cmp_rc_cfg4 wbc_cmp_rc_cfg4; /* 0xbf14 */ ++ volatile u_wbc_cmp_rc_cfg5 wbc_cmp_rc_cfg5; /* 0xbf18 */ ++ volatile u_wbc_cmp_rc_cfg6 wbc_cmp_rc_cfg6; /* 0xbf1c */ ++ volatile u_wbc_cmp_rc_cfg7 wbc_cmp_rc_cfg7; /* 0xbf20 */ ++ volatile u_wbc_cmp_rc_cfg8 wbc_cmp_rc_cfg8; /* 0xbf24 */ ++ volatile u_wbc_cmp_rc_cfg10 wbc_cmp_rc_cfg10; /* 0xbf28 */ ++ volatile u_wbc_cmp_outsize0 wbc_cmp_outsize0; /* 0xbf2c */ ++ volatile unsigned int wbc_cmp_dbg_reg0; /* 0xbf30 */ ++ volatile u_wbc_cmp_max_row wbc_cmp_max_row; /* 0xbf34 */ ++ volatile u_wbc_bmp_ctrl wbc_bmp_ctrl; /* 0xbf38 */ ++ volatile u_wbc_bmp_upd wbc_bmp_upd; /* 0xbf3c */ ++ volatile unsigned int wbc_bmp_yaddr; /* 0xbf40 */ ++ volatile unsigned int reserved_108[23]; /* 23:0xbf44~0xbf9c */ ++ volatile u_wbc_bmp_oreso wbc_bmp_oreso; /* 0xbfa0 */ ++ volatile u_wbc_bmp_sum wbc_bmp_sum; /* 0xbfa4 */ ++ volatile unsigned int reserved_109[18]; /* 18:0xbfa8~0xbfec */ ++ volatile unsigned int wbc_bmp_checksum_y; /* 0xbff0 */ ++ volatile unsigned int wbc_bmp_checksum_c; /* 0xbff4 */ ++ volatile unsigned int reserved_110[2]; /* 2:0xbff8~0xbffc */ ++ volatile u_wbc_dhd0_ctrl wbc_dhd0_ctrl; /* 0xc000 */ ++ volatile u_wbc_dhd0_upd wbc_dhd0_upd; /* 0xc004 */ ++ volatile u_wbc_dhd0_oreso wbc_dhd0_oreso; /* 0xc008 */ ++ volatile unsigned int reserved_111[29]; /* 29:0xc00c~0xc07c */ ++ volatile u_wd_hpzme_ctrl wd_hpzme_ctrl; /* 0xc080 */ ++ volatile u_wd_hpzmecoef01 wd_hpzmecoef01; /* 0xc084 */ ++ volatile u_wd_hpzmecoef23 wd_hpzmecoef23; /* 0xc088 */ ++ volatile u_wd_hpzmecoef45 wd_hpzmecoef45; /* 0xc08c */ ++ volatile u_wd_hpzmecoef67 wd_hpzmecoef67; /* 0xc090 */ ++ volatile unsigned int reserved_112[91]; /* 91:0xc094~0xc1fc */ ++ volatile u_wd_hcds_ctrl wd_hcds_ctrl; /* 0xc200 */ ++ volatile u_wd_hcdscoef01 wd_hcdscoef01; /* 0xc204 */ ++ volatile u_wd_hcdscoef23 wd_hcdscoef23; /* 0xc208 */ ++ volatile u_wd_hcdscoef45 wd_hcdscoef45; /* 0xc20c */ ++ volatile u_wd_hcdscoef67 wd_hcdscoef67; /* 0xc210 */ ++ volatile unsigned int reserved_113[27]; /* 27:0xc214~0xc27c */ ++ volatile u_dither_ctrl dither_ctrl; /* 0xc280 */ ++ volatile u_dither_sed_y0 dither_sed_y0; /* 0xc284 */ ++ volatile u_dither_sed_u0 dither_sed_u0; /* 0xc288 */ ++ volatile u_dither_sed_v0 dither_sed_v0; /* 0xc28c */ ++ volatile u_dither_sed_w0 dither_sed_w0; /* 0xc290 */ ++ volatile u_dither_sed_y1 dither_sed_y1; /* 0xc294 */ ++ volatile u_dither_sed_u1 dither_sed_u1; /* 0xc298 */ ++ volatile u_dither_sed_v1 dither_sed_v1; /* 0xc29c */ ++ volatile u_dither_sed_w1 dither_sed_w1; /* 0xc2a0 */ ++ volatile u_dither_sed_y2 dither_sed_y2; /* 0xc2a4 */ ++ volatile u_dither_sed_u2 dither_sed_u2; /* 0xc2a8 */ ++ volatile u_dither_sed_v2 dither_sed_v2; /* 0xc2ac */ ++ volatile u_dither_sed_w2 dither_sed_w2; /* 0xc2b0 */ ++ volatile u_dither_sed_y3 dither_sed_y3; /* 0xc2b4 */ ++ volatile u_dither_sed_u3 dither_sed_u3; /* 0xc2b8 */ ++ volatile u_dither_sed_v3 dither_sed_v3; /* 0xc2bc */ ++ volatile u_dither_sed_w3 dither_sed_w3; /* 0xc2c0 */ ++ volatile u_dither_thr dither_thr; /* 0xc2c4 */ ++ volatile unsigned int reserved_114[14]; /* 14:0xc2c8~0xc2fc */ ++ volatile u_wd_zme_hinfo wd_zme_hinfo; /* 0xc300 */ ++ volatile u_wd_zme_hsp wd_zme_hsp; /* 0xc304 */ ++ volatile u_wd_zme_hloffset wd_zme_hloffset; /* 0xc308 */ ++ volatile u_wd_zme_hcoffset wd_zme_hcoffset; /* 0xc30c */ ++ volatile unsigned int reserved_115[5]; /* 5:0xc310~0xc320 */ ++ volatile u_wd_zme_hcoef_ren wd_zme_hcoef_ren; /* 0xc324 */ ++ volatile u_wd_zme_hcoef_rdata wd_zme_hcoef_rdata; /* 0xc328 */ ++ volatile u_wd_zme_hdraw wd_zme_hdraw; /* 0xc32c */ ++ volatile u_wd_zme_hratio wd_zme_hratio; /* 0xc330 */ ++ volatile unsigned int reserved_116[51]; /* 51:0xc334~0xc3fc */ ++ volatile u_wd_zme_vinfo wd_zme_vinfo; /* 0xc400 */ ++ volatile u_wd_zme_vsp wd_zme_vsp; /* 0xc404 */ ++ volatile u_wd_zme_voffset wd_zme_voffset; /* 0xc408 */ ++ volatile u_wd_zme_vboffset wd_zme_vboffset; /* 0xc40c */ ++ volatile unsigned int reserved_117[5]; /* 5:0xc410~0xc420 */ ++ volatile u_wd_zme_vcoef_ren wd_zme_vcoef_ren; /* 0xc424 */ ++ volatile u_wd_zme_vcoef_rdata wd_zme_vcoef_rdata; /* 0xc428 */ ++ volatile u_wd_zme_vdraw wd_zme_vdraw; /* 0xc42c */ ++ volatile u_wd_zme_vratio wd_zme_vratio; /* 0xc430 */ ++ volatile unsigned int reserved_118[755]; /* 755:0xc434~0xcffc */ ++ volatile u_dhd0_ctrl dhd0_ctrl; /* 0xd000 */ ++ volatile u_dhd0_vsync1 dhd0_vsync1; /* 0xd004 */ ++ volatile u_dhd0_vsync2 dhd0_vsync2; /* 0xd008 */ ++ volatile u_dhd0_hsync1 dhd0_hsync1; /* 0xd00c */ ++ volatile u_dhd0_hsync2 dhd0_hsync2; /* 0xd010 */ ++ volatile u_dhd0_vplus1 dhd0_vplus1; /* 0xd014 */ ++ volatile u_dhd0_vplus2 dhd0_vplus2; /* 0xd018 */ ++ volatile u_dhd0_pwr dhd0_pwr; /* 0xd01c */ ++ volatile u_dhd0_vtthd3 dhd0_vtthd3; /* 0xd020 */ ++ volatile u_dhd0_vtthd dhd0_vtthd; /* 0xd024 */ ++ volatile u_dhd0_parathd dhd0_parathd; /* 0xd028 */ ++ volatile u_dhd0_precharge_thd dhd0_precharge_thd; /* 0xd02c */ ++ volatile u_dhd0_start_pos dhd0_start_pos; /* 0xd030 */ ++ volatile u_dhd0_start_pos1 dhd0_start_pos1; /* 0xd034 */ ++ volatile u_dhd0_paraup dhd0_paraup; /* 0xd038 */ ++ volatile u_dhd0_sync_inv dhd0_sync_inv; /* 0xd03c */ ++ volatile u_dhd0_clk_dv_ctrl dhd0_clk_dv_ctrl; /* 0xd040 */ ++ volatile u_dhd0_rgb_fix_ctrl dhd0_rgb_fix_ctrl; /* 0xd044 */ ++ volatile u_dhd0_lockcfg dhd0_lockcfg; /* 0xd048 */ ++ volatile unsigned int dhd0_cap_frm_cnt; /* 0xd04c */ ++ volatile unsigned int dhd0_vdp_frm_cnt; /* 0xd050 */ ++ volatile unsigned int dhd0_vsync_cap_vdp_cnt; /* 0xd054 */ ++ volatile unsigned int dhd0_intf_chksum_y; /* 0xd058 */ ++ volatile unsigned int dhd0_intf_chksum_u; /* 0xd05c */ ++ volatile unsigned int dhd0_intf_chksum_v; /* 0xd060 */ ++ volatile unsigned int dhd0_intf1_chksum_y; /* 0xd064 */ ++ volatile unsigned int dhd0_intf1_chksum_u; /* 0xd068 */ ++ volatile unsigned int dhd0_intf1_chksum_v; /* 0xd06c */ ++ volatile u_dhd0_intf_chksum_high1 dhd0_intf_chksum_high1; /* 0xd070 */ ++ volatile u_dhd0_intf_chksum_high2 dhd0_intf_chksum_high2; /* 0xd074 */ ++ volatile unsigned int reserved_119[3]; /* 3:0xd078~0xd080 */ ++ volatile unsigned int dhd0_afifo_pre_thd; /* 0xd084 */ ++ volatile u_dhd0_state dhd0_state; /* 0xd088 */ ++ volatile u_dhd0_uf_state dhd0_uf_state; /* 0xd08c */ ++ volatile u_vo_mux vo_mux; /* 0xd090 */ ++ volatile u_vo_mux_sync vo_mux_sync; /* 0xd094 */ ++ volatile u_vo_mux_data vo_mux_data; /* 0xd098 */ ++ volatile unsigned int reserved_120; /* 0xd09c */ ++ volatile u_dhd0_vsync_te_state dhd0_vsync_te_state; /* 0xd0a0 */ ++ volatile u_dhd0_vsync_te_state1 dhd0_vsync_te_state1; /* 0xd0a4 */ ++ volatile unsigned int reserved_121[6]; /* 6:0xd0a8~0xd0bc */ ++ volatile u_dhd0_ccdoimgmod dhd0_ccdoimgmod; /* 0xd0c0 */ ++ volatile u_dhd0_ccdoposmskh dhd0_ccdoposmskh; /* 0xd0c4 */ ++ volatile u_dhd0_ccdoposmskl dhd0_ccdoposmskl; /* 0xd0c8 */ ++ volatile unsigned int reserved_122; /* 0xd0cc */ ++ volatile u_dhd0_dacdet1 dhd0_dacdet1; /* 0xd0d0 */ ++ volatile u_dhd0_dacdet2 dhd0_dacdet2; /* 0xd0d4 */ ++ volatile unsigned int reserved_123[2]; /* 2:0xd0d8~0xd0dc */ ++ volatile u_dhd0_ccd_info1 dhd0_ccd_info1; /* 0xd0e0 */ ++ volatile u_dhd0_ccd_info2 dhd0_ccd_info2; /* 0xd0e4 */ ++ volatile u_dhd0_ccd_info3 dhd0_ccd_info3; /* 0xd0e8 */ ++ volatile unsigned int reserved_124[5]; /* 5:0xd0ec~0xd0fc */ ++ volatile u_intf_hdmi_ctrl intf_hdmi_ctrl; /* 0xd100 */ ++ volatile u_intf_hdmi_upd intf_hdmi_upd; /* 0xd104 */ ++ volatile u_intf_hdmi_sync_inv intf_hdmi_sync_inv; /* 0xd108 */ ++ volatile unsigned int reserved_125; /* 0xd10c */ ++ volatile unsigned int hdmi_intf_chksum_y; /* 0xd110 */ ++ volatile unsigned int hdmi_intf_chksum_u; /* 0xd114 */ ++ volatile unsigned int hdmi_intf_chksum_v; /* 0xd118 */ ++ volatile u_hdmi_intf_chksum_high hdmi_intf_chksum_high; /* 0xd11c */ ++ volatile unsigned int hdmi_intf1_chksum_y; /* 0xd120 */ ++ volatile unsigned int hdmi_intf1_chksum_u; /* 0xd124 */ ++ volatile unsigned int hdmi_intf1_chksum_v; /* 0xd128 */ ++ volatile u_hdmi_intf1_chksum_high hdmi_intf1_chksum_high; /* 0xd12c */ ++ volatile unsigned int reserved_126[8]; /* 8:0xd130~0xd14c */ ++ volatile u_hdmi_hfir_coef0 hdmi_hfir_coef0; /* 0xd150 */ ++ volatile u_hdmi_hfir_coef1 hdmi_hfir_coef1; /* 0xd154 */ ++ volatile u_hdmi_hfir_coef2 hdmi_hfir_coef2; /* 0xd158 */ ++ volatile u_hdmi_hfir_coef3 hdmi_hfir_coef3; /* 0xd15c */ ++ volatile u_hdmi_csc_idc hdmi_csc_idc; /* 0xd160 */ ++ volatile u_hdmi_csc_odc hdmi_csc_odc; /* 0xd164 */ ++ volatile u_hdmi_csc_iodc hdmi_csc_iodc; /* 0xd168 */ ++ volatile u_hdmi_csc_p0 hdmi_csc_p0; /* 0xd16c */ ++ volatile u_hdmi_csc_p1 hdmi_csc_p1; /* 0xd170 */ ++ volatile u_hdmi_csc_p2 hdmi_csc_p2; /* 0xd174 */ ++ volatile u_hdmi_csc_p3 hdmi_csc_p3; /* 0xd178 */ ++ volatile u_hdmi_csc_p4 hdmi_csc_p4; /* 0xd17c */ ++ volatile u_intf_mipi_ctrl intf_mipi_ctrl; /* 0xd180 */ ++ volatile u_intf_mipi_upd intf_mipi_upd; /* 0xd184 */ ++ volatile u_intf_mipi_sync_inv intf_mipi_sync_inv; /* 0xd188 */ ++ volatile unsigned int reserved_127; /* 0xd18c */ ++ volatile unsigned int mipi_intf_chksum_y; /* 0xd190 */ ++ volatile unsigned int mipi_intf_chksum_u; /* 0xd194 */ ++ volatile unsigned int mipi_intf_chksum_v; /* 0xd198 */ ++ volatile u_mipi_intf_chksum_high mipi_intf_chksum_high; /* 0xd19c */ ++ volatile unsigned int mipi_intf1_chksum_y; /* 0xd1a0 */ ++ volatile unsigned int mipi_intf1_chksum_u; /* 0xd1a4 */ ++ volatile unsigned int mipi_intf1_chksum_v; /* 0xd1a8 */ ++ volatile u_mipi_intf1_chksum_high mipi_intf1_chksum_high; /* 0xd1ac */ ++ volatile unsigned int reserved_128[8]; /* 8:0xd1b0~0xd1cc */ ++ volatile u_mipi_hfir_coef0 mipi_hfir_coef0; /* 0xd1d0 */ ++ volatile u_mipi_hfir_coef1 mipi_hfir_coef1; /* 0xd1d4 */ ++ volatile u_mipi_hfir_coef2 mipi_hfir_coef2; /* 0xd1d8 */ ++ volatile u_mipi_hfir_coef3 mipi_hfir_coef3; /* 0xd1dc */ ++ volatile unsigned int reserved_129[8]; /* 8:0xd1e0~0xd1fc */ ++ volatile u_intf_bt_ctrl intf_bt_ctrl; /* 0xd200 */ ++ volatile u_intf_bt_upd intf_bt_upd; /* 0xd204 */ ++ volatile u_intf_bt_sync_inv intf_bt_sync_inv; /* 0xd208 */ ++ volatile unsigned int reserved_130; /* 0xd20c */ ++ volatile u_bt_clip0_l bt_clip0_l; /* 0xd210 */ ++ volatile u_bt_clip0_h bt_clip0_h; /* 0xd214 */ ++ volatile unsigned int reserved_131[26]; /* 26:0xd218~0xd27c */ ++ volatile u_bt_dither_ctrl bt_dither_ctrl; /* 0xd280 */ ++ volatile u_bt_dither_sed_y0 bt_dither_sed_y0; /* 0xd284 */ ++ volatile u_bt_dither_sed_u0 bt_dither_sed_u0; /* 0xd288 */ ++ volatile u_bt_dither_sed_v0 bt_dither_sed_v0; /* 0xd28c */ ++ volatile u_bt_dither_sed_w0 bt_dither_sed_w0; /* 0xd290 */ ++ volatile u_bt_dither_sed_y1 bt_dither_sed_y1; /* 0xd294 */ ++ volatile u_bt_dither_sed_u1 bt_dither_sed_u1; /* 0xd298 */ ++ volatile u_bt_dither_sed_v1 bt_dither_sed_v1; /* 0xd29c */ ++ volatile u_bt_dither_sed_w1 bt_dither_sed_w1; /* 0xd2a0 */ ++ volatile u_bt_dither_sed_y2 bt_dither_sed_y2; /* 0xd2a4 */ ++ volatile u_bt_dither_sed_u2 bt_dither_sed_u2; /* 0xd2a8 */ ++ volatile u_bt_dither_sed_v2 bt_dither_sed_v2; /* 0xd2ac */ ++ volatile u_bt_dither_sed_w2 bt_dither_sed_w2; /* 0xd2b0 */ ++ volatile u_bt_dither_sed_y3 bt_dither_sed_y3; /* 0xd2b4 */ ++ volatile u_bt_dither_sed_u3 bt_dither_sed_u3; /* 0xd2b8 */ ++ volatile u_bt_dither_sed_v3 bt_dither_sed_v3; /* 0xd2bc */ ++ volatile u_bt_dither_sed_w3 bt_dither_sed_w3; /* 0xd2c0 */ ++ volatile u_bt_dither_thr bt_dither_thr; /* 0xd2c4 */ ++ volatile unsigned int reserved_132[10]; /* 10:0xd2c8~0xd2ec */ ++ volatile unsigned int bt_intf_chksum_y; /* 0xd2f0 */ ++ volatile unsigned int bt_intf_chksum_u; /* 0xd2f4 */ ++ volatile unsigned int bt_intf_chksum_v; /* 0xd2f8 */ ++ volatile unsigned int reserved_133; /* 0xd2fc */ ++ volatile u_intf_lcd_ctrl intf_lcd_ctrl; /* 0xd300 */ ++ volatile u_intf_lcd_upd intf_lcd_upd; /* 0xd304 */ ++ volatile u_intf_lcd_sync_inv intf_lcd_sync_inv; /* 0xd308 */ ++ volatile unsigned int reserved_134[29]; /* 29:0xd30c~0xd37c */ ++ volatile u_lcd_dither_ctrl lcd_dither_ctrl; /* 0xd380 */ ++ volatile u_lcd_dither_sed_y0 lcd_dither_sed_y0; /* 0xd384 */ ++ volatile u_lcd_dither_sed_u0 lcd_dither_sed_u0; /* 0xd388 */ ++ volatile u_lcd_dither_sed_v0 lcd_dither_sed_v0; /* 0xd38c */ ++ volatile u_lcd_dither_sed_w0 lcd_dither_sed_w0; /* 0xd390 */ ++ volatile u_lcd_dither_sed_y1 lcd_dither_sed_y1; /* 0xd394 */ ++ volatile u_lcd_dither_sed_u1 lcd_dither_sed_u1; /* 0xd398 */ ++ volatile u_lcd_dither_sed_v1 lcd_dither_sed_v1; /* 0xd39c */ ++ volatile u_lcd_dither_sed_w1 lcd_dither_sed_w1; /* 0xd3a0 */ ++ volatile u_lcd_dither_sed_y2 lcd_dither_sed_y2; /* 0xd3a4 */ ++ volatile u_lcd_dither_sed_u2 lcd_dither_sed_u2; /* 0xd3a8 */ ++ volatile u_lcd_dither_sed_v2 lcd_dither_sed_v2; /* 0xd3ac */ ++ volatile u_lcd_dither_sed_w2 lcd_dither_sed_w2; /* 0xd3b0 */ ++ volatile u_lcd_dither_sed_y3 lcd_dither_sed_y3; /* 0xd3b4 */ ++ volatile u_lcd_dither_sed_u3 lcd_dither_sed_u3; /* 0xd3b8 */ ++ volatile u_lcd_dither_sed_v3 lcd_dither_sed_v3; /* 0xd3bc */ ++ volatile u_lcd_dither_sed_w3 lcd_dither_sed_w3; /* 0xd3c0 */ ++ volatile u_lcd_dither_thr lcd_dither_thr; /* 0xd3c4 */ ++ volatile unsigned int reserved_135[10]; /* 10:0xd3c8~0xd3ec */ ++ volatile unsigned int lcd_intf_chksum_y; /* 0xd3f0 */ ++ volatile unsigned int lcd_intf_chksum_u; /* 0xd3f4 */ ++ volatile unsigned int lcd_intf_chksum_v; /* 0xd3f8 */ ++ volatile unsigned int reserved_136; /* 0xd3fc */ ++ volatile u_intf_hdmi1_ctrl intf_hdmi1_ctrl; /* 0xd400 */ ++ volatile u_intf_hdmi1_upd intf_hdmi1_upd; /* 0xd404 */ ++ volatile u_intf_hdmi1_sync_inv intf_hdmi1_sync_inv; /* 0xd408 */ ++ volatile unsigned int reserved_137; /* 0xd40c */ ++ volatile unsigned int hdmi1_intf_chksum_y; /* 0xd410 */ ++ volatile unsigned int hdmi1_intf_chksum_u; /* 0xd414 */ ++ volatile unsigned int hdmi1_intf_chksum_v; /* 0xd418 */ ++ volatile u_hdmi1_intf_chksum_high hdmi1_intf_chksum_high; /* 0xd41c */ ++ volatile unsigned int hdmi1_intf1_chksum_y; /* 0xd420 */ ++ volatile unsigned int hdmi1_intf1_chksum_u; /* 0xd424 */ ++ volatile unsigned int hdmi1_intf1_chksum_v; /* 0xd428 */ ++ volatile u_hdmi1_intf1_chksum_high hdmi1_intf1_chksum_high; /* 0xd42c */ ++ volatile unsigned int reserved_138[8]; /* 8:0xd430~0xd44c */ ++ volatile u_hdmi1_hfir_coef0 hdmi1_hfir_coef0; /* 0xd450 */ ++ volatile u_hdmi1_hfir_coef1 hdmi1_hfir_coef1; /* 0xd454 */ ++ volatile u_hdmi1_hfir_coef2 hdmi1_hfir_coef2; /* 0xd458 */ ++ volatile u_hdmi1_hfir_coef3 hdmi1_hfir_coef3; /* 0xd45c */ ++ volatile unsigned int reserved_139[40]; /* 40:0xd460~0xd4fc */ ++ volatile u_intf_vga_ctrl intf_vga_ctrl; /* 0xd500 */ ++ volatile u_intf_vga_upd intf_vga_upd; /* 0xd504 */ ++ volatile u_intf_vga_sync_inv intf_vga_sync_inv; /* 0xd508 */ ++ volatile unsigned int reserved_140[5]; /* 5:0xd50c~0xd51c */ ++ volatile u_vga_csc_idc vga_csc_idc; /* 0xd520 */ ++ volatile u_vga_csc_odc vga_csc_odc; /* 0xd524 */ ++ volatile u_vga_csc_iodc vga_csc_iodc; /* 0xd528 */ ++ volatile u_vga_csc_p0 vga_csc_p0; /* 0xd52c */ ++ volatile u_vga_csc_p1 vga_csc_p1; /* 0xd530 */ ++ volatile u_vga_csc_p2 vga_csc_p2; /* 0xd534 */ ++ volatile u_vga_csc_p3 vga_csc_p3; /* 0xd538 */ ++ volatile u_vga_csc_p4 vga_csc_p4; /* 0xd53c */ ++ volatile u_vga_hspcfg0 vga_hspcfg0; /* 0xd540 */ ++ volatile u_vga_hspcfg1 vga_hspcfg1; /* 0xd544 */ ++ volatile unsigned int reserved_141[3]; /* 3:0xd548~0xd550 */ ++ volatile u_vga_hspcfg5 vga_hspcfg5; /* 0xd554 */ ++ volatile u_vga_hspcfg6 vga_hspcfg6; /* 0xd558 */ ++ volatile u_vga_hspcfg7 vga_hspcfg7; /* 0xd55c */ ++ volatile u_vga_hspcfg8 vga_hspcfg8; /* 0xd560 */ ++ volatile unsigned int reserved_142[3]; /* 3:0xd564~0xd56c */ ++ volatile u_vga_hspcfg12 vga_hspcfg12; /* 0xd570 */ ++ volatile u_vga_hspcfg13 vga_hspcfg13; /* 0xd574 */ ++ volatile u_vga_hspcfg14 vga_hspcfg14; /* 0xd578 */ ++ volatile u_vga_hspcfg15 vga_hspcfg15; /* 0xd57c */ ++ volatile unsigned int reserved_143[28]; /* 28:0xd580~0xd5ec */ ++ volatile unsigned int vga_intf_chksum_y; /* 0xd5f0 */ ++ volatile unsigned int vga_intf_chksum_u; /* 0xd5f4 */ ++ volatile unsigned int vga_intf_chksum_v; /* 0xd5f8 */ ++ volatile unsigned int reserved_144; /* 0xd5fc */ ++ volatile u_intf_date_ctrl intf_date_ctrl; /* 0xd600 */ ++ volatile u_intf_date_upd intf_date_upd; /* 0xd604 */ ++ volatile u_intf_date_sync_inv intf_date_sync_inv; /* 0xd608 */ ++ volatile unsigned int reserved_145; /* 0xd60c */ ++ volatile u_date_clip0_l date_clip0_l; /* 0xd610 */ ++ volatile u_date_clip0_h date_clip0_h; /* 0xd614 */ ++ volatile unsigned int reserved_146[58]; /* 58:0xd618~0xd6fc */ ++ volatile u_intf0_dither_ctrl intf0_dither_ctrl; /* 0xd700 */ ++ volatile u_intf0_dither_sed_y0 intf0_dither_sed_y0; /* 0xd704 */ ++ volatile u_intf0_dither_sed_u0 intf0_dither_sed_u0; /* 0xd708 */ ++ volatile u_intf0_dither_sed_v0 intf0_dither_sed_v0; /* 0xd70c */ ++ volatile u_intf0_dither_sed_w0 intf0_dither_sed_w0; /* 0xd710 */ ++ volatile u_intf0_dither_sed_y1 intf0_dither_sed_y1; /* 0xd714 */ ++ volatile u_intf0_dither_sed_u1 intf0_dither_sed_u1; /* 0xd718 */ ++ volatile u_intf0_dither_sed_v1 intf0_dither_sed_v1; /* 0xd71c */ ++ volatile u_intf0_dither_sed_w1 intf0_dither_sed_w1; /* 0xd720 */ ++ volatile u_intf0_dither_sed_y2 intf0_dither_sed_y2; /* 0xd724 */ ++ volatile u_intf0_dither_sed_u2 intf0_dither_sed_u2; /* 0xd728 */ ++ volatile u_intf0_dither_sed_v2 intf0_dither_sed_v2; /* 0xd72c */ ++ volatile u_intf0_dither_sed_w2 intf0_dither_sed_w2; /* 0xd730 */ ++ volatile u_intf0_dither_sed_y3 intf0_dither_sed_y3; /* 0xd734 */ ++ volatile u_intf0_dither_sed_u3 intf0_dither_sed_u3; /* 0xd738 */ ++ volatile u_intf0_dither_sed_v3 intf0_dither_sed_v3; /* 0xd73c */ ++ volatile u_intf0_dither_sed_w3 intf0_dither_sed_w3; /* 0xd740 */ ++ volatile u_intf0_dither_thr intf0_dither_thr; /* 0xd744 */ ++ volatile unsigned int reserved_147[558]; /* 558:0xd748~0xdffc */ ++ volatile u_dhd1_ctrl dhd1_ctrl; /* 0xe000 */ ++ volatile u_dhd1_vsync1 dhd1_vsync1; /* 0xe004 */ ++ volatile u_dhd1_vsync2 dhd1_vsync2; /* 0xe008 */ ++ volatile u_dhd1_hsync1 dhd1_hsync1; /* 0xe00c */ ++ volatile u_dhd1_hsync2 dhd1_hsync2; /* 0xe010 */ ++ volatile u_dhd1_vplus1 dhd1_vplus1; /* 0xe014 */ ++ volatile u_dhd1_vplus2 dhd1_vplus2; /* 0xe018 */ ++ volatile u_dhd1_pwr dhd1_pwr; /* 0xe01c */ ++ volatile u_dhd1_vtthd3 dhd1_vtthd3; /* 0xe020 */ ++ volatile u_dhd1_vtthd dhd1_vtthd; /* 0xe024 */ ++ volatile u_dhd1_parathd dhd1_parathd; /* 0xe028 */ ++ volatile u_dhd1_precharge_thd dhd1_precharge_thd; /* 0xe02c */ ++ volatile u_dhd1_start_pos dhd1_start_pos; /* 0xe030 */ ++ volatile u_dhd1_start_pos1 dhd1_start_pos1; /* 0xe034 */ ++ volatile u_dhd1_paraup dhd1_paraup; /* 0xe038 */ ++ volatile u_dhd1_sync_inv dhd1_sync_inv; /* 0xe03c */ ++ volatile u_dhd1_clk_dv_ctrl dhd1_clk_dv_ctrl; /* 0xe040 */ ++ volatile u_dhd1_rgb_fix_ctrl dhd1_rgb_fix_ctrl; /* 0xe044 */ ++ volatile u_dhd1_lockcfg dhd1_lockcfg; /* 0xe048 */ ++ volatile unsigned int dhd1_cap_frm_cnt; /* 0xe04c */ ++ volatile unsigned int dhd1_vdp_frm_cnt; /* 0xe050 */ ++ volatile unsigned int dhd1_vsync_cap_vdp_cnt; /* 0xe054 */ ++ volatile unsigned int dhd1_intf_chksum_y; /* 0xe058 */ ++ volatile unsigned int dhd1_intf_chksum_u; /* 0xe05c */ ++ volatile unsigned int dhd1_intf_chksum_v; /* 0xe060 */ ++ volatile unsigned int dhd1_intf1_chksum_y; /* 0xe064 */ ++ volatile unsigned int dhd1_intf1_chksum_u; /* 0xe068 */ ++ volatile unsigned int dhd1_intf1_chksum_v; /* 0xe06c */ ++ volatile u_dhd1_intf_chksum_high1 dhd1_intf_chksum_high1; /* 0xe070 */ ++ volatile u_dhd1_intf_chksum_high2 dhd1_intf_chksum_high2; /* 0xe074 */ ++ volatile unsigned int reserved_148[3]; /* 3:0xe078~0xe080 */ ++ volatile unsigned int dhd1_afifo_pre_thd; /* 0xe084 */ ++ volatile u_dhd1_state dhd1_state; /* 0xe088 */ ++ volatile u_dhd1_uf_state dhd1_uf_state; /* 0xe08c */ ++ volatile unsigned int reserved_149[4]; /* 4:0xe090~0xe09c */ ++ volatile u_dhd1_vsync_te_state dhd1_vsync_te_state; /* 0xe0a0 */ ++ volatile u_dhd1_vsync_te_state1 dhd1_vsync_te_state1; /* 0xe0a4 */ ++ volatile unsigned int reserved_150[406]; /* 406:0xe0a8~0xe6fc */ ++ volatile u_intf1_dither_ctrl intf1_dither_ctrl; /* 0xe700 */ ++ volatile u_intf1_dither_sed_y0 intf1_dither_sed_y0; /* 0xe704 */ ++ volatile u_intf1_dither_sed_u0 intf1_dither_sed_u0; /* 0xe708 */ ++ volatile u_intf1_dither_sed_v0 intf1_dither_sed_v0; /* 0xe70c */ ++ volatile u_intf1_dither_sed_w0 intf1_dither_sed_w0; /* 0xe710 */ ++ volatile u_intf1_dither_sed_y1 intf1_dither_sed_y1; /* 0xe714 */ ++ volatile u_intf1_dither_sed_u1 intf1_dither_sed_u1; /* 0xe718 */ ++ volatile u_intf1_dither_sed_v1 intf1_dither_sed_v1; /* 0xe71c */ ++ volatile u_intf1_dither_sed_w1 intf1_dither_sed_w1; /* 0xe720 */ ++ volatile u_intf1_dither_sed_y2 intf1_dither_sed_y2; /* 0xe724 */ ++ volatile u_intf1_dither_sed_u2 intf1_dither_sed_u2; /* 0xe728 */ ++ volatile u_intf1_dither_sed_v2 intf1_dither_sed_v2; /* 0xe72c */ ++ volatile u_intf1_dither_sed_w2 intf1_dither_sed_w2; /* 0xe730 */ ++ volatile u_intf1_dither_sed_y3 intf1_dither_sed_y3; /* 0xe734 */ ++ volatile u_intf1_dither_sed_u3 intf1_dither_sed_u3; /* 0xe738 */ ++ volatile u_intf1_dither_sed_v3 intf1_dither_sed_v3; /* 0xe73c */ ++ volatile u_intf1_dither_sed_w3 intf1_dither_sed_w3; /* 0xe740 */ ++ volatile u_intf1_dither_thr intf1_dither_thr; /* 0xe744 */ ++ volatile unsigned int reserved_151[558]; /* 558:0xe748~0xeffc */ ++ volatile u_dhd2_ctrl dhd2_ctrl; /* 0xf000 */ ++ volatile u_dhd2_vsync1 dhd2_vsync1; /* 0xf004 */ ++ volatile u_dhd2_vsync2 dhd2_vsync2; /* 0xf008 */ ++ volatile u_dhd2_hsync1 dhd2_hsync1; /* 0xf00c */ ++ volatile u_dhd2_hsync2 dhd2_hsync2; /* 0xf010 */ ++ volatile u_dhd2_vplus1 dhd2_vplus1; /* 0xf014 */ ++ volatile u_dhd2_vplus2 dhd2_vplus2; /* 0xf018 */ ++ volatile u_dhd2_pwr dhd2_pwr; /* 0xf01c */ ++ volatile u_dhd2_vtthd3 dhd2_vtthd3; /* 0xf020 */ ++ volatile u_dhd2_vtthd dhd2_vtthd; /* 0xf024 */ ++ volatile u_dhd2_parathd dhd2_parathd; /* 0xf028 */ ++ volatile u_dhd2_precharge_thd dhd2_precharge_thd; /* 0xf02c */ ++ volatile u_dhd2_start_pos dhd2_start_pos; /* 0xf030 */ ++ volatile u_dhd2_start_pos1 dhd2_start_pos1; /* 0xf034 */ ++ volatile u_dhd2_paraup dhd2_paraup; /* 0xf038 */ ++ volatile u_dhd2_sync_inv dhd2_sync_inv; /* 0xf03c */ ++ volatile u_dhd2_clk_dv_ctrl dhd2_clk_dv_ctrl; /* 0xf040 */ ++ volatile u_dhd2_rgb_fix_ctrl dhd2_rgb_fix_ctrl; /* 0xf044 */ ++ volatile u_dhd2_lockcfg dhd2_lockcfg; /* 0xf048 */ ++ volatile unsigned int dhd2_cap_frm_cnt; /* 0xf04c */ ++ volatile unsigned int dhd2_vdp_frm_cnt; /* 0xf050 */ ++ volatile unsigned int dhd2_vsync_cap_vdp_cnt; /* 0xf054 */ ++ volatile unsigned int dhd2_intf_chksum_y; /* 0xf058 */ ++ volatile unsigned int dhd2_intf_chksum_u; /* 0xf05c */ ++ volatile unsigned int dhd2_intf_chksum_v; /* 0xf060 */ ++ volatile unsigned int dhd2_intf1_chksum_y; /* 0xf064 */ ++ volatile unsigned int dhd2_intf1_chksum_u; /* 0xf068 */ ++ volatile unsigned int dhd2_intf1_chksum_v; /* 0xf06c */ ++ volatile u_dhd2_intf_chksum_high1 dhd2_intf_chksum_high1; /* 0xf070 */ ++ volatile u_dhd2_intf_chksum_high2 dhd2_intf_chksum_high2; /* 0xf074 */ ++ volatile unsigned int reserved_152[3]; /* 3:0xf078~0xf080 */ ++ volatile unsigned int dhd2_afifo_pre_thd; /* 0xf084 */ ++ volatile u_dhd2_state dhd2_state; /* 0xf088 */ ++ volatile u_dhd2_uf_state dhd2_uf_state; /* 0xf08c */ ++ volatile unsigned int reserved_153[4]; /* 4:0xf090~0xf09c */ ++ volatile u_dhd2_vsync_te_state dhd2_vsync_te_state; /* 0xf0a0 */ ++ volatile u_dhd2_vsync_te_state1 dhd2_vsync_te_state1; /* 0xf0a4 */ ++ volatile unsigned int reserved_154[406]; /* 406:0xf0a8~0xf6fc */ ++ volatile u_intf2_dither_ctrl intf2_dither_ctrl; /* 0xf700 */ ++ volatile u_intf2_dither_sed_y0 intf2_dither_sed_y0; /* 0xf704 */ ++ volatile u_intf2_dither_sed_u0 intf2_dither_sed_u0; /* 0xf708 */ ++ volatile u_intf2_dither_sed_v0 intf2_dither_sed_v0; /* 0xf70c */ ++ volatile u_intf2_dither_sed_w0 intf2_dither_sed_w0; /* 0xf710 */ ++ volatile u_intf2_dither_sed_y1 intf2_dither_sed_y1; /* 0xf714 */ ++ volatile u_intf2_dither_sed_u1 intf2_dither_sed_u1; /* 0xf718 */ ++ volatile u_intf2_dither_sed_v1 intf2_dither_sed_v1; /* 0xf71c */ ++ volatile u_intf2_dither_sed_w1 intf2_dither_sed_w1; /* 0xf720 */ ++ volatile u_intf2_dither_sed_y2 intf2_dither_sed_y2; /* 0xf724 */ ++ volatile u_intf2_dither_sed_u2 intf2_dither_sed_u2; /* 0xf728 */ ++ volatile u_intf2_dither_sed_v2 intf2_dither_sed_v2; /* 0xf72c */ ++ volatile u_intf2_dither_sed_w2 intf2_dither_sed_w2; /* 0xf730 */ ++ volatile u_intf2_dither_sed_y3 intf2_dither_sed_y3; /* 0xf734 */ ++ volatile u_intf2_dither_sed_u3 intf2_dither_sed_u3; /* 0xf738 */ ++ volatile u_intf2_dither_sed_v3 intf2_dither_sed_v3; /* 0xf73c */ ++ volatile u_intf2_dither_sed_w3 intf2_dither_sed_w3; /* 0xf740 */ ++ volatile u_intf2_dither_thr intf2_dither_thr; /* 0xf744 */ ++ volatile unsigned int reserved_155[46]; /* 46:0xf748~0xf7fc */ ++ volatile u_date_coeff0 date_coeff0; /* 0xf800 */ ++ volatile u_date_coeff1 date_coeff1; /* 0xf804 */ ++ volatile unsigned int date_coeff2; /* 0xf808 */ ++ volatile u_date_coeff3 date_coeff3; /* 0xf80c */ ++ volatile u_date_coeff4 date_coeff4; /* 0xf810 */ ++ volatile u_date_coeff5 date_coeff5; /* 0xf814 */ ++ volatile u_date_coeff6 date_coeff6; /* 0xf818 */ ++ volatile u_date_coeff7 date_coeff7; /* 0xf81c */ ++ volatile unsigned int date_coeff8; /* 0xf820 */ ++ volatile unsigned int date_coeff9; /* 0xf824 */ ++ volatile u_date_coeff10 date_coeff10; /* 0xf828 */ ++ volatile u_date_coeff11 date_coeff11; /* 0xf82c */ ++ volatile u_date_coeff12 date_coeff12; /* 0xf830 */ ++ volatile u_date_coeff13 date_coeff13; /* 0xf834 */ ++ volatile u_date_coeff14 date_coeff14; /* 0xf838 */ ++ volatile u_date_coeff15 date_coeff15; /* 0xf83c */ ++ volatile u_date_coeff16 date_coeff16; /* 0xf840 */ ++ volatile unsigned int date_coeff17; /* 0xf844 */ ++ volatile unsigned int date_coeff18; /* 0xf848 */ ++ volatile u_date_coeff19 date_coeff19; /* 0xf84c */ ++ volatile u_date_coeff20 date_coeff20; /* 0xf850 */ ++ volatile u_date_coeff21 date_coeff21; /* 0xf854 */ ++ volatile u_date_coeff22 date_coeff22; /* 0xf858 */ ++ volatile u_date_coeff23 date_coeff23; /* 0xf85c */ ++ volatile unsigned int date_coeff24; /* 0xf860 */ ++ volatile u_date_coeff25 date_coeff25; /* 0xf864 */ ++ volatile u_date_coeff26 date_coeff26; /* 0xf868 */ ++ volatile u_date_coeff27 date_coeff27; /* 0xf86c */ ++ volatile u_date_coeff28 date_coeff28; /* 0xf870 */ ++ volatile u_date_coeff29 date_coeff29; /* 0xf874 */ ++ volatile u_date_coeff30 date_coeff30; /* 0xf878 */ ++ volatile unsigned int reserved_156; /* 0xf87c */ ++ volatile u_date_isrmask date_isrmask; /* 0xf880 */ ++ volatile u_date_isrstate date_isrstate; /* 0xf884 */ ++ volatile u_date_isr date_isr; /* 0xf888 */ ++ volatile unsigned int reserved_157; /* 0xf88c */ ++ volatile unsigned int date_version; /* 0xf890 */ ++ volatile u_date_coeff37 date_coeff37; /* 0xf894 */ ++ volatile u_date_coeff38 date_coeff38; /* 0xf898 */ ++ volatile u_date_coeff39 date_coeff39; /* 0xf89c */ ++ volatile u_date_coeff40 date_coeff40; /* 0xf8a0 */ ++ volatile u_date_coeff41 date_coeff41; /* 0xf8a4 */ ++ volatile u_date_coeff42 date_coeff42; /* 0xf8a8 */ ++ volatile unsigned int reserved_158[5]; /* 5:0xf8ac~0xf8bc */ ++ volatile u_date_dacdet1 date_dacdet1; /* 0xf8c0 */ ++ volatile u_date_dacdet2 date_dacdet2; /* 0xf8c4 */ ++ volatile u_date_coeff50 date_coeff50; /* 0xf8c8 */ ++ volatile u_date_coeff51 date_coeff51; /* 0xf8cc */ ++ volatile u_date_coeff52 date_coeff52; /* 0xf8d0 */ ++ volatile u_date_coeff53 date_coeff53; /* 0xf8d4 */ ++ volatile u_date_coeff54 date_coeff54; /* 0xf8d8 */ ++ volatile u_date_coeff55 date_coeff55; /* 0xf8dc */ ++ volatile unsigned int reserved_159[456]; /* 456:0xf8e0~0xfffc */ ++ volatile u_mac_outstanding mac_outstanding; /* 0x10000 */ ++ volatile u_mac_ctrl mac_ctrl; /* 0x10004 */ ++ volatile unsigned int reserved_160[2]; /* 2:0x10008~0x1000c */ ++ volatile u_mac_rchn_prio mac_rchn_prio; /* 0x10010 */ ++ volatile unsigned int reserved_161; /* 0x10014 */ ++ volatile u_mac_wchn_prio mac_wchn_prio; /* 0x10018 */ ++ volatile unsigned int reserved_162; /* 0x1001c */ ++ volatile u_mac_rchn_sel0 mac_rchn_sel0; /* 0x10020 */ ++ volatile unsigned int mac_rchn_sel1; /* 0x10024 */ ++ volatile unsigned int reserved_163[2]; /* 2:0x10028~0x1002c */ ++ volatile u_mac_wchn_sel0 mac_wchn_sel0; /* 0x10030 */ ++ volatile unsigned int reserved_164[3]; /* 3:0x10034~0x1003c */ ++ volatile u_mac_bus_err_clr mac_bus_err_clr; /* 0x10040 */ ++ volatile u_mac_bus_err mac_bus_err; /* 0x10044 */ ++ volatile unsigned int reserved_165[2]; /* 2:0x10048~0x1004c */ ++ volatile unsigned int mac_src0_status0; /* 0x10050 */ ++ volatile unsigned int mac_src0_status1; /* 0x10054 */ ++ volatile unsigned int mac_src1_status0; /* 0x10058 */ ++ volatile unsigned int mac_src1_status1; /* 0x1005c */ ++ volatile unsigned int mac_src2_status0; /* 0x10060 */ ++ volatile unsigned int mac_src2_status1; /* 0x10064 */ ++ volatile unsigned int reserved_166[2]; /* 2:0x10068~0x1006c */ ++ volatile u_mac_debug_ctrl mac_debug_ctrl; /* 0x10070 */ ++ volatile u_mac_debug_clr mac_debug_clr; /* 0x10074 */ ++ volatile unsigned int reserved_167[2]; /* 2:0x10078~0x1007c */ ++ volatile unsigned int mac0_debug_info; /* 0x10080 */ ++ volatile unsigned int reserved_168[3]; /* 3:0x10084~0x1008c */ ++ volatile unsigned int mac0_rd_info; /* 0x10090 */ ++ volatile unsigned int mac0_wr_info; /* 0x10094 */ ++ volatile unsigned int mac1_rd_info; /* 0x10098 */ ++ volatile unsigned int mac1_wr_info; /* 0x1009c */ ++ volatile unsigned int mac2_rd_info; /* 0x100a0 */ ++ volatile unsigned int mac2_wr_info; /* 0x100a4 */ ++ volatile unsigned int reserved_169[2]; /* 2:0x100a8~0x100ac */ ++ volatile unsigned int mac0_det_latency0; /* 0x100b0 */ ++ volatile unsigned int mac0_det_latency1; /* 0x100b4 */ ++ volatile unsigned int mac0_det_latency2; /* 0x100b8 */ ++ volatile unsigned int mac0_det_latency3; /* 0x100bc */ ++ volatile unsigned int mac0_det_latency4; /* 0x100c0 */ ++ volatile unsigned int mac0_det_latency5; /* 0x100c4 */ ++ volatile unsigned int mac1_det_latency0; /* 0x100c8 */ ++ volatile unsigned int mac1_det_latency1; /* 0x100cc */ ++ volatile unsigned int mac1_det_latency2; /* 0x100d0 */ ++ volatile unsigned int mac1_det_latency3; /* 0x100d4 */ ++ volatile unsigned int mac1_det_latency4; /* 0x100d8 */ ++ volatile unsigned int mac1_det_latency5; /* 0x100dc */ ++ volatile unsigned int reserved_170[72]; /* 72:0x100e0~0x101fc */ ++ volatile u_vid_read_ctrl vid_read_ctrl; /* 0x10200 */ ++ volatile u_vid_mac_ctrl vid_mac_ctrl; /* 0x10204 */ ++ volatile unsigned int reserved_171[2]; /* 2:0x10208~0x1020c */ ++ volatile u_vid_out_ctrl vid_out_ctrl; /* 0x10210 */ ++ volatile u_vid_mute_alpha vid_mute_alpha; /* 0x10214 */ ++ volatile unsigned int reserved_172; /* 0x10218 */ ++ volatile u_vid_mute_bk vid_mute_bk; /* 0x1021c */ ++ volatile unsigned int reserved_173[8]; /* 8:0x10220~0x1023c */ ++ volatile u_vid_src_info vid_src_info; /* 0x10240 */ ++ volatile u_vid_src_reso vid_src_reso; /* 0x10244 */ ++ volatile u_vid_src_crop vid_src_crop; /* 0x10248 */ ++ volatile u_vid_in_reso vid_in_reso; /* 0x1024c */ ++ volatile unsigned int vid_addr_h; /* 0x10250 */ ++ volatile unsigned int vid_addr_l; /* 0x10254 */ ++ volatile unsigned int vid_caddr_h; /* 0x10258 */ ++ volatile unsigned int vid_caddr_l; /* 0x1025c */ ++ volatile unsigned int vid_naddr_h; /* 0x10260 */ ++ volatile unsigned int vid_naddr_l; /* 0x10264 */ ++ volatile unsigned int vid_ncaddr_h; /* 0x10268 */ ++ volatile unsigned int vid_ncaddr_l; /* 0x1026c */ ++ volatile u_vid_stride vid_stride; /* 0x10270 */ ++ volatile u_vid_2bit_stride vid_2bit_stride; /* 0x10274 */ ++ volatile u_vid_head_stride vid_head_stride; /* 0x10278 */ ++ volatile unsigned int reserved_174; /* 0x1027c */ ++ volatile u_vid_smmu_bypass vid_smmu_bypass; /* 0x10280 */ ++ volatile unsigned int reserved_175[3]; /* 3:0x10284~0x1028c */ ++ volatile unsigned int vid_head_addr_h; /* 0x10290 */ ++ volatile unsigned int vid_head_addr_l; /* 0x10294 */ ++ volatile unsigned int vid_head_caddr_h; /* 0x10298 */ ++ volatile unsigned int vid_head_caddr_l; /* 0x1029c */ ++ volatile u_vid_testpat_cfg vid_testpat_cfg; /* 0x102a0 */ ++ volatile u_vid_testpat_seed vid_testpat_seed; /* 0x102a4 */ ++ volatile unsigned int vid_testpat_chksum_y; /* 0x102a8 */ ++ volatile unsigned int vid_testpat_chksum_c; /* 0x102ac */ ++ volatile unsigned int reserved_176[20]; /* 20:0x102b0~0x102fc */ ++ volatile unsigned int vid_l_cur_flow; /* 0x10300 */ ++ volatile unsigned int vid_l_cur_sreq_time; /* 0x10304 */ ++ volatile unsigned int vid_c_cur_flow; /* 0x10308 */ ++ volatile unsigned int vid_c_cur_sreq_time; /* 0x1030c */ ++ volatile unsigned int vid_l_last_flow; /* 0x10310 */ ++ volatile unsigned int vid_l_last_sreq_time; /* 0x10314 */ ++ volatile unsigned int vid_c_last_flow; /* 0x10318 */ ++ volatile unsigned int vid_c_last_sreq_time; /* 0x1031c */ ++ volatile unsigned int vid_l_busy_time; /* 0x10320 */ ++ volatile unsigned int vid_l_neednordy_time; /* 0x10324 */ ++ volatile unsigned int vid_l2_neednordy_time; /* 0x10328 */ ++ volatile unsigned int vid_c_busy_time; /* 0x1032c */ ++ volatile unsigned int vid_c_neednordy_time; /* 0x10330 */ ++ volatile unsigned int vid_c2_neednordy_time; /* 0x10334 */ ++ volatile unsigned int reserved_177[2]; /* 2:0x10338~0x1033c */ ++ volatile u_vid_dcmp_ctrl vid_dcmp_ctrl; /* 0x10340 */ ++ volatile unsigned int vid_dcmp_l_fsize; /* 0x10344 */ ++ volatile unsigned int reserved_178[14]; /* 14:0x10348~0x1037c */ ++ volatile u_vdp_v3r2_lineseg_dcmp_glb_info vdp_v3r2_lineseg_dcmp_glb_info; /* 0x10380 */ ++ volatile u_vdp_v3r2_lineseg_dcmp_frame_size vdp_v3r2_lineseg_dcmp_frame_size; /* 0x10384 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0; /* 0x10388 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1; /* 0x1038c */ ++ volatile u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; /* 0x10390 */ ++ volatile u_vdp_v3r2_lineseg_dcmp_error_sta vdp_v3r2_lineseg_dcmp_error_sta; /* 0x10394 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra; /* 0x10398 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg; /* 0x1039c */ ++ volatile unsigned int reserved_179[8]; /* 8:0x103a0~0x103bc */ ++ volatile u_vdp_v3r2_lineseg_dcmp_glb_info_c vdp_v3r2_lineseg_dcmp_glb_info_c; /* 0x103c0 */ ++ volatile u_vdp_v3r2_lineseg_dcmp_frame_size_c vdp_v3r2_lineseg_dcmp_frame_size_c; /* 0x103c4 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0_c; /* 0x103c8 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1_c; /* 0x103cc */ ++ volatile u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; /* 0x103d0 */ ++ volatile u_vdp_v3r2_lineseg_dcmp_error_sta_c vdp_v3r2_lineseg_dcmp_error_sta_c; /* 0x103d4 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra_c; /* 0x103d8 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg_c; /* 0x103dc */ ++ volatile unsigned int reserved_180[648]; /* 648:0x103e0~0x10dfc */ ++ volatile u_gfx_read_ctrl gfx_read_ctrl; /* 0x10e00 */ ++ volatile u_gfx_mac_ctrl gfx_mac_ctrl; /* 0x10e04 */ ++ volatile u_gfx_out_ctrl gfx_out_ctrl; /* 0x10e08 */ ++ volatile unsigned int reserved_181; /* 0x10e0c */ ++ volatile u_gfx_mute_alpha gfx_mute_alpha; /* 0x10e10 */ ++ volatile u_gfx_mute_bk gfx_mute_bk; /* 0x10e14 */ ++ volatile unsigned int reserved_182[2]; /* 2:0x10e18~0x10e1c */ ++ volatile u_gfx_smmu_bypass gfx_smmu_bypass; /* 0x10e20 */ ++ volatile unsigned int reserved_183; /* 0x10e24 */ ++ volatile u_gfx_1555_alpha gfx_1555_alpha; /* 0x10e28 */ ++ volatile unsigned int reserved_184[5]; /* 5:0x10e2c~0x10e3c */ ++ volatile u_gfx_src_info gfx_src_info; /* 0x10e40 */ ++ volatile u_gfx_src_reso gfx_src_reso; /* 0x10e44 */ ++ volatile u_gfx_src_crop gfx_src_crop; /* 0x10e48 */ ++ volatile u_gfx_ireso gfx_ireso; /* 0x10e4c */ ++ volatile unsigned int gfx_addr_h; /* 0x10e50 */ ++ volatile unsigned int gfx_addr_l; /* 0x10e54 */ ++ volatile unsigned int gfx_naddr_h; /* 0x10e58 */ ++ volatile unsigned int gfx_naddr_l; /* 0x10e5c */ ++ volatile u_gfx_stride gfx_stride; /* 0x10e60 */ ++ volatile unsigned int reserved_185[3]; /* 3:0x10e64~0x10e6c */ ++ volatile unsigned int gfx_dcmp_addr_h; /* 0x10e70 */ ++ volatile unsigned int gfx_dcmp_addr_l; /* 0x10e74 */ ++ volatile unsigned int gfx_dcmp_naddr_h; /* 0x10e78 */ ++ volatile unsigned int gfx_dcmp_naddr_l; /* 0x10e7c */ ++ volatile unsigned int reserved_186[32]; /* 32:0x10e80~0x10efc */ ++ volatile u_gfx_ckey_max gfx_ckey_max; /* 0x10f00 */ ++ volatile u_gfx_ckey_min gfx_ckey_min; /* 0x10f04 */ ++ volatile u_gfx_ckey_mask gfx_ckey_mask; /* 0x10f08 */ ++ volatile unsigned int reserved_187; /* 0x10f0c */ ++ volatile u_gfx_testpat_cfg gfx_testpat_cfg; /* 0x10f10 */ ++ volatile u_gfx_testpat_seed gfx_testpat_seed; /* 0x10f14 */ ++ volatile unsigned int reserved_188[2]; /* 2:0x10f18~0x10f1c */ ++ volatile unsigned int gfx_dcmp_framesize0; /* 0x10f20 */ ++ volatile unsigned int gfx_dcmp_framesize1; /* 0x10f24 */ ++ volatile unsigned int reserved_189[2]; /* 2:0x10f28~0x10f2c */ ++ volatile unsigned int gfx_cur_flow; /* 0x10f30 */ ++ volatile unsigned int gfx_cur_sreq_time; /* 0x10f34 */ ++ volatile unsigned int gfx_last_flow; /* 0x10f38 */ ++ volatile unsigned int gfx_last_sreq_time; /* 0x10f3c */ ++ volatile unsigned int gfx_busy_time; /* 0x10f40 */ ++ volatile unsigned int gfx_ar_neednordy_time; /* 0x10f44 */ ++ volatile unsigned int gfx_gb_neednordy_time; /* 0x10f48 */ ++ volatile unsigned int reserved_190_1[1]; /* 0x10f4c */ ++ volatile u_gfx_ld_ctrl gfx_ld_ctrl; /* 0x10f50 */ ++ volatile unsigned int gfx_tde_safe_dis; /* 0x10f54 */ ++ volatile u_gfx_ld_smute_ctrl gfx_ld_smute_ctrl; /* 0x10f58 */ ++ volatile u_gfx_ld_err_sta gfx_ld_err_sta; /* 0x10f5c */ ++ volatile unsigned int gfx_ld_debug0; /* 0x10f60 */ ++ volatile unsigned int gfx_ld_debug1; /* 0x10f64 */ ++ volatile unsigned int gfx_ld_debug2; /* 0x10f68 */ ++ volatile unsigned int gfx_ld_debug3; /* 0x10f6c */ ++ volatile unsigned int gfx_ld_debug4; /* 0x10f70 */ ++ volatile unsigned int gfx_ld_debug5; /* 0x10f74 */ ++ volatile unsigned int reserved_190_2[2]; /* 2:0x10f78~0x10f7c */ ++ volatile u_vdp_v3r2_line_osd_dcmp_glb_info vdp_v3r2_line_osd_dcmp_glb_info; /* 0x10f80 */ ++ volatile u_vdp_v3r2_line_osd_dcmp_frame_size vdp_v3r2_line_osd_dcmp_frame_size; /* 0x10f84 */ ++ volatile u_vdp_v3r2_line_osd_dcmp_error_sta vdp_v3r2_line_osd_dcmp_error_sta; /* 0x10f88 */ ++ volatile unsigned int reserved_191[541]; /* 0x10f8c~0x117fc 541 regs */ ++ volatile u_wbc_ctrl wbc_ctrl; /* 0x11800 */ ++ volatile u_wbc_mac_ctrl wbc_mac_ctrl; /* 0x11804 */ ++ volatile unsigned int reserved_193[3]; /* 3:0x11808~0x11810 */ ++ volatile u_wbc_smmu_bypass wbc_smmu_bypass; /* 0x11814 */ ++ volatile unsigned int reserved_194[2]; /* 2:0x11818~0x1181c */ ++ volatile u_wbc_lowdlyctrl wbc_lowdlyctrl; /* 0x11820 */ ++ volatile unsigned int wbc_tunladdr_h; /* 0x11824 */ ++ volatile unsigned int wbc_tunladdr_l; /* 0x11828 */ ++ volatile u_wbc_lowdlysta wbc_lowdlysta; /* 0x1182c */ ++ volatile unsigned int reserved_195[8]; /* 8:0x11830~0x1184c */ ++ volatile unsigned int wbc_yaddr_h; /* 0x11850 */ ++ volatile unsigned int wbc_yaddr_l; /* 0x11854 */ ++ volatile unsigned int wbc_caddr_h; /* 0x11858 */ ++ volatile unsigned int wbc_caddr_l; /* 0x1185c */ ++ volatile u_wbc_ystride wbc_ystride; /* 0x11860 */ ++ volatile u_wbc_cstride wbc_cstride; /* 0x11864 */ ++ volatile unsigned int reserved_196[2]; /* 2:0x11868~0x1186c */ ++ volatile unsigned int wbc_ynaddr_h; /* 0x11870 */ ++ volatile unsigned int wbc_ynaddr_l; /* 0x11874 */ ++ volatile unsigned int wbc_cnaddr_h; /* 0x11878 */ ++ volatile unsigned int wbc_cnaddr_l; /* 0x1187c */ ++ volatile u_wbc_ynstride wbc_ynstride; /* 0x11880 */ ++ volatile u_wbc_cnstride wbc_cnstride; /* 0x11884 */ ++ volatile unsigned int reserved_197[10]; /* 10:0x11888~0x118ac */ ++ volatile u_wbc_sta wbc_sta; /* 0x118b0 */ ++ volatile u_wbc_line_num wbc_line_num; /* 0x118b4 */ ++ volatile u_wbc_cap_reso wbc_cap_reso; /* 0x118b8 */ ++ volatile unsigned int wbc_cap_info; /* 0x118bc */ ++ volatile unsigned int reserved_198[16]; /* 16:0x118c0~0x118fc */ ++ volatile u_vdp_v3r2_lineseg_cmp_glb_info vdp_v3r2_lineseg_cmp_glb_info; /* 0x11900 */ ++ volatile u_vdp_v3r2_lineseg_cmp_frame_size vdp_v3r2_lineseg_cmp_frame_size; /* 0x11904 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg0 vdp_v3r2_lineseg_cmp_rc_cfg0; /* 0x11908 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg1 vdp_v3r2_lineseg_cmp_rc_cfg1; /* 0x1190c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2; /* 0x11910 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3; /* 0x11914 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4; /* 0x11918 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5; /* 0x1191c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6; /* 0x11920 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7; /* 0x11924 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8; /* 0x11928 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9; /* 0x1192c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10; /* 0x11930 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11; /* 0x11934 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg12 vdp_v3r2_lineseg_cmp_rc_cfg12; /* 0x11938 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg13 vdp_v3r2_lineseg_cmp_rc_cfg13; /* 0x1193c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14; /* 0x11940 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15; /* 0x11944 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0; /* 0x11948 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1; /* 0x1194c */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg16 vdp_v3r2_lineseg_cmp_rc_cfg16; /* 0x11950 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg; /* 0x11954 */ ++ volatile u_vdp_v3r2_lineseg_cmp_glb_st vdp_v3r2_lineseg_cmp_glb_st; /* 0x11958 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg; /* 0x1195c */ ++ volatile unsigned int reserved_199[8]; /* 8:0x11960~0x1197c */ ++ volatile u_vdp_v3r2_lineseg_cmp_glb_info_c vdp_v3r2_lineseg_cmp_glb_info_c; /* 0x11980 */ ++ volatile u_vdp_v3r2_lineseg_cmp_frame_size_c vdp_v3r2_lineseg_cmp_frame_size_c; /* 0x11984 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg0_c vdp_v3r2_lineseg_cmp_rc_cfg0_c; /* 0x11988 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg1_c vdp_v3r2_lineseg_cmp_rc_cfg1_c; /* 0x1198c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2_c; /* 0x11990 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3_c; /* 0x11994 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4_c; /* 0x11998 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5_c; /* 0x1199c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6_c; /* 0x119a0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7_c; /* 0x119a4 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8_c; /* 0x119a8 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9_c; /* 0x119ac */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10_c; /* 0x119b0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11_c; /* 0x119b4 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg12_c vdp_v3r2_lineseg_cmp_rc_cfg12_c; /* 0x119b8 */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg13_c vdp_v3r2_lineseg_cmp_rc_cfg13_c; /* 0x119bc */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14_c; /* 0x119c0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15_c; /* 0x119c4 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0_c; /* 0x119c8 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1_c; /* 0x119cc */ ++ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg16_c vdp_v3r2_lineseg_cmp_rc_cfg16_c; /* 0x119d0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg_c; /* 0x119d4 */ ++ volatile u_vdp_v3r2_lineseg_cmp_glb_st_c vdp_v3r2_lineseg_cmp_glb_st_c; /* 0x119d8 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg_c; /* 0x119dc */ ++ volatile unsigned int reserved_200[264]; /* 264:0x119e0~0x11dfc */ ++ volatile u_wbc_cmp_ctrl wbc_cmp_ctrl; /* 0x11e00 */ ++ volatile u_wbc_cmp_upd wbc_cmp_upd; /* 0x11e04 */ ++ volatile u_wbc_cmp_height wbc_cmp_height; /* 0x11e08 */ ++ volatile u_wbc_cmp_oreso wbc_cmp_oreso; /* 0x11e0c */ ++ volatile unsigned int wbc_cmp_yaddr; /* 0x11e10 */ ++ volatile unsigned int wbc_cmp_yaddr1; /* 0x11e14 */ ++ volatile unsigned int wbc_cmp_caddr; /* 0x11e18 */ ++ volatile unsigned int wbc_cmp_caddr1; /* 0x11e1c */ ++ volatile unsigned int wbc_cmp_addr0_t0; /* 0x11e20 */ ++ volatile unsigned int wbc_cmp_addr1_t0; /* 0x11e24 */ ++ volatile unsigned int wbc_cmp_addr0_t1; /* 0x11e28 */ ++ volatile unsigned int wbc_cmp_addr1_t1; /* 0x11e2c */ ++ volatile unsigned int wbc_cmp_l_fsize; /* 0x11e30 */ ++ volatile unsigned int wbc_cmp_c_fsize; /* 0x11e34 */ ++ volatile unsigned int wbc_cmp_t0_fsize; /* 0x11e38 */ ++ volatile unsigned int wbc_cmp_t1_fsize; /* 0x11e3c */ ++ volatile unsigned int wbc_sety_fsize; /* 0x11e40 */ ++ volatile unsigned int wbc_setc_fsize; /* 0x11e44 */ ++ volatile unsigned int wbc_sett0_fsize; /* 0x11e48 */ ++ volatile unsigned int wbc_sett1_fsize; /* 0x11e4c */ ++ volatile u_wbc_od_state wbc_od_state; /* 0x11e50 */ ++ volatile unsigned int reserved_201[43]; /* 43:0x11e54~0x11efc */ ++ volatile u_od_pic_osd_glb_info od_pic_osd_glb_info; /* 0x11f00 */ ++ volatile u_od_pic_osd_frame_size od_pic_osd_frame_size; /* 0x11f04 */ ++ volatile u_od_pic_osd_rc_cfg0 od_pic_osd_rc_cfg0; /* 0x11f08 */ ++ volatile u_od_pic_osd_rc_cfg1 od_pic_osd_rc_cfg1; /* 0x11f0c */ ++ volatile u_od_pic_osd_rc_cfg2 od_pic_osd_rc_cfg2; /* 0x11f10 */ ++ volatile u_od_pic_osd_rc_cfg3 od_pic_osd_rc_cfg3; /* 0x11f14 */ ++ volatile u_od_pic_osd_rc_cfg4 od_pic_osd_rc_cfg4; /* 0x11f18 */ ++ volatile u_od_pic_osd_rc_cfg5 od_pic_osd_rc_cfg5; /* 0x11f1c */ ++ volatile u_od_pic_osd_rc_cfg6 od_pic_osd_rc_cfg6; /* 0x11f20 */ ++ volatile u_od_pic_osd_rc_cfg7 od_pic_osd_rc_cfg7; /* 0x11f24 */ ++ volatile u_od_pic_osd_rc_cfg8 od_pic_osd_rc_cfg8; /* 0x11f28 */ ++ volatile u_od_pic_osd_rc_cfg9 od_pic_osd_rc_cfg9; /* 0x11f2c */ ++ volatile u_od_pic_osd_rc_cfg10 od_pic_osd_rc_cfg10; /* 0x11f30 */ ++ volatile u_od_pic_osd_rc_cfg11 od_pic_osd_rc_cfg11; /* 0x11f34 */ ++ volatile u_od_pic_osd_rc_cfg12 od_pic_osd_rc_cfg12; /* 0x11f38 */ ++ volatile u_od_pic_osd_rc_cfg13 od_pic_osd_rc_cfg13; /* 0x11f3c */ ++ volatile u_od_pic_osd_rc_cfg14 od_pic_osd_rc_cfg14; /* 0x11f40 */ ++ volatile u_od_pic_osd_rc_cfg15 od_pic_osd_rc_cfg15; /* 0x11f44 */ ++ volatile u_od_pic_osd_rc_cfg16 od_pic_osd_rc_cfg16; /* 0x11f48 */ ++ volatile u_od_pic_osd_rc_cfg17 od_pic_osd_rc_cfg17; /* 0x11f4c */ ++ volatile u_od_pic_osd_rc_cfg18 od_pic_osd_rc_cfg18; /* 0x11f50 */ ++ volatile u_od_pic_osd_rc_cfg19 od_pic_osd_rc_cfg19; /* 0x11f54 */ ++ volatile unsigned int reserved_202[2]; /* 2:0x11f58~0x11f5c */ ++ volatile u_od_pic_osd_stat_thr od_pic_osd_stat_thr; /* 0x11f60 */ ++ volatile u_od_pic_osd_pcmp od_pic_osd_pcmp; /* 0x11f64 */ ++ volatile unsigned int reserved_203[6]; /* 6:0x11f68~0x11f7c */ ++ volatile u_od_pic_osd_bs_size od_pic_osd_bs_size; /* 0x11f80 */ ++ volatile u_od_pic_osd_worst_row od_pic_osd_worst_row; /* 0x11f84 */ ++ volatile u_od_pic_osd_best_row od_pic_osd_best_row; /* 0x11f88 */ ++ volatile u_od_pic_osd_stat_info od_pic_osd_stat_info; /* 0x11f8c */ ++ volatile unsigned int od_pic_osd_debug0; /* 0x11f90 */ ++ volatile unsigned int od_pic_osd_debug1; /* 0x11f94 */ ++ volatile unsigned int reserved_204[26]; /* 26:0x11f98~0x11ffc */ ++ volatile u_v0_mrg_ctrl v0_mrg_ctrl; /* 0x12000 */ ++ volatile u_v0_mrg_disp_pos v0_mrg_disp_pos; /* 0x12004 */ ++ volatile u_v0_mrg_disp_reso v0_mrg_disp_reso; /* 0x12008 */ ++ volatile u_v0_mrg_src_reso v0_mrg_src_reso; /* 0x1200c */ ++ volatile u_v0_mrg_src_offset v0_mrg_src_offset; /* 0x12010 */ ++ volatile unsigned int v0_mrg_y_addr; /* 0x12014 */ ++ volatile unsigned int v0_mrg_c_addr; /* 0x12018 */ ++ volatile u_v0_mrg_stride v0_mrg_stride; /* 0x1201c */ ++ volatile unsigned int v0_mrg_yh_addr; /* 0x12020 */ ++ volatile unsigned int v0_mrg_ch_addr; /* 0x12024 */ ++ volatile u_v0_mrg_hstride v0_mrg_hstride; /* 0x12028 */ ++ volatile unsigned int reserved_205[5]; /* 5:0x1202c~0x1203c */ ++ volatile u_v0_mrg_read_ctrl v0_mrg_read_ctrl; /* 0x12040 */ ++ volatile u_v0_mrg_read_en v0_mrg_read_en; /* 0x12044 */ ++ volatile unsigned int reserved_206[750]; /* 750:0x12048~0x12bfc */ ++ volatile u_v1_mrg_ctrl v1_mrg_ctrl; /* 0x12c00 */ ++ volatile u_v1_mrg_disp_pos v1_mrg_disp_pos; /* 0x12c04 */ ++ volatile u_v1_mrg_disp_reso v1_mrg_disp_reso; /* 0x12c08 */ ++ volatile u_v1_mrg_src_reso v1_mrg_src_reso; /* 0x12c0c */ ++ volatile u_v1_mrg_src_offset v1_mrg_src_offset; /* 0x12c10 */ ++ volatile unsigned int v1_mrg_y_addr; /* 0x12c14 */ ++ volatile unsigned int v1_mrg_c_addr; /* 0x12c18 */ ++ volatile u_v1_mrg_stride v1_mrg_stride; /* 0x12c1c */ ++ volatile unsigned int v1_mrg_yh_addr; /* 0x12c20 */ ++ volatile unsigned int v1_mrg_ch_addr; /* 0x12c24 */ ++ volatile u_v1_mrg_hstride v1_mrg_hstride; /* 0x12c28 */ ++ volatile unsigned int reserved_207[5]; /* 5:0x12c2c~0x12c3c */ ++ volatile u_v1_mrg_read_ctrl v1_mrg_read_ctrl; /* 0x12c40 */ ++ volatile u_v1_mrg_read_en v1_mrg_read_en; /* 0x12c44 */ ++ volatile unsigned int reserved_208_1[1262]; /* 1262:0x12c48~0x14ffc */ ++ volatile u_osb_ctrl1_box_0 osb_ctrl1_box_0; /* 0x14000 */ ++ volatile u_osb_ctrl2_box_0 osb_ctrl2_box_0; /* 0x14004 */ ++ volatile u_osb_ctrl3_box_0 osb_ctrl3_box_0; /* 0x14008 */ ++ volatile unsigned int reserved_208_2[1021]; /* 1021:0x1400c~0x14ffc 1021 regs */ ++ volatile u_v1_csc_idc v1_csc_idc; /* 0x15000 */ ++ volatile u_v1_csc_odc v1_csc_odc; /* 0x15004 */ ++ volatile u_v1_csc_iodc v1_csc_iodc; /* 0x15008 */ ++ volatile u_v1_csc_p0 v1_csc_p0; /* 0x1500c */ ++ volatile u_v1_csc_p1 v1_csc_p1; /* 0x15010 */ ++ volatile u_v1_csc_p2 v1_csc_p2; /* 0x15014 */ ++ volatile u_v1_csc_p3 v1_csc_p3; /* 0x15018 */ ++ volatile u_v1_csc_p4 v1_csc_p4; /* 0x1501c */ ++ volatile u_v1_csc1_idc v1_csc1_idc; /* 0x15020 */ ++ volatile u_v1_csc1_odc v1_csc1_odc; /* 0x15024 */ ++ volatile u_v1_csc1_iodc v1_csc1_iodc; /* 0x15028 */ ++ volatile u_v1_csc1_p0 v1_csc1_p0; /* 0x1502c */ ++ volatile u_v1_csc1_p1 v1_csc1_p1; /* 0x15030 */ ++ volatile u_v1_csc1_p2 v1_csc1_p2; /* 0x15034 */ ++ volatile u_v1_csc1_p3 v1_csc1_p3; /* 0x15038 */ ++ volatile u_v1_csc1_p4 v1_csc1_p4; /* 0x1503c */ ++ volatile unsigned int reserved_209[48]; /* 48:0x15040~0x150fc */ ++ volatile u_v2_csc_idc v2_csc_idc; /* 0x15100 */ ++ volatile u_v2_csc_odc v2_csc_odc; /* 0x15104 */ ++ volatile u_v2_csc_iodc v2_csc_iodc; /* 0x15108 */ ++ volatile u_v2_csc_p0 v2_csc_p0; /* 0x1510c */ ++ volatile u_v2_csc_p1 v2_csc_p1; /* 0x15110 */ ++ volatile u_v2_csc_p2 v2_csc_p2; /* 0x15114 */ ++ volatile u_v2_csc_p3 v2_csc_p3; /* 0x15118 */ ++ volatile u_v2_csc_p4 v2_csc_p4; /* 0x1511c */ ++ volatile u_v2_csc1_idc v2_csc1_idc; /* 0x15120 */ ++ volatile u_v2_csc1_odc v2_csc1_odc; /* 0x15124 */ ++ volatile u_v2_csc1_iodc v2_csc1_iodc; /* 0x15128 */ ++ volatile u_v2_csc1_p0 v2_csc1_p0; /* 0x1512c */ ++ volatile u_v2_csc1_p1 v2_csc1_p1; /* 0x15130 */ ++ volatile u_v2_csc1_p2 v2_csc1_p2; /* 0x15134 */ ++ volatile u_v2_csc1_p3 v2_csc1_p3; /* 0x15138 */ ++ volatile u_v2_csc1_p4 v2_csc1_p4; /* 0x1513c */ ++ volatile unsigned int reserved_210[48]; /* 48:0x15140~0x151fc */ ++ volatile u_g1_csc_idc g1_csc_idc; /* 0x15200 */ ++ volatile u_g1_csc_odc g1_csc_odc; /* 0x15204 */ ++ volatile u_g1_csc_iodc g1_csc_iodc; /* 0x15208 */ ++ volatile u_g1_csc_p0 g1_csc_p0; /* 0x1520c */ ++ volatile u_g1_csc_p1 g1_csc_p1; /* 0x15210 */ ++ volatile u_g1_csc_p2 g1_csc_p2; /* 0x15214 */ ++ volatile u_g1_csc_p3 g1_csc_p3; /* 0x15218 */ ++ volatile u_g1_csc_p4 g1_csc_p4; /* 0x1521c */ ++ volatile u_g1_csc1_idc g1_csc1_idc; /* 0x15220 */ ++ volatile u_g1_csc1_odc g1_csc1_odc; /* 0x15224 */ ++ volatile u_g1_csc1_iodc g1_csc1_iodc; /* 0x15228 */ ++ volatile u_g1_csc1_p0 g1_csc1_p0; /* 0x1522c */ ++ volatile u_g1_csc1_p1 g1_csc1_p1; /* 0x15230 */ ++ volatile u_g1_csc1_p2 g1_csc1_p2; /* 0x15234 */ ++ volatile u_g1_csc1_p3 g1_csc1_p3; /* 0x15238 */ ++ volatile u_g1_csc1_p4 g1_csc1_p4; /* 0x1523c */ ++ volatile unsigned int reserved_211[48]; /* 48:0x15240~0x152fc */ ++ volatile u_g3_csc_idc g3_csc_idc; /* 0x15300 */ ++ volatile u_g3_csc_odc g3_csc_odc; /* 0x15304 */ ++ volatile u_g3_csc_iodc g3_csc_iodc; /* 0x15308 */ ++ volatile u_g3_csc_p0 g3_csc_p0; /* 0x1530c */ ++ volatile u_g3_csc_p1 g3_csc_p1; /* 0x15310 */ ++ volatile u_g3_csc_p2 g3_csc_p2; /* 0x15314 */ ++ volatile u_g3_csc_p3 g3_csc_p3; /* 0x15318 */ ++ volatile u_g3_csc_p4 g3_csc_p4; /* 0x1531c */ ++ volatile u_g3_csc1_idc g3_csc1_idc; /* 0x15320 */ ++ volatile u_g3_csc1_odc g3_csc1_odc; /* 0x15324 */ ++ volatile u_g3_csc1_iodc g3_csc1_iodc; /* 0x15328 */ ++ volatile u_g3_csc1_p0 g3_csc1_p0; /* 0x1532c */ ++ volatile u_g3_csc1_p1 g3_csc1_p1; /* 0x15330 */ ++ volatile u_g3_csc1_p2 g3_csc1_p2; /* 0x15334 */ ++ volatile u_g3_csc1_p3 g3_csc1_p3; /* 0x15338 */ ++ volatile u_g3_csc1_p4 g3_csc1_p4; /* 0x1533c */ ++ volatile unsigned int reserved_212[48]; /* 48:0x15340~0x153fc */ ++ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; /* 0x15400 */ ++ volatile u_v0_cvfir_vsp v0_cvfir_vsp; /* 0x15404 */ ++ volatile u_v0_cvfir_voffset v0_cvfir_voffset; /* 0x15408 */ ++ volatile u_v0_cvfir_vboffset v0_cvfir_vboffset; /* 0x1540c */ ++ volatile unsigned int reserved_213[8]; /* 8:0x15410~0x1542c */ ++ volatile u_v0_cvfir_vcoef0 v0_cvfir_vcoef0; /* 0x15430 */ ++ volatile u_v0_cvfir_vcoef1 v0_cvfir_vcoef1; /* 0x15434 */ ++ volatile u_v0_cvfir_vcoef2 v0_cvfir_vcoef2; /* 0x15438 */ ++ volatile unsigned int reserved_214[721]; /* 721:0x1543c~0x15f7c */ ++ volatile u_gfx_osd_glb_info gfx_osd_glb_info; /* 0x15f80 */ ++ volatile u_gfx_osd_frame_size gfx_osd_frame_size; /* 0x15f84 */ ++ volatile unsigned int reserved_215[2]; /* 2:0x15f88~0x15f8c */ ++ volatile u_gfx_osd_dbg_reg gfx_osd_dbg_reg; /* 0x15f90 */ ++ volatile u_gfx_osd_dbg_reg1 gfx_osd_dbg_reg1; /* 0x15f94 */ ++} vdp_regs_type; ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif /* __cplusplus */ ++#endif /* __cplusplus */ ++ ++#endif /* GFBG_REG_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.c b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.c +new file mode 100755 +index 000000000..a7a7a4da0 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.c +@@ -0,0 +1,180 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#include "hdmi_product_define.h" ++#include "hdmi_reg_video_path.h" ++ ++#define CRG_RESET_DELAY 2 ++#define HDMI_IO_CFG_HPD_SEL 0x2801 ++#define HDMI_IO_CFG_DDC_SEL 0x6801 ++ ++void hdmi_tx_reg_write(unsigned int *reg_addr, unsigned int value) ++{ ++ *(volatile unsigned int *)reg_addr = value; ++ return; ++} ++ ++unsigned int hdmi_tx_reg_read(const unsigned int *reg_addr) ++{ ++ return *(volatile unsigned int *)(reg_addr); ++} ++ ++void hdmi_reg_write_u32(unsigned int reg_addr, unsigned int value) ++{ ++ volatile unsigned int *addr = NULL; ++ ++ addr = (volatile unsigned int *)ioremap((unsigned long long)reg_addr, HDMI_REGISTER_SIZE); ++ if (addr != NULL) { ++ *addr = value; ++ iounmap((void *)addr); ++ } else { ++ printk("ioremap addr=0x%x err!\n", reg_addr); ++ } ++ ++ return; ++} ++ ++unsigned int hdmi_reg_read_u32(unsigned int reg_addr) ++{ ++ volatile unsigned int *addr = NULL; ++ unsigned int value = 0; ++ ++ ++ addr = (volatile unsigned int *)ioremap((unsigned long long)reg_addr, HDMI_REGISTER_SIZE); ++ if (addr != NULL) { ++ value = *addr; ++ iounmap((void *)addr); ++ } else { ++ printk("ioremap addr=0x%x\n err!\n", reg_addr); ++ } ++ ++ return value; ++} ++ ++void drv_hdmi_prod_io_cfg_set(void) ++{ ++ ++ hdmi_if_fpga_return_void(); ++ ++ hdmi_reg_write_u32(HDMI_ADDR_IO_CFG_HOTPLUG, HDMI_IO_CFG_HPD_SEL); ++ hdmi_reg_write_u32(HDMI_ADDR_IO_CFG_SDA, HDMI_IO_CFG_DDC_SEL); ++ hdmi_reg_write_u32(HDMI_ADDR_IO_CFG_SCL, HDMI_IO_CFG_DDC_SEL); ++ ++ return; ++} ++ ++void drv_hdmi_prod_crg_gate_set(bool enable) ++{ ++ ++ hdmi_if_fpga_return_void(); ++ ++ hdmi_reg_ctrl_osc_24m_cken_set(enable); ++ hdmi_reg_ctrl_cec_cken_set(enable); ++ hdmi_reg_ctrl_os_cken_set(enable); ++ hdmi_reg_ctrl_as_cken_set(enable); ++ hdmi_reg_hdmitx_phy_tmds_cken_set(enable); ++ hdmi_reg_hdmitx_phy_modclk_cken_set(enable); ++ hdmi_reg_ac_ctrl_modclk_cken_set(enable); ++ hdmi_reg_phy_clk_pctrl_set(0); ++ ++ return; ++} ++ ++void drv_hdmi_prod_crg_all_reset_set(bool enable) ++{ ++ ++ hdmi_if_fpga_return_void(); ++ ++ ++ hdmi_reg_ctrl_bus_srst_req_set(enable); ++ hdmi_reg_ctrl_srst_req_set(enable); ++ hdmi_reg_ctrl_cec_srst_req_set(enable); ++ hdmi_reg_phy_srst_req_set(enable); ++ hdmi_reg_phy_bus_srst_req_set(enable); ++ hdmi_reg_ac_ctrl_srst_req_set(enable); ++ hdmi_reg_ac_ctrl_bus_srst_req_set(enable); ++ enable = !enable; ++ /* ++ * 2, 2us. to ensure ctrl reset success. ++ * because internal clock of HDMI is smaller than APB clock. ++ */ ++ udelay(CRG_RESET_DELAY); ++ hdmi_reg_ctrl_bus_srst_req_set(enable); ++ hdmi_reg_ctrl_srst_req_set(enable); ++ hdmi_reg_ctrl_cec_srst_req_set(enable); ++ hdmi_reg_phy_srst_req_set(enable); ++ hdmi_reg_phy_bus_srst_req_set(enable); ++ hdmi_reg_ac_ctrl_srst_req_set(enable); ++ hdmi_reg_ac_ctrl_bus_srst_req_set(enable); ++ ++ return; ++} ++ ++void drv_hdmi_low_power_set(bool enable) ++{ ++ ++ hdmi_if_fpga_return_void(); ++ ++ if ((hdmi_reg_crg_init() != 0) || hdmi_video_path_regs_is_inited() != 0) { ++ ++ return; ++ } ++ ++ enable = !enable; ++ hdmi_reg_ctrl_os_cken_set(enable); ++ hdmi_reg_ctrl_as_cken_set(enable); ++ /* blank data help for low power. */ ++ hdmi_reg_video_blank_en_set(enable); ++ ++ return; ++} ++ ++void drv_hdmi_prod_crg_init(void) ++{ ++ ++ drv_hdmi_prod_io_cfg_set(); ++ drv_hdmi_prod_crg_gate_set(1); ++ drv_hdmi_prod_crg_all_reset_set(1); ++ drv_hdmi_low_power_set(1); ++ ++ return; ++} ++ ++void drv_hdmi_hardware_reset(unsigned int id) ++{ ++ ++ hdmi_if_fpga_return_void(); ++ ++ if (hdmi_reg_crg_init() != 0) { ++ printk("CRG reg io map error!\n"); ++ return; ++ } ++ /* reset all module */ ++ hdmi_reg_ctrl_bus_srst_req_set(1); ++ hdmi_reg_ctrl_srst_req_set(1); ++ hdmi_reg_ctrl_cec_srst_req_set(1); ++ hdmi_reg_phy_srst_req_set(1); ++ hdmi_reg_phy_bus_srst_req_set(1); ++ hdmi_reg_ac_ctrl_srst_req_set(1); ++ hdmi_reg_ac_ctrl_bus_srst_req_set(1); ++ /* close all clk */ ++ drv_hdmi_prod_crg_gate_set(0); ++ hdmi_reg_crg_deinit(); ++ ++ return; ++} +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.h +new file mode 100755 +index 000000000..d7ef6b3f0 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.h +@@ -0,0 +1,160 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HDMI_PRODUCT_DEFINE_H ++#define HDMI_PRODUCT_DEFINE_H ++ ++#include ++#include ++#include ++#include ++#include "hdmi_reg_crg.h" ++ ++/* ++ * ------------- reg base addr -------- ++ * ctrl | dphy | ++ * hdmi0 : 0x17B40000 | 0x17BC0000 | ++ * -------------------|---------------- ++ */ ++#define CRG_BASE_ADDR 0x11010000 ++#define HDMI_CRG_OFFSET 0x7F40 ++#define HDMI_CRG_ADDR ((CRG_BASE_ADDR) + (HDMI_CRG_OFFSET)) ++/* pin mux */ ++#define HDMI_ADDR_BASE_IO_CFG 0x102F0000 ++#define HDMI_ADDR_IO_CFG_HOTPLUG (HDMI_ADDR_BASE_IO_CFG + 0xE4) ++#define HDMI_ADDR_IO_CFG_SDA (HDMI_ADDR_BASE_IO_CFG + 0xE8) ++#define HDMI_ADDR_IO_CFG_SCL (HDMI_ADDR_BASE_IO_CFG + 0xEC) ++/* color bar */ ++#define HDMI_COLOR_BAR_MASK 0x60000000 ++#define HDMI_COLOR_BAR_UPDATE_MASK 0x00000001 ++#define HDMI_COLOR_BAR_BASE 0x17A0D000 ++/* sub-module offset */ ++#define HDMI_TX_BASE_ADDR_CTRL 0x0000 ++#define HDMI_TX_BASE_ADDR_VIDEO 0x0800 ++#define HDMI_TX_BASE_ADDR_AUDIO 0x1000 ++#define HDMI_TX_BASE_ADDR_HDMITX 0x1800 ++#define HDMI_TX_BASE_ADDR_AON 0x4000 ++/* other macro */ ++#define HDMI_FILE_MODE 0777 ++#ifdef OT_ADVCA_FUNCTION_RELEASE ++#define CONFIG_HDMI_PROC_DISABLE ++#define CONFIG_HDMI_DEBUG_DISABLE ++#endif ++ ++#define VERSION_STRING ("[HDMI] Version: [" OT_MPP_VERSION "], Build Time["__DATE__", "__TIME__"]") ++#define hdmi_get_current_id() (get_current()->tgid) ++ ++#define hdmi_err_trace(fmt, ...) ++ ++#define hdmi_warn_trace(fmt, ...) ++ ++#define hdmi_info_trace(fmt, ...) ++ ++#define hdmi_fatal_trace(fmt, ...) ++ ++ ++ ++ ++#ifdef HDMI_LOG_SUPPORT ++#ifndef OT_ADVCA_FUNCTION_RELEASE ++#define hdmi_printk(fmt, args...) printk(fmt, ##args) ++#else ++#define hdmi_printk(fmt, args...) ++#endif ++#else ++#define hdmi_printk(fmt, args...) ++#endif ++ ++#ifdef CONFIG_HDMI_DEBUG_DISABLE ++#define edid_info(fmt...) ++#define edid_warn(fmt...) ++#define edid_err(fmt...) ++#define edid_faital(fmt...) ++#define hdmi_info(fmt...) ++#define hdmi_warn(fmt...) ++#define hdmi_err(fmt...) ++#define hdmi_fatal(fmt...) ++#elif defined(HDMI_LOG_SUPPORT) ++#define edid_info(fmt...) ++#define edid_warn(fmt...) ++#define edid_err(fmt...) ++#define edid_faital(fmt...) ++#define hdmi_info(fmt...) hdmi_info_trace(fmt) ++#define hdmi_warn(fmt...) hdmi_warn_trace(fmt) ++#define hdmi_err(fmt...) hdmi_err_trace(fmt) ++#define hdmi_fatal(fmt...) hdmi_fatal_trace(fmt) ++#else ++#define edid_info(fmt...) hdmi_info_trace(fmt) ++#define edid_warn(fmt...) hdmi_warn_trace(fmt) ++#define edid_err(fmt...) hdmi_err_trace(fmt) ++#define edid_faital(fmt...) hdmi_fatal_trace(fmt) ++#define hdmi_fatal(fmt...) hdmi_fatal_trace(fmt) ++#define hdmi_err(fmt...) hdmi_err_trace(fmt) ++#define hdmi_warn(fmt...) hdmi_warn_trace(fmt) ++#define hdmi_info(fmt...) hdmi_info_trace(fmt) ++#endif ++ ++typedef struct { ++ unsigned int ssc_bypass_div; ++ unsigned int tmds_clk_div; ++} hdmi_crg_cfg; ++ ++void hdmi_tx_reg_write(unsigned int *reg_addr, unsigned int value); ++ ++unsigned int hdmi_tx_reg_read(const unsigned int *reg_addr); ++ ++void hdmi_reg_write_u32(unsigned int reg_addr, unsigned int value); ++ ++unsigned int hdmi_reg_read_u32(unsigned int reg_addr); ++ ++void drv_hdmi_prod_io_cfg_set(void); ++ ++void drv_hdmi_prod_crg_all_reset_set(bool enable); ++ ++void drv_hdmi_prod_crg_gate_set(bool enable); ++ ++void drv_hdmi_prod_crg_phy_reset_set(bool enable); ++ ++void drv_hdmi_prod_crg_phy_reset_get(bool *enable); ++ ++void drv_hdmi_prod_crg_init(void); ++ ++void drv_hdmi_proc_crg_deinit(void); ++ ++void drv_hdmi_hardware_reset(unsigned int id); ++ ++void drv_hdmi_low_power_set(bool enable); ++ ++ ++#define HDMI_REGISTER_SIZE 4 ++#define hdmi_if_fpga_return(ret) ++#define hdmi_if_fpga_return_void() ++typedef enum { ++ HDMI_DEVICE_ID0, ++ HDMI_DEVICE_ID1, ++ HDMI_DEVICE_ID_BUTT ++} hdmi_device_id; ++ ++#ifdef HDMI_SUPPORT_DUAL_CHANNEL ++#define HDMI_ID_MAX HDMI_DEVICE_ID_BUTT ++#else ++#define HDMI_ID_MAX HDMI_DEVICE_ID1 ++#endif ++ ++#endif /* HDMI_PRODUCT_DEFINE_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/ot_board.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/ot_board.h +new file mode 100755 +index 000000000..729a5464c +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/ot_board.h +@@ -0,0 +1,424 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef OT_BOARD_H ++#define OT_BOARD_H ++ ++ ++#define DDR_BUS_FR (310000000) /* ddr bus 频率:310M */ ++ ++#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ ++ ++#define DDRC0_REG_ADDR 0x11140000 ++#define DDRC_REGS_SIZE 0x20000 ++ ++#define CRG_REGS_ADDR 0x11010000 ++#define CRG_REGS_ADDR_OFFSET 0x4500 ++#define CRG_REGS_SIZE (0x10000 - CRG_REGS_ADDR_OFFSET) ++ ++#define SYS_REGS_ADDR 0x11020000 ++#define SYS_REGS_SIZE 0x4000 ++ ++#define MISC_REGS_ADDR 0x11024000 ++#define MISC_REGS_SIZE 0x5000 ++ ++#define IOCFG_REGS_ADDR 0x200F0000 ++#define IOCFG_REGS_SIZE 0x10000 ++ ++#define VOU_REGS_ADDR 0x17A00000 ++#define VOU_REGS_SIZE 0x40000 ++ ++#define VGS0_REGS_ADDR 0x17240000 ++#define VGS1_REGS_ADDR 0x17250000 ++#define VGS_REGS_SIZE 0x10000 ++ ++#define GDC0_BASE_ADDR 0x172c0000 ++#define GDC1_BASE_ADDR 0x172c0000 ++#define GDC_REGS_SIZE 0x10000 ++ ++#define VPSS_REGS_ADDR 0x17900000 ++#define VPSS_REGS_SIZE 0x10000 ++ ++#define VI_CAP_REGS_ADDR 0x17400000 ++ ++#define VDAU_REGS_ADDR 0x170c0000 ++ ++#define OTP_USER_REGS_ADDR 0x10122000 ++#define OTP_USER_REGS_SIZE 0x2000 ++ ++#define VI_ANR_MISC_REGS_ADDR 0x17920000 ++#define VI_ANR_MISC_REGS_SIZE 0x200 ++ ++#define GFBG_SOFT_INT_ADDR 0x1202001c ++ ++#define MIPI_CTRL_REGS_ADDR 0x11310000 ++ ++#define VEDU_0_REGS_ADDR 0x17140000 ++#define VEDU_REGS_SIZE 0x10000 ++ ++#define DIS_REGS_ADDR 0x11200000 ++#define DIS_REGS_SIZE 0x10000 ++ ++#define DIS_SOFTRST_REGS_ADDR (0x3C + MISC_REGS_ADDR) ++#define DIS_SOFTRST_REGS_SIZE 0x100 ++ ++#define AVS_BASE_ADDR 0x17930000 ++#define AVS_REG_SIZE 0x10000 ++ ++#define HEVC0_REGS_ADDR 0x11300000 ++#define HEVC_REGS_SIZE 0x10000 ++ ++#define JPEGU_REGS_ADDR 0x171c0000 ++#define JPEGU_REGS_SIZE 0x10000 ++ ++#define JPEGD_REGS_ADDR (0x17180000) ++#define JPEGD_REGS_SIZE 0x6BF ++ ++#define IVE_REGS_ADDR 0x17000000 ++#define IVE_REGS_SIZE 0x10000 ++#define IVE_CRG_RESET_REGS_ADDR 0x110167C0 ++ ++#define FD_BASE_ADDR 0x11E00000 ++#define FD_REGS_SIZE 0x10000 ++#define FD_CRG_RESET_REGS_ADDR 0x12010070 ++ ++#define DSP0_REGS_ADDR 0x16110000 ++#define DSP1_REGS_ADDR 0x16310000 ++ ++#define DPU_REGS_ADDR 0x17030000 ++ ++#define SVP_MAU_0_REGS_ADDR 0x17030000 ++#define SVP_MAU_0_REGS_SIZE 0x10000 ++ ++#define PQP0_REGS_ADDR 0x15000000 ++#define PQP0_REGS_SIZE 0x10000 ++ ++#define SVP_NPU0_REGS_ADDR 0x15000000 ++#define SVP_NPU0_REGS_SIZE 0x10000 ++ ++#define AIAO_REG_ADDR 0x17c00000 ++#define AIAO_REG_SIZE 0x10000 ++ ++#define ACODEC_REG_ADDR 0x17c40000 ++#define ACODEC_REG_SIZE 0x10000 ++ ++/* Interrupt Request Number */ ++#define VOU_IRQ_NR 191 ++#define VOU1_IRQ_NR 192 ++#define MIPI_IRQ_NR 60 ++#define VI_CAP0_IRQ_NR 92 ++#define VI_PROC0_IRQ_NR 93 ++#define VI_PROC1_IRQ_NR 94 ++#define VPSS_IRQ_NR 158 ++#define TDE_IRQ_NR 66 ++#define VGS0_IRQ_NR 170 ++#define VGS1_IRQ_NR 171 ++#define AIO_IRQ_NR 194 ++#define VEDU_0_IRQ_NR 183 ++#define JPEGU_IRQ_NR 181 ++#define JPEGD_IRQ_NR 179 ++#define HEVCU_IRQ_NR 69 ++#define IVE_IRQ_NR 181 ++#define FD_IRQ_NR 89 ++#define GDC0_IRQ_NR 179 ++#define GDC1_IRQ_NR 179 ++#define DIS_IRQ_NR 83 ++#define AVS_IRQ_NR 184 ++#define SVP_MAU_IRQ_NR0 196 ++#define DPU_RECT_IRQ_NR 225 ++#define DPU_MATCH_IRQ_NR 226 ++#define DPU_POSTPROC_IRQ_NR 227 ++#define VDAU_IRQ_NR 183 ++#define PQP0_NS_IRQ_NR 190 ++#define PQP0_S_IRQ_NR 191 ++#define SVP_NPU0_NS_IRQ_NR 190 ++#define SVP_NPU0_S_IRQ_NR 191 ++ ++#define SYS_PERCTL0_ADDR (0x0 + SYS_REGS_ADDR) ++#define SYS_PERCTL1_ADDR (0x4 + SYS_REGS_ADDR) ++#define SYS_PERCTL2_ADDR (0x8 + SYS_REGS_ADDR) ++#define SYS_PERCTL3_ADDR (0xc + SYS_REGS_ADDR) ++#define SYS_PERCTL4_ADDR (0x10 + SYS_REGS_ADDR) ++#define SYS_PERCTL5_ADDR (0x14 + SYS_REGS_ADDR) ++#define SYS_PERCTL6_ADDR (0x18 + SYS_REGS_ADDR) ++#define SYS_PERCTL7_ADDR (0x1c + SYS_REGS_ADDR) ++#define SYS_PERCTL8_ADDR (0x20 + SYS_REGS_ADDR) ++#define SYS_PERCTL9_ADDR (0x24 + SYS_REGS_ADDR) ++#define SYS_PERCTL10_ADDR (0x28 + SYS_REGS_ADDR) ++#define SYS_PERCTL11_ADDR (0x2C + SYS_REGS_ADDR) ++#define SYS_PERCTL12_ADDR (0x30 + SYS_REGS_ADDR) ++#define SYS_PERCTL13_ADDR (0x34 + SYS_REGS_ADDR) ++#define SYS_PERCTL14_ADDR (0x38 + SYS_REGS_ADDR) ++#define SYS_PERCTL15_ADDR (0x3C + SYS_REGS_ADDR) ++#define SYS_PERCTL16_ADDR (0x40 + SYS_REGS_ADDR) ++#define SYS_PERCTL17_ADDR (0x44 + SYS_REGS_ADDR) ++#define SYS_PERCTL18_ADDR (0x48 + SYS_REGS_ADDR) ++#define SYS_PERCTL19_ADDR (0x4c + SYS_REGS_ADDR) ++#define SYS_PERCTL20_ADDR (0x50 + SYS_REGS_ADDR) ++#define SYS_PERCTL21_ADDR (0x54 + SYS_REGS_ADDR) ++#define SYS_PERCTL22_ADDR (0x58 + SYS_REGS_ADDR) ++#define SYS_PERCTL23_ADDR (0x5c + SYS_REGS_ADDR) ++#define SYS_PERCTL24_ADDR (0x60 + SYS_REGS_ADDR) ++#define SYS_PERCTL25_ADDR (0x64 + SYS_REGS_ADDR) ++#define SYS_PERCTL26_ADDR (0x68 + SYS_REGS_ADDR) ++#define SYS_PERCTL27_ADDR (0x6C + SYS_REGS_ADDR) ++#define SYS_PERCTL28_ADDR (0x70 + SYS_REGS_ADDR) ++#define SYS_PERCTL29_ADDR (0x74 + SYS_REGS_ADDR) ++#define SYS_PERCTL30_ADDR (0x78 + SYS_REGS_ADDR) ++#define SYS_PERCTL31_ADDR (0x7C + SYS_REGS_ADDR) ++#define SYS_PERCTL32_ADDR (0x80 + SYS_REGS_ADDR) ++#define SYS_PERCTL33_ADDR (0x84 + SYS_REGS_ADDR) ++#define SYS_PERCTL34_ADDR (0x88 + SYS_REGS_ADDR) ++#define SYS_PERCTL35_ADDR (0x8C + SYS_REGS_ADDR) ++#define SYS_PERCTL36_ADDR (0x90 + SYS_REGS_ADDR) ++#define SYS_PERCTL37_ADDR (0x94 + SYS_REGS_ADDR) ++#define SYS_PERCTL38_ADDR (0x98 + SYS_REGS_ADDR) ++#define SYS_PERCTL39_ADDR (0x9C + SYS_REGS_ADDR) ++#define SYS_PERCTL40_ADDR (0xa0 + SYS_REGS_ADDR) ++#define SYS_PERCTL41_ADDR (0xa4 + SYS_REGS_ADDR) ++#define SYS_PERCTL42_ADDR (0xa8 + SYS_REGS_ADDR) ++#define SYS_PERCTL43_ADDR (0xaC + SYS_REGS_ADDR) ++#define SYS_PERCTL44_ADDR (0xb0 + SYS_REGS_ADDR) ++#define SYS_PERCTL45_ADDR (0xb4 + SYS_REGS_ADDR) ++#define SYS_PERCTL46_ADDR (0xb8 + SYS_REGS_ADDR) ++#define SYS_PERCTL47_ADDR (0xbC + SYS_REGS_ADDR) ++#define SYS_PERCTL48_ADDR (0xc0 + SYS_REGS_ADDR) ++#define SYS_PERCTL49_ADDR (0xc4 + SYS_REGS_ADDR) ++#define SYS_PERCTL50_ADDR (0xc8 + SYS_REGS_ADDR) ++#define SYS_PERCTL51_ADDR (0xcC + SYS_REGS_ADDR) ++#define SYS_PERCTL52_ADDR (0xd0 + SYS_REGS_ADDR) ++#define SYS_PERCTL53_ADDR (0xd4 + SYS_REGS_ADDR) ++#define SYS_PERCTL54_ADDR (0xd8 + SYS_REGS_ADDR) ++#define SYS_PERCTL55_ADDR (0xdC + SYS_REGS_ADDR) ++#define SYS_PERCTL56_ADDR (0xe0 + SYS_REGS_ADDR) ++#define SYS_PERCTL57_ADDR (0xe4 + SYS_REGS_ADDR) ++#define SYS_PERCTL58_ADDR (0xe8 + SYS_REGS_ADDR) ++#define SYS_PERCTL59_ADDR (0xeC + SYS_REGS_ADDR) ++#define SYS_PERCTL60_ADDR (0xf0 + SYS_REGS_ADDR) ++#define SYS_PERCTL61_ADDR (0xf4 + SYS_REGS_ADDR) ++#define SYS_PERCTL62_ADDR (0xf8 + SYS_REGS_ADDR) ++#define SYS_PERCTL63_ADDR (0xfC + SYS_REGS_ADDR) ++#define SYS_PERCTL64_ADDR (0x100 + SYS_REGS_ADDR) ++#define SYS_PERCTL65_ADDR (0x104 + SYS_REGS_ADDR) ++#define SYS_PERCTL66_ADDR (0x108 + SYS_REGS_ADDR) ++#define SYS_PERCTL67_ADDR (0x10c + SYS_REGS_ADDR) ++#define SYS_PERCTL68_ADDR (0x110 + SYS_REGS_ADDR) ++#define SYS_PERCTL69_ADDR (0x114 + SYS_REGS_ADDR) ++#define SYS_PERCTL70_ADDR (0x118 + SYS_REGS_ADDR) ++#define SYS_PERCTL71_ADDR (0x11c + SYS_REGS_ADDR) ++#define SYS_PERCTL72_ADDR (0x120 + SYS_REGS_ADDR) ++#define SYS_PERCTL73_ADDR (0x124 + SYS_REGS_ADDR) ++#define SYS_PERCTL74_ADDR (0x128 + SYS_REGS_ADDR) ++#define SYS_PERCTL75_ADDR (0x12C + SYS_REGS_ADDR) ++#define SYS_PERCTL76_ADDR (0x130 + SYS_REGS_ADDR) ++#define SYS_PERCTL77_ADDR (0x134 + SYS_REGS_ADDR) ++#define SYS_PERCTL78_ADDR (0x138 + SYS_REGS_ADDR) ++#define SYS_PERCTL79_ADDR (0x13C + SYS_REGS_ADDR) ++#define SYS_PERCTL80_ADDR (0x140 + SYS_REGS_ADDR) ++#define SYS_PERCTL81_ADDR (0x144 + SYS_REGS_ADDR) ++#define SYS_PERCTL82_ADDR (0x148 + SYS_REGS_ADDR) ++#define SYS_PERCTL83_ADDR (0x14c + SYS_REGS_ADDR) ++#define SYS_PERCTL84_ADDR (0x150 + SYS_REGS_ADDR) ++#define SYS_PERCTL85_ADDR (0x154 + SYS_REGS_ADDR) ++#define SYS_PERCTL86_ADDR (0x158 + SYS_REGS_ADDR) ++#define SYS_PERCTL87_ADDR (0x15c + SYS_REGS_ADDR) ++#define SYS_PERCTL88_ADDR (0x160 + SYS_REGS_ADDR) ++#define SYS_PERCTL89_ADDR (0x164 + SYS_REGS_ADDR) ++#define SYS_PERCTL90_ADDR (0x168 + SYS_REGS_ADDR) ++#define SYS_PERCTL91_ADDR (0x16C + SYS_REGS_ADDR) ++#define SYS_PERCTL92_ADDR (0x170 + SYS_REGS_ADDR) ++#define SYS_PERCTL93_ADDR (0x174 + SYS_REGS_ADDR) ++#define SYS_PERCTL94_ADDR (0x178 + SYS_REGS_ADDR) ++#define SYS_PERCTL95_ADDR (0x17C + SYS_REGS_ADDR) ++#define SYS_PERCTL96_ADDR (0x180 + SYS_REGS_ADDR) ++#define SYS_PERCTL97_ADDR (0x184 + SYS_REGS_ADDR) ++#define SYS_PERCTL98_ADDR (0x188 + SYS_REGS_ADDR) ++#define SYS_PERCTL99_ADDR (0x18C + SYS_REGS_ADDR) ++#define SYS_PERCTL100_ADDR (0x190 + SYS_REGS_ADDR) ++#define SYS_PERCTL101_ADDR (0x194 + SYS_REGS_ADDR) ++#define SYS_PERCTL102_ADDR (0x198 + SYS_REGS_ADDR) ++#define SYS_PERCTL103_ADDR (0x19C + SYS_REGS_ADDR) ++#define SYS_PERCTL104_ADDR (0x1a0 + SYS_REGS_ADDR) ++#define SYS_PERCTL105_ADDR (0x1a4 + SYS_REGS_ADDR) ++#define SYS_PERCTL106_ADDR (0x1a8 + SYS_REGS_ADDR) ++#define SYS_PERCTL107_ADDR (0x1aC + SYS_REGS_ADDR) ++#define SYS_PERCTL108_ADDR (0x1b0 + SYS_REGS_ADDR) ++#define SYS_PERCTL109_ADDR (0x1b4 + SYS_REGS_ADDR) ++#define SYS_PERCTL110_ADDR (0x1b8 + SYS_REGS_ADDR) ++#define SYS_PERCTL111_ADDR (0x1bC + SYS_REGS_ADDR) ++#define SYS_PERCTL112_ADDR (0x1c0 + SYS_REGS_ADDR) ++#define SYS_PERCTL113_ADDR (0x1c4 + SYS_REGS_ADDR) ++#define SYS_PERCTL114_ADDR (0x1c8 + SYS_REGS_ADDR) ++#define SYS_PERCTL115_ADDR (0x1cC + SYS_REGS_ADDR) ++#define SYS_PERCTL116_ADDR (0x1d0 + SYS_REGS_ADDR) ++#define SYS_PERCTL117_ADDR (0x1d4 + SYS_REGS_ADDR) ++#define SYS_PERCTL118_ADDR (0x1d8 + SYS_REGS_ADDR) ++#define SYS_PERCTL119_ADDR (0x1dC + SYS_REGS_ADDR) ++#define SYS_PERCTL120_ADDR (0x1e0 + SYS_REGS_ADDR) ++#define SYS_PERCTL121_ADDR (0x1e4 + SYS_REGS_ADDR) ++#define SYS_PERCTL122_ADDR (0x1e8 + SYS_REGS_ADDR) ++#define SYS_PERCTL123_ADDR (0x1eC + SYS_REGS_ADDR) ++#define SYS_PERCTL124_ADDR (0x1f0 + SYS_REGS_ADDR) ++#define SYS_PERCTL125_ADDR (0x1f4 + SYS_REGS_ADDR) ++#define SYS_PERCTL126_ADDR (0x1f8 + SYS_REGS_ADDR) ++#define SYS_PERCTL127_ADDR (0x1fC + SYS_REGS_ADDR) ++ ++#define CRG_PERCTL_PLL96_ADDR (0x0180 + CRG_REGS_ADDR) ++#define CRG_PERCTL_PLL97_ADDR (0x0184 + CRG_REGS_ADDR) ++#define CRG_PERCTL_PLL224_ADDR (0x0380 + CRG_REGS_ADDR) ++#define CRG_PERCTL_PLL225_ADDR (0x0384 + CRG_REGS_ADDR) ++ ++#define CRG_PERCTL_PLL0_ADDR (0x0000 + CRG_REGS_ADDR) ++#define CRG_PERCTL_PLL1_ADDR (0x0004 + CRG_REGS_ADDR) ++ ++#define CRG_PERCTL4448_ADDR (0x4580 + CRG_REGS_ADDR) ++#define CRG_PERCTL4496_ADDR (0x4640 + CRG_REGS_ADDR) ++#define CRG_PERCTL4498_ADDR (0x4648 + CRG_REGS_ADDR) ++#define CRG_PERCTL4688_ADDR (0x4940 + CRG_REGS_ADDR) ++#define CRG_PERCTL4768_ADDR (0x4A80 + CRG_REGS_ADDR) ++#define CRG_PERCTL4896_ADDR (0x4C80 + CRG_REGS_ADDR) ++#define CRG_PERCTL4897_ADDR (0x4C84 + CRG_REGS_ADDR) ++#define CRG_PERCTL4898_ADDR (0x4C88 + CRG_REGS_ADDR) ++#define CRG_PERCTL5029_ADDR (0x4E94 + CRG_REGS_ADDR) ++#define CRG_PERCTL6464_ADDR (0x6500 + CRG_REGS_ADDR) ++#define CRG_PERCTL6470_ADDR (0x6518 + CRG_REGS_ADDR) ++#define CRG_PERCTL6560_ADDR (0x6680 + CRG_REGS_ADDR) ++#define CRG_PERCTL6561_ADDR (0x6684 + CRG_REGS_ADDR) ++#define CRG_PERCTL6592_ADDR (0x6700 + CRG_REGS_ADDR) ++#define CRG_PERCTL6624_ADDR (0x6780 + CRG_REGS_ADDR) ++#define CRG_PERCTL6625_ADDR (0x6784 + CRG_REGS_ADDR) ++#define CRG_PERCTL6640_ADDR (0x67C0 + CRG_REGS_ADDR) ++#define CRG_PERCTL6704_ADDR (0x68C0 + CRG_REGS_ADDR) ++#define CRG_PERCTL7248_ADDR (0x7140 + CRG_REGS_ADDR) ++#define CRG_PERCTL7256_ADDR (0x7160 + CRG_REGS_ADDR) ++#define CRG_PERCTL7264_ADDR (0x7180 + CRG_REGS_ADDR) ++#define CRG_PERCTL7376_ADDR (0x7340 + CRG_REGS_ADDR) ++#define CRG_PERCTL7408_ADDR (0x73C0 + CRG_REGS_ADDR) ++#define CRG_PERCTL7568_ADDR (0x7640 + CRG_REGS_ADDR) ++#define CRG_PERCTL8144_ADDR (0x7F40 + CRG_REGS_ADDR) ++#define CRG_PERCTL8152_ADDR (0x7F60 + CRG_REGS_ADDR) ++#define CRG_PERCTL8336_ADDR (0x8240 + CRG_REGS_ADDR) ++#define CRG_PERCTL8338_ADDR (0x8248 + CRG_REGS_ADDR) ++#define CRG_PERCTL8340_ADDR (0x8250 + CRG_REGS_ADDR) ++#define CRG_PERCTL8341_ADDR (0x8254 + CRG_REGS_ADDR) ++#define CRG_PERCTL8342_ADDR (0x8258 + CRG_REGS_ADDR) ++#define CRG_PERCTL8346_ADDR (0x8268 + CRG_REGS_ADDR) ++#define CRG_PERCTL8348_ADDR (0x8270 + CRG_REGS_ADDR) ++#define CRG_PERCTL8349_ADDR (0x8274 + CRG_REGS_ADDR) ++#define CRG_PERCTL8350_ADDR (0x8278 + CRG_REGS_ADDR) ++#define CRG_PERCTL8351_ADDR (0x827C + CRG_REGS_ADDR) ++#define CRG_PERCTL8352_ADDR (0x8280 + CRG_REGS_ADDR) ++#define CRG_PERCTL8528_ADDR (0x8540 + CRG_REGS_ADDR) ++#define CRG_PERCTL8536_ADDR (0x8560 + CRG_REGS_ADDR) ++#define CRG_PERCTL8544_ADDR (0x8580 + CRG_REGS_ADDR) ++#define CRG_PERCTL8552_ADDR (0x85A0 + CRG_REGS_ADDR) ++#define CRG_PERCTL8560_ADDR (0x85C0 + CRG_REGS_ADDR) ++#define CRG_PERCTL8568_ADDR (0x85E0 + CRG_REGS_ADDR) ++#define CRG_PERCTL8576_ADDR (0x8600 + CRG_REGS_ADDR) ++#define CRG_PERCTL8584_ADDR (0x8620 + CRG_REGS_ADDR) ++#define CRG_PERCTL8592_ADDR (0x8640 + CRG_REGS_ADDR) ++#define CRG_PERCTL8784_ADDR (0x8940 + CRG_REGS_ADDR) ++#define CRG_PERCTL8792_ADDR (0x8960 + CRG_REGS_ADDR) ++#define CRG_PERCTL8800_ADDR (0x8980 + CRG_REGS_ADDR) ++#define CRG_PERCTL8808_ADDR (0x89A0 + CRG_REGS_ADDR) ++#define CRG_PERCTL9296_ADDR (0x9140 + CRG_REGS_ADDR) ++#define CRG_PERCTL9297_ADDR (0x9144 + CRG_REGS_ADDR) ++#define CRG_PERCTL9298_ADDR (0x9148 + CRG_REGS_ADDR) ++#define CRG_PERCTL9300_ADDR (0x9150 + CRG_REGS_ADDR) ++#define CRG_PERCTL9301_ADDR (0x9154 + CRG_REGS_ADDR) ++#define CRG_PERCTL9302_ADDR (0x9158 + CRG_REGS_ADDR) ++#define CRG_PERCTL9303_ADDR (0x915C + CRG_REGS_ADDR) ++#define CRG_PERCTL9304_ADDR (0x9160 + CRG_REGS_ADDR) ++#define CRG_PERCTL9305_ADDR (0x9164 + CRG_REGS_ADDR) ++#define CRG_PERCTL9313_ADDR (0x9184 + CRG_REGS_ADDR) ++#define CRG_PERCTL9321_ADDR (0x91A4 + CRG_REGS_ADDR) ++#define CRG_PERCTL9329_ADDR (0x91C4 + CRG_REGS_ADDR) ++#define CRG_PERCTL9680_ADDR (0x9740 + CRG_REGS_ADDR) ++#define CRG_PERCTL9681_ADDR (0x9744 + CRG_REGS_ADDR) ++#define CRG_PERCTL9688_ADDR (0x9760 + CRG_REGS_ADDR) ++#define CRG_PERCTL9689_ADDR (0x9764 + CRG_REGS_ADDR) ++#define CRG_PERCTL9936_ADDR (0x9B40 + CRG_REGS_ADDR) ++#define CRG_PERCTL9937_ADDR (0x9B44 + CRG_REGS_ADDR) ++#define CRG_PERCTL9944_ADDR (0x9B60 + CRG_REGS_ADDR) ++#define CRG_PERCTL9945_ADDR (0x9B64 + CRG_REGS_ADDR) ++#define CRG_PERCTL9952_ADDR (0x9B80 + CRG_REGS_ADDR) ++#define CRG_PERCTL9953_ADDR (0x9B84 + CRG_REGS_ADDR) ++#define CRG_PERCTL10064_ADDR (0x9D40 + CRG_REGS_ADDR) ++#define CRG_PERCTL10065_ADDR (0x9D44 + CRG_REGS_ADDR) ++#define CRG_PERCTL10128_ADDR (0x9E40 + CRG_REGS_ADDR) ++#define CRG_PERCTL10129_ADDR (0x9E44 + CRG_REGS_ADDR) ++#define CRG_PERCTL10160_ADDR (0x9EC0 + CRG_REGS_ADDR) ++#define CRG_PERCTL10161_ADDR (0x9EC4 + CRG_REGS_ADDR) ++#define CRG_PERCTL10168_ADDR (0x9EE0 + CRG_REGS_ADDR) ++#define CRG_PERCTL10169_ADDR (0x9EE4 + CRG_REGS_ADDR) ++#define CRG_PERCTL10256_ADDR (0xA040 + CRG_REGS_ADDR) ++#define CRG_PERCTL10784_ADDR (0xA880 + CRG_REGS_ADDR) ++#define CRG_PERCTL10912_ADDR (0xAA80 + CRG_REGS_ADDR) ++#define CRG_PERCTL12288_ADDR (0xC000 + CRG_REGS_ADDR) ++#define CRG_PERCTL12289_ADDR (0xC004 + CRG_REGS_ADDR) ++#define CRG_PERCTL12290_ADDR (0xC008 + CRG_REGS_ADDR) ++ ++#define VI_PORT_CLK_OFFSET 12 ++#define VI_PORT_CLK_MASK 0x7 ++ ++#define MISC_CTL12C_ADDR (0x12C + MISC_REGS_ADDR) ++#define MISC_CTL98_ADDR (0x98 + MISC_REGS_ADDR) ++#define MISC_CTL9C_ADDR (0x9C + MISC_REGS_ADDR) ++#define MISC_CTLAC_ADDR (0xAC + MISC_REGS_ADDR) ++#define MISC_CTLB0_ADDR (0xB0 + MISC_REGS_ADDR) ++#define MISC_CTL2014_ADDR (0x2014 + MISC_REGS_ADDR) ++ ++#define MISC_VICTRL_ADDR (0x009c + MISC_REGS_ADDR) ++#define MISC_VICTRL1_ADDR (0x1000 + MISC_REGS_ADDR) ++ ++#define SYS_VI_DIV_SEL2 0x00 /* 2 division */ ++#define SYS_VI_DIV_SEL4 0x01 /* 4 division */ ++#define SYS_VI_DIV_SEL1 0x02 /* no division */ ++ ++#define SYS_VO_DIV_SEL1 0x00 /* 1 division */ ++#define SYS_VO_DIV_SEL2 0x01 /* 2 division */ ++#define SYS_VO_DIV_SEL4 0x02 /* 4 division */ ++ ++#define SYS_AIO_SAMPLE_CLK16 0x0 /* 16 division */ ++#define SYS_AIO_SAMPLE_CLK32 0x01 /* 32 division */ ++#define SYS_AIO_SAMPLE_CLK48 0x02 /* 48 division */ ++#define SYS_AIO_SAMPLE_CLK64 0x03 /* 64 division */ ++#define SYS_AIO_SAMPLE_CLK128 0x04 /* 128 division */ ++#define SYS_AIO_SAMPLE_CLK256 0x05 /* 256 division */ ++#define SYS_AIO_SAMPLE_CLK320 0x06 /* 320 division */ ++#define SYS_AIO_SAMPLE_CLK384 0x07 /* 384 division */ ++ ++#define SYS_AIO_BS_CLK1 0x00 /* 1 division */ ++#define SYS_AIO_BS_CLK2 0x02 /* 2 division */ ++#define SYS_AIO_BS_CLK3 0x01 /* 3 division */ ++#define SYS_AIO_BS_CLK4 0x03 /* 4 division */ ++#define SYS_AIO_BS_CLK6 0x04 /* 6 division */ ++#define SYS_AIO_BS_CLK8 0x05 /* 8 division */ ++#define SYS_AIO_BS_CLK12 0x06 /* 12 division */ ++#define SYS_AIO_BS_CLK16 0x07 /* 16 division */ ++#define SYS_AIO_BS_CLK24 0x08 /* 24 division */ ++#define SYS_AIO_BS_CLK32 0x09 /* 32 division */ ++#define SYS_AIO_BS_CLK48 0x0a /* 48 division */ ++#define SYS_AIO_BS_CLK64 0x0b /* 64 division */ ++ ++#define MIPI_RX_CFG_ADDR (0x0 + VI_ANR_MISC_REGS_ADDR) ++ ++#define OTP_USER_LOCKABLE0 (0x58 + OTP_USER_REGS_ADDR) ++ ++#endif /* OT_BOARD_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.c b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.c +new file mode 100755 +index 000000000..b48e6d53f +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.c +@@ -0,0 +1,251 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#include "hdmi_reg_crg.h" ++#include "hdmi_product_define.h" ++ ++volatile hdmi_reg_crg *g_crg_regs = NULL; ++ ++int hdmi_reg_crg_init(void) ++{ ++ ++ if (g_crg_regs != NULL) { ++ return 0; ++ } ++ g_crg_regs = (volatile hdmi_reg_crg *)ioremap(HDMI_CRG_ADDR, sizeof(hdmi_reg_crg)); ++ if (g_crg_regs == NULL) { ++ printk("crg addr ioremap failed!\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int hdmi_reg_crg_deinit(void) ++{ ++ if (g_crg_regs != NULL) { ++ iounmap((void *)g_crg_regs); ++ g_crg_regs = NULL; ++ } ++ return 0; ++} ++ ++void hdmi_reg_ctrl_osc_24m_cken_set(unsigned char hdmitx_ctrl_osc_24m_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_osc_24m_cken = hdmitx_ctrl_osc_24m_cken; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctrl_cec_cken_set(unsigned char hdmitx_ctrl_cec_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_cec_cken = hdmitx_ctrl_cec_cken; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctrl_os_cken_set(unsigned char hdmitx_ctrl_os_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_os_cken = hdmitx_ctrl_os_cken; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctrl_as_cken_set(unsigned char as_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_as_cken = as_cken; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctrl_bus_srst_req_set(unsigned char bus_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_bus_srst_req = bus_srst_req; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctrl_srst_req_set(unsigned char srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_srst_req = srst_req; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctrl_cec_srst_req_set(unsigned char cec_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8144 crg8144; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); ++ crg8144.u32 = hdmi_tx_reg_read(reg_addr); ++ crg8144.bits.hdmitx_ctrl_cec_srst_req = cec_srst_req; ++ hdmi_tx_reg_write(reg_addr, crg8144.u32); ++ ++ return; ++} ++ ++void hdmi_reg_hdmitx_phy_tmds_cken_set(unsigned char phy_tmds_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.hdmitx_phy_tmds_cken = phy_tmds_cken; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++void hdmi_reg_hdmitx_phy_modclk_cken_set(unsigned char phy_modclk_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.hdmitx_phy_modclk_cken = phy_modclk_cken; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ac_ctrl_modclk_cken_set(unsigned char ac_ctrl_modclk_cken) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.ac_ctrl_modclk_cken = ac_ctrl_modclk_cken; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++void hdmi_reg_phy_srst_req_set(unsigned char phy_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.hdmitx_phy_srst_req = phy_srst_req; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_phy_srst_req_get(void) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ return crg_8152.bits.hdmitx_phy_srst_req; ++} ++ ++void hdmi_reg_phy_bus_srst_req_set(unsigned char bus_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.hdmitx_phy_bus_srst_req = bus_srst_req; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ac_ctrl_srst_req_set(unsigned char ac_ctrl_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.ac_ctrl_srst_req = ac_ctrl_srst_req; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ac_ctrl_bus_srst_req_set(unsigned char ac_ctrl_bus_srst_req) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.ac_ctrl_bus_srst_req = ac_ctrl_bus_srst_req; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} ++ ++void hdmi_reg_phy_clk_pctrl_set(unsigned char clk_pctrl) ++{ ++ unsigned int *reg_addr = NULL; ++ peri_crg8152 crg_8152; ++ ++ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); ++ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); ++ crg_8152.bits.hdmitx_phy_clk_pctrl = clk_pctrl; ++ hdmi_tx_reg_write(reg_addr, crg_8152.u32); ++ ++ return; ++} +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.h +new file mode 100755 +index 000000000..6f759f814 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.h +@@ -0,0 +1,79 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HDMI_REG_CRG_H ++#define HDMI_REG_CRG_H ++ ++ ++typedef union { ++ struct { ++ unsigned int rsv_0 : 2; /* [1..0] */ ++ unsigned int hdmitx_ctrl_osc_24m_cken : 1; /* [2] */ ++ unsigned int hdmitx_ctrl_cec_cken : 1; /* [3] */ ++ unsigned int hdmitx_ctrl_os_cken : 1; /* [4] */ ++ unsigned int hdmitx_ctrl_as_cken : 1; /* [5] */ ++ unsigned int hdmitx_ctrl_bus_srst_req : 1; /* [6] */ ++ unsigned int hdmitx_ctrl_srst_req : 1; /* [7] */ ++ unsigned int hdmitx_ctrl_cec_srst_req : 1; /* [8] */ ++ unsigned int rsv_1 : 23; /* [31..9] */ ++ } bits; ++ unsigned int u32; ++} peri_crg8144; ++ ++typedef union { ++ struct { ++ unsigned int hdmitx_phy_tmds_cken : 1; /* [0] */ ++ unsigned int hdmitx_phy_modclk_cken : 1; /* [1] */ ++ unsigned int ac_ctrl_modclk_cken : 1; /* [2] */ ++ unsigned int rsv_0 : 1; /* [3] */ ++ unsigned int hdmitx_phy_srst_req : 1; /* [4] */ ++ unsigned int hdmitx_phy_bus_srst_req : 1; /* [5] */ ++ unsigned int ac_ctrl_srst_req : 1; /* [6] */ ++ unsigned int ac_ctrl_bus_srst_req : 1; /* [7] */ ++ unsigned int hdmitx_phy_clk_pctrl : 1; /* [8] */ ++ unsigned int rsv_1 : 23; /* [31..9] */ ++ } bits; ++ unsigned int u32; ++} peri_crg8152; ++ ++typedef struct { ++ volatile peri_crg8144 crg8144; /* 0x7F40 */ ++ volatile unsigned int rsv[7]; /* 0x7F44~0x0x7F5C */ ++ volatile peri_crg8152 crg8152; /* 0x7F60 */ ++} hdmi_reg_crg; ++ ++int hdmi_reg_crg_init(void); ++int hdmi_reg_crg_deinit(void); ++void hdmi_reg_ctrl_osc_24m_cken_set(unsigned char hdmitx_ctrl_osc_24m_cken); ++void hdmi_reg_ctrl_cec_cken_set(unsigned char hdmitx_ctrl_cec_cken); ++void hdmi_reg_ctrl_os_cken_set(unsigned char hdmitx_ctrl_os_cken); ++void hdmi_reg_ctrl_as_cken_set(unsigned char hdmitx_ctrl_as_cken); ++void hdmi_reg_ctrl_bus_srst_req_set(unsigned char hdmitx_ctrl_bus_srst_req); ++void hdmi_reg_ctrl_srst_req_set(unsigned char hdmitx_ctrl_srst_req); ++void hdmi_reg_ctrl_cec_srst_req_set(unsigned char hdmitx_ctrl_cec_srst_req); ++void hdmi_reg_hdmitx_phy_tmds_cken_set(unsigned char phy_tmds_cken); ++void hdmi_reg_hdmitx_phy_modclk_cken_set(unsigned char phy_modclk_cken); ++void hdmi_reg_ac_ctrl_modclk_cken_set(unsigned char ac_ctrl_modclk_cken); ++void hdmi_reg_phy_srst_req_set(unsigned char hdmitx_phy_srst_req); ++unsigned char hdmi_reg_phy_srst_req_get(void); ++void hdmi_reg_phy_bus_srst_req_set(unsigned char hdmitx_phy_bus_srst_req); ++void hdmi_reg_ac_ctrl_srst_req_set(unsigned char ac_ctrl_srst_req); ++void hdmi_reg_ac_ctrl_bus_srst_req_set(unsigned char ac_ctrl_bus_srst_req); ++void hdmi_reg_phy_clk_pctrl_set(unsigned char hdmitx_phy_clk_pctrl); ++#endif ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.c b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.c +new file mode 100755 +index 000000000..736bb0220 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.c +@@ -0,0 +1,1056 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#include "hdmi_reg_dphy.h" ++#include "hdmi_product_define.h" ++ ++static volatile hdmitx21_dphy_reg_type *g_hdmitx_dphy_regs[HDMI_ID_MAX] = {NULL}; ++ ++int hdmi_reg_tx_phy_init(unsigned int id, char *addr) ++{ ++ ++ g_hdmitx_dphy_regs[id] = (hdmitx21_dphy_reg_type *)(addr); ++ return 0; ++} ++ ++unsigned int *hdmi_reg_tx_get_phy_addr(unsigned int id) ++{ ++ ++ return (unsigned int *)g_hdmitx_dphy_regs[id]; ++} ++ ++int hdmi_reg_tx_phy_deinit(unsigned int id) ++{ ++ ++ if (g_hdmitx_dphy_regs[id] != NULL) { ++ g_hdmitx_dphy_regs[id] = NULL; ++ } ++ return 0; ++} ++ ++static void hdmi21_tx_reg_write(unsigned int *reg_addr, unsigned int value) ++{ ++ ++ *(volatile unsigned int *)reg_addr = value; ++ return; ++} ++ ++static unsigned int hdmi21_tx_reg_read(const unsigned int *reg_addr) ++{ ++ ++ return *(volatile unsigned int *)(reg_addr); ++} ++ ++void hdmi_reg_stb_cs_en_set(unsigned int id, unsigned short stb_cs_en) ++{ ++ unsigned int *reg_addr = NULL; ++ phy_csen csen; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_cs_en.u32); ++ csen.u32 = hdmi21_tx_reg_read(reg_addr); ++ csen.bits.stb_cs_en = stb_cs_en; ++ hdmi21_tx_reg_write(reg_addr, csen.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_wen_set(unsigned int id, unsigned char stb_wen) ++{ ++ unsigned int *reg_addr = NULL; ++ phy_wr tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_write_en.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.stb_wen = stb_wen; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_resetn_set(unsigned int id, unsigned char reg_resetn) ++{ ++ unsigned int *reg_addr = NULL; ++ resetn tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_reset.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.resetn = reg_resetn; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_resetn_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ resetn tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_reset.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ ++ return tmp.bits.resetn; ++} ++ ++void hdmi_reg_src_enable_set(unsigned int id, unsigned char src_enable) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcparam tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.src_enable = src_enable; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_wdata_set(unsigned int id, unsigned char stb_wdata) ++{ ++ unsigned int *reg_addr = NULL; ++ phy_wdata wdata; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_wdata.u32); ++ wdata.u32 = hdmi21_tx_reg_read(reg_addr); ++ wdata.bits.stb_wdata = stb_wdata; ++ hdmi21_tx_reg_write(reg_addr, wdata.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fcg_lock_en_set(unsigned int id, unsigned char up_fcg_lock_en) ++{ ++ unsigned int *reg_addr = NULL; ++ fcgset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fcg_lock_en = up_fcg_lock_en; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_addr_set(unsigned int id, unsigned char stb_addr) ++{ ++ unsigned int *reg_addr = NULL; ++ phy_addr tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_addr.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.stb_addr = stb_addr; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_stb_rdata_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ phy_rdata rdata; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_rdata.u32); ++ rdata.u32 = hdmi21_tx_reg_read(reg_addr); ++ ++ return rdata.bits.stb_rdata; ++} ++ ++void hdmi_reg_src_lock_cnt_set(unsigned int id, unsigned char src_lock_cnt) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcparam tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.src_lock_cnt = src_lock_cnt; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_src_lock_val_set(unsigned int id, unsigned char src_lock_val) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcparam tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.src_lock_val = src_lock_val; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_src_freq_ext_set(unsigned int id, unsigned short src_freq_ext) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcfreq tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.src_freq_ext = src_freq_ext; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fdsrcfreq_unused2_set(unsigned int id, unsigned char fdsrcfreq_unused_2) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcfreq tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fdsrcfreq_unused_2 = fdsrcfreq_unused_2; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_txfifoset0_unused_set(unsigned int id, unsigned char txfifoset0_unused) ++{ ++ unsigned int *reg_addr = NULL; ++ txfifoset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->tx_fifo_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.txfifoset0_unused = txfifoset0_unused; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_src_freq_opt_set(unsigned int id, unsigned char src_freq_opt) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcfreq tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.src_freq_opt = src_freq_opt; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fdsrcfreq_unused1_set(unsigned int id, unsigned char fdsrcfreq_unused_1) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcfreq tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fdsrcfreq_unused_1 = fdsrcfreq_unused_1; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_src_cnt_opt_set(unsigned int id, unsigned char src_cnt_opt) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcfreq tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.src_cnt_opt = src_cnt_opt; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++unsigned int hdmi_reg_src_cnt_out_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcres tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_res.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ ++ return tmp.bits.src_cnt_out; ++} ++ ++unsigned char hdmi_reg_src_det_stat_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcres tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_res.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ ++ return tmp.bits.src_det_stat; ++} ++ ++void hdmi_reg_clkdet_sel_set(unsigned int id, unsigned char i_clkdet_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ fcopt tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_opt.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.i_clkdet_sel = i_clkdet_sel; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_up_sampler_ratio_sel_set(unsigned int id, unsigned char up_sampler_ratio_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ fcdstepsetl tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_dstep_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.up_sampler_ratio_sel = up_sampler_ratio_sel; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fcdstepset_unused_set(unsigned int id, unsigned char fcdstepset_unused) ++{ ++ unsigned int *reg_addr = NULL; ++ fcdstepsetl tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_dstep_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fcdstepset_unused = fcdstepset_unused; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_divn_h20_set(unsigned int id, unsigned char up_divn_h20) ++{ ++ unsigned int *reg_addr = NULL; ++ fcdstepsetl tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_dstep_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.divn_h20 = up_divn_h20; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_en_sdm_set(unsigned int id, unsigned char en_sdm) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sdm = en_sdm; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mode_en_set(unsigned int id, unsigned char reg_hdmi_mode_en) ++{ ++ unsigned int *reg_addr = NULL; ++ hdmi_mode mode; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_hdmi_mode.u32); ++ mode.u32 = hdmi21_tx_reg_read(reg_addr); ++ mode.bits.reg_hdmi_mode_en = reg_hdmi_mode_en; ++ hdmi21_tx_reg_write(reg_addr, mode.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_en_sdm_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ ++ return tmp.bits.sdm; ++} ++ ++void hdmi_reg_en_mod_set(unsigned int id, unsigned char en_mod) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.mod = en_mod; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_en_mod_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ return tmp.bits.mod; ++} ++ ++void hdmi_reg_en_ctrl_set(unsigned int id, unsigned char en_ctrl) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.ctrl = en_ctrl; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++unsigned char hdmi_reg_en_ctrl_get(unsigned int id) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ ++ return tmp.bits.ctrl; ++} ++ ++void hdmi_reg_init_set(unsigned int id, unsigned char init) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.init = init; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mod_n_set(unsigned int id, unsigned short mod_n) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset3 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set3.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.mod_n = mod_n; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mod_t_set(unsigned int id, unsigned char mod_t) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset3 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set3.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.mod_t = mod_t; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mod_len_set(unsigned int id, unsigned char mod_len) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset3 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set3.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.mod_len = mod_len; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mod_d_set(unsigned int id, unsigned short mod_d) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivset4 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set4.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.mod_d = mod_d; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fdsrcparam_unused_set(unsigned int id, unsigned char fdsrcparam_unused) ++{ ++ unsigned int *reg_addr = NULL; ++ fdsrcparam tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fdsrcparam_unused = fdsrcparam_unused; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fdiv_in_set(unsigned int id, unsigned int i_fdiv_in) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivs_tat1 fdivstat1; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_stat1.u32); ++ fdivstat1.u32 = hdmi21_tx_reg_read(reg_addr); ++ fdivstat1.bits.i_fdiv_in = i_fdiv_in; ++ hdmi21_tx_reg_write(reg_addr, fdivstat1.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mdiv_set(unsigned int id, unsigned char i_mdiv) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivmanual tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_manual.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.i_mdiv = i_mdiv; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_frl_clock_set(unsigned int id, unsigned char sw_reset_frl_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_frl_clock = sw_reset_frl_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_manual_en_set(unsigned int id, unsigned char i_manual_en) ++{ ++ unsigned int *reg_addr = NULL; ++ fdivmanual tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_manual.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.i_manual_en = i_manual_en; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_delay1_set(unsigned int id, unsigned char stb_delay1) ++{ ++ unsigned int *reg_addr = NULL; ++ stb_opt stbopt; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); ++ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); ++ stbopt.bits.stb_delay1 = stb_delay1; ++ hdmi21_tx_reg_write(reg_addr, stbopt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ref_clk_sel_set(unsigned int id, unsigned char i_ref_clk_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ refclksel tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->ref_clk_sel.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.i_ref_clk_sel = i_ref_clk_sel; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fcg_dither_en_set(unsigned int id, unsigned char up_fcg_dither_en) ++{ ++ unsigned int *reg_addr = NULL; ++ fcgset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fcg_dither_en = up_fcg_dither_en; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fcg_dlf_en_set(unsigned int id, unsigned char up_fcg_dlf_en) ++{ ++ unsigned int *reg_addr = NULL; ++ fcgset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fcg_dlf_en = up_fcg_dlf_en; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fcg_en_set(unsigned int id, unsigned char up_fcg_en) ++{ ++ unsigned int *reg_addr = NULL; ++ fcgset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.fcg_en = up_fcg_en; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_enable_h20_set(unsigned int id, unsigned char up_enable_h20) ++{ ++ unsigned int *reg_addr = NULL; ++ txfifoset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->tx_fifo_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.enable_h20 = up_enable_h20; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_pr_en_h20_set(unsigned int id, unsigned char up_pr_en_h20) ++{ ++ unsigned int *reg_addr = NULL; ++ txfifoset0 tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->tx_fifo_set0.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.pr_en_h20 = up_pr_en_h20; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ch_out_sel_set(unsigned int id, unsigned char up_ch_out_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ tx_data_out_sel txdataoutsel; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->data_out_sel.u32); ++ txdataoutsel.u32 = hdmi21_tx_reg_read(reg_addr); ++ txdataoutsel.bits.ch_out_sel = up_ch_out_sel; ++ hdmi21_tx_reg_write(reg_addr, txdataoutsel.u32); ++ ++ return; ++} ++ ++void hdmi_reg_hsset_set(unsigned int id, unsigned char up_hsset) ++{ ++ unsigned int *reg_addr = NULL; ++ hsset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->hs_set.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.hsset = up_hsset; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_global_reset_set(unsigned int id, unsigned char global_reset) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.global_reset = global_reset; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_swreset_unused_set(unsigned int id, unsigned short swreset_unused) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.swreset_unused = swreset_unused; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_dac_clock_gat_set(unsigned int id, unsigned char dac_clock_gat) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.dac_clock_gat = dac_clock_gat; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_delay2_set(unsigned int id, unsigned char stb_delay2) ++{ ++ unsigned int *reg_addr = NULL; ++ stb_opt stbopt; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); ++ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); ++ stbopt.bits.stb_delay2 = stb_delay2; ++ hdmi21_tx_reg_write(reg_addr, stbopt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_cs_sel_set(unsigned int id, unsigned char stb_cs_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ stb_opt stbopt; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); ++ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); ++ stbopt.bits.stb_cs_sel = stb_cs_sel; ++ hdmi21_tx_reg_write(reg_addr, stbopt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_acc_sel_set(unsigned int id, unsigned char stb_acc_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ stb_opt stbopt; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); ++ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); ++ stbopt.bits.stb_acc_sel = stb_acc_sel; ++ hdmi21_tx_reg_write(reg_addr, stbopt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_stb_delay0_set(unsigned int id, unsigned char stb_delay0) ++{ ++ unsigned int *reg_addr = NULL; ++ stb_opt stbopt; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); ++ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); ++ stbopt.bits.stb_delay0 = stb_delay0; ++ hdmi21_tx_reg_write(reg_addr, stbopt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fd_clk_sel_set(unsigned int id, unsigned char up_fd_clk_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ clk_set clkset; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); ++ clkset.u32 = hdmi21_tx_reg_read(reg_addr); ++ clkset.bits.fd_clk_sel = up_fd_clk_sel; ++ hdmi21_tx_reg_write(reg_addr, clkset.u32); ++ ++ return; ++} ++ ++void hdmi_reg_refclk_sel_set(unsigned int id, unsigned char up_refclk_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ clk_set clkset; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); ++ clkset.u32 = hdmi21_tx_reg_read(reg_addr); ++ clkset.bits.refclk_sel = up_refclk_sel; ++ hdmi21_tx_reg_write(reg_addr, clkset.u32); ++ ++ return; ++} ++ ++void hdmi_reg_ctman_set(unsigned int id, unsigned char up_ctman) ++{ ++ unsigned int *reg_addr = NULL; ++ clk_set clkset; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); ++ clkset.u32 = hdmi21_tx_reg_read(reg_addr); ++ clkset.bits.ctman = up_ctman; ++ hdmi21_tx_reg_write(reg_addr, clkset.u32); ++ ++ return; ++} ++ ++void hdmi_reg_req_length_set(unsigned int id, unsigned char req_length) ++{ ++ unsigned int *reg_addr = NULL; ++ stb_opt stbopt; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); ++ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); ++ stbopt.bits.req_length = req_length; ++ hdmi21_tx_reg_write(reg_addr, stbopt.u32); ++ ++ return; ++} ++ ++void hdmi_reg_fdivclk_sel_set(unsigned int id, unsigned char up_fdivclk_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ clk_set clkset; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); ++ clkset.u32 = hdmi21_tx_reg_read(reg_addr); ++ clkset.bits.fdivclk_sel = up_fdivclk_sel; ++ hdmi21_tx_reg_write(reg_addr, clkset.u32); ++ ++ return; ++} ++ ++void hdmi_reg_mod_div_val_set(unsigned int id, unsigned char mod_div_val) ++{ ++ unsigned int *reg_addr = NULL; ++ clk_set clkset; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); ++ clkset.u32 = hdmi21_tx_reg_read(reg_addr); ++ clkset.bits.mod_div_val = mod_div_val; ++ hdmi21_tx_reg_write(reg_addr, clkset.u32); ++ ++ return; ++} ++ ++void hdmi_reg_modclk_sel_set(unsigned int id, unsigned char up_modclk_sel) ++{ ++ unsigned int *reg_addr = NULL; ++ clk_set clkset; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); ++ clkset.u32 = hdmi21_tx_reg_read(reg_addr); ++ clkset.bits.modclk_sel = up_modclk_sel; ++ hdmi21_tx_reg_write(reg_addr, clkset.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_mod_clock_set(unsigned int id, unsigned char sw_reset_mod_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_mod_clock = sw_reset_mod_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_tmds_clock_set(unsigned int id, unsigned char sw_reset_tmds_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_tmds_clock = sw_reset_tmds_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_mpll_clock_set(unsigned int id, unsigned char sw_reset_mpll_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_mpll_clock = sw_reset_mpll_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_nco_clock_set(unsigned int id, unsigned char sw_reset_nco_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_nco_clock = sw_reset_nco_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_fd_clock_set(unsigned int id, unsigned char sw_reset_fd_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_fd_clock = sw_reset_fd_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_mod_and_mpll_clock_set(unsigned int id, unsigned char sw_reset_mod_and_mpll_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_mod_and_mpll_clock = sw_reset_mod_and_mpll_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_mod_and_nco_clock_set(unsigned int id, unsigned char sw_reset_mod_and_nco_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_mod_and_nco_clock = sw_reset_mod_and_nco_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_mod_and_fd_clock_set(unsigned int id, unsigned char sw_reset_mod_and_fd_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_mod_and_fd_clock = sw_reset_mod_and_fd_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_hsfifo_clock_set(unsigned int id, unsigned char sw_reset_hsfifo_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_hsfifo_clock = sw_reset_hsfifo_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_txfifo_clock_set(unsigned int id, unsigned char sw_reset_txfifo_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_txfifo_clock = sw_reset_txfifo_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_data_clock_set(unsigned int id, unsigned char sw_reset_data_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_data_clock = sw_reset_data_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_hs_clock_set(unsigned int id, unsigned char sw_reset_hs_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_hs_clock = sw_reset_hs_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_pllref_clock_set(unsigned int id, unsigned char sw_reset_pllref_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_pllref_clock = sw_reset_pllref_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_sw_reset_dac_clock_set(unsigned int id, unsigned char sw_reset_dac_clock) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.sw_reset_dac_clock = sw_reset_dac_clock; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ ++void hdmi_reg_up_sample_fifo_clock_swrst_set(unsigned int id, unsigned char up_sample_fifo_clock_swrst) ++{ ++ unsigned int *reg_addr = NULL; ++ sw_reset tmp; ++ ++ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); ++ tmp.u32 = hdmi21_tx_reg_read(reg_addr); ++ tmp.bits.up_sample_fifo_clock_swrst = up_sample_fifo_clock_swrst; ++ hdmi21_tx_reg_write(reg_addr, tmp.u32); ++ ++ return; ++} ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.h b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.h +new file mode 100755 +index 000000000..dbfe6424c +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.h +@@ -0,0 +1,1095 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++#ifndef HDMI_REG_DPHY_H ++#define HDMI_REG_DPHY_H ++ ++ ++typedef union { ++ struct { ++ unsigned int gpport0 : 16; /* [15:0] */ ++ unsigned int rsv_0 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} t2gpport0; ++ ++typedef union { ++ struct { ++ unsigned int gpport1 : 16; /* [15:0] */ ++ unsigned int rsv_1 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} t2gpport1; ++ ++typedef union { ++ struct { ++ unsigned int stb_cs_en : 16; /* [15:0] */ ++ unsigned int rsv_2 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} phy_csen; ++ ++typedef union { ++ struct { ++ unsigned int stb_wen : 1; /* [0] */ ++ unsigned int rsv_3 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} phy_wr; ++ ++typedef union { ++ struct { ++ unsigned int resetn : 1; /* [0] */ ++ unsigned int rsv_4 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} resetn; ++ ++typedef union { ++ struct { ++ unsigned int stb_addr : 4; /* [3:0] */ ++ unsigned int rsv_5 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} phy_addr; ++ ++typedef union { ++ struct { ++ unsigned int stb_wdata : 8; /* [7:0] */ ++ unsigned int rsv_6 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} phy_wdata; ++ ++typedef union { ++ struct { ++ unsigned int stb_rdata : 8; /* [7:0] */ ++ unsigned int rsv_7 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} phy_rdata; ++ ++typedef union { ++ struct { ++ unsigned int zcal : 5; /* [4:0] */ ++ unsigned int zcaldone : 1; /* [5] */ ++ unsigned int zcalsub : 2; /* [7:6] */ ++ unsigned int rxsense : 4; /* [11:8] */ ++ unsigned int rsv_8 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} zcalreg; ++ ++typedef union { ++ struct { ++ unsigned int zcalclk : 1; /* [0] */ ++ unsigned int rsv_9 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} zcalclk; ++ ++typedef union { ++ struct { ++ unsigned int c0shortdet : 1; /* [0] */ ++ unsigned int c1shortdet : 1; /* [1] */ ++ unsigned int c2shortdet : 1; /* [2] */ ++ unsigned int clkshortdet : 1; /* [3] */ ++ unsigned int rsv_10 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} shortdet; ++ ++typedef union { ++ struct { ++ unsigned int rsv_11 : 12; /* [11:0] */ ++ unsigned int t2_plllkvdetl : 1; /* [12] */ ++ unsigned int t2_plllkcdet : 1; /* [13] */ ++ unsigned int t2_plllkvdet2 : 1; /* [14] */ ++ unsigned int t2_lkvdetlow : 1; /* [15] */ ++ unsigned int t2_lkvdethigh : 1; /* [16] */ ++ unsigned int rsv_12 : 15; /* [31:17] */ ++ } bits; ++ unsigned int u32; ++} det; ++ ++typedef union { ++ struct { ++ unsigned int src_lock_val : 8; /* [7:0] */ ++ unsigned int src_lock_cnt : 8; /* [15:8] */ ++ unsigned int src_enable : 1; /* [16] */ ++ unsigned int fdsrcparam_unused : 3; /* [19:17] */ ++ unsigned int rsv_13 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} fdsrcparam; ++ ++typedef union { ++ struct { ++ unsigned int src_cnt_opt : 3; /* [2:0] */ ++ unsigned int fdsrcfreq_unused_1 : 1; /* [3] */ ++ unsigned int src_freq_opt : 2; /* [5:4] */ ++ unsigned int fdsrcfreq_unused_2 : 2; /* [7:6] */ ++ unsigned int src_freq_ext : 16; /* [23:8] */ ++ unsigned int rsv_14 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fdsrcfreq; ++ ++typedef union { ++ struct { ++ unsigned int src_det_stat : 4; /* [3:0] */ ++ unsigned int src_cnt_out : 20; /* [23:4] */ ++ unsigned int rsv_15 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fdsrcres; ++ ++typedef union { ++ struct { ++ unsigned int i_enable : 1; /* [0] */ ++ unsigned int i_run : 1; /* [1] */ ++ unsigned int ctset0_unused : 2; /* [3:2] */ ++ unsigned int rsv_16 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} ctset0; ++ ++typedef union { ++ struct { ++ unsigned int i_mpll_fcon : 10; /* [9:0] */ ++ unsigned int i_mpll_divn : 3; /* [12:10] */ ++ unsigned int i_mpll_ctlck : 1; /* [13] */ ++ unsigned int ctset1_unused : 18; /* [31:14] */ ++ } bits; ++ unsigned int u32; ++} ctset1; ++ ++typedef union { ++ struct { ++ unsigned int i_deci_cnt_len : 8; /* [7:0] */ ++ unsigned int i_vco_st_wait_len : 8; /* [15:8] */ ++ unsigned int i_vco_end_wait_len : 8; /* [23:16] */ ++ unsigned int i_ref_cnt_len : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fccntr0; ++ ++typedef union { ++ struct { ++ unsigned int i_ct_sel : 1; /* [0] */ ++ unsigned int i_clkdet_sel : 1; /* [1] */ ++ unsigned int i_ct_mode : 2; /* [3:2] */ ++ unsigned int fcopt_unused_1 : 4; /* [7:4] */ ++ unsigned int i_ct_en : 1; /* [8] */ ++ unsigned int fcopt_unused_2 : 3; /* [11:9] */ ++ unsigned int i_ct_idx_sel : 1; /* [12] */ ++ unsigned int i_deci_try_sel : 1; /* [13] */ ++ unsigned int fcopt_unused : 2; /* [15:14] */ ++ unsigned int rsv_17 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fcopt; ++ ++typedef union { ++ struct { ++ unsigned int clk_ok : 1; /* [0] */ ++ unsigned int busy : 1; /* [1] */ ++ unsigned int done : 1; /* [2] */ ++ unsigned int error : 1; /* [3] */ ++ unsigned int divn : 3; /* [6:4] */ ++ unsigned int fcstat_unused_1 : 1; /* [7] */ ++ unsigned int ref_clk_stat : 1; /* [8] */ ++ unsigned int pllvco_clk_stat : 1; /* [9] */ ++ unsigned int fcstat_unused_2 : 2; /* [11:10] */ ++ unsigned int confin_stat : 6; /* [17:12] */ ++ unsigned int fcstat_unused_3 : 2; /* [19:18] */ ++ unsigned int fcon_init : 10; /* [29:20] */ ++ unsigned int rsv_18 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} fcstat; ++ ++typedef union { ++ struct { ++ unsigned int cnt_ref : 16; /* [15:0] */ ++ unsigned int rsv_19 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fccntval0; ++ ++typedef union { ++ struct { ++ unsigned int cnt_mpll : 16; /* [15:0] */ ++ unsigned int rsv_20 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fccntval1; ++ ++typedef union { ++ struct { ++ unsigned int divn_mpll : 3; /* [2:0] */ ++ unsigned int fcresval_unused : 1; /* [3] */ ++ unsigned int fcon_mpll : 10; /* [13:4] */ ++ unsigned int rsv_21 : 18; /* [31:14] */ ++ } bits; ++ unsigned int u32; ++} fcresval; ++ ++typedef union { ++ struct { ++ unsigned int divn_h20 : 3; /* [2:0] */ ++ unsigned int fcdstepset_unused : 1; /* [3] */ ++ unsigned int up_sampler_ratio_sel : 1; /* [4] */ ++ unsigned int rsv_22 : 27; /* [31:5] */ ++ } bits; ++ unsigned int u32; ++} fcdstepsetl; ++ ++typedef union { ++ struct { ++ unsigned int i_h2_sel : 1; /* [0] */ ++ unsigned int i_deci_sel : 1; /* [1] */ ++ unsigned int rsv_23 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} fcdstepth; ++ ++typedef union { ++ struct { ++ unsigned int i_deci2x_th : 16; /* [15:0] */ ++ unsigned int i_deci4x_th : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fcdstepth0; ++ ++typedef union { ++ struct { ++ unsigned int i_deci8x_th : 16; /* [15:0] */ ++ unsigned int i_deci16x_th : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fcdstepth1; ++ ++typedef union { ++ struct { ++ unsigned int i_ref_cnt : 16; /* [15:0] */ ++ unsigned int rsv_24 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fccntr1; ++ ++typedef union { ++ struct { ++ unsigned int contin_upd_en : 1; /* [0] */ ++ unsigned int contin_upd_opt : 1; /* [1] */ ++ unsigned int contin_upd_pol : 1; /* [2] */ ++ unsigned int fccontinset0_unused : 1; /* [3] */ ++ unsigned int contin_upd_step : 4; /* [7:4] */ ++ unsigned int rsv_25 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} fccontinset0; ++ ++typedef union { ++ struct { ++ unsigned int contin_upd_rate : 28; /* [27:0] */ ++ unsigned int contin_upd_time : 4; /* [31:28] */ ++ } bits; ++ unsigned int u32; ++} fccontinset1; ++ ++typedef union { ++ struct { ++ unsigned int contin_upd_th_dn : 10; /* [9:0] */ ++ unsigned int fccontinset2_unused : 2; /* [11:10] */ ++ unsigned int contin_upd_th_up : 10; /* [21:12] */ ++ unsigned int rsv_26 : 10; /* [31:22] */ ++ } bits; ++ unsigned int u32; ++} fccontinset2; ++ ++typedef union { ++ struct { ++ unsigned int init : 1; /* [0] */ ++ unsigned int ctrl : 1; /* [1] */ ++ unsigned int mod : 1; /* [2] */ ++ unsigned int sdm : 1; /* [3] */ ++ unsigned int rsv_27 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} fdivset0; ++ ++typedef union { ++ struct { ++ unsigned int step_d : 8; /* [7:0] */ ++ unsigned int step_t : 8; /* [15:8] */ ++ unsigned int step_n : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fdivset1; ++ ++typedef union { ++ struct { ++ unsigned int up : 1; /* [0] */ ++ unsigned int dn : 1; /* [1] */ ++ unsigned int rsv_28 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} fdivset2; ++ ++typedef union { ++ struct { ++ unsigned int mod_len : 8; /* [7:0] */ ++ unsigned int mod_t : 8; /* [15:8] */ ++ unsigned int mod_n : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fdivset3; ++ ++typedef union { ++ struct { ++ unsigned int mod_d : 16; /* [15:0] */ ++ unsigned int rsv_29 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fdivset4; ++ ++typedef union { ++ struct { ++ unsigned int mod_up : 1; /* [0] */ ++ unsigned int mod_dn : 1; /* [1] */ ++ unsigned int fdivset5_unused : 2; /* [3:2] */ ++ unsigned int rsv_30 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} fdivset5; ++ ++typedef union { ++ struct { ++ unsigned int stc_run : 1; /* [0] */ ++ unsigned int stc_dir : 1; /* [1] */ ++ unsigned int stc_ov : 1; /* [2] */ ++ unsigned int stc_un : 1; /* [3] */ ++ unsigned int stc_cnt : 16; /* [19:4] */ ++ unsigned int rsv_31 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} fdivs_tat0; ++ ++typedef union { ++ struct { ++ unsigned int i_fdiv_in : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} fdivs_tat1; ++ ++typedef union { ++ struct { ++ unsigned int div_out : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} fdivs_tat2; ++ ++typedef union { ++ struct { ++ unsigned int div_sdm : 16; /* [15:0] */ ++ unsigned int rsv_32 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fdivs_tat3; ++ ++typedef union { ++ struct { ++ unsigned int stm_run : 1; /* [0] */ ++ unsigned int stm_ph : 2; /* [2:1] */ ++ unsigned int stm_ov : 1; /* [3] */ ++ unsigned int stm_un : 1; /* [4] */ ++ unsigned int fdivstat4_unused : 3; /* [7:5] */ ++ unsigned int stm_cnt : 16; /* [23:8] */ ++ unsigned int rsv_33 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fdivs_tat4; ++ ++typedef union { ++ struct { ++ unsigned int i_manual_en : 4; /* [3:0] */ ++ unsigned int i_divn : 3; /* [6:4] */ ++ unsigned int fdivmanual_unused : 1; /* [7] */ ++ unsigned int i_mdiv : 4; /* [11:8] */ ++ unsigned int i_ref_cnt_div : 2; /* [13:12] */ ++ unsigned int i_dc_sel : 2; /* [15:14] */ ++ unsigned int i_vic : 8; /* [23:16] */ ++ unsigned int rsv_34 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fdivmanual; ++ ++typedef union { ++ struct { ++ unsigned int t2_refclksel : 1; /* [0] */ ++ unsigned int t2_refclksel2 : 1; /* [1] */ ++ unsigned int i_ref_clk_sel : 1; /* [2] */ ++ unsigned int refclksel_unused_1 : 1; /* [3] */ ++ unsigned int t2_pixelclksel : 1; /* [4] */ ++ unsigned int refclksel_unused_2 : 1; /* [5] */ ++ unsigned int pr_enc_val : 2; /* [7:6] */ ++ unsigned int rsv_35 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} refclksel; ++ ++typedef union { ++ struct { ++ unsigned int pll_lock_val : 8; /* [7:0] */ ++ unsigned int pll_lock_cnt : 8; /* [15:8] */ ++ unsigned int pll_enable : 1; /* [16] */ ++ unsigned int fdpllparam_unused : 3; /* [19:17] */ ++ unsigned int rsv_36 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} fdpllparam; ++ ++typedef union { ++ struct { ++ unsigned int pll_cnt_opt : 3; /* [2:0] */ ++ unsigned int fdpllfreq_unused_1 : 1; /* [3] */ ++ unsigned int pll_freq_opt : 2; /* [5:4] */ ++ unsigned int fdpllfreq_unused_2 : 2; /* [7:6] */ ++ unsigned int pll_freq_ext : 16; /* [23:8] */ ++ unsigned int rsv_37 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fdpllfreq; ++ ++typedef union { ++ struct { ++ unsigned int pll_det_stat : 4; /* [3:0] */ ++ unsigned int pll_cnt_out : 20; /* [23:4] */ ++ unsigned int rsv_38 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} fdpllres; ++ ++typedef union { ++ struct { ++ unsigned int fcg_en : 1; /* [0] */ ++ unsigned int fcg_dlf_en : 1; /* [1] */ ++ unsigned int fcg_dither_en : 1; /* [2] */ ++ unsigned int fcg_lock_en : 1; /* [3] */ ++ unsigned int rsv_39 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} fcgset; ++ ++typedef union { ++ struct { ++ unsigned int tmds_cnt_val : 16; /* [15:0] */ ++ unsigned int cnt1_target : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} fcgcnt; ++ ++typedef union { ++ struct { ++ unsigned int lock_cnt : 8; /* [7:0] */ ++ unsigned int lock_th : 8; /* [15:8] */ ++ unsigned int ki : 6; /* [21:16] */ ++ unsigned int lock_mode : 1; /* [22] */ ++ unsigned int rsv_40 : 9; /* [31:23] */ ++ } bits; ++ unsigned int u32; ++} fcgparam; ++ ++typedef union { ++ struct { ++ unsigned int dlf_lock : 1; /* [0] */ ++ unsigned int dlf_ov : 1; /* [1] */ ++ unsigned int dlf_un : 1; /* [2] */ ++ unsigned int rsv_41 : 29; /* [31:3] */ ++ } bits; ++ unsigned int u32; ++} fcgstate; ++ ++typedef union { ++ struct { ++ unsigned int ch_en_h20 : 4; /* [3:0] */ ++ unsigned int prbs_clr_h20 : 4; /* [7:4] */ ++ unsigned int ch_en_h21 : 4; /* [11:8] */ ++ unsigned int prbs_clr_h21 : 4; /* [15:12] */ ++ unsigned int test_pat_type : 3; /* [18:16] */ ++ unsigned int ch_test_en : 1; /* [19] */ ++ unsigned int test_4to1_mux_sel0 : 2; /* [21:20] */ ++ unsigned int test_4to1_mux_sel1 : 2; /* [23:22] */ ++ unsigned int test_4to1_mux_sel2 : 2; /* [25:24] */ ++ unsigned int test_4to1_mux_sel3 : 2; /* [27:26] */ ++ unsigned int rsv_42 : 4; /* [31:28] */ ++ } bits; ++ unsigned int u32; ++} txteloset; ++ ++typedef union { ++ struct { ++ unsigned int test_pat_ch0 : 20; /* [19:0] */ ++ unsigned int test_pat_ch1_l : 10; /* [29:20] */ ++ unsigned int rsv_43 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} txtelocont0; ++ ++typedef union { ++ struct { ++ unsigned int test_pat_ch1_h : 10; /* [9:0] */ ++ unsigned int test_pat_ch2 : 20; /* [29:10] */ ++ unsigned int rsv_44 : 2; /* [31:30] */ ++ } bits; ++ unsigned int u32; ++} txtelocont1; ++ ++typedef union { ++ struct { ++ unsigned int test_pat_ch3 : 20; /* [19:0] */ ++ unsigned int rsv_45 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} txtelocont2; ++ ++typedef union { ++ struct { ++ unsigned int pr_en_h20 : 1; /* [0] */ ++ unsigned int enable_h20 : 1; /* [1] */ ++ unsigned int txfifoset0_unused : 6; /* [7:2] */ ++ unsigned int rsv_46 : 24; /* [31:8] */ ++ } bits; ++ unsigned int u32; ++} txfifoset0; ++ ++typedef union { ++ struct { ++ unsigned int pol_inv0_h20 : 4; /* [3:0] */ ++ unsigned int data_swap0_h20 : 4; /* [7:4] */ ++ unsigned int ch_sel0_h20 : 8; /* [15:8] */ ++ unsigned int pol_inv1_h20 : 4; /* [19:16] */ ++ unsigned int data_swap1_h20 : 4; /* [23:20] */ ++ unsigned int ch_sel1_h20 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} txfifoset1; ++ ++typedef union { ++ struct { ++ unsigned int pr_fifo_state_h20 : 12; /* [11:0] */ ++ unsigned int txfifostat0_unused : 12; /* [23:12] */ ++ unsigned int rsv_47 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} tx_fifo_stat0; ++ ++typedef union { ++ struct { ++ unsigned int txfifostat1_unused_0 : 12; /* [11:0] */ ++ unsigned int txfifostat1_unused_1 : 12; /* [23:12] */ ++ unsigned int rsv_48 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} tx_fifo_stat1; ++ ++typedef union { ++ struct { ++ unsigned int tx_fifo_state_h20 : 12; /* [11:0] */ ++ unsigned int txfifostat2_unused : 12; /* [23:12] */ ++ unsigned int rsv_49 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} tx_fifo_stat2; ++ ++typedef union { ++ struct { ++ unsigned int txfifostat3_unused_0 : 12; /* [11:0] */ ++ unsigned int txfifostat3_unused_1 : 12; /* [23:12] */ ++ unsigned int rsv_50 : 8; /* [31:24] */ ++ } bits; ++ unsigned int u32; ++} tx_fifo_stat3; ++ ++typedef union { ++ struct { ++ unsigned int dataclkinv : 1; /* [0] */ ++ unsigned int rsv_51 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} data_clk_inv; ++ ++typedef union { ++ struct { ++ unsigned int ch_out_sel : 2; /* [1:0] */ ++ unsigned int rsv_52 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} tx_data_out_sel; ++ ++typedef union { ++ struct { ++ unsigned int reg_hdmi_mode_en : 1; /* [0] */ ++ unsigned int rsv_53 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} hdmi_mode; ++ ++typedef union { ++ struct { ++ unsigned int reg_clk_data_phase0 : 10; /* [9:0] */ ++ unsigned int reg_clk_data_phase1 : 10; /* [19:10] */ ++ unsigned int reg_sw_clk_en : 1; /* [20] */ ++ unsigned int rsv_54 : 11; /* [31:21] */ ++ } bits; ++ unsigned int u32; ++} clk_data1; ++ ++typedef union { ++ struct { ++ unsigned int reg_clk_data_phase2 : 10; /* [9:0] */ ++ unsigned int reg_clk_data_phase3 : 10; /* [19:10] */ ++ unsigned int rsv_55 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} clk_data2; ++ ++typedef union { ++ struct { ++ unsigned int reg_18to20_fifo_rd_rst : 1; /* [0] */ ++ unsigned int reg_18to20_fifo_wr_rst : 1; /* [1] */ ++ unsigned int reg_rd_bypass : 1; /* [2] */ ++ unsigned int reg_status_rrst : 1; /* [3] */ ++ unsigned int reg_status_wrst : 1; /* [4] */ ++ unsigned int rsv_56 : 27; /* [31:5] */ ++ } bits; ++ unsigned int u32; ++} cfg_18_to_20; ++ ++typedef union { ++ struct { ++ unsigned int empty_status : 1; /* [0] */ ++ unsigned int aempty_status : 1; /* [1] */ ++ unsigned int full_status : 1; /* [2] */ ++ unsigned int afull_status : 1; /* [3] */ ++ unsigned int rsv_57 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} fifo_stat_18_to_20; ++ ++typedef union { ++ struct { ++ unsigned int hsset : 2; /* [1:0] */ ++ unsigned int rsv_58 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} hsset; ++ ++typedef union { ++ struct { ++ unsigned int w_hsrxsense : 2; /* [1:0] */ ++ unsigned int rsv_59 : 30; /* [31:2] */ ++ } bits; ++ unsigned int u32; ++} hsrxsense; ++ ++typedef union { ++ struct { ++ unsigned int fifo_state_hs : 12; /* [11:0] */ ++ unsigned int rsv_60 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} hs_fifo_stat; ++ ++typedef union { ++ struct { ++ unsigned int hs_fifo_empty_intr : 1; /* [0] */ ++ unsigned int hs_fifo_full_intr : 1; /* [1] */ ++ unsigned int up_sample_fifo_empty_intr : 1; /* [2] */ ++ unsigned int up_sample_fifo_full_intr : 1; /* [3] */ ++ unsigned int trinsmitter_fifo_empty_intr : 1; /* [4] */ ++ unsigned int trinsmitter_fifo_full_intr : 1; /* [5] */ ++ unsigned int lkvdethigh_intr : 1; /* [6] */ ++ unsigned int lkvdetlow_intr : 1; /* [7] */ ++ unsigned int ct_fcon_intr : 1; /* [8] */ ++ unsigned int rsv_61 : 23; /* [31:9] */ ++ } bits; ++ unsigned int u32; ++} intr_stat; ++ ++typedef union { ++ struct { ++ unsigned int hs_fifo_empty_intr_mask : 1; /* [0] */ ++ unsigned int hs_fifo_full_intr_mask : 1; /* [1] */ ++ unsigned int up_sample_fifo_empty_intr_mask : 1; /* [2] */ ++ unsigned int up_sample_fifo_full_intr_mask : 1; /* [3] */ ++ unsigned int trinsmitter_fifo_empty_intr_mask : 1; /* [4] */ ++ unsigned int trinsmitter_fifo_full_intr_mask : 1; /* [5] */ ++ unsigned int lkvdethigh_intr_mask : 1; /* [6] */ ++ unsigned int lkvdetlow_intr_mask : 1; /* [7] */ ++ unsigned int ct_fcon_intr_mask : 1; /* [8] */ ++ unsigned int rsv_62 : 23; /* [31:9] */ ++ } bits; ++ unsigned int u32; ++} intr_mask; ++ ++typedef union { ++ struct { ++ unsigned int hs_fifo_empty_triger_type : 3; /* [2:0] */ ++ unsigned int hs_fifo_empty_intr_en : 1; /* [3] */ ++ unsigned int hs_fifo_full_triger_type : 3; /* [6:4] */ ++ unsigned int hs_fifo_full_intr_en : 1; /* [7] */ ++ unsigned int up_sample_fifo_empty_triger_type : 3; /* [10:8] */ ++ unsigned int up_sample_fifo_empty_intr_en : 1; /* [11] */ ++ unsigned int up_sample_fifo_full_triger_type : 3; /* [14:12] */ ++ unsigned int up_sample_fifo_full_intr_en : 1; /* [15] */ ++ unsigned int transmitter_fifo_empty_triger_type : 3; /* [18:16] */ ++ unsigned int transmitter_fifo_empty_intr_en : 1; /* [19] */ ++ unsigned int transmitter_fifo_full_triger_type : 3; /* [22:20] */ ++ unsigned int transmitter_fifo_full_intr_en : 1; /* [23] */ ++ unsigned int lkvdethigh_triger_type : 3; /* [26:24] */ ++ unsigned int lkvdethigh_intr_en : 1; /* [27] */ ++ unsigned int lkvdetlow_triger_type : 3; /* [30:28] */ ++ unsigned int lkvdetlow_intr_en : 1; /* [31] */ ++ } bits; ++ unsigned int u32; ++} intr_set; ++ ++typedef union { ++ struct { ++ unsigned int fd_clk_sel : 2; /* [1:0] */ ++ unsigned int refclk_sel : 2; /* [3:2] */ ++ unsigned int ctman : 2; /* [5:4] */ ++ unsigned int modclk_sel : 1; /* [6] */ ++ unsigned int fdivclk_sel : 1; /* [7] */ ++ unsigned int mod_div_val : 4; /* [11:8] */ ++ unsigned int rsv_63 : 20; /* [31:12] */ ++ } bits; ++ unsigned int u32; ++} clk_set; ++ ++typedef union { ++ struct { ++ unsigned int sw_reset_mod_clock : 1; /* [0] */ ++ unsigned int sw_reset_tmds_clock : 1; /* [1] */ ++ unsigned int sw_reset_mpll_clock : 1; /* [2] */ ++ unsigned int sw_reset_nco_clock : 1; /* [3] */ ++ unsigned int sw_reset_fd_clock : 1; /* [4] */ ++ unsigned int sw_reset_mod_and_mpll_clock : 1; /* [5] */ ++ unsigned int sw_reset_mod_and_nco_clock : 1; /* [6] */ ++ unsigned int sw_reset_mod_and_fd_clock : 1; /* [7] */ ++ unsigned int sw_reset_hsfifo_clock : 1; /* [8] */ ++ unsigned int sw_reset_txfifo_clock : 1; /* [9] */ ++ unsigned int sw_reset_data_clock : 1; /* [10] */ ++ unsigned int sw_reset_hs_clock : 1; /* [11] */ ++ unsigned int sw_reset_pllref_clock : 1; /* [12] */ ++ unsigned int sw_reset_dac_clock : 1; /* [13] */ ++ unsigned int dac_clock_gat : 1; /* [14] */ ++ unsigned int up_sample_fifo_clock_swrst : 1; /* [15] */ ++ unsigned int sw_reset_frl_clock : 1; /* [16] */ ++ unsigned int swreset_unused : 14; /* [30:17] */ ++ unsigned int global_reset : 1; /* [31] */ ++ } bits; ++ unsigned int u32; ++} sw_reset; ++ ++typedef union { ++ struct { ++ unsigned int clk0_div : 4; /* [3:0] */ ++ unsigned int clk1_div : 4; /* [7:4] */ ++ unsigned int clk2_div : 4; /* [11:8] */ ++ unsigned int clk3_div : 4; /* [15:12] */ ++ unsigned int clk4_div : 4; /* [19:16] */ ++ unsigned int clk5_div : 4; /* [23:20] */ ++ unsigned int clk6_div : 4; /* [27:24] */ ++ unsigned int clk7_div : 4; /* [31:28] */ ++ } bits; ++ unsigned int u32; ++} glueset0; ++ ++typedef union { ++ struct { ++ unsigned int clk8_div : 4; /* [3:0] */ ++ unsigned int glueset1_unused_1 : 4; /* [7:4] */ ++ unsigned int clk10_div : 4; /* [11:8] */ ++ unsigned int clk11_div : 4; /* [15:12] */ ++ unsigned int clk_sel : 4; /* [19:16] */ ++ unsigned int glueset1_unused_2 : 12; /* [31:20] */ ++ } bits; ++ unsigned int u32; ++} glueset1; ++ ++typedef union { ++ struct { ++ unsigned int ct_fcon_triger_type : 3; /* [2:0] */ ++ unsigned int ct_fcon_intr_en : 1; /* [3] */ ++ unsigned int rsv_64 : 28; /* [31:4] */ ++ } bits; ++ unsigned int u32; ++} ct_intr_set; ++ ++typedef union { ++ struct { ++ unsigned int hw_info : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} hw_info; ++ ++typedef union { ++ struct { ++ unsigned int hw_vers_unused_1 : 4; /* [3:0] */ ++ unsigned int hdmi20_compliance : 1; /* [4] */ ++ unsigned int hdmi21_compliance : 1; /* [5] */ ++ unsigned int hw_vers_unused_2 : 26; /* [31:6] */ ++ } bits; ++ unsigned int u32; ++} hw_vers; ++ ++typedef union { ++ struct { ++ unsigned int ras_mode : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} hw_ras_mode; ++ ++typedef union { ++ struct { ++ unsigned int rfs_mode : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} hw_rfs_mode; ++ ++typedef union { ++ struct { ++ unsigned int rft_mode : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} hw_rft_mode; ++ ++typedef union { ++ struct { ++ unsigned int req_length : 2; /* [1:0] */ ++ unsigned int stb_delay2 : 4; /* [5:2] */ ++ unsigned int stb_delay1 : 4; /* [9:6] */ ++ unsigned int stb_delay0 : 4; /* [13:10] */ ++ unsigned int stb_acc_sel : 1; /* [14] */ ++ unsigned int stb_cs_sel : 1; /* [15] */ ++ unsigned int rsv_65 : 16; /* [31:16] */ ++ } bits; ++ unsigned int u32; ++} stb_opt; ++ ++typedef union { ++ struct { ++ unsigned int req_done : 1; /* [0] */ ++ unsigned int rsv_66 : 31; /* [31:1] */ ++ } bits; ++ unsigned int u32; ++} stb_req; ++ ++typedef union { ++ struct { ++ unsigned int stb_auto_rdata : 32; /* [31:0] */ ++ } bits; ++ unsigned int u32; ++} stb_data; ++ ++typedef struct { ++ volatile t2gpport0 t2gp_port0; /* 0 */ ++ volatile t2gpport1 t2gp_port1; /* 4 */ ++ volatile phy_csen stb_cs_en; /* 8 */ ++ volatile phy_wr stb_write_en; /* C */ ++ volatile resetn stb_reset; /* 10 */ ++ volatile phy_addr stb_addr; /* 14 */ ++ volatile phy_wdata stb_wdata; /* 18 */ ++ volatile phy_rdata stb_rdata; /* 1C */ ++ volatile zcalreg zcal_reg; /* 20 */ ++ volatile zcalclk zcal_clk; /* 24 */ ++ volatile shortdet short_det; /* 28 */ ++ volatile det stb_det; /* 2C */ ++ volatile fdsrcparam fd_src_param; /* 30 */ ++ volatile fdsrcfreq fd_src_freq; /* 34 */ ++ volatile fdsrcres fd_src_res; /* 38 */ ++ volatile ctset0 ct_set0; /* 3C */ ++ volatile ctset1 ct_set1; /* 40 */ ++ unsigned int reserved_0; /* 44 */ ++ volatile fccntr0 fc_cntr0; /* 48 */ ++ volatile fcopt fc_opt; /* 4C */ ++ volatile fcstat fc_stat; /* 50 */ ++ volatile fccntval0 fc_cnt_val0; /* 54 */ ++ volatile fccntval1 fc_cnt_val1; /* 58 */ ++ volatile fcresval fc_res_sval; /* 5C */ ++ volatile fcdstepsetl fc_dstep_set; /* 60 */ ++ volatile fcdstepth fc_dstep_th; /* 64 */ ++ volatile fcdstepth0 fc_dstep_th0; /* 68 */ ++ volatile fcdstepth1 fc_dstep_th1; /* 6C */ ++ volatile fccntr1 fc_cntr1; /* 70 */ ++ volatile fccontinset0 fc_contin_set0; /* 74 */ ++ volatile fccontinset1 fc_contin_set1; /* 78 */ ++ volatile fccontinset2 fc_contin_set2; /* 7C */ ++ unsigned int reserved_1[4]; /* 80-8C */ ++ volatile fdivset0 fdiv_set0; /* 90 */ ++ volatile fdivset1 fdiv_set1; /* 94 */ ++ volatile fdivset2 fdiv_set2; /* 98 */ ++ volatile fdivset3 fdiv_set3; /* 9C */ ++ volatile fdivset4 fdiv_set4; /* A0 */ ++ volatile fdivset5 fdiv_set5; /* A4 */ ++ volatile fdivs_tat0 fdiv_stat0; /* A8 */ ++ volatile fdivs_tat1 fdiv_stat1; /* AC */ ++ volatile fdivs_tat2 fdiv_stat2; /* B0 */ ++ volatile fdivs_tat3 fdiv_stat3; /* B4 */ ++ volatile fdivs_tat4 fdiv_stat4; /* B8 */ ++ volatile fdivmanual fdiv_manual; /* BC */ ++ volatile refclksel ref_clk_sel; /* C0 */ ++ unsigned int reserved_2[15]; /* C4-FC */ ++ volatile fdpllparam fd_pll_param; /* 100 */ ++ volatile fdpllfreq fd_pll_freq; /* 104 */ ++ volatile fdpllres fd_pll_res; /* 108 */ ++ unsigned int reserved_3[5]; /* 10c-11c */ ++ volatile fcgset fcg_set; /* 120 */ ++ volatile fcgcnt fcg_cnt; /* 124 */ ++ volatile fcgparam fcg_param; /* 128 */ ++ volatile fcgstate fcg_state; /* 12C */ ++ unsigned int reserved_4[52]; /* 130-1FC */ ++ volatile txteloset telo_set; /* 200 */ ++ volatile txtelocont0 telo_cnt0; /* 204 */ ++ volatile txtelocont1 telo_cnt1; /* 208 */ ++ volatile txtelocont2 telo_cnt2; /* 20C */ ++ volatile txfifoset0 tx_fifo_set0; /* 210 */ ++ volatile txfifoset1 tx_fifo_set1; /* 214 */ ++ volatile tx_fifo_stat0 tx_fifo_stat0; /* 218 */ ++ volatile tx_fifo_stat1 tx_fifo_stat1; /* 21C */ ++ volatile tx_fifo_stat2 tx_fifo_stat2; /* 220 */ ++ volatile tx_fifo_stat3 tx_fifo_stat3; /* 224 */ ++ volatile data_clk_inv data_clk_inv; /* 228 */ ++ volatile tx_data_out_sel data_out_sel; /* 22C */ ++ volatile hdmi_mode stb_hdmi_mode; /* 230 */ ++ volatile clk_data1 clk_data1; /* 234 */ ++ volatile clk_data2 clk_data2; /* 238 */ ++ volatile cfg_18_to_20 cfg15_to_20; /* 23C */ ++ volatile fifo_stat_18_to_20 fifo_stat18_to_20; /* 240 */ ++ unsigned int reserved_5[7]; /* 244-25c */ ++ volatile hsset hs_set; /* 260 */ ++ volatile hsrxsense hs_rxsense; /* 264 */ ++ volatile hs_fifo_stat hs_fifo_stat; /* 268 */ ++ unsigned int reserved_6[37]; /* 26C-2FC */ ++ volatile intr_stat intr_stat; /* 300 */ ++ volatile intr_mask intr_mask; /* 304 */ ++ volatile intr_set intr_set; /* 308 */ ++ volatile clk_set clk_set; /* 30C */ ++ volatile sw_reset sw_rst; /* 310 */ ++ volatile glueset0 glue_set0; /* 314 */ ++ volatile glueset1 glue_set1; /* 318 */ ++ volatile ct_intr_set ct_intr_set; /* 31C */ ++ unsigned int reserved_7[56]; /* 320-3FC */ ++ volatile hw_info info_hw; /* 400 */ ++ volatile hw_vers vers_hw; /* 404 */ ++ unsigned int reserved_8[6]; /* 408-41C */ ++ volatile hw_ras_mode ras_mode; /* 420 */ ++ volatile hw_rfs_mode rfs_mode; /* 424 */ ++ volatile hw_rft_mode rft_mode; /* 428 */ ++ unsigned int reserved_9[181]; /* 42C-6FC */ ++ volatile stb_opt opt; /* 700 */ ++ volatile stb_req req; /* 704 */ ++ volatile stb_data rdata; /* 708 */ ++} hdmitx21_dphy_reg_type; ++ ++int hdmi_reg_tx_phy_init(unsigned int id, char *addr); ++unsigned int *hdmi_reg_tx_get_phy_addr(unsigned int id); ++int hdmi_reg_tx_phy_deinit(unsigned int id); ++void hdmi_reg_stb_cs_en_set(unsigned int id, unsigned short stb_cs_en); ++void hdmi_reg_stb_wen_set(unsigned int id, unsigned char stb_wen); ++void hdmi_reg_resetn_set(unsigned int id, unsigned char reg_resetn); ++unsigned char hdmi_reg_resetn_get(unsigned int id); ++void hdmi_reg_stb_addr_set(unsigned int id, unsigned char stb_addr); ++void hdmi_reg_stb_wdata_set(unsigned int id, unsigned char stb_wdata); ++unsigned char hdmi_reg_stb_rdata_get(unsigned int id); ++void hdmi_reg_src_lock_val_set(unsigned int id, unsigned char src_lock_val); ++void hdmi_reg_src_lock_cnt_set(unsigned int id, unsigned char src_lock_cnt); ++void hdmi_reg_src_enable_set(unsigned int id, unsigned char src_enable); ++void hdmi_reg_src_cnt_opt_set(unsigned int id, unsigned char src_cnt_opt); ++void hdmi_reg_fdsrcfreq_unused1_set(unsigned int id, unsigned char fdsrcfreq_unused_1); ++void hdmi_reg_src_freq_opt_set(unsigned int id, unsigned char src_freq_opt); ++void hdmi_reg_fdsrcfreq_unused2_set(unsigned int id, unsigned char fdsrcfreq_unused_2); ++void hdmi_reg_src_freq_ext_set(unsigned int id, unsigned short src_freq_ext); ++unsigned char hdmi_reg_src_det_stat_get(unsigned int id); ++unsigned int hdmi_reg_src_cnt_out_get(unsigned int id); ++void hdmi_reg_clkdet_sel_set(unsigned int id, unsigned char i_clkdet_sel); ++void hdmi_reg_divn_h20_set(unsigned int id, unsigned char up_divn_h20); ++void hdmi_reg_up_sampler_ratio_sel_set(unsigned int id, unsigned char up_sampler_ratio_sel); ++void hdmi_reg_init_set(unsigned int id, unsigned char init); ++void hdmi_reg_en_ctrl_set(unsigned int id, unsigned char en_ctrl); ++unsigned char hdmi_reg_en_ctrl_get(unsigned int id); ++void hdmi_reg_en_mod_set(unsigned int id, unsigned char en_mod); ++unsigned char hdmi_reg_en_mod_get(unsigned int id); ++void hdmi_reg_en_sdm_set(unsigned int id, unsigned char en_sdm); ++unsigned char hdmi_reg_en_sdm_get(unsigned int id); ++void hdmi_reg_mod_len_set(unsigned int id, unsigned char mod_len); ++void hdmi_reg_mod_t_set(unsigned int id, unsigned char mod_t); ++void hdmi_reg_mod_n_set(unsigned int id, unsigned short mod_n); ++void hdmi_reg_mod_d_set(unsigned int id, unsigned short mod_d); ++void hdmi_reg_fdiv_in_set(unsigned int id, unsigned int i_fdiv_in); ++void hdmi_reg_manual_en_set(unsigned int id, unsigned char i_manual_en); ++void hdmi_reg_mdiv_set(unsigned int id, unsigned char i_mdiv); ++void hdmi_reg_ref_clk_sel_set(unsigned int id, unsigned char i_ref_clk_sel); ++void hdmi_reg_pr_en_h20_set(unsigned int id, unsigned char up_pr_en_h20); ++void hdmi_reg_enable_h20_set(unsigned int id, unsigned char up_enable_h20); ++void hdmi_reg_ch_out_sel_set(unsigned int id, unsigned char up_ch_out_sel); ++void hdmi_reg_hsset_set(unsigned int id, unsigned char up_hsset); ++void hdmi_reg_fd_clk_sel_set(unsigned int id, unsigned char up_fd_clk_sel); ++void hdmi_reg_refclk_sel_set(unsigned int id, unsigned char up_refclk_sel); ++void hdmi_reg_ctman_set(unsigned int id, unsigned char up_ctman); ++void hdmi_reg_modclk_sel_set(unsigned int id, unsigned char up_modclk_sel); ++void hdmi_reg_fdivclk_sel_set(unsigned int id, unsigned char up_fdivclk_sel); ++void hdmi_reg_mod_div_val_set(unsigned int id, unsigned char mod_div_val); ++void hdmi_reg_dac_clock_gat_set(unsigned int id, unsigned char dac_clock_gat); ++void hdmi_reg_swreset_unused_set(unsigned int id, unsigned short swreset_unused); ++void hdmi_reg_global_reset_set(unsigned int id, unsigned char global_reset); ++void hdmi_reg_sw_reset_mod_clock_set(unsigned int id, unsigned char sw_reset_mod_clock); ++void hdmi_reg_sw_reset_tmds_clock_set(unsigned int id, unsigned char sw_reset_tmds_clock); ++void hdmi_reg_sw_reset_mpll_clock_set(unsigned int id, unsigned char sw_reset_mpll_clock); ++void hdmi_reg_sw_reset_nco_clock_set(unsigned int id, unsigned char sw_reset_nco_clock); ++void hdmi_reg_sw_reset_fd_clock_set(unsigned int id, unsigned char sw_reset_fd_clock); ++void hdmi_reg_sw_reset_mod_and_mpll_clock_set(unsigned int id, unsigned char sw_reset_mod_and_mpll_clock); ++void hdmi_reg_sw_reset_mod_and_nco_clock_set(unsigned int id, unsigned char sw_reset_mod_and_nco_clock); ++void hdmi_reg_sw_reset_mod_and_fd_clock_set(unsigned int id, unsigned char sw_reset_mod_and_fd_clock); ++void hdmi_reg_sw_reset_hsfifo_clock_set(unsigned int id, unsigned char sw_reset_hsfifo_clock); ++void hdmi_reg_sw_reset_txfifo_clock_set(unsigned int id, unsigned char sw_reset_txfifo_clock); ++void hdmi_reg_sw_reset_data_clock_set(unsigned int id, unsigned char sw_reset_data_clock); ++void hdmi_reg_sw_reset_hs_clock_set(unsigned int id, unsigned char sw_reset_hs_clock); ++void hdmi_reg_sw_reset_pllref_clock_set(unsigned int id, unsigned char sw_reset_pllref_clock); ++void hdmi_reg_sw_reset_dac_clock_set(unsigned int id, unsigned char sw_reset_dac_clock); ++void hdmi_reg_up_sample_fifo_clock_swrst_set(unsigned int id, unsigned char up_sample_fifo_clock_swrst); ++void hdmi_reg_fcdstepset_unused_set(unsigned int id, unsigned char fcdstepset_unused); ++void hdmi_reg_req_length_set(unsigned int id, unsigned char req_length); ++void hdmi_reg_stb_cs_sel_set(unsigned int id, unsigned char stb_cs_sel); ++void hdmi_reg_fdsrcparam_unused_set(unsigned int id, unsigned char fdsrcparam_unused); ++void hdmi_reg_fcg_en_set(unsigned int id, unsigned char up_fcg_en); ++void hdmi_reg_fcg_dlf_en_set(unsigned int id, unsigned char up_fcg_dlf_en); ++void hdmi_reg_fcg_dither_en_set(unsigned int id, unsigned char up_fcg_dither_en); ++void hdmi_reg_fcg_lock_en_set(unsigned int id, unsigned char up_fcg_lock_en); ++void hdmi_reg_lock_th_set(unsigned int id, unsigned char up_lock_th); ++void hdmi_reg_txfifoset0_unused_set(unsigned int id, unsigned char txfifoset0_unused); ++void hdmi_reg_mode_en_set(unsigned int id, unsigned char reg_hdmi_mode_en); ++void hdmi_reg_sw_reset_frl_clock_set(unsigned int id, unsigned char sw_reset_frl_clock); ++void hdmi_reg_stb_delay2_set(unsigned int id, unsigned char stb_delay2); ++void hdmi_reg_stb_delay1_set(unsigned int id, unsigned char stb_delay1); ++void hdmi_reg_stb_delay0_set(unsigned int id, unsigned char stb_delay0); ++void hdmi_reg_stb_acc_sel_set(unsigned int id, unsigned char stb_acc_sel); ++#endif /* HDMI_REG_DPHY_H */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c +new file mode 100755 +index 000000000..1911959b6 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c +@@ -0,0 +1,782 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "smart_drm_drv.h" ++#include "smart_vo.h" ++#include "hdmi_reg_audio_path.h" ++#include "hdmi_reg_ctrl.h" ++#include "hdmi_reg_tx.h" ++ ++#define DRIVER_NAME "smart" ++#define DRIVER_DESC "SMART VISION Soc DRM" ++#define DRIVER_DATE "20250922" ++#define DRIVER_MAJOR 1 ++#define DRIVER_MINOR 0 ++ ++static const struct drm_driver smart_drm_driver; ++ ++#define SMART_HDMI_AUDIO_FRAME_LENGTH 10 ++#define SMART_HDMI_INFOFRAME_HEADER_SIZE 3 ++#define SMART_HDMI_AUDIO_INFOFRAME_SIZE (SMART_HDMI_INFOFRAME_HEADER_SIZE + SMART_HDMI_AUDIO_FRAME_LENGTH) ++#define SMART_HDMI_INFOFRAME_BUFFER_SIZE 31 ++#define SMART_HDMI_AUDIO_DEFAULT_TMDS_CLK 148500 ++#define SMART_HDMI_AUDIO_N_DEFAULT 6144 ++#define SMART_HDMI_AUDIO_NCTS_DEVIATION 20 ++#define SMART_HDMI_AUDIO_I2S_SD_ALL 0xf ++#define SMART_HDMI_AUDIO_HBRA_MASK_NONE 0xf ++#define SMART_HDMI_AUDIO_CLK_ACCURACY_LEVEL2 0x0 ++#define SMART_HDMI_AUDIO_CODING_STREAM 0x0 ++#define SMART_HDMI_AUDIO_INTF_I2S 0x0 ++#define SMART_HDMI_AUDIO_INTF_SPDIF 0x1 ++#define SMART_HDMI_AUDIO_INTF_HBRA 0x2 ++ ++struct smart_drm_audio_frame { ++ __u32 enable; ++ __u32 sample_rate; ++ __u32 bit_depth; ++ __u32 channels; ++ __u32 sound_intf; ++ __u32 tmds_clk; ++ __u64 pcm_addr; ++ __u32 pcm_bytes; ++ __u32 reserved; ++}; ++ ++struct smart_drm_hdmi_sink_status { ++ __u32 connected; ++ __u32 sink_has_audio; ++ __u32 connector_status; ++ __u32 reserved; ++}; ++ ++struct smart_hdmi_audio_cts_n { ++ __u32 sample_rate; ++ __u32 tmds_clk; ++ __u32 n; ++}; ++ ++struct smart_hdmi_audio_rate_reg { ++ __u32 sample_rate; ++ __u8 fs; ++ __u8 org_fs; ++}; ++ ++struct smart_hdmi_audio_bit_reg { ++ __u32 bit_depth; ++ __u8 reg; ++}; ++ ++static const struct smart_hdmi_audio_cts_n smart_hdmi_audio_cts_n[] = { ++ { 32000, 25174, 4576 }, { 32000, 25200, 4096 }, { 32000, 27000, 4096 }, ++ { 32000, 27027, 4096 }, { 32000, 54000, 4096 }, { 32000, 54054, 4096 }, ++ { 32000, 74175, 11648 }, { 32000, 74250, 4096 }, { 32000, 148351, 11648 }, ++ { 32000, 148500, 4096 }, { 32000, 296703, 5824 }, { 32000, 297000, 3072 }, ++ { 32000, 593406, 5824 }, { 32000, 594000, 3072 }, { 32000, 0, 4096 }, ++ { 44100, 25174, 7007 }, { 44100, 25200, 6272 }, { 44100, 27000, 6272 }, ++ { 44100, 27027, 6272 }, { 44100, 54000, 6272 }, { 44100, 54054, 6272 }, ++ { 44100, 74175, 17836 }, { 44100, 74250, 6272 }, { 44100, 148351, 8918 }, ++ { 44100, 148500, 6272 }, { 44100, 296703, 4459 }, { 44100, 297000, 4704 }, ++ { 44100, 593406, 8918 }, { 44100, 594000, 9408 }, { 44100, 0, 6272 }, ++ { 48000, 25174, 6864 }, { 48000, 25200, 6144 }, { 48000, 27000, 6144 }, ++ { 48000, 27027, 6144 }, { 48000, 54000, 6144 }, { 48000, 54054, 6144 }, ++ { 48000, 74175, 11648 }, { 48000, 74250, 6144 }, { 48000, 148351, 5824 }, ++ { 48000, 148500, 6144 }, { 48000, 296703, 5824 }, { 48000, 297000, 5120 }, ++ { 48000, 593406, 5824 }, { 48000, 594000, 6144 }, { 48000, 0, 6144 }, ++}; ++ ++static const struct smart_hdmi_audio_rate_reg smart_hdmi_audio_rate_regs[] = { ++ { 32000, 0x03, 0x0c }, ++ { 44100, 0x00, 0x0f }, ++ { 48000, 0x02, 0x0d }, ++}; ++ ++static const struct smart_hdmi_audio_bit_reg smart_hdmi_audio_bit_regs[] = { ++ { 16, 0x2 }, ++ { 17, 0xc }, ++ { 18, 0x4 }, ++ { 19, 0x8 }, ++ { 20, 0xa }, ++ { 21, 0xd }, ++ { 22, 0x5 }, ++ { 23, 0x9 }, ++ { 24, 0xb }, ++}; ++ ++static const struct smart_hdmi_audio_rate_reg *smart_hdmi_audio_rate_reg_get(__u32 sample_rate) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(smart_hdmi_audio_rate_regs); i++) { ++ if (smart_hdmi_audio_rate_regs[i].sample_rate == sample_rate) ++ return &smart_hdmi_audio_rate_regs[i]; ++ } ++ ++ return NULL; ++} ++ ++static __u8 smart_hdmi_audio_bit_reg_get(__u32 bit_depth) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(smart_hdmi_audio_bit_regs); i++) { ++ if (smart_hdmi_audio_bit_regs[i].bit_depth == bit_depth) ++ return smart_hdmi_audio_bit_regs[i].reg; ++ } ++ ++ return 0; ++} ++ ++static __u32 smart_hdmi_audio_n_get(__u32 sample_rate, __u32 tmds_clk) ++{ ++ int i; ++ __u32 lower = tmds_clk > SMART_HDMI_AUDIO_NCTS_DEVIATION ? ++ tmds_clk - SMART_HDMI_AUDIO_NCTS_DEVIATION : 0; ++ __u32 upper = tmds_clk + SMART_HDMI_AUDIO_NCTS_DEVIATION; ++ ++ for (i = 0; i < ARRAY_SIZE(smart_hdmi_audio_cts_n); i++) { ++ const struct smart_hdmi_audio_cts_n *ncts = &smart_hdmi_audio_cts_n[i]; ++ ++ if (ncts->sample_rate != sample_rate) ++ continue; ++ ++ if (ncts->tmds_clk == tmds_clk) ++ return ncts->n; ++ ++ if (ncts->tmds_clk >= lower && ncts->tmds_clk <= upper) ++ return ncts->n; ++ ++ if (ncts->tmds_clk == 0) ++ return ncts->n; ++ } ++ ++ return SMART_HDMI_AUDIO_N_DEFAULT; ++} ++ ++static void smart_hdmi_audio_reset(void) ++{ ++ hdmi_reg_tx_afifo_srst_req_set(1); ++ hdmi_reg_tx_acr_srst_req_set(1); ++ hdmi_reg_tx_aud_srst_req_set(1); ++ hdmi_reg_tx_afifo_srst_req_set(0); ++ hdmi_reg_tx_acr_srst_req_set(0); ++ hdmi_reg_tx_aud_srst_req_set(0); ++} ++ ++static void smart_hdmi_audio_infoframe_checksum(__u8 *buffer, __u32 length) ++{ ++ __u8 checksum = 0; ++ __u32 i; ++ ++ buffer[3] = 0; ++ for (i = 0; i < length; i++) ++ checksum += buffer[i]; ++ ++ buffer[3] = 0 - checksum; ++} ++ ++static __u8 smart_hdmi_audio_channel_allocation(__u32 channels) ++{ ++ switch (channels) { ++ case 3: ++ return 0x01; ++ case 6: ++ return 0x0b; ++ case 8: ++ return 0x13; ++ default: ++ return 0x00; ++ } ++} ++ ++static void smart_hdmi_audio_infoframe_enable(bool enable) ++{ ++ hdmi_reg_cea_aud_rpt_en_set(enable); ++ hdmi_reg_cea_aud_en_set(enable); ++} ++ ++static void smart_hdmi_audio_infoframe_send(const struct smart_drm_audio_frame *frame) ++{ ++ __u8 buffer[SMART_HDMI_INFOFRAME_BUFFER_SIZE] = {0}; ++ __u8 channel_count = 0; ++ ++ if (frame->sound_intf == SMART_HDMI_AUDIO_INTF_I2S && frame->channels >= 2) ++ channel_count = frame->channels - 1; ++ ++ buffer[0] = 0x84; ++ buffer[1] = 0x01; ++ buffer[2] = SMART_HDMI_AUDIO_FRAME_LENGTH; ++ buffer[4] = (SMART_HDMI_AUDIO_CODING_STREAM << 4) | (channel_count & 0x7); ++ if (frame->sound_intf == SMART_HDMI_AUDIO_INTF_I2S) ++ buffer[7] = smart_hdmi_audio_channel_allocation(frame->channels); ++ smart_hdmi_audio_infoframe_checksum(buffer, SMART_HDMI_AUDIO_INFOFRAME_SIZE); ++ ++ smart_hdmi_audio_infoframe_enable(false); ++ hdmi_reg_audio_pkt_header_set(buffer[0], buffer[1], buffer[2]); ++ hdmi_reg_audio_pkt0_low_set(buffer[3], buffer[4], buffer[5], buffer[6]); ++ hdmi_reg_audio_pkt0_high_set(buffer[7], buffer[8], buffer[9]); ++ hdmi_reg_audio_pkt1_low_set(buffer[10], buffer[11], buffer[12], buffer[13]); ++ hdmi_reg_audio_pkt1_high_set(buffer[14], buffer[15], buffer[16]); ++ hdmi_reg_audio_pkt2_low_set(buffer[17], buffer[18], buffer[19], buffer[20]); ++ hdmi_reg_audio_pkt2_high_set(buffer[21], buffer[22], buffer[23]); ++ hdmi_reg_audio_pkt3_low_set(buffer[24], buffer[25], buffer[26], buffer[27]); ++ hdmi_reg_audio_pkt3_high_set(buffer[28], buffer[29], buffer[30]); ++ smart_hdmi_audio_infoframe_enable(true); ++} ++ ++static int smart_hdmi_audio_frame_normalize(struct smart_drm_audio_frame *frame) ++{ ++ if (!frame->sample_rate) ++ frame->sample_rate = 48000; ++ if (!frame->bit_depth) ++ frame->bit_depth = 16; ++ if (!frame->channels) ++ frame->channels = 2; ++ if (!frame->tmds_clk) ++ frame->tmds_clk = SMART_HDMI_AUDIO_DEFAULT_TMDS_CLK; ++ ++ if (frame->sample_rate != 32000 && frame->sample_rate != 44100 && ++ frame->sample_rate != 48000) ++ return -EINVAL; ++ ++ if (frame->bit_depth != 16) ++ return -EOPNOTSUPP; ++ ++ if (frame->channels < 2 || frame->channels > 8) ++ return -EINVAL; ++ ++ if (frame->sound_intf != SMART_HDMI_AUDIO_INTF_I2S && ++ frame->sound_intf != SMART_HDMI_AUDIO_INTF_SPDIF && ++ frame->sound_intf != SMART_HDMI_AUDIO_INTF_HBRA) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int smart_hdmi_audio_path_config(struct smart_drm_audio_frame *frame) ++{ ++ const struct smart_hdmi_audio_rate_reg *rate_reg; ++ __u8 bit_reg; ++ __u32 n; ++ ++ if (!frame->enable) { ++ hdmi_reg_aud_in_en_set(0); ++ smart_hdmi_audio_infoframe_enable(false); ++ return 0; ++ } ++ ++ rate_reg = smart_hdmi_audio_rate_reg_get(frame->sample_rate); ++ bit_reg = smart_hdmi_audio_bit_reg_get(frame->bit_depth); ++ if (!rate_reg || !bit_reg) ++ return -EINVAL; ++ ++ hdmi_reg_aud_in_en_set(0); ++ smart_hdmi_audio_reset(); ++ ++ hdmi_reg_aud_layout_set(frame->channels == 8); ++ hdmi_reg_i2s_1st_shift_set(0); ++ hdmi_reg_i2s_ws_polarity_set(0); ++ hdmi_reg_i2s_justify_set(0); ++ hdmi_reg_i2s_data_dir_set(0); ++ hdmi_reg_i2s_vbit_set(0); ++ hdmi_reg_i2s_length_set(bit_reg); ++ hdmi_reg_i2s_ch_swap_set(0); ++ ++ hdmi_reg_chst_byte0_aset(0); ++ hdmi_reg_chst_byte0_bset(0); ++ hdmi_reg_chst_byte3_fs_set(rate_reg->fs); ++ hdmi_reg_chst_byte3_clock_accuracy_set(SMART_HDMI_AUDIO_CLK_ACCURACY_LEVEL2); ++ hdmi_reg_chst_byte4_org_fs_set(rate_reg->org_fs); ++ hdmi_reg_chst_byte4_length_set(bit_reg); ++ ++ hdmi_reg_aud_fifo_test_set(0); ++ hdmi_reg_aud_fifo_hbr_mask_set(SMART_HDMI_AUDIO_HBRA_MASK_NONE); ++ hdmi_reg_acr_cts_hw_sw_sel_set(0); ++ n = smart_hdmi_audio_n_get(frame->sample_rate, frame->tmds_clk); ++ hdmi_reg_acr_n_val_sw_set(n); ++ ++ hdmi_reg_aud_i2s_en_set(SMART_HDMI_AUDIO_I2S_SD_ALL); ++ hdmi_reg_aud_spdif_en_set(0); ++ hdmi_reg_i2s_hbra_on_set(0); ++ smart_hdmi_audio_infoframe_send(frame); ++ hdmi_reg_aud_in_en_set(1); ++ ++ return 0; ++} ++ ++static int smart_hdmi_audio_pcm_receive(const struct smart_drm_audio_frame *frame) ++{ ++ void *pcm; ++ ++ if (!frame->pcm_addr || !frame->pcm_bytes) ++ return 0; ++ ++ pcm = memdup_user(u64_to_user_ptr(frame->pcm_addr), frame->pcm_bytes); ++ if (IS_ERR(pcm)) ++ return PTR_ERR(pcm); ++ ++ /* ++ * HDMI TX consumes samples from the SoC AO/I2S input. The ioctl owns ++ * HDMI audio path setup; PCM playback still depends on the AO block ++ * being configured to INNERHDMI by the caller. ++ */ ++ kfree(pcm); ++ return 0; ++} ++ ++ ++ ++static int smart_drm_init_iommu(struct drm_device *drm_dev) ++{ ++ struct smart_drm_private *private = drm_dev->dev_private; ++ struct iommu_domain_geometry *geometry; ++ u64 start, end; ++ ++ if (IS_ERR_OR_NULL(private->iommu_dev)) ++ return 0; ++ ++ private->domain = iommu_domain_alloc(private->iommu_dev->bus); ++ if (!private->domain) ++ return -ENOMEM; ++ ++ geometry = &private->domain->geometry; ++ start = geometry->aperture_start; ++ end = geometry->aperture_end; ++ ++ printk("IOMMU context initialized (aperture: %#llx-%#llx)\n", ++ start, end); ++ drm_mm_init(&private->mm, start, end - start + 1); ++ mutex_init(&private->mm_lock); ++ ++ return 0; ++} ++ ++static void smart_iommu_cleanup(struct drm_device *drm_dev) ++{ ++ struct smart_drm_private *private = drm_dev->dev_private; ++ ++ if (!private->domain) ++ return; ++ ++ drm_mm_takedown(&private->mm); ++ iommu_domain_free(private->domain); ++} ++ ++static const struct drm_mode_config_helper_funcs smart_drm_mode_config_helper = { ++ .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, ++}; ++ ++static const struct drm_mode_config_funcs smart_drm_mode_config_funcs = { ++ .fb_create = drm_gem_fb_create, ++ .output_poll_changed = drm_fb_helper_output_poll_changed, ++ .atomic_check = drm_atomic_helper_check, ++ .atomic_commit = drm_atomic_helper_commit, ++}; ++ ++void smart_drm_mode_config_init(struct drm_device *dev) ++{ ++ ++ dev->mode_config.min_width = 0; ++ dev->mode_config.min_height = 0; ++ ++ /* ++ * set max width and height as default value(4096x4096). ++ * this value would be used to check framebuffer size limitation ++ * at drm_mode_addfb(). ++ */ ++ dev->mode_config.max_width = 4096; ++ dev->mode_config.max_height = 4096; ++ ++ dev->mode_config.funcs = &smart_drm_mode_config_funcs; ++ dev->mode_config.helper_private = &smart_drm_mode_config_helper; ++} ++ ++ ++static int smart_drm_bind(struct device *dev) ++{ ++ struct drm_device *drm_dev; ++ struct smart_drm_private *private; ++ int ret; ++ //struct drm_crtc *crtc; ++ ++ /* Remove existing drivers that may own the framebuffer memory. */ ++ ret = drm_aperture_remove_framebuffers(&smart_drm_driver); ++ if (ret) { ++ DRM_DEV_ERROR(dev, ++ "Failed to remove existing framebuffers - %d.\n", ++ ret); ++ return ret; ++ } ++ ++ drm_dev = drm_dev_alloc(&smart_drm_driver, dev); ++ if (IS_ERR(drm_dev)) ++ return PTR_ERR(drm_dev); ++ ++ dev_set_drvdata(dev, drm_dev); ++ ++ private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL); ++ if (!private) { ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ ++ drm_dev->dev_private = private; ++ ++ ret = drmm_mode_config_init(drm_dev); ++ if (ret) ++ goto err_free; ++ ++ smart_drm_mode_config_init(drm_dev); ++ ++ ++ /* Try to bind all sub drivers. */ ++ ret = component_bind_all(dev, drm_dev); ++ if (ret) ++ goto err_free; ++ ++ ret = smart_drm_init_iommu(drm_dev); ++ if (ret) ++ goto err_unbind_all; ++ ++ ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc); ++ if (ret) ++ goto err_iommu_cleanup; ++ ++ drm_mode_config_reset(drm_dev); ++ ++ /* init kms poll for handling hpd */ ++ drm_kms_helper_poll_init(drm_dev); ++ ++ ret = drm_dev_register(drm_dev, 0); ++ if (ret) ++ goto err_kms_helper_poll_fini; ++ ++ drm_fbdev_generic_setup(drm_dev, 0); ++ return 0; ++err_kms_helper_poll_fini: ++ drm_kms_helper_poll_fini(drm_dev); ++err_iommu_cleanup: ++ smart_iommu_cleanup(drm_dev); ++err_unbind_all: ++ component_unbind_all(dev, drm_dev); ++err_free: ++ drm_dev_put(drm_dev); ++ return ret; ++} ++ ++static void smart_drm_unbind(struct device *dev) ++{ ++ struct drm_device *drm_dev = dev_get_drvdata(dev); ++ ++ drm_dev_unregister(drm_dev); ++ ++ drm_kms_helper_poll_fini(drm_dev); ++ ++ drm_atomic_helper_shutdown(drm_dev); ++ component_unbind_all(dev, drm_dev); ++ smart_iommu_cleanup(drm_dev); ++ ++ drm_dev_put(drm_dev); ++} ++ ++// 私有ioctl命令定义 ++#define DRM_HI3403V100_OVERLAY_FLUSH 1 ++#define DRM_IOCTL_HI3403V100_OVERLAY_FLUSH DRM_IOWR(DRM_COMMAND_BASE + DRM_HI3403V100_OVERLAY_FLUSH, ot_video_frame_info) ++ ++static int smart_drm_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) ++{ ++ ot_video_frame_info video_frame_info = {0}; ++ ++ // 复制用户数据到内核空间 ++ if(data == NULL) { ++ printk("%s,%d data == NULL\n",__func__,__LINE__); ++ return -EINVAL; ++ } ++ memcpy(&video_frame_info, data, sizeof(video_frame_info)); ++ drm_overlay_update(&video_frame_info); ++ return 0; ++} ++ ++#define DRM_HI3403V100_AUDIO_SET_CONFIG 2 ++#define DRM_IOCTL_HI3403V100_AUDIO_SET_CONFIG DRM_IOWR(DRM_COMMAND_BASE + DRM_HI3403V100_AUDIO_SET_CONFIG, struct smart_drm_audio_frame) ++ ++static int smart_drm_audio_set_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) ++{ ++ struct smart_drm_audio_frame audio_frame = {0}; ++ int ret; ++ ++ if (data == NULL) { ++ printk("%s,%d data == NULL\n", __func__, __LINE__); ++ return -EINVAL; ++ } ++ ++ memcpy(&audio_frame, data, sizeof(audio_frame)); ++ ret = smart_hdmi_audio_frame_normalize(&audio_frame); ++ if (ret != 0) ++ return ret; ++ ++ ret = smart_hdmi_audio_path_config(&audio_frame); ++ if (ret != 0) ++ return ret; ++ ++ return smart_hdmi_audio_pcm_receive(&audio_frame); ++} ++ ++#define DRM_HI3403V100_HDMI_GET_SINK_STATUS 3 ++#define DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS DRM_IOWR(DRM_COMMAND_BASE + DRM_HI3403V100_HDMI_GET_SINK_STATUS, struct smart_drm_hdmi_sink_status) ++ ++static int smart_drm_hdmi_get_sink_status_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) ++{ ++ struct smart_drm_hdmi_sink_status status = {0}; ++ struct drm_connector_list_iter conn_iter; ++ struct drm_connector *connector; ++ ++ if (data == NULL) { ++ printk("%s,%d data == NULL\n", __func__, __LINE__); ++ return -EINVAL; ++ } ++ ++ status.connector_status = connector_status_unknown; ++ ++ drm_connector_list_iter_begin(dev, &conn_iter); ++ drm_for_each_connector_iter(connector, &conn_iter) { ++ if (connector->connector_type != DRM_MODE_CONNECTOR_HDMIA && ++ connector->connector_type != DRM_MODE_CONNECTOR_HDMIB) ++ continue; ++ ++ if (connector->funcs && connector->funcs->detect) ++ connector->status = connector->funcs->detect(connector, false); ++ ++ status.connector_status = connector->status; ++ status.connected = connector->status == connector_status_connected; ++ status.sink_has_audio = connector->display_info.has_audio; ++ break; ++ } ++ drm_connector_list_iter_end(&conn_iter); ++ ++ memcpy(data, &status, sizeof(status)); ++ return 0; ++} ++ ++static const struct drm_ioctl_desc smart_ioctls[] = { ++ DRM_IOCTL_DEF_DRV(HI3403V100_OVERLAY_FLUSH, smart_drm_flush_ioctl, DRM_AUTH), ++ DRM_IOCTL_DEF_DRV(HI3403V100_AUDIO_SET_CONFIG, smart_drm_audio_set_config_ioctl, DRM_AUTH), ++ DRM_IOCTL_DEF_DRV(HI3403V100_HDMI_GET_SINK_STATUS, smart_drm_hdmi_get_sink_status_ioctl, DRM_AUTH), ++}; ++ ++ ++DEFINE_DRM_GEM_FOPS(smart_drm_driver_fops); ++ ++static const struct drm_driver smart_drm_driver = { ++ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, ++ .dumb_create = drm_gem_dma_dumb_create, ++ .gem_prime_import_sg_table = drm_gem_dma_prime_import_sg_table, ++ .ioctls = smart_ioctls, ++ .num_ioctls = ARRAY_SIZE(smart_ioctls), ++ .fops = &smart_drm_driver_fops, ++ .name = DRIVER_NAME, ++ .desc = DRIVER_DESC, ++ .date = DRIVER_DATE, ++ .major = DRIVER_MAJOR, ++ .minor = DRIVER_MINOR, ++}; ++ ++#ifdef CONFIG_PM_SLEEP ++static int smart_drm_sys_suspend(struct device *dev) ++{ ++ struct drm_device *drm = dev_get_drvdata(dev); ++ ++ return drm_mode_config_helper_suspend(drm); ++} ++ ++static int smart_drm_sys_resume(struct device *dev) ++{ ++ struct drm_device *drm = dev_get_drvdata(dev); ++ ++ return drm_mode_config_helper_resume(drm); ++} ++#endif ++ ++static const struct dev_pm_ops smart_drm_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(smart_drm_sys_suspend, ++ smart_drm_sys_resume) ++}; ++ ++#define MAX_SMART_SUB_DRIVERS 16 ++static struct platform_driver *smart_sub_drivers[MAX_SMART_SUB_DRIVERS]; ++static int num_smart_sub_drivers; ++ ++ ++static void smart_drm_match_remove(struct device *dev) ++{ ++ struct device_link *link; ++ ++ list_for_each_entry(link, &dev->links.consumers, s_node) ++ device_link_del(link); ++} ++ ++static struct component_match *smart_drm_match_add(struct device *dev) ++{ ++ struct component_match *match = NULL; ++ int i; ++ for (i = 0; i < num_smart_sub_drivers; i++) { ++ struct platform_driver *drv = smart_sub_drivers[i]; ++ struct device *p = NULL, *d; ++ ++ do { ++ d = platform_find_device_by_driver(p, &drv->driver); ++ put_device(p); ++ p = d; ++ ++ if (!d) ++ break; ++ ++ device_link_add(dev, d, DL_FLAG_STATELESS); ++ component_match_add(dev, &match, component_compare_dev, d); ++ } while (true); ++ } ++ ++ if (IS_ERR(match)) ++ smart_drm_match_remove(dev); ++ return match ?: ERR_PTR(-ENODEV); ++} ++ ++static const struct component_master_ops smart_drm_ops = { ++ .bind = smart_drm_bind, ++ .unbind = smart_drm_unbind, ++}; ++ ++static int smart_drm_platform_of_probe(struct device *dev) ++{ ++ ++ return 0; ++} ++ ++static int smart_drm_platform_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct component_match *match = NULL; ++ int ret; ++ ++ ret = smart_drm_platform_of_probe(dev); ++ if (ret) ++ return ret; ++ ++ match = smart_drm_match_add(dev); ++ if (IS_ERR(match)) ++ return PTR_ERR(match); ++ ++ ret = component_master_add_with_match(dev, &smart_drm_ops, match); ++ if (ret < 0) { ++ smart_drm_match_remove(dev); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void smart_drm_platform_remove(struct platform_device *pdev) ++{ ++ ++ component_master_del(&pdev->dev, &smart_drm_ops); ++ ++ smart_drm_match_remove(&pdev->dev); ++} ++ ++static void smart_drm_platform_shutdown(struct platform_device *pdev) ++{ ++ struct drm_device *drm = platform_get_drvdata(pdev); ++ ++ if (drm) ++ drm_atomic_helper_shutdown(drm); ++} ++ ++static const struct of_device_id smart_drm_dt_ids[] = { ++ { .compatible = "vendor,drm", }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, smart_drm_dt_ids); ++ ++static struct platform_driver smart_drm_platform_driver = { ++ .probe = smart_drm_platform_probe, ++ .remove_new = smart_drm_platform_remove, ++ .shutdown = smart_drm_platform_shutdown, ++ .driver = { ++ .name = "smart-drm", ++ .of_match_table = smart_drm_dt_ids, ++ .pm = &smart_drm_pm_ops, ++ }, ++}; ++ ++#define ADD_SMART_SUB_DRIVER(drv, cond) { \ ++ if (IS_ENABLED(cond) && \ ++ !WARN_ON(num_smart_sub_drivers >= MAX_SMART_SUB_DRIVERS)) \ ++ smart_sub_drivers[num_smart_sub_drivers++] = &drv; \ ++} ++ ++static int __init smart_drm_init(void) ++{ ++ int ret; ++ ++ ++ num_smart_sub_drivers = 0; ++ ADD_SMART_SUB_DRIVER(smart_vop_driver, ++ CONFIG_DRM_HISI_SMART_VISION); ++ ++ ADD_SMART_SUB_DRIVER(smart_hdmi_driver, ++ CONFIG_DRM_HISI_SMART_VISION); ++ ++ ret = platform_register_drivers(smart_sub_drivers, ++ num_smart_sub_drivers); ++ ++ ++ if (ret) ++ return ret; ++ ++ ret = platform_driver_register(&smart_drm_platform_driver); ++ if (ret) ++ goto err_unreg_drivers; ++ ++ return 0; ++ ++err_unreg_drivers: ++ platform_unregister_drivers(smart_sub_drivers, ++ num_smart_sub_drivers); ++ ++ return ret; ++} ++ ++static void __exit smart_drm_fini(void) ++{ ++ platform_driver_unregister(&smart_drm_platform_driver); ++ ++ platform_unregister_drivers(smart_sub_drivers, ++ num_smart_sub_drivers); ++} ++ ++module_init(smart_drm_init); ++module_exit(smart_drm_fini); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("runkaihong"); ++MODULE_DESCRIPTION("SMART DRM for platform/SoC device"); ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.h b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.h +new file mode 100755 +index 000000000..bff908db8 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.h +@@ -0,0 +1,104 @@ ++#ifndef _HI3403V100_DRM_DRV_H ++#define _HI3403V100_DRM_DRV_H ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define HI3403V100_MAX_FB_BUFFER 3 ++#define HI3403V100_MAX_CONNECTOR 2 ++#define HI3403V100_MAX_CRTC 4 ++ ++ ++#define HI3403V100_OUT_MODE_P888 0 ++#define HI3403V100_OUT_MODE_BT1120 0 ++#define HI3403V100_OUT_MODE_P666 1 ++#define HI3403V100_OUT_MODE_P565 2 ++#define HI3403V100_OUT_MODE_BT656 5 ++#define HI3403V100_OUT_MODE_S888 8 ++#define HI3403V100_OUT_MODE_S888_DUMMY 12 ++#define HI3403V100_OUT_MODE_YUV420 14 ++/* for use special outface */ ++#define HI3403V100_OUT_MODE_AAAA 15 ++ ++/* output flags */ ++#define HI3403V100_OUTPUT_DSI_DUAL BIT(0) ++ ++struct drm_device; ++struct drm_connector; ++struct iommu_domain; ++ ++ ++typedef struct { ++ bool syncm; /* RW; sync mode(0:timing,as BT.656; 1:signal,as LCD) */ ++ bool iop; /* RW; interlaced or progressive display(0:i; 1:p) */ ++ unsigned char intfb; /* RW; interlaced bit width while output */ ++ ++ unsigned short vact; /* RW; vertical active area */ ++ unsigned short vbb; /* RW; vertical back blank porch */ ++ unsigned short vfb; /* RW; vertical front blank porch */ ++ ++ unsigned short hact; /* RW; horizontal active area */ ++ unsigned short hbb; /* RW; horizontal back blank porch */ ++ unsigned short hfb; /* RW; horizontal front blank porch */ ++ unsigned short hmid; /* RW; bottom horizontal active area */ ++ ++ unsigned short bvact; /* RW; bottom vertical active area */ ++ unsigned short bvbb; /* RW; bottom vertical back blank porch */ ++ unsigned short bvfb; /* RW; bottom vertical front blank porch */ ++ ++ unsigned short hpw; /* RW; horizontal pulse width */ ++ unsigned short vpw; /* RW; vertical pulse width */ ++ ++ bool idv; /* RW; inverse data valid of output */ ++ bool ihs; /* RW; inverse horizontal synchronization signal */ ++ bool ivs; /* RW; inverse vertical synchronization signal */ ++} ot_vo_sync_info; ++ ++struct smart_crtc_state { ++ struct drm_crtc_state base; ++ u8 encoder_type; ++ unsigned int bg_color; /* RW; background color of a device, in RGB format. */ ++ unsigned int intf_type; /* RW; type of a VO interface */ ++ unsigned int intf_sync; /* RW; type of a VO interface timing */ ++ ot_vo_sync_info sync_info; /* RW; information about VO interface timing */ ++}; ++#define to_smart_crtc_state(s) \ ++ container_of(s, struct smart_crtc_state, base) ++ ++ ++struct smart_drm_private { ++ struct iommu_domain *domain; ++ struct device *iommu_dev; ++ struct mutex mm_lock; ++ struct drm_mm mm; ++}; ++ ++struct smart_encoder { ++ int crtc_endpoint_id; ++ struct drm_encoder encoder; ++}; ++ ++int smart_drm_dma_attach_device(struct drm_device *drm_dev, ++ struct device *dev); ++void smart_drm_dma_detach_device(struct drm_device *drm_dev, ++ struct device *dev); ++void smart_drm_dma_init_device(struct drm_device *drm_dev, ++ struct device *dev); ++int smart_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); ++int smart_drm_encoder_set_crtc_endpoint_id(struct smart_encoder *rencoder, ++ struct device_node *np, int port, int reg); ++int smart_drm_endpoint_is_subdriver(struct device_node *ep); ++extern struct platform_driver smart_hdmi_driver; ++extern struct platform_driver smart_vop_driver; ++static inline struct smart_encoder *to_smart_encoder(struct drm_encoder *encoder) ++{ ++ return container_of(encoder, struct smart_encoder, encoder); ++} ++ ++#endif /* _HI3403V100_DRM_DRV_H_ */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.c b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.c +new file mode 100755 +index 000000000..9f113ec5f +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.c +@@ -0,0 +1,2122 @@ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "smart_hdmi.h" ++#include "smart_vo.h" ++#include "smart_drm_drv.h" ++ ++ ++struct hdmi_data_info { ++ int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ ++ bool sink_is_hdmi; ++ bool sink_has_audio; ++ ++ unsigned int enc_out_format; ++ unsigned int colorimetry; ++ unsigned int quant_range; ++}; ++ ++struct smart_hdmi { ++ struct device *dev; ++ struct drm_device *drm_dev; ++ ++ struct drm_connector connector; ++ struct smart_encoder encoder; ++ ++ unsigned int tmdsclk; ++ spinlock_t reg_lock; ++ ++ struct hdmi_data_info hdmi_data; ++ struct drm_display_mode previous_mode; ++ ++}; ++ ++struct hdmi_video_def g_cea_video_codes_des[CEA_VIDEO_CODE_MAX] = { ++// { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++// HDMI_PICTURE_ASPECT_NONE, HDMI_VIDEO_TIMING_UNKNOWN, HDMI_VIDEO_UNKNOWN, "NONE" }, ++ { HDMI_640X480P60_4_3, 25175, 59940, 640, 480, 160, 45, 16, 96, 48, 10, 2, 33, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_640X480P_60000, HDMI_VIDEO_PROGRESSIVE, "640*480p60 4:3" }, ++ { HDMI_720X480P60_4_3, 27000, 59940, 720, 480, 138, 45, 16, 62, 60, 9, 6, 30, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_720X480P_60000, HDMI_VIDEO_PROGRESSIVE, "720*480p60 4:3" }, ++ { HDMI_720X480P60_16_9, 27000, 59940, 720, 480, 138, 45, 16, 62, 60, 9, 6, 30, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_720X480P_60000, HDMI_VIDEO_PROGRESSIVE, "720*480p60 16:9" }, ++ { HDMI_1280X720P60_16_9, 74250, 60000, 1280, 720, 370, 30, 110, 40, 220, 5, 5, 20, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1280X720P_60000, HDMI_VIDEO_PROGRESSIVE, "1280*720p60 16:9" }, ++ { HDMI_1920X1080I60_16_9, 74250, 60000, 1920, 1080, 280, 22, 88, 44, 148, 2, 5, 15, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080I_60000, HDMI_VIDEO_INTERLACE, "1920*1080i60 16:9" }, ++ { HDMI_1440X480I60_4_3, 27000, 59940, 1440, 480, 276, 22, 38, 124, 114, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X480I_60000, HDMI_VIDEO_INTERLACE, "1440*480i60 4:3" }, ++ { HDMI_1440X480I60_16_9, 27000, 59940, 1440, 480, 276, 22, 38, 124, 114, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X480I_60000, HDMI_VIDEO_INTERLACE, "1440*480i60 16:9" }, ++ { HDMI_1440X240P60_4_3, 27000, 60054, 1440, 240, 276, 22, 38, 124, 114, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X240P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*240p60 4:3" }, ++ { HDMI_1440X240P60_16_9, 27000, 60054, 1440, 240, 276, 22, 38, 124, 114, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X240P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*240p60 16:9" }, ++ { HDMI_2880X480I60_4_3, 54000, 59940, 2880, 480, 552, 22, 76, 248, 228, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_2880X480I_60000, HDMI_VIDEO_INTERLACE, "2880*480i60 4:3" }, ++ { HDMI_2880X480I60_16_9, 54000, 59940, 2880, 480, 552, 22, 76, 248, 228, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_2880X480I_60000, HDMI_VIDEO_INTERLACE, "2880*480i60 16:9" }, ++ { HDMI_2880X240P60_4_3, 54000, 60054, 2880, 240, 552, 22, 76, 248, 228, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_2880X240I_60000, HDMI_VIDEO_PROGRESSIVE, "2880*240i60 4:3" }, ++ { HDMI_2880X240P60_16_9, 54000, 60054, 2880, 240, 552, 23, 76, 248, 228, 4, 3, 15, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_2880X240I_60000, HDMI_VIDEO_PROGRESSIVE, "2880*240i60 16:9" }, ++ { HDMI_1440X480P60_4_3, 54000, 59940, 1440, 480, 276, 45, 32, 124, 120, 9, 6, 30, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X480P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*480p60 4:3" }, ++ { HDMI_1440X480P60_16_9, 54000, 59940, 1440, 480, 276, 45, 32, 124, 120, 9, 6, 30, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X480P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*480p60 16:9" }, ++ { HDMI_1920X1080P60_16_9, 148500, 60000, 1920, 1080, 280, 45, 88, 44, 148, 4, 5, 36, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_60000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p60 16:9" }, ++ { HDMI_720X576P50_4_3, 27000, 50000, 720, 576, 144, 49, 12, 64, 68, 5, 5, 39, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_720X576P_50000, HDMI_VIDEO_PROGRESSIVE, "720*576p50 4:3" }, ++ { HDMI_720X576P50_16_9, 27000, 50000, 720, 576, 144, 49, 12, 64, 68, 5, 5, 39, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_720X576P_50000, HDMI_VIDEO_PROGRESSIVE, "720*576p50 16:9" }, ++ { HDMI_1280X720P50_16_9, 74250, 50000, 1280, 720, 700, 30, 440, 40, 220, 5, 5, 20, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1280X720P_50000, HDMI_VIDEO_PROGRESSIVE, "1280*720p50 16:9" }, ++ { HDMI_1920X1080I50_16_9, 74250, 50000, 1920, 1080, 720, 24, 528, 44, 148, 2, 5, 15, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080I_50000, HDMI_VIDEO_INTERLACE, "1920*1080i50 16:9" }, ++ { HDMI_1440X576I50_4_3, 27000, 50000, 1440, 576, 288, 24, 24, 126, 138, 2, 3, 19, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X576I_50000, HDMI_VIDEO_INTERLACE, "1440*576i50 4:3" }, ++ { HDMI_1440X576I50_16_9, 27000, 50000, 1440, 576, 288, 24, 24, 126, 138, 2, 3, 19, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X576I_50000, HDMI_VIDEO_INTERLACE, "1440*576i50 16:9" }, ++ { HDMI_1440X576P50_4_3, 54000, 50000, 1440, 576, 288, 49, 24, 128, 136, 5, 5, 39, ++ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X576P_50000, HDMI_VIDEO_PROGRESSIVE, "1440*576p50 4:3" }, ++ { HDMI_1440X576P50_16_9, 54000, 50000, 1440, 576, 288, 49, 24, 128, 136, 5, 5, 39, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X576P_50000, HDMI_VIDEO_PROGRESSIVE, "1440*576p50 16:9" }, ++ { HDMI_1920X1080P50_16_9, 148500, 50000, 1920, 1080, 720, 45, 528, 44, 148, 4, 5, 36, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_50000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p50 16:9" }, ++ { HDMI_1920X1080P24_16_9, 742500, 24000, 1920, 1080, 830, 45, 638, 44, 148, 4, 5, 36, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_24000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p24 16:9" }, ++ { HDMI_1920X1080P25_16_9, 742500, 25000, 1920, 1080, 720, 45, 528, 44, 148, 4, 5, 36, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_25000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p25 16:9" }, ++ { HDMI_1920X1080P30_16_9, 742500, 30000, 1920, 1080, 280, 45, 88, 44, 148, 4, 5, 36, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_30000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p30 16:9" }, ++ { HDMI_3840X2160P24_16_9, 297000, 24000, 3840, 2160, 1660, 90, 1276, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_24000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p24 16:9" }, ++ { HDMI_3840X2160P25_16_9, 297000, 25000, 3840, 2160, 1440, 90, 1056, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_25000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p25 16:9" }, ++ { HDMI_3840X2160P30_16_9, 297000, 30000, 3840, 2160, 560, 90, 176, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_30000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p30 16:9" }, ++ { HDMI_3840X2160P50_16_9, 594000, 50000, 3840, 2160, 1440, 90, 1056, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_50000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p50 16:9" }, ++ { HDMI_3840X2160P60_16_9, 594000, 60000, 3840, 2160, 560, 90, 176, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_60000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p60 16:9" }, ++ { HDMI_4096X2160P24_256_135, 297000, 24000, 4096, 2160, 1404, 90, 1020, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_24000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p24 256:135" }, ++ { HDMI_4096X2160P25_256_135, 297000, 25000, 4096, 2160, 1184, 90, 968, 88, 128, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_25000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p25 256:135" }, ++ { HDMI_4096X2160P30_256_135, 297000, 30000, 4096, 2160, 304, 90, 88, 88, 128, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_30000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p30 256:135" }, ++ { HDMI_4096X2160P50_256_135, 594000, 50000, 4096, 2160, 1184, 90, 968, 88, 128, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_50000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p50 256:135" }, ++ { HDMI_4096X2160P60_256_135, 594000, 60000, 4096, 2160, 304, 90, 88, 88, 128, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_60000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p60 256:135" }, ++ { HDMI_3840X2160P120_16_9, 1188000, 120000, 3840, 2160, 560, 90, 176, 88, 296, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_120000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p120 16:9" }, ++ { HDMI_7680X4320P24_16_9, 1188000, 24000, 7680, 4320, 3320, 180, 2552, 176, 592, 16, 20, 144, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_7680X4320P_24000, HDMI_VIDEO_PROGRESSIVE, "7680*4320p24 16:9" }, ++ { HDMI_7680X4320P25_16_9, 1188000, 25000, 7680, 4320, 3120, 80, 2352, 176, 592, 16, 20, 44, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_7680X4320P_25000, HDMI_VIDEO_PROGRESSIVE, "7680*4320p25 16:9" }, ++ { HDMI_7680X4320P30_16_9, 1188000, 30000, 7680, 4320, 1320, 80, 552, 176, 592, 16, 20, 44, ++ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_7680X4320P_30000, HDMI_VIDEO_PROGRESSIVE, "7680*4320p30 16:9" }, ++ { HDMI_4096X2160P120_256_135, 1188000, 120000, 4096, 2160, 304, 90, 88, 88, 128, 8, 10, 72, ++ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_120000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p120 16:9" } ++}; ++ ++static struct smart_hdmi *encoder_to_smart_hdmi(struct drm_encoder *encoder) ++{ ++ struct smart_encoder *rkencoder = to_smart_encoder(encoder); ++ return container_of(rkencoder, struct smart_hdmi, encoder); ++} ++ ++static struct smart_hdmi *connector_to_smart_hdmi(struct drm_connector *connector) ++{ ++ return container_of(connector, struct smart_hdmi, connector); ++} ++ ++static inline u8 smart_hdmi_get_power_mode(struct smart_hdmi *hdmi) ++{ ++ ++ return 0; ++} ++ ++static void smart_hdmi_set_power_mode(struct smart_hdmi *hdmi, int mode) ++{ ++ ++} ++ ++static int ctrl_avi_infoframe_data_set(const unsigned char *data) ++{ ++ hdmi_reg_avi_pkt_header_hb_set(data[AVI_OFFSET_TYPE], data[AVI_OFFSET_VERSION], data[AVI_OFFSET_LENGTH]); ++ hdmi_reg_avi_pkt0_low_set(data[AVI_OFFSET_CHECKSUM], ++ data[AVI_OFFSET_PB1], data[AVI_OFFSET_PB2], data[AVI_OFFSET_PB3]); ++ hdmi_reg_avi_pkt0_high_set(data[AVI_OFFSET_VIC], data[AVI_OFFSET_PB5], data[AVI_OFFSET_TOP_BAR_LOWER]); ++ hdmi_reg_avi_pkt1_low_set(data[AVI_OFFSET_TOP_BAR_UPPER], ++ data[AVI_OFFSET_BOTTOM_BAR_LOWER], data[AVI_OFFSET_BOTTOM_BAR_UPPER], data[AVI_OFFSET_LEFT_BAR_LOWER]); ++ hdmi_reg_avi_pkt1_high_set(data[AVI_OFFSET_LEFT_BAR_UPPER], ++ data[AVI_OFFSET_RIGHT_BAR_LOWER], data[AVI_OFFSET_RIGHT_BAR_UPPER]); ++ hdmi_reg_avi_pkt2_low_set(data[AVI_OFFSET_PB14], ++ data[AVI_OFFSET_PB15], data[AVI_OFFSET_PB16], data[AVI_OFFSET_PB17]); ++ hdmi_reg_avi_pkt2_high_set(data[AVI_OFFSET_PB18], data[AVI_OFFSET_PB19], data[AVI_OFFSET_PB20]); ++ hdmi_reg_avi_pkt3_low_set(data[AVI_OFFSET_PB21], ++ data[AVI_OFFSET_PB22], data[AVI_OFFSET_PB23], data[AVI_OFFSET_PB24]); ++ hdmi_reg_avi_pkt3_high_set(data[AVI_OFFSET_PB25], data[AVI_OFFSET_PB26], data[AVI_OFFSET_PB27]); ++ ++ return 0; ++} ++ ++static int ctrl_avi_infoframe_en_set(bool enable) ++{ ++ /* repeat enable */ ++ hdmi_reg_cea_avi_rpt_en_set(enable); ++ /* info_frame enable */ ++ hdmi_reg_cea_avi_en_set(enable); ++ ++ return 0; ++} ++ ++static int ++smart_hdmi_upload_frame(struct smart_hdmi *hdmi, int setup_rc, ++ union hdmi_infoframe *frame, u32 frame_index, ++ u32 mask, u32 disable, u32 enable) ++{ ++ if (setup_rc >= 0) { ++ u8 packed_frame[HDMI_INFOFRAME_BUFFER_SIZE]; // HDMI_INFOFRAME_BUFFER_SIZE 32 ++ ssize_t rc, i; ++ ++ rc = hdmi_infoframe_pack(frame, packed_frame, ++ sizeof(packed_frame)); ++ ++ if (rc < 0) ++ return rc; ++ ++ ++ //ctrl_avi_infoframe_data_set(packed_frame); ++ ctrl_avi_infoframe_en_set(0); ++ ctrl_avi_infoframe_data_set(packed_frame); ++ ctrl_avi_infoframe_en_set(1); ++ } ++ ++ return setup_rc; ++} ++ ++static int smart_hdmi_config_avi(struct smart_hdmi *hdmi, ++ struct drm_display_mode *mode) ++{ ++ union hdmi_infoframe frame; ++ int rc; ++ rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, ++ &hdmi->connector, mode); ++ ++ ++ if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444) ++ frame.avi.colorspace = HDMI_COLORSPACE_YUV444;//2 ++ else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422) ++ frame.avi.colorspace = HDMI_COLORSPACE_YUV422;//1 ++ else ++ frame.avi.colorspace = HDMI_COLORSPACE_RGB;//0 ++ ++ ++ ++ frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;//1 HDMI_COLORIMETRY_ITU_601 ++ frame.avi.scan_mode = HDMI_SCAN_MODE_NONE; ++ frame.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;//8 ++ frame.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9;//2 ++ frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;//2 ++ frame.avi.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;//0 ++ frame.avi.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;//1 ++ frame.avi.content_type = HDMI_CONTENT_TYPE_GRAPHICS;//0 ++ ++ ++ return smart_hdmi_upload_frame(hdmi, rc, &frame, ++ HDMI_INFOFRAME_TYPE_AVI, 0, 0, 0); ++} ++ ++void drm_mode_to_hal_syncinfo(struct drm_display_mode *mode, hal_disp_syncinfo *syncinfo) { ++ syncinfo->vact = mode->vdisplay; ++ syncinfo->vbb = mode->vtotal - mode->vsync_end; ++ syncinfo->vfb = mode->vsync_start - mode->vdisplay; ++ syncinfo->hact = mode->hdisplay; ++ syncinfo->hbb = mode->htotal - mode->hsync_end; ++ syncinfo->hfb = mode->hsync_start - mode->hdisplay; ++ syncinfo->hmid = 0; // 可�?�字�? ++ syncinfo->hpw = mode->hsync_end - mode->hsync_start; ++ syncinfo->vpw = mode->vsync_end - mode->vsync_start; ++ syncinfo->idv = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; ++ syncinfo->ihs = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; ++ syncinfo->ivs = (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1 : 0; ++} ++ ++extern void vo_hal_intf_set_sync_info_other(ot_vo_dev dev, ++ const hal_disp_syncinfo *sync_info); ++extern void vo_hal_intf_set_sync_info_hvsync(ot_vo_dev dev, ++ const hal_disp_syncinfo *sync_info); ++extern void vo_hal_intf_set_hdmi_sync_inv(const hal_disp_syncinv *inv); ++ ++static int smart_hdmi_config_video_timing(struct smart_hdmi *hdmi, ++ struct drm_display_mode *mode) ++{ ++ unsigned int sync_pol_cfg = 0; ++ ++ hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_H_BIT); ++ hdmi_set_bit(sync_pol_cfg, CTRL_SYCN_POL_V_BIT); ++ hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_DE_BIT); ++ ++ hdmi_reg_inver_sync_set((unsigned char )sync_pol_cfg); ++ hdmi_reg_syncmask_en_set(0); ++ return 0; ++} ++ ++static int smart_hdmi_config_video_csc(struct smart_hdmi *hdmi) ++{ ++ unsigned int csc_mode = 0; ++ struct hdmi_data_info *data = &hdmi->hdmi_data; ++ unsigned int out_colormetry = data->colorimetry; ++ unsigned int in_colormetry = data->colorimetry; ++ unsigned int in_rgb = 0; ++ unsigned int dwsm_hori_enable = 0; ++ unsigned int y422_enable = 0; ++ unsigned int dwsm_vert_enable = 0; ++ unsigned int y420_enable = 0; ++ unsigned int csc_enable = 0; ++ unsigned int out_rgb = 0; ++ ++ //ctrl_video_dither_set ++ hdmi_reg_dither_rnd_bypass_set((unsigned char)(!1)); ++ hdmi_reg_dither_mode_set((unsigned char)HDMI_VIDEO_DITHER_10_8);//hdmi_reg_dither_mode_set((unsigned char)HDMI_VIDEO_DITHER_DISALBE); ++ //ctrl_video_path_deep_clr_set ++ hdmi_reg_tmds_pack_mode_set((unsigned char)HDMI_DEEP_COLOR_24BIT); ++ hdmi_reg_dc_pkt_en_set(0); ++ ++ //ctrl_video_path_colorimetry_set ++ csc_mode = hdmi_reg_csc_mode_get(); ++ out_colormetry = (unsigned int )out_colormetry & CTRL_COLORMETRY_MASK; ++ csc_mode &= CTRL_COLORMETRY_OUT_MASK; ++ csc_mode |= (unsigned int )out_colormetry << CTRL_COLORMETRY_OUT_BIT; ++ ++ in_colormetry = (unsigned int )in_colormetry & CTRL_COLORMETRY_MASK; ++ csc_mode &= CTRL_COLORMETRY_IN_MASK; ++ csc_mode |= (unsigned int )in_colormetry << CTRL_COLORMETRY_IN_BIT; ++ ++ //hdmi_reg_csc_mode_set((unsigned char )csc_mode); ++ ++ //ctrl_video_path_quantization_set ++ //csc_mode = hdmi_reg_csc_mode_get(); ++ ++ if (data->quant_range != HDMI_QUANTIZATION_RANGE_LIMITED) { ++ hdmi_set_bit(csc_mode, CTRL_QUANTIZAION_IN_BIT); ++ } else { ++ hdmi_clr_bit(csc_mode, CTRL_QUANTIZAION_IN_BIT); ++ } ++ ++ if (data->quant_range != HDMI_QUANTIZATION_RANGE_LIMITED) { ++ hdmi_set_bit(csc_mode, CTRL_QUANTIZAION_OUT_BIT); ++ } else { ++ hdmi_clr_bit(csc_mode, CTRL_QUANTIZAION_OUT_BIT); ++ } ++ ++ // hdmi_reg_csc_mode_set((unsigned char )csc_mode); ++ hdmi_reg_csc_saturate_en_set(1); ++ ++ //ctrl_video_color_rgb_set ++ //csc_mode = hdmi_reg_csc_mode_get(); ++ if (in_rgb) { ++ hdmi_set_bit(csc_mode, CTRL_RGB_IN_BIT); ++ } else { ++ hdmi_clr_bit(csc_mode, CTRL_RGB_IN_BIT); ++ } ++ ++ if (out_rgb) { ++ hdmi_set_bit(csc_mode, CTRL_RGB_OUT_BIT); ++ } else { ++ hdmi_clr_bit(csc_mode, CTRL_RGB_OUT_BIT); ++ } ++ hdmi_reg_csc_mode_set((unsigned char )csc_mode); ++ //ctrl_video_color_ycbcr422_set ++ if (y422_enable) { ++ hdmi_reg_vmux_y_sel_set(CTRL_CHANNEL0_Y422); ++ hdmi_reg_vmux_cb_sel_set(CTRL_CHANNEL1_Y422); ++ hdmi_reg_vmux_cr_sel_set(CTRL_CHANNEL2_Y422); ++ } else { ++ hdmi_reg_vmux_y_sel_set(CTRL_CHANNEL0_Y); ++ hdmi_reg_vmux_cb_sel_set(CTRL_CHANNEL1_CB); ++ hdmi_reg_vmux_cr_sel_set(CTRL_CHANNEL2_CR); ++ } ++ //ctrl_video_color_dwsm_hori_set ++ hdmi_reg_hori_filter_en_set((unsigned char)dwsm_hori_enable); ++ hdmi_reg_dwsm_hori_en_set((unsigned char)dwsm_hori_enable); ++ ++ //ctrl_video_color_ycbcr420_set ++ hdmi_reg_demux_420_en_set((unsigned char)y420_enable); ++ hdmi_reg_pxl_div_en_set((unsigned char)y420_enable); ++ ++ //ctrl_video_color_dwsm_vert_set ++ hdmi_reg_dwsm_vert_bypass_set((unsigned char)(!dwsm_vert_enable)); ++ hdmi_reg_dwsm_vert_en_set((unsigned char)dwsm_vert_enable); ++ ++ //ctrl_video_color_csc_set ++ hdmi_reg_csc_en_set((unsigned char)csc_enable); ++ return 0; ++} ++ ++static int ctrl_tmds_mode_get(hdmi_tmds_mode *tmds_mode) ++{ ++ bool hdmi_mode, hdmi2x_enable; ++ hdmi_mode = hdmi_reg_hdmi_mode_get(); ++ hdmi2x_enable = hdmi_reg_enc_hdmi2_on_get(); ++ if (!hdmi_mode) { ++ *tmds_mode = HDMI_TMDS_MODE_DVI; ++ } else if (hdmi_mode && (!hdmi2x_enable)) { ++ *tmds_mode = HDMI_TMDS_MODE_HDMI_1_4; ++ } else if (hdmi_mode && hdmi2x_enable) { ++ *tmds_mode = HDMI_TMDS_MODE_HDMI_2_0; ++ } else { ++ printk("un-config tmds mode!\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static int ctrl_tmds_mode_set(hdmi_tmds_mode tmds_mode) ++{ ++ switch (tmds_mode) { ++ case HDMI_TMDS_MODE_DVI: ++ hdmi_reg_hdmi_mode_set(0); ++ break; ++ case HDMI_TMDS_MODE_HDMI_1_4: ++ hdmi_reg_hdmi_mode_set(1); ++ hdmi_reg_enc_hdmi2_on_set(0); ++ break; ++ case HDMI_TMDS_MODE_HDMI_2_0: ++ hdmi_reg_hdmi_mode_set(1); ++ hdmi_reg_enc_hdmi2_on_set(1); ++ hdmi_reg_enc_bypass_set(0); ++ break; ++ default: ++ printk("un-known tmds mode:%u\n", tmds_mode); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static void phy_hw_reset_release(unsigned int id) ++{ ++ hdmi_reg_phy_bus_srst_req_set(1); ++ msleep(1); ++ hdmi_reg_phy_bus_srst_req_set(0); ++ ++ msleep(1); ++ hdmi_reg_resetn_set(id, 0); ++ hdmi_reg_sw_reset_mod_clock_set(id, 0); ++ hdmi_reg_sw_reset_tmds_clock_set(id, 0); ++ hdmi_reg_sw_reset_mpll_clock_set(id, 0); ++ hdmi_reg_sw_reset_nco_clock_set(id, 0); ++ hdmi_reg_sw_reset_fd_clock_set(id, 0); ++ hdmi_reg_sw_reset_mod_and_mpll_clock_set(id, 0); ++ hdmi_reg_sw_reset_mod_and_nco_clock_set(id, 0); ++ hdmi_reg_sw_reset_mod_and_fd_clock_set(id, 0); ++ hdmi_reg_sw_reset_hsfifo_clock_set(id, 0); ++ hdmi_reg_sw_reset_txfifo_clock_set(id, 0); ++ hdmi_reg_sw_reset_data_clock_set(id, 0); ++ hdmi_reg_sw_reset_hs_clock_set(id, 0); ++ hdmi_reg_sw_reset_pllref_clock_set(id, 0); ++ hdmi_reg_sw_reset_dac_clock_set(id, 0); ++ hdmi_reg_dac_clock_gat_set(id, 0); ++ hdmi_reg_sw_reset_frl_clock_set(id, 0); ++ hdmi_reg_up_sample_fifo_clock_swrst_set(id, 0); ++ hdmi_reg_swreset_unused_set(id, 0); ++ hdmi_reg_global_reset_set(id, 1); ++ hdmi_reg_resetn_set(id, 1); ++ hdmi_reg_global_reset_set(id, 0); ++ hdmi_reg_dac_clock_gat_set(id, 1); ++ hdmi_reg_fd_clk_sel_set(id, 0); ++ hdmi_reg_refclk_sel_set(id, 0); ++ hdmi_reg_ctman_set(id, 0); ++ hdmi_reg_modclk_sel_set(id, 1); ++ hdmi_reg_fdivclk_sel_set(id, 0); ++ hdmi_reg_mod_div_val_set(id, 0); ++ hdmi_reg_ref_clk_sel_set(id, 1); ++ hdmi_reg_req_length_set(id, 0x0); ++ hdmi_reg_stb_delay2_set(id, 0x2); ++ hdmi_reg_stb_delay1_set(id, 0x2); ++ hdmi_reg_stb_delay0_set(id, 0x2); ++ hdmi_reg_stb_acc_sel_set(id, 0); ++ hdmi_reg_stb_cs_sel_set(id, 0); ++ return; ++} ++ ++static int phy_hw_input_clock_check(unsigned int id, unsigned int *pixel_clk) ++{ ++ unsigned int reg_ret_value, input_clk; ++ /* select pixel clock */ ++ hdmi_reg_fd_clk_sel_set(id, 0x0); ++ hdmi_reg_refclk_sel_set(id, 0x0); ++ hdmi_reg_ctman_set(id, 0x0); ++ hdmi_reg_modclk_sel_set(id, 0x1); ++ hdmi_reg_fdivclk_sel_set(id, 0x0); ++ hdmi_reg_mod_div_val_set(id, 0x0); ++ /* set lock_val and lock_cnt */ ++ hdmi_reg_src_lock_val_set(id, 0x04); ++ hdmi_reg_src_lock_cnt_set(id, 0x02); ++ hdmi_reg_src_enable_set(id, 0x0); ++ hdmi_reg_fdsrcparam_unused_set(id, 0x0); ++ /* set frequency options */ ++ hdmi_reg_src_cnt_opt_set(id, 0x1); ++ hdmi_reg_fdsrcfreq_unused1_set(id, 0); ++ hdmi_reg_src_freq_opt_set(id, 0); ++ hdmi_reg_fdsrcfreq_unused2_set(id, 0); ++ hdmi_reg_src_freq_ext_set(id, 0); ++ /* FD enable */ ++ hdmi_reg_src_lock_val_set(id, 0x4); ++ hdmi_reg_src_lock_cnt_set(id, 0x2); ++ hdmi_reg_src_enable_set(id, 0x1); ++ hdmi_reg_fdsrcparam_unused_set(id, 0x0); ++ /* delay time */ ++ msleep(1); ++ /* read status and result */ ++ reg_ret_value = hdmi_reg_src_det_stat_get(id); ++ input_clk = hdmi_reg_src_cnt_out_get(id); ++ printk("input clock = : %u khz\n", input_clk); ++ if ((reg_ret_value & 0xF) == 0xF) { ++ printk("input clock quality : stable\n"); ++ *pixel_clk = input_clk; ++ } else { ++ printk("warning! input clock is unstable!\n"); ++ *pixel_clk = input_clk; ++ return -1; ++ } ++ ++ return 0; ++} ++static void phy_hw_write_stb1_byte(unsigned int id, unsigned int cs, aphy_offset_addr aphy_offset, unsigned int wdata) ++{ ++ /* CS reset */ ++ hdmi_reg_stb_cs_en_set(id, 0x00); ++ /* WR reset */ ++ hdmi_reg_stb_wen_set(id, 0); ++ /* WDATA set */ ++ hdmi_reg_stb_wdata_set(id, wdata); ++ /* ADDR set */ ++ hdmi_reg_stb_addr_set(id, aphy_offset); ++ udelay(1); ++ /* WR set */ ++ hdmi_reg_stb_wen_set(id, 1); ++ /* CS set */ ++ hdmi_reg_stb_cs_en_set(id, cs); ++ udelay(1); ++ /* CS reset */ ++ hdmi_reg_stb_cs_en_set(id, 0x00); ++ /* WR reset */ ++ hdmi_reg_stb_wen_set(id, 0); ++ ++ return; ++} ++ ++static void phy_hw_ref_clk_div_set(unsigned int id, unsigned int pixel_clk) ++{ ++ unsigned int ref_clk_div = 0; ++ if (pixel_clk < g_phy_hw_def_clk_div[0].clk_range.clk_max) { ++ ref_clk_div = g_phy_hw_def_clk_div[0].seek_value; ++ } else if (pixel_clk >= g_phy_hw_def_clk_div[1].clk_range.clk_min && ++ pixel_clk < g_phy_hw_def_clk_div[1].clk_range.clk_max) { ++ ref_clk_div = g_phy_hw_def_clk_div[1].seek_value; ++ } else if (pixel_clk >= g_phy_hw_def_clk_div[2].clk_range.clk_min && ++ pixel_clk < g_phy_hw_def_clk_div[2].clk_range.clk_max) { ++ ref_clk_div = g_phy_hw_def_clk_div[2].seek_value; ++ } else if (pixel_clk >= g_phy_hw_def_clk_div[3].clk_range.clk_min && ++ pixel_clk < g_phy_hw_def_clk_div[3].clk_range.clk_max) { ++ ref_clk_div = g_phy_hw_def_clk_div[3].seek_value; ++ } else if (pixel_clk >= g_phy_hw_def_clk_div[4].clk_range.clk_min && ++ pixel_clk < g_phy_hw_def_clk_div[4].clk_range.clk_max) { ++ ref_clk_div = g_phy_hw_def_clk_div[4].seek_value; ++ } ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_2, ref_clk_div); ++ ++ return; ++} ++ ++static int phy_hw_divn_sel_get(unsigned int tmds_clk, unsigned char *tmds_divn) ++{ ++ unsigned int i; ++ const phy_clk_range_value *phy_tmds_divnsel = NULL; ++ ++ for (i = 0, phy_tmds_divnsel = &g_phy_hw_tmds_divn_sel[0]; ++ (i < hdmi_array_size(g_phy_hw_tmds_divn_sel)); phy_tmds_divnsel++, i++) { ++ if ((tmds_clk >= phy_tmds_divnsel->clk_range.clk_min) && (tmds_clk < phy_tmds_divnsel->clk_range.clk_max)) { ++ *tmds_divn = phy_tmds_divnsel->seek_value; ++ return 0; ++ } ++ } ++ printk("can't find param, tmds_clk:%u\n", tmds_clk); ++ return -1; ++} ++ ++static void phy_hw_tmds_clk_div_set(unsigned int id, unsigned int tmds_clk) ++{ ++ int ret; ++ unsigned char tmds_clk_div = 0; ++ ++ ret = phy_hw_divn_sel_get(tmds_clk, &tmds_clk_div); ++ if (ret != 0) { ++ return; ++ } ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_3, ((0x14 << 0x3) | (tmds_clk_div & 0x7))); ++} ++ ++static void phy_hw_init_tmds(unsigned int id, const hdmi_phy_tmds_cfg *hdmi_spec_cfg) ++{ ++ /* PLL settings */ ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_E, 0x11); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_0, 0xFF); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_1, 0x11); ++ ++ /* aphy refclk select */ ++ phy_hw_ref_clk_div_set(id, hdmi_spec_cfg->pixel_clk); ++ phy_hw_tmds_clk_div_set(id, hdmi_spec_cfg->tmds_clk); ++ ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_4, 0x00); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_9, 0x00); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_A, 0x03); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_B, 0xE0); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_C, 0x14); ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_D, 0xF0); ++ ++ return; ++} ++ ++static const phy_ssc g_phy_ssc_cfg[] = { ++ {{ 25000, 70000 }, { 0, 0 }}, // 0ppm ++ {{ 70001, 90000 }, { 150, 45000 }}, // 0.15 ++ {{ 90001, 110000 }, { 70, 45000 }}, // 0.07% ++ {{ 110001, 145000 }, { 50, 45000 }}, // 0.05% ++ {{ 145001, 180000 }, { 100, 45000 }}, // 0.10% ++ {{ 180001, 220000 }, { 40, 45000 }}, // 0.04% ++ {{ 220001, 250000 }, { 40, 45000 }}, // 0.04% ++ {{ 250001, 300000 }, { 40, 45000 }}, // 0.04% ++ {{ 300001, 600000 }, { 0, 0 }}, // 0 ++}; ++ ++static const phy_ssc_cfg *phy_ssc_data_get(unsigned int tmds_clk) ++{ ++ unsigned int i; ++ const phy_ssc *ssc_cfg = NULL; ++ ++ for (i = 0, ssc_cfg = &g_phy_ssc_cfg[0]; (ssc_cfg && (i < hdmi_array_size(g_phy_ssc_cfg))); ssc_cfg++, i++) { ++ if ((tmds_clk >= ssc_cfg->phy_tmds_clk_range.clk_min) && (tmds_clk <= ssc_cfg->phy_tmds_clk_range.clk_max)) { ++ return (&ssc_cfg->ssc_cfg); ++ } ++ } ++ ++ return NULL; ++} ++ ++unsigned long long hi_div_u64_rem(unsigned long long dividend, unsigned int divisor) ++{ ++ unsigned int remainder; ++ ++ div_u64_rem(dividend, divisor, &remainder); ++ ++ return remainder; ++} ++ ++static void hal_hdmi_phy_ssc_init(unsigned int id, unsigned short mod_d, unsigned short mod_n) ++{ ++ ++ /* MOD_N MOD_T */ ++ hdmi_reg_mod_len_set(id, 0); ++ hdmi_reg_mod_t_set(id, 1); ++ hdmi_reg_mod_n_set(id, mod_n); ++ /* MOD_D */ ++ hdmi_reg_mod_d_set(id, mod_d); ++ /* FDIV init */ ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 0); ++ hdmi_reg_en_mod_set(id, 0); ++ hdmi_reg_en_sdm_set(id, 0); ++ /* FDIV init */ ++ hdmi_reg_init_set(id, 1); ++ udelay(1); /* 150 nsec */ ++ /* FDIV control */ ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 0); ++ hdmi_reg_en_mod_set(id, 0); ++ hdmi_reg_en_sdm_set(id, 0); ++ udelay(1); /* 150 nsec */ ++ /* FDIV control */ ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 1); ++ hdmi_reg_en_mod_set(id, 0); ++ hdmi_reg_en_sdm_set(id, 0); ++ /* FDIV control */ ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 1); ++ hdmi_reg_en_mod_set(id, 1); ++ hdmi_reg_en_sdm_set(id, 0); ++ /* FDIV control */ ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 1); ++ hdmi_reg_en_mod_set(id, 1); ++ hdmi_reg_en_sdm_set(id, 1); ++ ++ return; ++} ++ ++static int phy_hw_clk_rang_value_get(unsigned int tmds_clk, unsigned char size, ++ const phy_clk_range_value *phy_rang_sel, unsigned char *seek_value) ++{ ++ unsigned int i; ++ const phy_clk_range_value *phy_rang = NULL; ++ ++ for (i = 0, phy_rang = &phy_rang_sel[0]; (i < size); phy_rang++, i++) { ++ if ((tmds_clk >= phy_rang->clk_range.clk_min) && (tmds_clk < phy_rang->clk_range.clk_max)) { ++ *seek_value = phy_rang->seek_value; ++ return 0; ++ } ++ } ++ printk("can't find param,tmds_clk:%u,i=%u\n", tmds_clk, i); ++ ++ return -1; ++} ++ ++static unsigned int phy_hw_pow(unsigned int base_num, unsigned int index_num) ++{ ++ unsigned int i; ++ unsigned int ret_val = 1; ++ ++ for (i = 0; i < index_num; i++) { ++ ret_val = ret_val * base_num; ++ } ++ ++ return ret_val; ++} ++ ++static int phy_hw_fractional_mnx_get(unsigned int tmds_clk, unsigned int pixel_clk, hdmi_deep_color deep_color) ++{ ++ unsigned char k, m_value, size; ++ unsigned int mn_value, pll_ref_clk; ++ unsigned char seek_value = 0; ++ unsigned char tmds_divnsel = 0; ++ ++ /* HDMI 2.0 configure pll feedback coefficient M, N, X */ ++ size = (unsigned char)hdmi_array_size(g_phy_hw_def_clk_div); ++ /* determine the reference clock division factor */ ++ if (phy_hw_clk_rang_value_get(pixel_clk, size, &g_phy_hw_def_clk_div[0], &seek_value) != 0) { ++ return -1; ++ } ++ ++ /* obtain TMDS_DIVNSEL */ ++ if (phy_hw_divn_sel_get(tmds_clk, &tmds_divnsel) != 0) { ++ return -1; ++ } ++ ++ printk("pixel_clk: %u, seek_value: %u-%u\n", pixel_clk, seek_value, phy_hw_pow(PHY_POW_BASE_NUM, seek_value)); ++ pll_ref_clk = pixel_clk / phy_hw_pow(PHY_POW_BASE_NUM, seek_value); ++ g_mnx_get.pll_ref_clk = pll_ref_clk; ++ printk("pll_ref_clk(%u), tmds_divnsel(%u), deep_color(%u) \n", g_mnx_get.pll_ref_clk, tmds_divnsel, deep_color); ++ switch (deep_color) { ++ case HDMI_DEEP_COLOR_30BIT: ++ mn_value = TMDS_CLK_FREQ_MUITIPLE * phy_hw_pow(PHY_POW_BASE_NUM, tmds_divnsel) * ++ phy_hw_pow(PHY_POW_BASE_NUM, seek_value) * 5 / 4; /* 5 and 4 means 10bit is std 5/4 multiple */ ++ break; ++ case HDMI_DEEP_COLOR_36BIT: ++ mn_value = TMDS_CLK_FREQ_MUITIPLE * phy_hw_pow(PHY_POW_BASE_NUM, tmds_divnsel) * ++ phy_hw_pow(PHY_POW_BASE_NUM, seek_value) * 3 / 2; /* 3 and 2 means 12bit is std 3/2 multiple */ ++ break; ++ default: ++ mn_value = TMDS_CLK_FREQ_MUITIPLE * phy_hw_pow(PHY_POW_BASE_NUM, tmds_divnsel) * ++ phy_hw_pow(PHY_POW_BASE_NUM, seek_value); ++ break; ++ } ++ printk("mn_value = %u \n", mn_value); ++ g_mnx_get.mn_value = mn_value; ++ ++ /* calculate N value */ ++ g_mnx_get.n_val = (unsigned char)(mn_value % 10); /* 10, about pll coefficient N calculate protocol */ ++ if (g_mnx_get.n_val == 0) { ++ k = 2; /* 2, means 1 + 1, about pll coefficient N real value calculate */ ++ g_mnx_get.n_val = 10; /* calculate result n_val is 0, get real n_val 10 */ ++ } else { ++ k = 1; ++ } ++ ++ /* calculate M value */ ++ m_value = (unsigned char)(mn_value / 10); /* 10, about pll coefficient M calculate protocol */ ++ g_mnx_get.m_val = m_value - k; ++ printk("get mnx M:%x, N:%u\n", g_mnx_get.m_val, g_mnx_get.n_val); ++ ++ return 0; ++} ++ ++int hal_hdmi_phy_ssc_set(unsigned int id, hdmi_phy_ssc_cfg *hdmi_ssc_cfg) ++{ ++ unsigned short mod_d, mod_n; ++ unsigned int mod_dn, ssc_freq; ++ unsigned int rem, ssc_amptd; ++ unsigned long long mod_dl; ++ const phy_ssc_cfg *phy_ssc_cfg_tmp = NULL; ++ ++ phy_ssc_cfg_tmp = phy_ssc_data_get(hdmi_ssc_cfg->tmds_clk); ++ if (hdmi_ssc_cfg->phy_ssc.ssc_enable == 1 && phy_ssc_cfg_tmp != NULL) { ++ hdmi_ssc_cfg->phy_ssc.ssc_cfg = *phy_ssc_cfg_tmp; ++ } else { ++ return -1; ++ } ++ ++ ssc_amptd = hdmi_ssc_cfg->phy_ssc.ssc_cfg.ssc_amptd; ++ ssc_freq = hdmi_ssc_cfg->phy_ssc.ssc_cfg.ssc_freq / HDMI_THOUSAND; /* k_hz/1000, unit is hz */ ++ if (ssc_freq == 0) { ++ return -1; ++ } ++ if (phy_hw_fractional_mnx_get(hdmi_ssc_cfg->tmds_clk, ++ hdmi_ssc_cfg->pix_clk, hdmi_ssc_cfg->deep_color) != 0) { ++ printk("MNX get fail\n"); ++ } ++ /* g_mnx_get.pll_ref_clk * 10000 / (ssc_freq * 4) */ ++ mod_dn = (unsigned int )div64_u64(((unsigned long long)g_mnx_get.pll_ref_clk * 2500), ssc_freq); /* 2500, means 10000/4 */ ++ /* 10000 eq 1000*10. 1000 get to unit k_hz; 10 is get 1 significant digits. 5000 means rounding off mod_n */ ++ mod_n = (mod_dn % MOD_N_MULTI_COEFFICIENT) >= 5000 ? (unsigned short )(mod_dn / MOD_N_MULTI_COEFFICIENT + 1) : ++ (unsigned short )(mod_dn / MOD_N_MULTI_COEFFICIENT); ++ /* relative deviation = (MOD_D(0x80A0[15:0])*MOD_N(0x809C[31:16])) / (65536*(((M+1)*10)+(N+X))) */ ++ if (mod_n == 0) { ++ return -1; ++ } ++ mod_dl = (unsigned long long)div64_u64(((unsigned long long)phy_hw_pow(PHY_POW_BASE_NUM, PHY_POW_INDEX_NUM) * ++ g_mnx_get.mn_value * ssc_amptd), mod_n); ++ /* 100000 eq 1000*100. 1000 get to unit k_hz; 100 is get 2 significant digits. */ ++ rem = (unsigned int )hi_div_u64_rem(mod_dl, MOD_D_MULTI_COEFFICIENT); ++ if (rem >= 50000) { /* 50000 means rounding off mod_n */ ++ mod_d = (unsigned short )(div64_u64(mod_dl, MOD_D_MULTI_COEFFICIENT) + 1); ++ } else { ++ mod_d = (unsigned short )div64_u64(mod_dl, MOD_D_MULTI_COEFFICIENT); ++ } ++ printk("mod_n = %x, mod_d = %x \n", mod_n, mod_d); ++ ++ if (hdmi_ssc_cfg->phy_ssc.ssc_enable) { ++ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_D, 0xFD); ++ hal_hdmi_phy_ssc_init(id, mod_d, mod_n); ++ } else { ++ /* FDIV init */ ++ hdmi_reg_init_set(id, 1); ++ udelay(1); ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 0); ++ hdmi_reg_en_mod_set(id, 0); ++ } ++ return 0; ++} ++ ++static void phy_hw_tmds_aphy_spec_set(unsigned int id, const struct tmds_spec_params *tmds) ++{ ++ const struct aphy_spec_params *data = &tmds->data.aphy; ++ const struct aphy_spec_params *clk = &tmds->clock.aphy; ++ /* data drv set */ ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_0, data->offset_0); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_1, data->offset_1); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_2, data->offset_2); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_3, data->offset_3); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_4, data->offset_4); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_5, data->offset_5); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_8, data->offset_8); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_9, data->offset_9); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_A, data->offset_a); ++ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_B, data->offset_b); ++ /* clk drv set */ ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_0, clk->offset_0); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_1, clk->offset_1); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_2, clk->offset_2); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_3, clk->offset_3); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_4, clk->offset_4); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_5, clk->offset_5); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_8, clk->offset_8); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_9, clk->offset_9); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_A, clk->offset_a); ++ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_B, clk->offset_b); ++} ++ ++static void hdmi_write_mask(unsigned int id, unsigned int offset, unsigned int val, unsigned int mask) ++{ ++ unsigned int tmp; ++ char *reg = NULL; ++ ++ reg = (char *)hdmi_reg_tx_get_phy_addr(id); ++ if (reg == NULL) { ++ hdmi_warn("phy addr is null!\n"); ++ return; ++ } ++ reg += offset; ++ tmp = *(volatile unsigned int *)(reg); ++ tmp = (tmp & ~mask) | (val & mask); ++ *(volatile unsigned int *)reg = tmp; ++} ++ ++static void phy_hw_tmds_dphy_spec_set(unsigned int id, const struct tmds_spec_params *tmds) ++{ ++ const struct dphy_spec_params *data = &tmds->data.dphy; ++ const struct dphy_spec_params *clk = &tmds->clock.dphy; ++ const struct dphy_spec_en *data_en = &tmds->data.en; ++ const struct dphy_spec_en *clk_en = &tmds->clock.en; ++ /* select dphy drv set mode */ ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_hdmi_ffe_sel(0x1), CFG_HDMI_FFE_SEL_M); ++ /* dphy data drv set */ ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_post2_ch0(data->drv_post2), CFG_DRV_POST2_CH0_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_post1_ch0(data->drv_post1), CFG_DRV_POST1_CH0_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_m_ch0(data->drv_main), CFG_DRV_M_CH0_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_pre_ch0(data->drv_pre), CFG_DRV_PRE_CH0_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_post2_ch1(data->drv_post2), CFG_DRV_POST2_CH1_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_post1_ch1(data->drv_post1), CFG_DRV_POST1_CH1_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_m_ch1(data->drv_main), CFG_DRV_M_CH1_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_pre_ch1(data->drv_pre), CFG_DRV_PRE_CH1_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_post2_ch2(data->drv_post2), CFG_DRV_POST2_CH2_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_post1_ch2(data->drv_post1), CFG_DRV_POST1_CH2_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_m_ch2(data->drv_main), CFG_DRV_M_CH2_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_pre_ch2(data->drv_pre), CFG_DRV_PRE_CH2_M); ++ /* dphy clk drv set */ ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_post2_ch3(clk->drv_post2), CFG_DRV_POST2_CH3_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_post1_ch3(clk->drv_post1), CFG_DRV_POST1_CH3_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_m_ch3(clk->drv_main), CFG_DRV_M_CH3_M); ++ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_pre_ch3(clk->drv_pre), CFG_DRV_PRE_CH3_M); ++ /* dphy data drv enable */ ++ hdmi_write_mask(id, FFE_EN_CFG, cfg_c2_pre_en((unsigned int)data_en->drv_pre_en) | ++ cfg_c2_post1_en((unsigned int)data_en->drv_post1_en) | cfg_c2_post2_en((unsigned int)data_en->drv_post2_en) | ++ cfg_c1_pre_en((unsigned int)data_en->drv_pre_en) | cfg_c1_post1_en((unsigned int)data_en->drv_post1_en) | ++ cfg_c1_post2_en((unsigned int)data_en->drv_post2_en) | cfg_c0_pre_en((unsigned int)data_en->drv_pre_en) | ++ cfg_c0_post1_en((unsigned int)data_en->drv_post1_en) | cfg_c0_post2_en((unsigned int)data_en->drv_post2_en), ++ CFG_C2_PRE_EN_M | CFG_C2_POST1_EN_M | CFG_C2_POST2_EN_M | CFG_C1_PRE_EN_M | ++ CFG_C1_POST1_EN_M | CFG_C1_POST2_EN_M | CFG_C0_PRE_EN_M | CFG_C0_POST1_EN_M | CFG_C0_POST2_EN_M); ++ /* dphy clock drv enable */ ++ hdmi_write_mask(id, FFE_EN_CFG, cfg_c3_pre_en((unsigned int)clk_en->drv_pre_en) | ++ cfg_c3_post1_en((unsigned int)clk_en->drv_post1_en) | cfg_c3_post2_en((unsigned int)clk_en->drv_post2_en), ++ CFG_C3_PRE_EN_M | CFG_C3_POST1_EN_M | CFG_C3_POST2_EN_M); ++} ++ ++static int phy_user_spec_param_set(unsigned int id, int tmds_clk, hdmi_trace_len len, struct tmds_spec_params *spec) ++{ ++ unsigned int i; ++ const struct tmds_spec_params *tmp = NULL; ++ tmp = &g_tmds_spec[0]; ++ ++ /* User's four frequency hw spec settings corresponding to four frequency are configured by default(g_tmds_spec). */ ++ for (i = 0; tmp != NULL && (i < hdmi_array_size(g_tmds_spec)); i++, tmp++) { ++ /* Confirm the current frequency band. */ ++ if (tmds_clk >= tmp->min_tmds_clk && tmds_clk <= tmp->max_tmds_clk) { ++ if (spec->data.dphy.drv_post1 != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_data) { ++ spec->data.dphy.drv_post1 = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_data; ++ } ++ if (spec->clock.dphy.drv_post1 != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_clk) { ++ spec->clock.dphy.drv_post1 = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_clk; ++ } ++ if (spec->data.dphy.drv_main != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_data) { ++ spec->data.dphy.drv_main = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_data; ++ } ++ if (spec->clock.dphy.drv_main != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_clk) { ++ spec->clock.dphy.drv_main = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_clk; ++ } ++ break; ++ } ++ } ++ return 0; ++} ++ ++static void phy_hw_tmds_spec_trace_len_get(const struct tmds_spec_params **hwspec_enhance, hdmi_trace_len trace_len) ++{ ++ const struct tmds_spec_params *hwspec = NULL; ++ switch (trace_len) { ++ case HDMI_TRACE_LEN_0: ++ hwspec = &g_tmds_spec_1inch[0]; ++ break; ++ case HDMI_TRACE_LEN_1: ++ hwspec = &g_tmds_spec_1p5inch[0]; ++ break; ++ case HDMI_TRACE_LEN_2: ++ hwspec = &g_tmds_spec_2inch[0]; ++ break; ++ case HDMI_TRACE_LEN_3: ++ hwspec = &g_tmds_spec_2p5inch[0]; ++ break; ++ case HDMI_TRACE_LEN_4: ++ hwspec = &g_tmds_spec_3inch[0]; ++ break; ++ case HDMI_TRACE_LEN_5: ++ hwspec = &g_tmds_spec_3p5inch[0]; ++ break; ++ case HDMI_TRACE_LEN_6: ++ hwspec = &g_tmds_spec_4inch[0]; ++ break; ++ case HDMI_TRACE_LEN_7: ++ hwspec = &g_tmds_spec_4p5inch[0]; ++ break; ++ case HDMI_TRACE_LEN_8: ++ hwspec = &g_tmds_spec_5inch[0]; ++ break; ++ default: ++ hwspec = &g_tmds_spec[0]; ++ break; ++ } ++ ++ *hwspec_enhance = hwspec; ++ ++ return; ++} ++ ++static const struct tmds_spec_params *get_tmds_spec_params(const hdmi_phy_tmds_cfg *tmds_cfg) ++{ ++ unsigned int i; ++ unsigned int len; ++ const struct tmds_spec_params *tmp = NULL; ++ if (tmds_cfg->trace_len == HDMI_TRACE_DEFAULT) { ++ tmp = &g_tmds_spec[0]; ++ } else { ++ phy_hw_tmds_spec_trace_len_get(&tmp, tmds_cfg->trace_len); ++ } ++ len = (unsigned int)hdmi_array_size(g_tmds_spec); ++ for (i = 0; i < len; i++) { ++ if (tmds_cfg->tmds_clk >= tmp[i].min_tmds_clk && tmds_cfg->tmds_clk < tmp[i].max_tmds_clk) { ++ return &tmp[i]; ++ } ++ } ++ return NULL; ++} ++ ++static int phy_tmds_spec_set(unsigned int id, const hdmi_phy_tmds_cfg *tmds_cfg) ++{ ++ int ret; ++ const struct tmds_spec_params *tmds = NULL; ++ struct tmds_spec_params tmds_spec = {0}; ++ ++ tmds = get_tmds_spec_params(tmds_cfg); ++ if(!tmds) { ++ return -1; ++ } ++ memcpy(&tmds_spec, tmds, sizeof(*tmds)); ++ ++ phy_user_spec_param_set(id, tmds_cfg->tmds_clk, tmds_cfg->trace_len, &tmds_spec); ++ ++ phy_hw_tmds_aphy_spec_set(id, &tmds_spec); ++ phy_hw_tmds_dphy_spec_set(id, &tmds_spec); ++ ++ return 0; ++} ++ ++static int hal_hdmi_clk_set_para_get(unsigned int id, phy_clk_set *phy_clk) ++{ ++ unsigned char size; ++ ++ size = (unsigned char)hdmi_array_size(g_phy_hw_fcd_step_set); ++ if (phy_hw_clk_rang_value_get(phy_clk->tmds_cfg.tmds_clk, size, ++ &g_phy_hw_fcd_step_set[0], &phy_clk->fcd_step) != 0) { ++ return -1; ++ } ++ printk("get fcd_step = %x\n", phy_clk->fcd_step); ++ ++ size = (unsigned int)hdmi_array_size(g_phy_hw_def_clk_div); ++ if (phy_hw_clk_rang_value_get(phy_clk->tmds_cfg.pixel_clk, size, ++ &g_phy_hw_def_clk_div[0], &phy_clk->ref_clk_div) != 0) { ++ return -1; ++ } ++ printk("get ref_clk_div = %x\n", phy_clk->ref_clk_div); ++ ++ size = (unsigned char)hdmi_array_size(g_phy_hw_tmds_divn_sel); ++ if (phy_hw_clk_rang_value_get(phy_clk->tmds_cfg.tmds_clk, size, ++ &g_phy_hw_tmds_divn_sel[0], &phy_clk->tmds_divnsel) != 0) { ++ return -1; ++ } ++ ++ /* shut down FCG */ ++ phy_hw_write_stb1_byte(id, 0x100, 0xB, 0x00); ++ hdmi_reg_fcg_en_set(id, 0); ++ hdmi_reg_fcg_dlf_en_set(id, 0); ++ hdmi_reg_fcg_dither_en_set(id, 0); ++ hdmi_reg_fcg_lock_en_set(id, 0); ++ printk("get tmds_divnsel = %x\n", phy_clk->tmds_divnsel); ++ ++ return 0; ++} ++ ++static void phy_hw_clock_tmds_set(unsigned int id, const phy_clk_set *phy_clk) ++{ ++ hdmi_reg_divn_h20_set(id, (phy_clk->fcd_step & 0x07)); ++ hdmi_reg_fcdstepset_unused_set(id, 0); ++ hdmi_reg_up_sampler_ratio_sel_set(id, 0); ++ hdmi_reg_manual_en_set(id, 0xe); ++ printk("g_mnx_get: M:%u, N:%u\n", g_mnx_get.m_val, g_mnx_get.n_val); ++ hdmi_reg_mdiv_set(id, g_mnx_get.m_val); ++ hdmi_reg_fdiv_in_set(id, ((unsigned int)g_mnx_get.n_val) << 24); /* 24'b, BIT[32:25] */ ++ hdmi_reg_mode_en_set(id, (phy_clk->tmds_cfg.tmds_clk > TMDS_CLOCK_340M) ? 0x1 : 0x0); ++ printk("tmds_clk: %u\n", phy_clk->tmds_cfg.tmds_clk); ++ /* FDIV init */ ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 0); ++ hdmi_reg_en_mod_set(id, 0); ++ hdmi_reg_en_sdm_set(id, 0); ++ hdmi_reg_init_set(id, 1); ++ /* delay 1us */ ++ udelay(1); ++ hdmi_reg_init_set(id, 0); ++ hdmi_reg_en_ctrl_set(id, 0); ++ hdmi_reg_en_mod_set(id, 0); ++ hdmi_reg_en_sdm_set(id, 0); ++ ++ return; ++} ++ ++static void phy_hw_clock_set(unsigned int id, const phy_clk_set *phy_clk) ++{ ++ if (phy_clk->tmds_cfg.mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { ++ phy_hw_clock_tmds_set(id, phy_clk); ++ } else { ++ printk("mode err.\n"); ++ } ++ ++ return; ++} ++ ++static int phy_tmds_clk_set(unsigned int id, const hdmi_phy_tmds_cfg *tmds_cfg, phy_clk_set *phy_clk) ++{ ++ int ret; ++ phy_clk->tmds_cfg.mode_cfg = tmds_cfg->mode_cfg; ++ phy_clk->tmds_cfg.deep_color = tmds_cfg->deep_color; ++ phy_clk->tmds_cfg.pixel_clk = tmds_cfg->pixel_clk; ++ phy_clk->tmds_cfg.tmds_clk = tmds_cfg->tmds_clk; ++ ++ if (tmds_cfg->mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { ++ /* calculate ll parameter */ ++ ret = hal_hdmi_clk_set_para_get(id, phy_clk); ++ if (ret != 0) { ++ printk("hal_hdmi_clk_set_para_get.\n"); ++ return -1; ++ } ++ /* pll feedback clock divider */ ++ ret = phy_hw_fractional_mnx_get(phy_clk->tmds_cfg.tmds_clk, phy_clk->tmds_cfg.pixel_clk, phy_clk->tmds_cfg.deep_color); ++ if (ret != 0) { ++ printk("phy_hw_fractional_mnx_get.\n"); ++ return -1; ++ } ++ } ++ phy_hw_clock_set(id, phy_clk); ++ ++ return 0; ++} ++ ++static void phy_hw_read_stb1_byte(unsigned int id, unsigned int cs, aphy_offset_addr aphy_offset, unsigned char *rdata) ++{ ++ /* CS reset */ ++ hdmi_reg_stb_cs_en_set(id, 0x00); ++ /* WR reset */ ++ hdmi_reg_stb_wen_set(id, 0); ++ /* ADDR set */ ++ hdmi_reg_stb_addr_set(id, aphy_offset); ++ udelay(1); ++ /* CS set */ ++ hdmi_reg_stb_cs_en_set(id, cs); ++ udelay(1); ++ /* RDATA read */ ++ *rdata = (unsigned char)hdmi_reg_stb_rdata_get(id); ++ /* CS reset */ ++ hdmi_reg_stb_cs_en_set(id, 0x00); ++ ++ return; ++} ++ ++static void phy_hw_write_stb(unsigned int id, write_param param) ++{ ++ unsigned char rdata = 0; ++ unsigned int mask_value, write_value; ++ if ((param.msb == 0x7) && (param.lsb == 0x0)) { ++ phy_hw_write_stb1_byte(id, param.cs, param.aphy_offset, param.wdata); ++ } else { ++ if (param.cs == (APHY_CS_012 | APHY_CS_3)) { ++ phy_hw_read_stb1_byte(id, APHY_CS_0, param.aphy_offset, &rdata); ++ } else if (param.cs == APHY_CS_4567) { ++ phy_hw_read_stb1_byte(id, APHY_CS_4, param.aphy_offset, &rdata); ++ } else { ++ phy_hw_read_stb1_byte(id, param.cs, param.aphy_offset, &rdata); ++ } ++ ++ mask_value = (0xff >> (0x7 - param.msb)) & (0xff << param.lsb); ++ write_value = (~mask_value & rdata) + (mask_value & (param.wdata << param.lsb)); ++ phy_hw_write_stb1_byte(id, param.cs, param.aphy_offset, write_value); ++ } ++ ++ return; ++} ++ ++static int phy_hw_post_set_up(unsigned int id, const hdmi_phy_tmds_cfg *tmds_cfg) ++{ ++ write_param param = {0}; ++ (void*)tmds_cfg; ++ hdmi_reg_hsset_set(id, 3); /* 3, HS FIFO enable & HS data selection: External(HS Link) */ ++ hdmi_reg_pr_en_h20_set(id, 1); ++ hdmi_reg_enable_h20_set(id, 1); ++ hdmi_reg_txfifoset0_unused_set(id, 0); ++ ++ hdmi_reg_ch_out_sel_set(id, 0x0); ++ param.cs = APHY_CS_0; ++ param.aphy_offset = APHY_OFFSET_0; ++ param.msb = 1; ++ param.lsb = 1; ++ param.wdata = 0x0; ++ phy_hw_write_stb(id, param); ++ param.cs = APHY_CS_1; ++ phy_hw_write_stb(id, param); ++ param.cs = APHY_CS_2; ++ phy_hw_write_stb(id, param); ++ param.cs = APHY_CS_3; ++ phy_hw_write_stb(id, param); ++ msleep(1); ++ param.cs = APHY_CS_0; ++ param.wdata = 0x1; ++ phy_hw_write_stb(id, param); ++ param.cs = APHY_CS_1; ++ phy_hw_write_stb(id, param); ++ param.cs = APHY_CS_2; ++ phy_hw_write_stb(id, param); ++ param.cs = APHY_CS_3; ++ phy_hw_write_stb(id, param); ++ ++ return 0; ++} ++ ++int hal_hdmi_phy_oe_set(unsigned int id, bool enable) ++{ ++ bool oe_en; ++ unsigned int oe_cfg, mask; ++ oe_en = enable; ++ g_hdmi_phy_info[id].oe_enable = oe_en; ++ ++ mask = CFG_HDMI_OE_CH3_M | CFG_HDMI_OE_CH2_M | CFG_HDMI_OE_CH1_M | CFG_HDMI_OE_CH0_M; ++ oe_cfg = cfg_hdmi_oe_ch3((unsigned int)oe_en) | cfg_hdmi_oe_ch2((unsigned int)oe_en) | ++ cfg_hdmi_oe_ch1((unsigned int)oe_en) | cfg_hdmi_oe_ch0((unsigned int)oe_en); ++ hdmi_write_mask(id, HDMI_OE_CFG, oe_cfg, mask); ++ ++ return 0; ++} ++ ++static unsigned int hdmi_read_mask(unsigned int id, unsigned int offset, unsigned int mask) ++{ ++ unsigned int tmp; ++ char *reg = NULL; ++ ++ reg = (char *)hdmi_reg_tx_get_phy_addr(id); ++ if (reg == NULL) { ++ hdmi_warn("phy addr is null!\n"); ++ return -1; ++ } ++ reg += offset; ++ tmp = *(volatile unsigned int *)(reg); ++ tmp = (tmp & mask); ++ ++ return tmp; ++} ++ ++int hdmi_phy_oe_get(unsigned int id) ++{ ++ unsigned int oe_status; ++ int enable = 0; ++ ++ ++ if (hdmi_reg_resetn_get(id) == 0) { ++ printk("phy is reset now, OE disable.\n"); ++ enable = 0; ++ return enable; ++ } ++ ++ oe_status = hdmi_read_mask(id, HDMI_OE_CFG, ++ CFG_HDMI_OE_CH0_M | CFG_HDMI_OE_CH1_M | CFG_HDMI_OE_CH2_M | CFG_HDMI_OE_CH3_M); ++ if (oe_status == 0xF) { ++ enable = 1; ++ } else { ++ enable = 0; ++ } ++ printk("%s,enable:%d OK\n",__func__,enable); ++ return enable; ++} ++ ++static void smart_hdmi_config_phy(struct smart_hdmi *hdmi) ++{ ++ hdmi_tmds_mode tmds_mode; ++ hdmi_phy_tmds_cfg cfg = {0}; ++ hdmi_phy_ssc_cfg hdmi_ssc_cfg = {0}; ++ int ret; ++ unsigned int pixel_clk = 0; ++ phy_clk_set phy_clk = {0}; ++ ++ /* reset: clear all the aphy register */ ++ phy_hw_reset_release(0); ++ /* input clock check: to configurate dphy source clock detection module */ ++ if (phy_hw_input_clock_check(0, &pixel_clk) != 0) { ++ printk("input clock unstable\n"); ++ } ++ ++ cfg.deep_color = HDMI_DEEP_COLOR_24BIT;//HI_HDMI_DEEP_COLOR_24BIT ++ cfg.emi_enable = 0; ++ cfg.mode_cfg = HDMI_PHY_MODE_CFG_TMDS; ++ cfg.pixel_clk = hdmi->tmdsclk ; ++ cfg.tmds_clk = hdmi->tmdsclk ; ++ cfg.trace_len = HDMI_TRACE_DEFAULT; ++ printk("TMDS mode: %u, pixel_clk: %u, tmds_clk: %u, deep_color: %u, trace_len: %u\n", cfg.mode_cfg, ++ cfg.pixel_clk, cfg.tmds_clk, cfg.deep_color, cfg.trace_len); ++ /* initial: finish aphy, dphy configuration, configurate the register no change with standard */ ++ if (cfg.mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { ++ phy_hw_init_tmds(0, &cfg); ++ } ++ ret = phy_tmds_clk_set(0, &cfg, &phy_clk); ++ if (ret != 0) { ++ printk("phy tmds clk set fail.\n"); ++ return; ++ } ++ hdmi_ssc_cfg.phy_ssc.ssc_enable = cfg.emi_enable; ++ hdmi_ssc_cfg.pix_clk = cfg.pixel_clk; ++ hdmi_ssc_cfg.tmds_clk = cfg.tmds_clk; ++ hdmi_ssc_cfg.deep_color = cfg.deep_color; ++ /* calculate spread spectrum */ ++ if (cfg.mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { ++ hal_hdmi_phy_ssc_set(0, &hdmi_ssc_cfg); ++ } ++ ++ /* initial: index */ ++ ret = phy_tmds_spec_set(0, &cfg); ++ if (ret != 0) { ++ printk("phy tmds spec set fail.\n"); ++ return; ++ } ++ ++ /* data path enable */ ++ phy_hw_post_set_up(0, &cfg); ++ hdmi_phy_oe_get(0); ++ memcpy(&g_hdmi_phy_info[0].tmds_cfg, &cfg, sizeof(hdmi_phy_tmds_cfg)); ++} ++ ++void hdmi_reg_write(volatile unsigned int *reg_addr, unsigned int value) ++{ ++ if (reg_addr != NULL) { ++ *(volatile unsigned int *)reg_addr = value; ++ } ++} ++ ++unsigned int hdmi_reg_read(volatile unsigned int *reg_addr) ++{ ++ if (reg_addr == NULL) { ++ return 0; ++ } ++ return *(volatile unsigned int *)reg_addr; ++} ++ ++ ++static void hdmi_cbar_enable(bool enable) ++{ ++ unsigned int *reg_addr = NULL; ++ unsigned int reg_value; ++ reg_addr = (unsigned int *)ioremap(HDMI_COLOR_BAR_BASE, 4); /* 4: register size */ ++ if (*reg_addr == NULL) { ++ return; ++ } ++ reg_value = hdmi_reg_read(reg_addr); ++ ++ if (enable) { ++ reg_value |= HDMI_COLOR_BAR_MASK; ++ reg_value |= HDMI_COLOR_BAR_UPDATE_MASK; ++ } else { ++ reg_value &= ~HDMI_COLOR_BAR_MASK; ++ reg_value |= HDMI_COLOR_BAR_UPDATE_MASK; ++ } ++ hdmi_reg_write(reg_addr, reg_value); ++ iounmap((void *)reg_addr); /* 4: register size */ ++} ++ ++int hal_hdmi_ctrl_data_reset(hdmi_device_id hdmi, bool debug_mode, unsigned int delay_ms) ++{ ++ static unsigned int delay; ++ ++ hdmi_reg_tx_acr_srst_req_set(1); ++ hdmi_reg_tx_afifo_srst_req_set(1); ++ hdmi_reg_tx_aud_srst_req_set(1); ++ hdmi_reg_tx_hdmi_srst_req_set(1); ++ udelay(CTRL_REAET_WAIT_TIME); ++ hdmi_reg_tx_acr_srst_req_set(0); ++ hdmi_reg_tx_afifo_srst_req_set(0); ++ hdmi_reg_tx_aud_srst_req_set(0); ++ /* TOP rst: will also pack_fifo_ctrl reg_fifo_manu_rst */ ++ hdmi_reg_tx_hdmi_srst_req_set(0); ++ ++ if (debug_mode) { ++ delay = delay_ms; ++ } ++ ++ if (delay) { ++ msleep(delay); ++ printk("data_rst %u ms\n", delay); ++ } ++ ++ return 0; ++} ++ ++int hal_hdmi_ctrl_tmds_stable_get(hdmi_device_id hdmi, bool *stable) ++{ ++ *stable = hdmi_reg_pclk2tclk_stable_get() ? 1 : 0; ++ return 0; ++} ++ ++static void hal_hdmi_ctrl_reset(void) ++{ ++ unsigned int i; ++ bool tmds_stable = 0; ++ bool output = 0; ++ ++ output = hdmi_phy_oe_get(0); ++ if (output == 1) { ++ printk("oe enable, do not reset!\n"); ++ return; ++ } ++ ++ ++ hal_hdmi_ctrl_data_reset(0, 0, 0); ++ ++ for (i = 0; (!tmds_stable) && (i < CTRL_RESET_WAIT); i++) { ++ msleep(1); ++ hal_hdmi_ctrl_tmds_stable_get(0, &tmds_stable); ++ } ++ ++ printk("wait %ums, tmds_stable=%u\n", i, tmds_stable); ++ ++ return; ++} ++ ++static void ctrl_video_mute_set(bool enable) ++{ ++ unsigned int data_value; ++ enum hdmi_colorspace in_color_space = HDMI_COLORSPACE_RGB; ++ enum hdmi_colorspace out_color_space = HDMI_COLORSPACE_RGB; ++ ++ ++ data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_R : CTRL_BLACK_DATA_YUV_CR; ++ hdmi_reg_solid_pattern_cr_set((unsigned short)data_value); ++ ++ data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_G : CTRL_BLACK_DATA_YUV_Y; ++ hdmi_reg_solid_pattern_y_set((unsigned short)data_value); ++ ++ data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_B : CTRL_BLACK_DATA_YUV_CB; ++ hdmi_reg_solid_pattern_cb_set((unsigned short)data_value); ++ ++ hdmi_reg_video_blank_en_set((unsigned char )enable); ++ hdmi_reg_solid_pattern_en_set((unsigned char )enable); ++ ++ return; ++} ++ ++static int smart_hdmi_setup(struct smart_hdmi *hdmi, ++ struct drm_display_mode *mode) ++{ ++ struct drm_display_info *display = &hdmi->connector.display_info; ++ hdmi_tmds_mode tmds_mode; ++ unsigned int pixel_clk = 0; ++ hdmi->hdmi_data.vic = drm_match_cea_mode(mode); ++ ++ ++ if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || ++ hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || ++ hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || ++ hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) ++ hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; ++ else ++ hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; ++ ++ hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; ++ ++ ++ hdmi->tmdsclk = mode->clock; ++ ++ /* Input video mode is RGB 24 bit. Use external data enable signal. */ ++ smart_hdmi_config_video_timing(hdmi, mode); ++ if (display->is_hdmi) { ++ smart_hdmi_config_avi(hdmi, mode); ++ } ++ ++ smart_hdmi_config_video_csc(hdmi); ++ ++ smart_hdmi_config_phy(hdmi); ++ //drv_hdmi_start ++ drv_hdmi_low_power_set(0); ++ //hal_hdmi_tmds_mode_set ++ if (hdmi->tmdsclk > HDMI_EDID_MAX_HDMI14_TMDS_RATE) { ++ tmds_mode = HDMI_TMDS_MODE_HDMI_2_0; ++ } else { ++ tmds_mode = HDMI_TMDS_MODE_HDMI_1_4; ++ } ++ ctrl_tmds_mode_set(tmds_mode); ++ //hal_hdmi_ctrl_reset ++ hal_hdmi_ctrl_reset(); ++ ++ //hdmi_phy_output_enable(hdmi_dev, 1); ++ hal_hdmi_phy_oe_set(0,1); ++ hdmi_phy_oe_get(0); ++ ctrl_video_mute_set(0); ++ ++ ++ //hdmi_cbar_enable(1); ++ return 0; ++} ++ ++static void ++smart_hdmi_encoder_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adj_mode) ++{ ++ struct smart_hdmi *hdmi = encoder_to_smart_hdmi(encoder); ++ ++ /* Store the display mode for plugin/DPMS poweron events. */ ++ drm_mode_copy(&hdmi->previous_mode, adj_mode); ++} ++ ++static void smart_hdmi_encoder_enable(struct drm_encoder *encoder) ++{ ++ struct smart_hdmi *hdmi = encoder_to_smart_hdmi(encoder); ++ ++ smart_hdmi_setup(hdmi, &hdmi->previous_mode); ++} ++ ++static void smart_hdmi_encoder_disable(struct drm_encoder *encoder) ++{ ++ struct smart_hdmi *hdmi = encoder_to_smart_hdmi(encoder); ++ ++ ++} ++ ++static bool ++smart_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adj_mode) ++{ ++ ++ return true; ++} ++ ++static int ++smart_hdmi_encoder_atomic_check(struct drm_encoder *encoder, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ struct smart_crtc_state *s = to_smart_crtc_state(crtc_state); ++ ++ return 0; ++} ++ ++static const ++struct drm_encoder_helper_funcs smart_hdmi_encoder_helper_funcs = { ++ .enable = smart_hdmi_encoder_enable, ++ .disable = smart_hdmi_encoder_disable, ++ .mode_fixup = smart_hdmi_encoder_mode_fixup, ++ .mode_set = smart_hdmi_encoder_mode_set, ++ .atomic_check = smart_hdmi_encoder_atomic_check, ++}; ++ ++static enum drm_connector_status ++smart_hdmi_connector_detect(struct drm_connector *connector, bool force) ++{ ++ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); ++ if(ctrl_hpd_get()) { ++ return connector_status_connected; ++ } ++ return connector_status_disconnected; ++} ++ ++static int ddc_access_enable_wait(unsigned int timeout) ++{ ++ int ret = 0; ++ unsigned int tmp_time = 0; ++ ++ hdmi_reg_cpu_ddc_req_set(1); ++ ++ while (!hdmi_reg_cpu_ddc_req_ack_get()) { ++ msleep(1); ++ tmp_time++; ++ if (tmp_time > timeout) { ++ ret = -1; ++ break; ++ } ++ } ++ return ret; ++} ++static int ddc_scl_wait(unsigned int timeout) ++{ ++ int ret = 0; ++ unsigned int tmp_time = 0; ++ ++ while (!hdmi_reg_ddc_scl_st_get()) { ++ msleep(1); ++ tmp_time += 1; ++ if (tmp_time > timeout) { ++ ret = -1; ++ break; ++ } ++ } ++ return ret; ++} ++ ++static int ddc_sda_wait(unsigned int timeout) ++{ ++ unsigned int tmp_timeout = 0; ++ int ret = 0; ++ if (!hdmi_reg_ddc_sda_st_get()) { ++ hdmi_reg_dcc_man_en_set(1); ++ while ((!hdmi_reg_ddc_sda_st_get()) && tmp_timeout < timeout) { ++ tmp_timeout++; ++ ++ /* pull scl high */ ++ hdmi_reg_ddc_scl_oen_set(1); ++ udelay(DDC_DEFAULT_DELAY); ++ /* pull scl low */ ++ hdmi_reg_ddc_scl_oen_set(0); ++ udelay(DDC_DEFAULT_DELAY); ++ } ++ ++ /* STOP contition */ ++ if (tmp_timeout < timeout && (hdmi_reg_ddc_sda_st_get())) { ++ /* pull sda low */ ++ hdmi_reg_ddc_sda_oen_set(0); ++ udelay(DDC_DEFAULT_DELAY); ++ /* pull scl high */ ++ hdmi_reg_ddc_scl_oen_set(1); ++ udelay(DDC_DEFAULT_DELAY); ++ /* pull sda high */ ++ hdmi_reg_ddc_sda_oen_set(1); ++ udelay(DDC_DEFAULT_DELAY); ++ printk("deadlock clear success\n"); ++ ret = 0; ++ } else { ++ printk("deadlock clear fail\n"); ++ ret = -1; ++ } ++ hdmi_reg_dcc_man_en_set(0); ++ } ++ ++ return ret; ++} ++ ++static int ddc_cmd_issue(unsigned char offset_data) ++{ ++ unsigned short data_size; ++ unsigned char slave_addr, segment, offset; ++ segment = 0; ++ offset = offset_data; ++ slave_addr = DDC_EDID_SALVE_ADDR; ++ data_size = HDMI_EDID_BLOCK_SIZE; ++ hdmi_reg_pwd_mst_cmd_set(DDC_CMD_FIFO_CLR); ++ hdmi_reg_pwd_slave_addr_set(slave_addr); ++ hdmi_reg_pwd_slave_seg_set(segment); ++ hdmi_reg_pwd_slave_offset_set(offset); ++ hdmi_reg_pwd_data_out_cnt_set(data_size); ++ udelay(DDC_DEFAULT_DELAY); ++ hdmi_reg_pwd_mst_cmd_set(DDC_MODE_READ_MUTIL_NO_ACK); ++ return 0; ++} ++ ++static int ddc_read(unsigned char *pdata) ++{ ++ unsigned int len; ++ ddc_func_type type; ++ unsigned char *data = NULL; ++ unsigned int i, retry, data_size; ++ ktime_t start_time, end_time; ++ unsigned int elapsed_ms = 0; ++ data = pdata; ++ type = DDC_FUNC_TYPE_EDID; ++ len = HDMI_EDID_BLOCK_SIZE; ++ retry = DDC_DEFAULT_TIMEOUT_SDA; ++ ++ for (data_size = 0; data_size < len; data_size++, data++) { ++ ++ start_time = ktime_get(); ++ end_time = start_time; ++ elapsed_ms = ktime_to_ns(ktime_sub(end_time, start_time)); ++ elapsed_ms = elapsed_ms / NSEC_PER_MSEC; ++ /* when read-fifo empty, every byte wait a max timeout */ ++ for (i = 0; ++ ((i < retry) && (hdmi_reg_pwd_fifo_empty_get() || (hdmi_reg_pwd_fifo_data_out_get() == 0))) && ++ (elapsed_ms <= DDC_DEFAULT_RETRY_TIMEOUT_ISSUE); ++ i++) { ++ /* wait ddc status update after DDC cmd set. */ ++ msleep(1); ++ if (hdmi_reg_ddc_i2c_no_ack_get() || hdmi_reg_ddc_i2c_bus_low_get()) { ++ hdmi_reg_pwd_mst_cmd_set(DDC_CMD_MASTER_ABORT); ++ printk("DDC status error!\n"); ++ return -1; ++ } ++ ++ end_time = ktime_get(); ++ } ++ ++ elapsed_ms = ktime_to_ns(ktime_sub(end_time, start_time)); ++ elapsed_ms = elapsed_ms / NSEC_PER_MSEC; ++ if ((i >= retry) || (elapsed_ms > DDC_DEFAULT_RETRY_TIMEOUT_ISSUE)) { ++ if (type != DDC_FUNC_TYPE_SCDC) { ++ printk("read fifo retry=%u ms, size=%u, timeout:%u!\n", ++ retry, len, elapsed_ms); ++ } else { ++ printk("read fifo retry=%u ms, size=%u, timeout:%u!\n", ++ retry, len, elapsed_ms); ++ } ++ return -1; ++ } ++ if (data != NULL) { ++ *data = hdmi_reg_rdata_pwd_fifo_data_out_get(); ++ /* ++ * the fifo status is not refresh promptly, ++ * so re-read the fifo status and delay 1us if the fifo is empty, ++ * wait the data ready. it must delay 1us after read fifo data. ++ */ ++ udelay(1); ++ } else { ++ printk("edid &data[%u]=null\n", data_size); ++ return -1; ++ } ++ } ++ ++ return data_size; ++} ++ ++static int ddc_in_prog_wait(unsigned int timeout) ++{ ++ int ret = 0; ++ unsigned int tmp_time = 0; ++ while (hdmi_reg_pwd_i2c_in_prog_get()) { ++ msleep(1); ++ tmp_time += 1; ++ if (tmp_time > timeout) { ++ ret = -1; ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static int ddc_access_disable_wait(unsigned int timeout) ++{ ++ int ret = 0; ++ unsigned int tmp_time = 0; ++ hdmi_reg_cpu_ddc_req_set(0); ++ while (hdmi_reg_cpu_ddc_req_ack_get()) { ++ msleep(1); ++ tmp_time += 1; ++ if (tmp_time > timeout) { ++ ret = -1; ++ break; ++ } ++ } ++ return ret; ++} ++ ++static int smart_hdmi_connector_get_modes(struct drm_connector *connector) ++{ ++ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); ++ struct edid *edid; ++ int ret = 0; ++ int data_size = 0; ++ unsigned char edid_data[HDMI_EDID_BLOCK_SIZE*2] = {0}; ++ ++ spin_lock(&hdmi->reg_lock); ++ if (ddc_access_enable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { ++ printk("wait access bus timeout!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ /* scl check */ ++ if (ddc_scl_wait(DDC_DEFAULT_TIMEOUT_SCL) != 0) { ++ printk("wait scl timeout!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ /* sda check */ ++ if (ddc_sda_wait(DDC_DEFAULT_TIMEOUT_SDA) != 0) { ++ printk("wait sda timeout!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ /* issue command */ ++ if (ddc_cmd_issue(0) != 0) { ++ printk("command issue fail!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ data_size = ddc_read(&edid_data[0]); ++ ++ if (ddc_in_prog_wait(DDC_DEFAULT_TIMEOUT_IN_PROG) != 0) { ++ printk("wait in prog timeout!\n"); ++ } ++ ++ if (ddc_access_disable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { ++ printk("wait access disable timeout!\n"); ++ } ++ ++ // BLOCK 1 ++ ++ if (ddc_access_enable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { ++ printk("wait access bus timeout!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ /* scl check */ ++ if (ddc_scl_wait(DDC_DEFAULT_TIMEOUT_SCL) != 0) { ++ printk("wait scl timeout!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ /* sda check */ ++ if (ddc_sda_wait(DDC_DEFAULT_TIMEOUT_SDA) != 0) { ++ printk("wait sda timeout!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ /* issue command */ ++ if (ddc_cmd_issue(HDMI_EDID_BLOCK_SIZE) != 0) { ++ printk("command issue fail!\n"); ++ spin_unlock(&hdmi->reg_lock); ++ return ret; ++ } ++ ++ data_size = ddc_read(&edid_data[HDMI_EDID_BLOCK_SIZE]); ++ if (ddc_in_prog_wait(DDC_DEFAULT_TIMEOUT_IN_PROG) != 0) { ++ printk("wait in prog timeout!\n"); ++ } ++ if (ddc_access_disable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { ++ printk("wait access disable timeout!\n"); ++ } ++ spin_unlock(&hdmi->reg_lock); ++ ++ edid = kmalloc(HDMI_EDID_BLOCK_SIZE * 2, GFP_KERNEL); ++ memcpy(edid, (struct edid *)edid_data, HDMI_EDID_BLOCK_SIZE * 2); ++ if (!drm_edid_is_valid(edid)) { ++ printk("Invalid EDID data read from registers\n"); ++ } else { ++ printk("EDID data read from registers\n"); ++ } ++ ++ if (edid) { ++ hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid); ++ hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid); ++ drm_connector_update_edid_property(connector, edid); ++ ret = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ return ret; ++} ++ ++static enum drm_mode_status ++smart_hdmi_connector_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) ++{ ++ struct hdmi_video_def *cfg = &g_cea_video_codes_des[0]; ++ int pclk = mode->clock; ++ bool valid = false; ++ int i; ++ ++ for (i = 0; cfg[i].pixclk != 0; i++) { ++ if (pclk == cfg[i].pixclk) { ++ valid = true; ++ break; ++ } ++ } ++ return (valid) ? MODE_OK : MODE_BAD; ++} ++ ++static struct drm_encoder * ++smart_hdmi_connector_best_encoder(struct drm_connector *connector) ++{ ++ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); ++ return &hdmi->encoder.encoder; ++} ++ ++static int ++smart_hdmi_probe_single_connector_modes(struct drm_connector *connector, ++ uint32_t maxX, uint32_t maxY) ++{ ++ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); ++ int ret; ++ ++ ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY); ++ return ret; ++} ++ ++static void smart_hdmi_connector_destroy(struct drm_connector *connector) ++{ ++ ++ drm_connector_unregister(connector); ++ drm_connector_cleanup(connector); ++} ++ ++static const struct drm_connector_funcs smart_hdmi_connector_funcs = { ++ .fill_modes = smart_hdmi_probe_single_connector_modes, ++ .detect = smart_hdmi_connector_detect, ++ .destroy = smart_hdmi_connector_destroy, ++ .reset = drm_atomic_helper_connector_reset, ++ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, ++}; ++ ++static const ++struct drm_connector_helper_funcs smart_hdmi_connector_helper_funcs = { ++ .get_modes = smart_hdmi_connector_get_modes, ++ .mode_valid = smart_hdmi_connector_mode_valid, ++ .best_encoder = smart_hdmi_connector_best_encoder, ++}; ++ ++static int ++smart_hdmi_register(struct drm_device *drm, struct smart_hdmi *hdmi) ++{ ++ struct drm_encoder *encoder = &hdmi->encoder.encoder; ++ struct device *dev = hdmi->dev; ++ int ret; ++ ++ if (!drm || !hdmi) ++ return -EINVAL; ++ ++ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ if (ret) { ++ dev_err(dev, "failed to init simple encoder: %d\n", ret); ++ return ret; ++ } ++ ++ drm_encoder_helper_add(encoder, &smart_hdmi_encoder_helper_funcs); ++ ++ ++ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); ++ ++ if (!encoder->possible_crtcs) { ++ dev_warn(dev, "No CRTCs found for HDMI encoder via DT, using fallback\n"); ++ if (drm->mode_config.num_crtc > 0) { ++ encoder->possible_crtcs = 1; // 绑定到crtc0 ++ } else { ++ dev_err(dev, "No fallback CRTC available\n"); ++ return -ENODEV; ++ } ++ } ++ ++ ++ /* 4. 配置连接器并初始�? */ ++ hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; ++ drm_connector_helper_add(&hdmi->connector, ++ &smart_hdmi_connector_helper_funcs); ++ ++ ret = drm_connector_init(drm, &hdmi->connector, ++ &smart_hdmi_connector_funcs, ++ DRM_MODE_CONNECTOR_HDMIA); ++ if (ret) { ++ dev_err(dev, "failed to init connector: %d\n", ret); ++ return ret; ++ } ++ ++ /* 5. 将连接器附加到编码器 */ ++ ret = drm_connector_attach_encoder(&hdmi->connector, encoder); ++ if (ret) { ++ dev_err(dev, "failed to attach connector to encoder: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static bool ctrl_hpd_get(void) ++{ ++ int hot_plug; ++ bool hpd; ++ ++ hot_plug = hdmi_reg_hotplug_state_get(); ++ if (hdmi_reg_hpd_polarity_ctl_get() > 0) { ++ hpd = (hot_plug > 0) ? 0 : 1; ++ } else { ++ hpd = (hot_plug > 0) ? 1 : 0; ++ } ++ return hpd; ++} ++ ++ ++static bool ctrl_rsen_get(void) ++{ ++ if (hdmi_reg_phy_rx_sense_get()) { ++ return 1; ++ } ++ return 0; ++} ++ ++static void ctrl_hpd_intr_enable(bool enable) ++{ ++ hdmi_reg_aon_intr_stat0_set(1); ++ hdmi_reg_aon_intr_mask0_set(enable); ++ return; ++} ++static void phy_default_spec_set(void) ++{ ++ unsigned char i; ++ hdmi_hw_spec *spec = NULL; ++ const struct tmds_spec_params *tmp = NULL; ++ hdmi_trace_len tmp_trace; ++ ++ for (tmp_trace = HDMI_TRACE_LEN_0; tmp_trace <= HDMI_TRACE_DEFAULT; tmp_trace++) { ++ spec = &g_hdmi_phy_info[0].hw_spec[tmp_trace]; ++ phy_hw_tmds_spec_trace_len_get(&tmp, tmp_trace); ++ for (i = 0; i < HDMI_HW_PARAM_NUM; i++) { ++ spec->hw_param[i].i_de_main_clk = tmp[i].clock.dphy.drv_post1; ++ spec->hw_param[i].i_de_main_data = tmp[i].data.dphy.drv_post1; ++ spec->hw_param[i].i_main_clk = tmp[i].clock.dphy.drv_main; ++ spec->hw_param[i].i_main_data = tmp[i].data.dphy.drv_main; ++ } ++ } ++ ++ return; ++} ++ ++static int smart_hdmi_bind(struct device *dev, struct device *master, ++ void *data) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct drm_device *drm = data; ++ struct smart_hdmi *hdmi; ++ int ret = 0; ++ static char *hdmi0_base; ++ static char *phy_base; ++ struct resource *res; ++ ++ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); ++ if (!hdmi) ++ return -ENOMEM; ++ ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,"hdmi0"); ++ if (!res) ++ return -ENODEV; ++ ++ hdmi0_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hdmi0_base)) { ++ dev_err(&pdev->dev, "Failed to map HDMI controller registers\n"); ++ return PTR_ERR(hdmi0_base); ++ } ++ ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); ++ if (!res) { ++ dev_err(&pdev->dev, "Failed to get HDMI PHY resource\n"); ++ return -ENODEV; ++ } ++ ++ phy_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(phy_base)) { ++ dev_err(&pdev->dev, "Failed to map HDMI PHY registers\n"); ++ return PTR_ERR(phy_base); ++ } ++ ++ //hal_hdmi_phy_init ++ hdmi_reg_tx_phy_init(0,phy_base); ++ phy_default_spec_set(); ++ ++ ret += hdmi_reg_crg_init(); ++ ret += hdmi_reg_aon_regs_init(hdmi0_base); ++ ret += hdmi_reg_audio_path_regs_init(hdmi0_base); ++ /* this functions will not be used at BVT */ ++ ret += hdmi_reg_tx_ctrl_regs_init(hdmi0_base); ++ ret += hdmi_reg_tx_hdmi_regs_init(hdmi0_base); ++ ret += hdmi_reg_video_path_regs_init(hdmi0_base); ++ ++ ++ //drv_hdmi_prod_crg_gate_set ++ drv_hdmi_prod_crg_gate_set(1); ++ //hal_hdmi_mach_start --> ctrl_hpd_intr_enable ++ ctrl_hpd_intr_enable(1); ++ ++ // hdmi_reg_video_blank_en_set(1); ++ ++ //hal_hdmi_phy_oe_get ++ hdmi_phy_oe_get(0); ++ ++ //drv_hdmi_prod_io_cfg_set ++ drv_hdmi_prod_crg_init(); ++ ++ //hal_hdmi_hot_plug_status_get ++ ctrl_hpd_get(); ++ ctrl_rsen_get(); ++ ++ ctrl_hpd_get(); ++ ctrl_rsen_get(); ++ ++ if(hdmi_reg_aon_intr_stat0_get()) { ++ hdmi_reg_aon_intr_stat0_set(1); ++ ctrl_hpd_get(); ++ } ++ ++ if(hdmi_reg_aon_intr_stat1_get()) { ++ hdmi_reg_aon_intr_stat1_set(1); ++ ctrl_rsen_get(); ++ } ++ hdmi->dev = dev; ++ hdmi->drm_dev = drm; ++ ++ ret = smart_hdmi_register(drm, hdmi); ++ if (ret) ++ goto err_cleanup_hdmi; ++ ++ dev_set_drvdata(dev, hdmi); ++ return 0; ++ ++err_cleanup_hdmi: ++ hdmi->connector.funcs->destroy(&hdmi->connector); ++ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); ++ return ret; ++} ++ ++static void smart_hdmi_unbind(struct device *dev, struct device *master, ++ void *data) ++{ ++ struct smart_hdmi *hdmi = dev_get_drvdata(dev); ++ hdmi->connector.funcs->destroy(&hdmi->connector); ++ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); ++} ++ ++static const struct component_ops smart_hdmi_ops = { ++ .bind = smart_hdmi_bind, ++ .unbind = smart_hdmi_unbind, ++}; ++ ++static int smart_hdmi_probe(struct platform_device *pdev) ++{ ++ return component_add(&pdev->dev, &smart_hdmi_ops); ++} ++ ++static void smart_hdmi_remove(struct platform_device *pdev) ++{ ++ component_del(&pdev->dev, &smart_hdmi_ops); ++} ++ ++static const struct of_device_id smart_hdmi_dt_ids[] = { ++ { .compatible = "vendor,hdmi" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, smart_hdmi_dt_ids); ++ ++struct platform_driver smart_hdmi_driver = { ++ .probe = smart_hdmi_probe, ++ .remove_new = smart_hdmi_remove, ++ .driver = { ++ .name = "hi3403v100-hdmi", ++ .of_match_table = smart_hdmi_dt_ids, ++ }, ++}; ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("runkaihong"); ++MODULE_DESCRIPTION("HI3403V100 HDMI for platform/SoC device"); +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.h b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.h +new file mode 100755 +index 000000000..39587fc92 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.h +@@ -0,0 +1,1329 @@ ++#ifndef __HI3403V100_HDMI_H__ ++#define __HI3403V100_HDMI_H__ ++ ++#include "hdmi_reg_aon.h" ++#include "hdmi_reg_audio_path.h" ++#include "hdmi_reg_ctrl.h" ++#include "hdmi_reg_tx.h" ++#include "hdmi_reg_video_path.h" ++#include "hdmi_reg_crg.h" ++#include "hdmi_product_define.h" ++#include "hdmi_reg_dphy.h" ++ ++#define DDC_SEGMENT_ADDR 0x30 ++#define HDMI_SCL_RATE (50 * 1000) ++#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x1F ++ ++#define HDMI_OE_CFG 0x520 ++#define cfg_oe_sync_en(x) (((x) & 0x1) << 4) ++#define CFG_OE_SYNC_EN_M (1 << 4) ++#define cfg_hdmi_oe_ch3(x) (((x) & 0x1) << 3) ++#define CFG_HDMI_OE_CH3_M (1 << 3) ++#define cfg_hdmi_oe_ch2(x) (((x) & 0x1) << 2) ++#define CFG_HDMI_OE_CH2_M (1 << 2) ++#define cfg_hdmi_oe_ch1(x) (((x) & 0x1) << 1) ++#define CFG_HDMI_OE_CH1_M (1 << 1) ++#define cfg_hdmi_oe_ch0(x) (((x) & 0x1) << 0) ++#define CFG_HDMI_OE_CH0_M (1 << 0) ++ ++/* AVI InfoFrame Packet byte offset define */ ++#define AVI_OFFSET_TYPE 0 ++#define AVI_OFFSET_VERSION 1 ++#define AVI_OFFSET_LENGTH 2 ++#define AVI_OFFSET_CHECKSUM 3 ++/* ++ * include : ++ * color space ++ * active information present ++ * bar Info data valid ++ * scan Information ++ */ ++#define AVI_OFFSET_PB1 4 ++/* ++ * include : ++ * colorimetry ++ * picture aspect ratio ++ * active format aspect ratio ++ */ ++#define AVI_OFFSET_PB2 5 ++/* ++ * include : ++ * IT content ++ * extended colorimetry ++ * quantization range ++ * non-uniform picture scaling ++ */ ++#define AVI_OFFSET_PB3 6 ++#define AVI_OFFSET_VIC 7 ++/* ++ * include : ++ * YCC quantization range ++ * content type ++ * pixel repetition factor ++ */ ++#define AVI_OFFSET_PB5 8 ++#define AVI_OFFSET_TOP_BAR_LOWER 9 ++#define AVI_OFFSET_TOP_BAR_UPPER 10 ++#define AVI_OFFSET_BOTTOM_BAR_LOWER 11 ++#define AVI_OFFSET_BOTTOM_BAR_UPPER 12 ++#define AVI_OFFSET_LEFT_BAR_LOWER 13 ++#define AVI_OFFSET_LEFT_BAR_UPPER 14 ++#define AVI_OFFSET_RIGHT_BAR_LOWER 15 ++#define AVI_OFFSET_RIGHT_BAR_UPPER 16 ++#define AVI_OFFSET_PB14 17 ++#define AVI_OFFSET_PB15 18 ++#define AVI_OFFSET_PB16 19 ++#define AVI_OFFSET_PB17 20 ++#define AVI_OFFSET_PB18 21 ++#define AVI_OFFSET_PB19 22 ++#define AVI_OFFSET_PB20 23 ++#define AVI_OFFSET_PB21 24 ++#define AVI_OFFSET_PB22 25 ++#define AVI_OFFSET_PB23 26 ++#define AVI_OFFSET_PB24 27 ++#define AVI_OFFSET_PB25 28 ++#define AVI_OFFSET_PB26 29 ++#define AVI_OFFSET_PB27 30 ++#define AVI_FRAME_COLORIMETRY_MASK 0x3 ++#define AVI_FRAME_PIC_ASPECT_MASK 0x3 ++#define AVI_FRAME_ACTIVE_ASPECT_MASK 0xF ++#define AVI_FRAME_EXT_COLORIMETRY_MASK 0x7 ++#define AVI_FRAME_QUANT_RANGE_MASK 0x3 ++#define AVI_FRAME_YCC_QUANT_RANGE_MASK 0x3 ++#define AVI_FRAME_PIXEL_REPET_MASK 0xF ++ ++//hdmi_hal_ddc.h ++#define DDC_MAX_RECORD_NUM 30 ++#define DDC_DEFAULT_TIMEOUT_ACCESS 100 ++#define DDC_DEFAULT_TIMEOUT_HPD 100 ++#define DDC_DEFAULT_TIMEOUT_IN_PROG 20 ++#define DDC_DEFAULT_TIMEOUT_SCL 1 ++#define DDC_DEFAULT_TIMEOUT_SDA 30 ++#define DDC_DEFAULT_TIMEOUT_ISSUE 20 ++#define DDC_DEFAULT_RETRY_TIMEOUT_ISSUE 60 ++ ++#define DDC_EDID_SALVE_ADDR 0xa0 ++#define DDC_HDCP_SALVE_ADDR 0x74 ++#define DDC_SCDC_SALVE_ADDR 0xa8 ++#define DDC_MAX_FIFO_SIZE 16 ++#define DDC_EXT_BLOCK_OFFSET 0x7e ++#define DDC_MAX_EDID_EXT_NUM 3 /* 3: 4(max block num) - 1(base block) */ ++#define DDC_DEFAULT_DELAY 8 /* 8us */ ++ ++static bool ctrl_hpd_get(void); ++ ++#define HDMI_EDID_BLOCK_SIZE 128 ++#define HDMI_EDID_TOTAL_BLOCKS 4 ++#define HDMI_EDID_SIZE (HDMI_EDID_BLOCK_SIZE * HDMI_EDID_TOTAL_BLOCKS) ++#define HDMI_REGISTER_SIZE 4 ++#define HDMI_EDID_MAX_BLOCK_NUM 4 ++#define HDMI_HW_PARAM_LEN 4 ++#define HDMI_EDID_TOTAL_SIZE ((HDMI_EDID_BLOCK_SIZE) * (HDMI_EDID_MAX_BLOCK_NUM)) ++ ++typedef enum { ++ DDC_CMD_READ_SINGLE_NO_ACK, ++ DDC_CMD_READ_SINGLE_ACK, ++ DDC_CMD_READ_MUTI_NO_ACK, ++ DDC_CMD_READ_MUTI_ACK, ++ DDC_CMD_READ_SEGMENT_NO_ACK, ++ DDC_CMD_READ_SEGMENT_ACK, ++ DDC_CMD_WRITE_MUTI_NO_ACK, ++ DDC_CMD_WRITE_MUTI_ACK, ++ DDC_CMD_FIFO_CLR = 0x09, ++ DDC_CMD_SCL_DRV, ++ DDC_CMD_MASTER_ABORT = 0x0f ++} ddc_issue_cmd; ++ ++typedef enum { ++ DDC_MODE_READ_SINGLE_NO_ACK, ++ DDC_MODE_READ_SINGLE_ACK, ++ DDC_MODE_READ_MUTIL_NO_ACK, ++ DDC_MODE_READ_MUTIL_ACK, ++ DDC_MODE_READ_SEGMENT_NO_ACK, ++ DDC_MODE_READ_SEGMENT_ACK, ++ DDC_MODE_WRITE_MUTIL_NO_ACK, ++ DDC_MODE_WRITE_MUTIL_ACK, ++ DDC_MODE_BUTT ++} ddc_issue_mode; ++ ++typedef enum { ++ DDC_FUNC_TYPE_EDID, ++ DDC_FUNC_TYPE_HDCP, ++ DDC_FUNC_TYPE_SCDC, ++ DDC_FUNC_TYPE_BUTT ++} ddc_func_type; ++ ++ ++ ++#define CEA_VIDEO_CODE_MAX 44 ++ ++#if 0 ++typedef enum { ++ /HDMI_PICTURE_ASPECT_NONE, ++ HDMI_PICTURE_ASPECT_4_3 = 1, ++ HDMI_PICTURE_ASPECT_16_9, ++ HDMI_PICTURE_ASPECT_64_27, ++ HDMI_PICTURE_ASPECT_256_135, ++ HDMI_PICTURE_ASPECT_FUTURE, ++ HDMI_PICTURE_ASPECT_BUTT ++} hdmi_picture_aspect; ++#endif ++ ++typedef enum { ++ HDMI_640X480P60_4_3 = 1, ++ HDMI_720X480P60_4_3, ++ HDMI_720X480P60_16_9, ++ HDMI_1280X720P60_16_9, ++ HDMI_1920X1080I60_16_9, ++ HDMI_1440X480I60_4_3, ++ HDMI_1440X480I60_16_9, // 7 ++ HDMI_1440X240P60_4_3, ++ HDMI_1440X240P60_16_9, ++ HDMI_2880X480I60_4_3, ++ HDMI_2880X480I60_16_9, ++ HDMI_2880X240P60_4_3, // 12 ++ HDMI_2880X240P60_16_9, ++ HDMI_1440X480P60_4_3, ++ HDMI_1440X480P60_16_9, ++ HDMI_1920X1080P60_16_9, ++ HDMI_720X576P50_4_3, ++ HDMI_720X576P50_16_9, ++ HDMI_1280X720P50_16_9, ++ HDMI_1920X1080I50_16_9, ++ HDMI_1440X576I50_4_3, ++ HDMI_1440X576I50_16_9, ++ HDMI_1440X288P50_4_3, ++ HDMI_1440X288P50_16_9, // 24 ++ HDMI_2880X576I50_4_3, ++ HDMI_2880X576I50_16_9, ++ HDMI_2880X288P50_4_3, ++ HDMI_2880X288P50_16_9, ++ HDMI_1440X576P50_4_3, ++ HDMI_1440X576P50_16_9, // 30 ++ HDMI_1920X1080P50_16_9, ++ HDMI_1920X1080P24_16_9, ++ HDMI_1920X1080P25_16_9, ++ HDMI_1920X1080P30_16_9, ++ HDMI_2880X480P60_4_3, ++ HDMI_2880X480P60_16_9, ++ HDMI_2880X576P50_4_3, ++ HDMI_2880X576P50_16_9, // 38 ++ HDMI_1920X1080I50_16_9_1250, ++ HDMI_1920X1080I100_16_9, ++ HDMI_1280X720P100_16_9, ++ HDMI_720X576P100_4_3, ++ HDMI_720X576P100_16_9, ++ HDMI_1440X576I100_4_3, ++ HDMI_1440X576I100_16_9, // 45 ++ HDMI_1920X1080I120_16_9, ++ HDMI_1280X720P120_16_9, ++ HDMI_720X480P120_4_3, ++ HDMI_720X480P120_16_9, ++ HDMI_1440X480I120_4_3, ++ HDMI_1440X480I120_16_9, // 51 ++ HDMI_720X576P200_4_3, ++ HDMI_720X576P200_16_9, ++ HDMI_1440X576I200_4_3, ++ HDMI_1440X576I200_16_9, ++ HDMI_720X480P240_4_3, ++ HDMI_720X480P240_16_9, ++ HDMI_1440X480I240_4_3, ++ HDMI_1440X480I240_16_9, // 59 ++ HDMI_1280X720P24_16_9, ++ HDMI_1280X720P25_16_9, ++ HDMI_1280X720P30_16_9, ++ HDMI_1920X1080P120_16_9, ++ HDMI_1920X1080P100_16_9, ++ HDMI_1280X720P24_64_27, ++ HDMI_1280X720P25_64_27, ++ HDMI_1280X720P30_64_27, ++ HDMI_1280X720P50_64_27, ++ HDMI_1280X720P60_64_27, // 69 ++ HDMI_1280X720P100_64_27, ++ HDMI_1280X720P120_64_27, ++ HDMI_1920X1080P24_64_27, ++ HDMI_1920X1080P25_64_27, ++ HDMI_1920X1080P30_64_27, ++ HDMI_1920X1080P50_64_27, ++ HDMI_1920X1080P60_64_27, // 76 ++ HDMI_1920X1080P100_64_27, ++ HDMI_1920X1080P120_64_27, ++ HDMI_1680X720P24_64_27, ++ HDMI_1680X720P25_64_27, ++ HDMI_1680X720P30_64_27, ++ HDMI_1680X720P50_64_27, ++ HDMI_1680X720P60_64_27, // 83 ++ HDMI_1680X720P100_64_27, ++ HDMI_1680X720P120_64_27, ++ HDMI_2560X1080P24_64_27, ++ HDMI_2560X1080P25_64_27, ++ HDMI_2560X1080P30_64_27, ++ HDMI_2560X1080P50_64_27, ++ HDMI_2560X1080P60_64_27, ++ HDMI_2560X1080P100_64_27, ++ HDMI_2560X1080P120_64_27, // 92 ++ HDMI_3840X2160P24_16_9, ++ HDMI_3840X2160P25_16_9, ++ HDMI_3840X2160P30_16_9, ++ HDMI_3840X2160P50_16_9, ++ HDMI_3840X2160P60_16_9, ++ HDMI_4096X2160P24_256_135, ++ HDMI_4096X2160P25_256_135, ++ HDMI_4096X2160P30_256_135, ++ HDMI_4096X2160P50_256_135, ++ HDMI_4096X2160P60_256_135, ++ HDMI_3840X2160P24_64_27, ++ HDMI_3840X2160P25_64_27, ++ HDMI_3840X2160P30_64_27, ++ HDMI_3840X2160P50_64_27, ++ HDMI_3840X2160P60_64_27, // 107 ++ HDMI_1280X720P48_16_9, ++ HDMI_1280X720P48_64_27, ++ HDMI_1680X720P48_64_27, ++ HDMI_1920X1080P48_16_9, ++ HDMI_1920X1080P48_64_27, ++ HDMI_2560X1080P48_64_27, ++ HDMI_3840X2160P48_16_9, ++ HDMI_4096X2160P48_256_135, ++ HDMI_3840X2160P48_64_27, ++ HDMI_3840X2160P100_16_9, ++ HDMI_3840X2160P120_16_9, ++ HDMI_3840X2160P100_64_27, ++ HDMI_3840X2160P120_64_27, ++ HDMI_5120X2160P24_64_27, // 121 ++ HDMI_5120X2160P25_64_27, ++ HDMI_5120X2160P30_64_27, ++ HDMI_5120X2160P48_64_27, ++ HDMI_5120X2160P50_64_27, ++ HDMI_5120X2160P60_64_27, ++ HDMI_5120X2160P100_64_27, // 127 ++ HDMI_5120X2160P120_64_27 = 193, ++ HDMI_7680X4320P24_16_9, ++ HDMI_7680X4320P25_16_9, ++ HDMI_7680X4320P30_16_9, ++ HDMI_7680X4320P48_16_9, ++ HDMI_7680X4320P50_16_9, ++ HDMI_7680X4320P60_16_9, ++ HDMI_7680X4320P100_16_9, // 200 ++ HDMI_7680X4320P120_16_9, ++ HDMI_7680X4320P24_64_27, ++ HDMI_7680X4320P25_64_27, ++ HDMI_7680X4320P30_64_27, ++ HDMI_7680X4320P48_64_27, ++ HDMI_7680X4320P50_64_27, ++ HDMI_7680X4320P60_64_27, ++ HDMI_7680X4320P100_64_27, ++ HDMI_7680X4320P120_64_27, ++ HDMI_10240X4320P24_64_27, ++ HDMI_10240X4320P25_64_27, ++ HDMI_10240X4320P30_64_27, ++ HDMI_10240X4320P48_64_27, ++ HDMI_10240X4320P50_64_27, // 214 ++ HDMI_10240X4320P60_64_27, ++ HDMI_10240X4320P100_64_27, ++ HDMI_10240X4320P120_64_27, ++ HDMI_4096X2160P100_256_135, ++ HDMI_4096X2160P120_256_135, // 219 ++ HDMI_VIDEO_CODE_BUTT ++} hdmi_video_code_vic; ++ ++typedef enum { ++ HDMI_VIDEO_TIMING_UNKNOWN, ++ HDMI_VIDEO_TIMING_640X480P_60000, ++ HDMI_VIDEO_TIMING_720X480P_60000, ++ HDMI_VIDEO_TIMING_720X480P_120000, ++ HDMI_VIDEO_TIMING_720X480P_240000, // 4 ++ HDMI_VIDEO_TIMING_720X576P_50000, ++ HDMI_VIDEO_TIMING_720X576P_100000, ++ HDMI_VIDEO_TIMING_720X576P_200000, // 7 ++ HDMI_VIDEO_TIMING_1280X720P_24000, ++ HDMI_VIDEO_TIMING_1280X720P_25000, ++ HDMI_VIDEO_TIMING_1280X720P_30000, // 10 ++ HDMI_VIDEO_TIMING_1280X720P_48000, ++ HDMI_VIDEO_TIMING_1280X720P_50000, ++ HDMI_VIDEO_TIMING_1280X720P_60000, ++ HDMI_VIDEO_TIMING_1280X720P_100000, ++ HDMI_VIDEO_TIMING_1280X720P_120000, ++ HDMI_VIDEO_TIMING_1440X240P_60000, // 16 ++ HDMI_VIDEO_TIMING_1440X288P_50000, ++ HDMI_VIDEO_TIMING_1440X480I_60000, ++ HDMI_VIDEO_TIMING_1440X480P_60000, ++ HDMI_VIDEO_TIMING_1440X480I_120000, ++ HDMI_VIDEO_TIMING_1440X480I_240000, ++ HDMI_VIDEO_TIMING_1440X576I_50000, // 22 ++ HDMI_VIDEO_TIMING_1440X576P_50000, ++ HDMI_VIDEO_TIMING_1440X576I_60000, ++ HDMI_VIDEO_TIMING_1440X576I_100000, ++ HDMI_VIDEO_TIMING_1440X576I_200000, ++ HDMI_VIDEO_TIMING_2880X288P_50000, // 27 ++ HDMI_VIDEO_TIMING_2880X480I_60000, ++ HDMI_VIDEO_TIMING_2880X480P_60000, ++ HDMI_VIDEO_TIMING_2880X240I_60000, ++ HDMI_VIDEO_TIMING_2880X576I_50000, ++ HDMI_VIDEO_TIMING_2880X576P_50000, ++ HDMI_VIDEO_TIMING_1680X720P_24000, // 33 ++ HDMI_VIDEO_TIMING_1680X720P_25000, ++ HDMI_VIDEO_TIMING_1680X720P_30000, ++ HDMI_VIDEO_TIMING_1680X720P_48000, ++ HDMI_VIDEO_TIMING_1680X720P_50000, ++ HDMI_VIDEO_TIMING_1680X720P_60000, ++ HDMI_VIDEO_TIMING_1680X720P_100000, ++ HDMI_VIDEO_TIMING_1680X720P_120000, ++ HDMI_VIDEO_TIMING_2560X1080P_24000, // 41 ++ HDMI_VIDEO_TIMING_2560X1080P_25000, ++ HDMI_VIDEO_TIMING_2560X1080P_30000, ++ HDMI_VIDEO_TIMING_2560X1080P_48000, ++ HDMI_VIDEO_TIMING_2560X1080P_50000, ++ HDMI_VIDEO_TIMING_2560X1080P_60000, ++ HDMI_VIDEO_TIMING_2560X1080P_100000, ++ HDMI_VIDEO_TIMING_2560X1080P_120000, // 48 ++ HDMI_VIDEO_TIMING_1920X1080I_60000, ++ HDMI_VIDEO_TIMING_1920X1080P_60000, ++ HDMI_VIDEO_TIMING_1920X1080I_50000, ++ HDMI_VIDEO_TIMING_1920X1080P_50000, ++ HDMI_VIDEO_TIMING_1920X1080P_24000, ++ HDMI_VIDEO_TIMING_1920X1080P_25000, ++ HDMI_VIDEO_TIMING_1920X1080P_30000, ++ HDMI_VIDEO_TIMING_1920X1080P_48000, ++ HDMI_VIDEO_TIMING_1920X1080I_100000, ++ HDMI_VIDEO_TIMING_1920X1080I_120000, ++ HDMI_VIDEO_TIMING_1920X1080P_120000, ++ HDMI_VIDEO_TIMING_1920X1080P_100000, // 60 ++ HDMI_VIDEO_TIMING_3840X2160P_24000, ++ HDMI_VIDEO_TIMING_3840X2160P_25000, ++ HDMI_VIDEO_TIMING_3840X2160P_30000, ++ HDMI_VIDEO_TIMING_3840X2160P_48000, ++ HDMI_VIDEO_TIMING_3840X2160P_50000, ++ HDMI_VIDEO_TIMING_3840X2160P_60000, ++ HDMI_VIDEO_TIMING_3840X2160P_100000, ++ HDMI_VIDEO_TIMING_3840X2160P_120000, ++ HDMI_VIDEO_TIMING_4096X2160P_24000, ++ HDMI_VIDEO_TIMING_4096X2160P_25000, ++ HDMI_VIDEO_TIMING_4096X2160P_30000, ++ HDMI_VIDEO_TIMING_4096X2160P_48000, ++ HDMI_VIDEO_TIMING_4096X2160P_50000, ++ HDMI_VIDEO_TIMING_4096X2160P_60000, // 74 ++ HDMI_VIDEO_TIMING_4096X2160P_100000, ++ HDMI_VIDEO_TIMING_4096X2160P_120000, ++ HDMI_VIDEO_TIMING_5120X2160P_24000, ++ HDMI_VIDEO_TIMING_5120X2160P_25000, ++ HDMI_VIDEO_TIMING_5120X2160P_30000, ++ HDMI_VIDEO_TIMING_5120X2160P_48000, ++ HDMI_VIDEO_TIMING_5120X2160P_50000, ++ HDMI_VIDEO_TIMING_5120X2160P_60000, ++ HDMI_VIDEO_TIMING_5120X2160P_100000, ++ HDMI_VIDEO_TIMING_5120X2160P_120000, ++ HDMI_VIDEO_TIMING_7680X4320P_24000, ++ HDMI_VIDEO_TIMING_7680X4320P_25000, ++ HDMI_VIDEO_TIMING_7680X4320P_30000, ++ HDMI_VIDEO_TIMING_7680X4320P_48000, ++ HDMI_VIDEO_TIMING_7680X4320P_50000, ++ HDMI_VIDEO_TIMING_7680X4320P_60000, ++ HDMI_VIDEO_TIMING_7680X4320P_100000, ++ HDMI_VIDEO_TIMING_7680X4320P_120000, ++ HDMI_VIDEO_TIMING_10240X4320P_24000, ++ HDMI_VIDEO_TIMING_10240X4320P_25000, ++ HDMI_VIDEO_TIMING_10240X4320P_30000, ++ HDMI_VIDEO_TIMING_10240X4320P_48000, ++ HDMI_VIDEO_TIMING_10240X4320P_50000, ++ HDMI_VIDEO_TIMING_10240X4320P_60000, ++ HDMI_VIDEO_TIMING_10240X4320P_100000, ++ HDMI_VIDEO_TIMING_10240X4320P_120000, ++ HDMI_VIDEO_TIMING_VESA_DEFINE, ++ HDMI_VIDEO_TIMING_VESA_800X600_60, ++ HDMI_VIDEO_TIMING_VESA_848X480_60, ++ HDMI_VIDEO_TIMING_VESA_1024X768_60, ++ HDMI_VIDEO_TIMING_VESA_1280X720_60, ++ HDMI_VIDEO_TIMING_VESA_1280X768_60, ++ HDMI_VIDEO_TIMING_VESA_1280X768_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1280X800_60, ++ HDMI_VIDEO_TIMING_VESA_1280X800_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1280X960_60, ++ HDMI_VIDEO_TIMING_VESA_1280X1024_60, ++ HDMI_VIDEO_TIMING_VESA_1360X768_60, ++ HDMI_VIDEO_TIMING_VESA_1366X768_60, ++ HDMI_VIDEO_TIMING_VESA_1400X1050_60, ++ HDMI_VIDEO_TIMING_VESA_1440X900_60, ++ HDMI_VIDEO_TIMING_VESA_1440X900_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1440X1050_60, ++ HDMI_VIDEO_TIMING_VESA_1440X1050_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1600X900_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1600X1200_60, ++ HDMI_VIDEO_TIMING_VESA_1680X1050_60, ++ HDMI_VIDEO_TIMING_VESA_1680X1050_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1792X1344_60, ++ HDMI_VIDEO_TIMING_VESA_1856X1392_60, ++ HDMI_VIDEO_TIMING_VESA_1920X1080_60, ++ HDMI_VIDEO_TIMING_VESA_1920X1200_60, ++ HDMI_VIDEO_TIMING_VESA_1920X1200_60_RB, ++ HDMI_VIDEO_TIMING_VESA_1920X1440_60, ++ HDMI_VIDEO_TIMING_VESA_2048X1152_60, ++ HDMI_VIDEO_TIMING_VESA_2560X1440_60_RB, ++ HDMI_VIDEO_TIMING_VESA_2560X1600_60, ++ HDMI_VIDEO_TIMING_VESA_2560X1600_60_RB, ++ HDMI_VIDEO_TIMING_USER_DEFINE, ++ HDMI_VIDEO_TIMING_USER_1920X2160_30, ++ HDMI_VIDEO_TIMING_USER_2560X1440_30, ++ HDMI_VIDEO_TIMING_USER_2560X1440_60, ++ HDMI_VIDEO_TIMING_USER_1280X720_60, ++ HDMI_VIDEO_TIMING_USER_1366X768_60, ++ HDMI_VIDEO_TIMING_USER_1600X900_60_RB, ++ HDMI_VIDEO_TIMING_USER_1920X1080_60, ++ HDMI_VIDEO_TIMING_USER_2048X1152_60, ++ HDMI_VIDEO_TIMING_BUTT ++} hdmi_video_timing; ++ ++typedef enum { ++ HDMI_VIDEO_UNKNOWN, ++ HDMI_VIDEO_PROGRESSIVE, ++ HDMI_VIDEO_INTERLACE, ++ HDMI_VIDEO_BUTT ++} hdmi_video_format_type; ++ ++struct hdmi_video_def { ++ hdmi_video_code_vic video_code; ++ unsigned int pixclk; ++ unsigned int rate; ++ unsigned int hactive; ++ unsigned int vactive; ++ unsigned int hblank; ++ unsigned int vblank; ++ unsigned int hfront; ++ unsigned int hsync; ++ unsigned int hback; ++ unsigned int vfront; ++ unsigned int vsync; ++ unsigned int vback; ++ unsigned int aspect_ratio; ++ hdmi_video_timing timing; ++ hdmi_video_format_type pi_type; ++ char *fmt_str; ++}; ++ ++#define hdmi_array_size(a) (sizeof(a) / sizeof(a[0])) ++ ++#define CTRL_CHANNEL0_Y 0x0 ++#define CTRL_CHANNEL0_Y422 0x3 ++#define CTRL_CHANNEL1_CB 0x1 ++#define CTRL_CHANNEL1_Y422 0x4 ++#define CTRL_CHANNEL2_CR 0x2 ++#define CTRL_CHANNEL2_Y422 0x3 ++#define CTRL_COLORMETRY_OUT_MASK 0xfc ++#define CTRL_COLORMETRY_OUT_BIT 0 /* out colormetry offset in reg_csc_mode */ ++#define CTRL_COLORMETRY_IN_MASK 0xcf ++#define CTRL_COLORMETRY_IN_BIT 0x4 /* in colormetry offset in reg_csc_mode */ ++#define CTRL_COLORMETRY_MASK 0x3 ++#define CTRL_RGB_OUT_BIT 0x3 /* out color space offset in reg_csc_mode */ ++#define CTRL_RGB_IN_BIT 0x7 /* in color space offset in reg_csc_mode */ ++#define CTRL_QUANTIZAION_OUT_BIT 0x2 /* out quantization offset in reg_csc_mode */ ++#define CTRL_QUANTIZAION_IN_BIT 0x6 /* in quantization offset in reg_csc_mode */ ++#define CTRL_SYCN_POL_V_BIT 0 /* vsync offset in reg_inver_sync */ ++#define CTRL_SYCN_POL_H_BIT 1 /* hsync offset in reg_inver_sync */ ++#define CTRL_SYCN_POL_DE_BIT 0x3 /* DE offset in reg_inver_sync */ ++#define CTRL_BLACK_Y_CB_CR 0x000000 ++#define CTRL_BLACK_DATA_YUV_CR 0x200 /* cr val for yuv black */ ++#define CTRL_BLACK_DATA_YUV_Y 0x40 /* y val for yuv black */ ++#define CTRL_BLACK_DATA_YUV_CB 0x200 /* cb val for yuv black */ ++#define CTRL_BLACK_DATA_RGB_R 0x40 /* r val for rgb black */ ++#define CTRL_BLACK_DATA_RGB_G 0x40 /* g val for rgb black */ ++#define CTRL_BLACK_DATA_RGB_B 0x40 /* b val for rgb black */ ++#define CTRL_AUDIO_INVALID_CFG 0xff ++#define CTRL_AUDIO_INVALID_RATE 0xffffffff ++#define CTRL_REAET_WAIT_TIME 5 ++#define HDMI_INFOFRAME_DATA_SIZE 31 ++ ++#define hdmi_set_bit(var, bit) \ ++ do { \ ++ (var) |= 1 << (bit); \ ++ } while (0) ++ ++#define hdmi_clr_bit(var, bit) \ ++ do { \ ++ (var) &= ~(1 << (bit)); \ ++ } while (0) ++ ++typedef enum { ++ HDMI_TMDS_MODE_NONE, ++ HDMI_TMDS_MODE_DVI, ++ HDMI_TMDS_MODE_HDMI_1_4, ++ HDMI_TMDS_MODE_HDMI_2_0, ++ HDMI_TMDS_MODE_AUTO, ++ HDMI_TMDS_MODE_HDMI_2_1, ++ HDMI_TMDS_MODE_BUTT ++} hdmi_tmds_mode; ++ ++typedef enum { ++ HDMI_PHY_MODE_CFG_TMDS, ++ HDMI_PHY_MODE_CFG_FRL, ++ HDMI_PHY_MODE_CFG_TXFFE ++} hdmi_phy_mode_cfg; ++ ++struct dphy_spec_en { ++ bool drv_post2_en; ++ bool drv_post1_en; ++ bool drv_pre_en; ++}; ++ ++struct dphy_spec_params { ++ unsigned char drv_post2; ++ unsigned char drv_post1; ++ unsigned char drv_main; ++ unsigned char drv_pre; ++}; ++ ++struct aphy_spec_params { ++ unsigned char offset_0; ++ unsigned char offset_1; ++ unsigned char offset_2; ++ unsigned char offset_3; ++ unsigned char offset_4; ++ unsigned char offset_5; ++ unsigned char offset_8; ++ unsigned char offset_9; ++ unsigned char offset_a; ++ unsigned char offset_b; ++}; ++ ++struct spec_params { ++ struct dphy_spec_en en; ++ struct dphy_spec_params dphy; ++ struct aphy_spec_params aphy; ++}; ++ ++struct tmds_spec_params { ++ u32 min_tmds_clk; ++ u32 max_tmds_clk; ++ struct spec_params data; ++ struct spec_params clock; ++}; ++ ++static const struct tmds_spec_params g_tmds_spec[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x1e, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x25, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 1.0 inch */ ++static const struct tmds_spec_params g_tmds_spec_1inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xE6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x1c, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x24, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x16, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 1.5 inch */ ++static const struct tmds_spec_params g_tmds_spec_1p5inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x1d, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x24, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x16, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 2.0 inch */ ++static const struct tmds_spec_params g_tmds_spec_2inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x1e, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x25, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 2.5 inch */ ++static const struct tmds_spec_params g_tmds_spec_2p5inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x01, 0x1e, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x25, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 3.0 inch */ ++static const struct tmds_spec_params g_tmds_spec_3inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x1e, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xc7, 0x05, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x25, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 3.5 inch */ ++static const struct tmds_spec_params g_tmds_spec_3p5inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x01, 0x1e, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xc7, 0x05, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x01, 0x26, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 4 inch */ ++static const struct tmds_spec_params g_tmds_spec_4inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x02, 0x1e, 0x02 }, ++ { 0x7f, 0x7e, 0x3e, 0xc7, 0x05, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x02, 0x27, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 4.5 inch */ ++static const struct tmds_spec_params g_tmds_spec_4p5inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x03, 0x1e, 0x03 }, ++ { 0x7f, 0x7e, 0x3e, 0xf7, 0x06, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x03, 0x28, 0x02 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++/* 5 inch */ ++static const struct tmds_spec_params g_tmds_spec_5inch[] = { ++ { 25000, 100000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x13, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 100000, 165000, ++ {{ 0, 1, 0 }, ++ { 0x00, 0x02, 0x15, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, ++ {{ 0, 0, 0 }, ++ { 0x00, 0x00, 0x14, 0x00 }, ++ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} ++ }, ++ { 165000, 340000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x04, 0x1e, 0x05 }, ++ { 0x7f, 0x7e, 0x3e, 0xf7, 0x06, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x00, 0x17, 0x00 }, ++ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} ++ }, ++ { 340000, 600000, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x04, 0x29, 0x05 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, ++ {{ 0, 1, 1 }, ++ { 0x00, 0x05, 0x17, 0x00 }, ++ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} ++ } ++}; ++ ++#define HDMI_EDID_MAX_HDMI14_TMDS_RATE 340000 // in khz ++#define HDMI_EDID_MAX_HDMI20_TMDS_RATE 600000 ++ ++//phy ++typedef enum { ++ PHY_RPRE_50, ++ PHY_RPRE_56, ++ PHY_RPRE_71, ++ PHY_RPRE_83, ++ PHY_RPRE_100, ++ PHY_RPRE_125, ++ PHY_RPRE_250, ++ PHY_RPRE_500, ++ PHY_RPRE_BUTT ++} phy_rpre; ++ ++typedef enum { ++ PHY_RTERM_MODE_SINGLE, ++ PHY_RTERM_MODE_SOURCE, ++ PHY_RTERM_MODE_LOAD, ++ PHY_RTERM_MODE_BUTT ++} phy_rterm_mode; ++ ++typedef enum { ++ HDMI_DEEP_COLOR_24BIT, ++ HDMI_DEEP_COLOR_30BIT, ++ HDMI_DEEP_COLOR_36BIT, ++ HDMI_DEEP_COLOR_48BIT, ++ HDMI_DEEP_COLOR_OFF = 0xff, ++ HDMI_DEEP_COLOR_BUTT ++} hdmi_deep_color; ++ ++typedef enum { ++ HDMI_TRACE_LEN_0, /* 1.0 inch */ ++ HDMI_TRACE_LEN_1, /* 1.5 inch */ ++ HDMI_TRACE_LEN_2, /* 2.0 inch */ ++ HDMI_TRACE_LEN_3, /* 2.5 inch */ ++ HDMI_TRACE_LEN_4, /* 3.0 inch */ ++ HDMI_TRACE_LEN_5, /* 3.5 inch */ ++ HDMI_TRACE_LEN_6, /* 4.0 inch */ ++ HDMI_TRACE_LEN_7, /* 4.5 inch */ ++ HDMI_TRACE_LEN_8, /* 5.0 inch */ ++ HDMI_TRACE_DEFAULT, /* default config */ ++ HDMI_TRACE_BUTT ++} hdmi_trace_len; ++ ++typedef struct { ++ unsigned int ssc_amptd; /* 1/1M ppm(spread rate range) */ ++ unsigned int ssc_freq; /* 1_hz(spread the frequency) */ ++} phy_ssc_cfg; ++ ++typedef struct { ++ bool ssc_enable; ++ bool ssc_debug_en; ++ phy_ssc_cfg ssc_cfg; ++} hdmi_phy_ssc; ++ ++typedef struct { ++ unsigned int pix_clk; /* pixel colck, in k_hz */ ++ unsigned int tmds_clk; /* TMDS colck, in k_hz */ ++ hdmi_deep_color deep_color; /* deep color(color depth) */ ++ hdmi_phy_ssc phy_ssc; /* spread spectrum ctrl(ssc) para */ ++} hdmi_phy_ssc_cfg; ++ ++typedef struct { ++ unsigned int i_main_clk; ++ unsigned int i_main_d0; ++ unsigned int i_main_d1; ++ unsigned int i_main_d2; ++ unsigned int i_pre_clk; ++ unsigned int i_pre_d0; ++ unsigned int i_pre_d1; ++ unsigned int i_pre_d2; ++ phy_rpre r_pre_clk; ++ phy_rpre r_pre_d0; ++ phy_rpre r_pre_d1; ++ phy_rpre r_pre_d2; ++ phy_rterm_mode r_term_mode_clk; ++ unsigned int r_term_clk; ++ phy_rterm_mode r_term_mode_d0; ++ unsigned int r_term_d0; ++ phy_rterm_mode r_term_mode_d1; ++ unsigned int r_term_d1; ++ phy_rterm_mode r_term_mode_d2; ++ unsigned int r_term_d2; ++} phy_hw_spec_cfg; ++ ++typedef struct { ++ bool hw_spec_debug_en; ++ phy_hw_spec_cfg spec_cfg; ++} hdmi_phy_hw_spec; ++ ++typedef struct { ++ unsigned int tmds_clk; /* TMDS colck, in k_hz */ ++ unsigned char frl_dat_rat; /* FRL_DATA_RATA */ ++ hdmi_trace_len trace_len; ++ hdmi_phy_hw_spec hdmi_phy_spec; /* phy specification para */ ++} hdmi_phy_hw_spec_cfg; ++ ++typedef struct { ++ unsigned int pixel_clk; ++ unsigned int tmds_clk; /* TMDS colck, in k_hz */ ++ bool emi_enable; ++ hdmi_deep_color deep_color; /* deep color(color depth) */ ++ hdmi_phy_mode_cfg mode_cfg; /* TMDS/FRL/tx_ffe */ ++ hdmi_trace_len trace_len; ++} hdmi_phy_tmds_cfg; ++ ++ ++typedef struct { ++ unsigned int i_de_main_clk; ++ unsigned int i_de_main_data; ++ unsigned int i_main_clk; ++ unsigned int i_main_data; ++ unsigned int ft_cap_clk; ++ unsigned int ft_cap_data; ++} hdmi_hw_param; ++ ++typedef struct { ++ hdmi_hw_param hw_param[HDMI_HW_PARAM_LEN]; ++} hdmi_hw_spec; ++ ++#define HDMI_TRACE_COUNT 10 ++typedef struct { ++ bool init; ++ bool power_enable; ++ bool oe_enable; ++ hdmi_phy_tmds_cfg tmds_cfg; ++ hdmi_phy_ssc ssc_cfg; ++ phy_hw_spec_cfg hw_spec_cfg; ++ hdmi_hw_spec spec_user[HDMI_TRACE_COUNT]; /* user set crg */ ++ hdmi_hw_spec hw_spec[HDMI_TRACE_COUNT]; /* drv use now = chip def + use set */ ++} hdmi_phy_info; ++ ++typedef struct { ++ hdmi_hw_spec hw_spec_cfg; ++ hdmi_hw_spec hw_spec_def; /* chip default cfg */ ++ hdmi_hw_param hw_param_cur; /* reg cfg now */ ++ hdmi_hw_spec spec_drv_use; /* drv use now */ ++ hdmi_hw_spec spec_user_set; /* user set cfg */ ++} hdmi_phy_hw_param; ++ ++typedef enum { ++ APHY_OFFSET_0, ++ APHY_OFFSET_1, ++ APHY_OFFSET_2, ++ APHY_OFFSET_3, ++ APHY_OFFSET_4, ++ APHY_OFFSET_5, ++ APHY_OFFSET_6, ++ APHY_OFFSET_7, ++ APHY_OFFSET_8, ++ APHY_OFFSET_9, ++ APHY_OFFSET_A, ++ APHY_OFFSET_B, ++ APHY_OFFSET_C, ++ APHY_OFFSET_D, ++ APHY_OFFSET_E, ++ APHY_OFFSET_F, ++ APHY_OFFSET_BUTT ++} aphy_offset_addr; ++ ++typedef struct { ++ unsigned int cs; ++ aphy_offset_addr aphy_offset; ++ unsigned char msb; ++ unsigned char lsb; ++ unsigned int wdata; ++} write_param; ++ ++ ++#define APHY_CS_0 0x1 ++#define APHY_CS_1 0x2 ++#define APHY_CS_2 0x4 ++#define APHY_CS_3 0x8 ++#define APHY_CS_4 0x10 ++#define APHY_CS_012 0x7 ++#define APHY_CS_4567 0xf0 ++#define APHY_CS_8 0x100 ++#define APHY_CS_9 0x200 ++#define TMDS_CLOCK_340M 340000 ++#define PHY_POW_BASE_NUM 2 ++#define PHY_POW_INDEX_NUM 24 ++#define TMDS_CLK_FREQ_MUITIPLE 5 ++#define MOD_N_MULTI_COEFFICIENT 10000 ++#define MOD_D_MULTI_COEFFICIENT 100000 ++#define PHY_HWSPEC_I_16 16 ++#define PHY_HWSPEC_I_8 8 ++#define HDMI_HW_PARAM_NUM 4 ++ ++typedef struct { ++ unsigned int clk_min; ++ unsigned int clk_max; ++} phy_clk_range; ++ ++typedef struct { ++ phy_clk_range clk_range; ++ unsigned char seek_value; ++} phy_clk_range_value; ++ ++static const phy_clk_range_value g_phy_hw_fcd_step_set[] = { ++ {{ 0, 37500 }, 4}, ++ {{ 37500, 75000 }, 3}, ++ {{ 75000, 150000 }, 2}, ++ {{ 150000, 300000 }, 1}, ++ {{ 300000, 600000 }, 0} ++}; ++ ++static const phy_clk_range_value g_phy_hw_def_clk_div[] = { ++ {{ 0, 37500 }, 0}, ++ {{ 37500, 75000 }, 1}, ++ {{ 75000, 150000 }, 2}, ++ {{ 150000, 300000 }, 3}, ++ {{ 300000, 600000 }, 4} ++}; ++typedef struct { ++ phy_clk_range phy_tmds_clk_range; ++ phy_ssc_cfg ssc_cfg; ++} phy_ssc; ++ ++static const phy_clk_range_value g_phy_hw_tmds_divn_sel[] = { ++ {{ 300000, 600000 }, 0}, ++ {{ 150000, 300000 }, 1}, ++ {{ 75000, 150000 }, 2}, ++ {{ 37500, 75000 }, 3}, ++ {{ 25000, 37500 }, 4} ++}; ++ ++typedef struct { ++ unsigned char ref_clk_div; ++ unsigned char vp_divnsel; ++ unsigned char cpzs; ++ unsigned char tmds_divnsel; ++ unsigned char vp_mode; ++ unsigned char fcd_step; ++ hdmi_phy_tmds_cfg tmds_cfg; ++} phy_clk_set; ++ ++typedef struct { ++ unsigned char m_val; ++ unsigned char n_val; ++ unsigned int pll_ref_clk; ++ unsigned int mn_value; ++} phy_mnx; ++ ++ ++static phy_mnx g_mnx_get; ++static hdmi_phy_info g_hdmi_phy_info[HDMI_ID_MAX]; ++ ++#define AEN_TX_FFE_LEN 4 ++#define MAX_FRL_RATE 6 ++#define HDMI_FRL_LANE_MAX_NUM 4 ++#define CEA_VIDEO_CODE_MAX 44 ++#define VESA_VIDEO_CODE_MAX 31 ++#define CEA861_F_VIDEO_CODES_MAX_4K 4 ++#define HDMI_INFO_FRAME_MAX_SIZE 31 ++#define SCDC_TMDS_BIT_CLK_RATIO_10X 10 ++#define SCDC_TMDS_BIT_CLK_RATIO_40X 40 ++#define HDMI_DECIMAL 10 ++#define HDMI_HUNDRED 100 ++#define HDMI_THOUSAND 1000 ++#define FMT_PIX_CLK_13400 13400 ++#define FMT_PIX_CLK_74250 74250 ++#define FMT_PIX_CLK_165000 165000 ++#define FMT_PIX_CLK_190000 190000 ++#define FMT_PIX_CLK_297000 297000 ++#define FMT_PIX_CLK_340000 340000 ++#define ZERO_DRMIF_SEND_TIME 2000 /* unit: ms */ ++#define HDRMODE_CHANGE_TIME 500 /* unit: ms */ ++ ++ ++#define TMDS_DRV_CFG_CH0 0x510 ++#define cfg_hdmi_ffe_sel(x) (((x) & 0x1) << 30) ++#define CFG_HDMI_FFE_SEL_M (0x1 << 30) ++#define cfg_drv_post2_ch0(x) (((x) & 0x3f) << 24) ++#define CFG_DRV_POST2_CH0_M (0x3f << 24) ++#define cfg_drv_post1_ch0(x) (((x) & 0x3f) << 16) ++#define CFG_DRV_POST1_CH0_M (0x3f << 16) ++#define cfg_drv_m_ch0(x) (((x) & 0x3f) << 8) ++#define CFG_DRV_M_CH0_M (0x3f << 8) ++#define cfg_drv_pre_ch0(x) (((x) & 0x3f) << 0) ++#define CFG_DRV_PRE_CH0_M (0x3f << 0) ++ ++#define TMDS_DRV_CFG_CH1 0x514 ++#define cfg_drv_post2_ch1(x) (((x) & 0x3f) << 24) ++#define CFG_DRV_POST2_CH1_M (0x3f << 24) ++#define cfg_drv_post1_ch1(x) (((x) & 0x3f) << 16) ++#define CFG_DRV_POST1_CH1_M (0x3f << 16) ++#define cfg_drv_m_ch1(x) (((x) & 0x3f) << 8) ++#define CFG_DRV_M_CH1_M (0x3f << 8) ++#define cfg_drv_pre_ch1(x) (((x) & 0x3f) << 0) ++#define CFG_DRV_PRE_CH1_M (0x3f << 0) ++ ++#define TMDS_DRV_CFG_CH2 0x518 ++#define cfg_drv_post2_ch2(x) (((x) & 0x3f) << 24) ++#define CFG_DRV_POST2_CH2_M (0x3f << 24) ++#define cfg_drv_post1_ch2(x) (((x) & 0x3f) << 16) ++#define CFG_DRV_POST1_CH2_M (0x3f << 16) ++#define cfg_drv_m_ch2(x) (((x) & 0x3f) << 8) ++#define CFG_DRV_M_CH2_M (0x3f << 8) ++#define cfg_drv_pre_ch2(x) (((x) & 0x3f) << 0) ++#define CFG_DRV_PRE_CH2_M (0x3f << 0) ++ ++#define TMDS_DRV_CFG_CH3 0x51C ++#define cfg_drv_post2_ch3(x) (((x) & 0x3f) << 24) ++#define CFG_DRV_POST2_CH3_M (0x3f << 24) ++#define cfg_drv_post1_ch3(x) (((x) & 0x3f) << 16) ++#define CFG_DRV_POST1_CH3_M (0x3f << 16) ++#define cfg_drv_m_ch3(x) (((x) & 0x3f) << 8) ++#define CFG_DRV_M_CH3_M (0x3f << 8) ++#define cfg_drv_pre_ch3(x) (((x) & 0x3f) << 0) ++#define CFG_DRV_PRE_CH3_M (0x3f << 0) ++ ++#define FFE_EN_CFG 0x67C ++#define cfg_c3_pre_en(x) (((x) & 0x1) << 11) ++#define CFG_C3_PRE_EN_M (1 << 11) ++#define cfg_c3_post1_en(x) (((x) & 0x1) << 10) ++#define CFG_C3_POST1_EN_M (1 << 10) ++#define cfg_c3_post2_en(x) (((x) & 0x1) << 9) ++#define CFG_C3_POST2_EN_M (1 << 9) ++#define cfg_c2_pre_en(x) (((x) & 0x1) << 8) ++#define CFG_C2_PRE_EN_M (1 << 8) ++#define cfg_c2_post1_en(x) (((x) & 0x1) << 7) ++#define CFG_C2_POST1_EN_M (1 << 7) ++#define cfg_c2_post2_en(x) (((x) & 0x1) << 6) ++#define CFG_C2_POST2_EN_M (1 << 6) ++#define cfg_c1_pre_en(x) (((x) & 0x1) << 5) ++#define CFG_C1_PRE_EN_M (1 << 5) ++#define cfg_c1_post1_en(x) (((x) & 0x1) << 4) ++#define CFG_C1_POST1_EN_M (1 << 4) ++#define cfg_c1_post2_en(x) (((x) & 0x1) << 3) ++#define CFG_C1_POST2_EN_M (1 << 3) ++#define cfg_c0_pre_en(x) (((x) & 0x1) << 2) ++#define CFG_C0_PRE_EN_M (1 << 2) ++#define cfg_c0_post1_en(x) (((x) & 0x1) << 1) ++#define CFG_C0_POST1_EN_M (1 << 1) ++#define cfg_c0_post2_en(x) (((x) & 0x1) << 0) ++#define CFG_C0_POST2_EN_M (1 << 0) ++ ++#define HDMI_OE_CFG 0x520 ++#define cfg_oe_sync_en(x) (((x) & 0x1) << 4) ++#define CFG_OE_SYNC_EN_M (1 << 4) ++#define cfg_hdmi_oe_ch3(x) (((x) & 0x1) << 3) ++#define CFG_HDMI_OE_CH3_M (1 << 3) ++#define cfg_hdmi_oe_ch2(x) (((x) & 0x1) << 2) ++#define CFG_HDMI_OE_CH2_M (1 << 2) ++#define cfg_hdmi_oe_ch1(x) (((x) & 0x1) << 1) ++#define CFG_HDMI_OE_CH1_M (1 << 1) ++#define cfg_hdmi_oe_ch0(x) (((x) & 0x1) << 0) ++#define CFG_HDMI_OE_CH0_M (1 << 0) ++ ++typedef enum { ++ HDMI_VIDEO_DITHER_12_10, ++ HDMI_VIDEO_DITHER_12_8, ++ HDMI_VIDEO_DITHER_10_8, ++ HDMI_VIDEO_DITHER_DISALBE ++} hdmi_video_dither; ++#define HDMI_INFOFRAME_BUFFER_SIZE 32 ++ ++ ++#define CTRL_REAET_WAIT_TIME 5 ++#define CTRL_RESET_WAIT 20 ++#define CTRL_BLACK_DATA_YUV_CR 0x200 /* cr val for yuv black */ ++#define CTRL_BLACK_DATA_YUV_Y 0x40 /* y val for yuv black */ ++#define CTRL_BLACK_DATA_YUV_CB 0x200 /* cb val for yuv black */ ++#define CTRL_BLACK_DATA_RGB_R 0x40 /* r val for rgb black */ ++#define CTRL_BLACK_DATA_RGB_G 0x40 /* g val for rgb black */ ++#define CTRL_BLACK_DATA_RGB_B 0x40 /* b val for rgb black */ ++ ++#endif /* __HI3403V100_HDMI_H__ */ ++ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.c b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.c +new file mode 100755 +index 000000000..8d2437446 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.c +@@ -0,0 +1,5306 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "smart_vo.h" ++#include "ot_board.h" ++ ++ ++#define to_vop(x) container_of(x, struct vop, crtc) ++ ++ ++/* ++ * The coefficients of the following matrix are all fixed points. ++ * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. ++ * They are all represented in two's complement. ++ */ ++ ++struct vop { ++ struct drm_crtc crtc; ++ struct device *dev; ++ struct drm_device *drm_dev; ++ bool is_enabled; ++ ++ struct completion dsp_hold_completion; ++ unsigned int win_enabled; ++ ++ /* protected by dev->event_lock */ ++ struct drm_pending_vblank_event *event; ++ ++ struct drm_flip_work fb_unref_work; ++ unsigned long pending; ++ ++ struct completion line_flag_completion; ++ struct drm_plane primary_plane; ++ ++ void __iomem *regs; ++ ++ ++ /* physical map length of vop register */ ++ uint32_t len; ++ ++ /* one time only one process allowed to config the register */ ++ spinlock_t reg_lock; ++ /* lock vop irq reg */ ++ spinlock_t irq_lock; ++ /* protects crtc enable/disable */ ++ struct mutex vop_lock; ++ ++ unsigned int irq; ++ ++ ot_vo_dev vo_dev; ++ ot_vo_csc csc; ++ ++ bool vblank_enabled; ++ phys_addr_t phys_addr; ++ void *virt_addr; ++ ++ struct sg_table *sgt; ++ size_t size; ++}; ++ ++ ++static void vop_crtc_atomic_disable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vop *vop = to_vop(crtc); ++ ++ WARN_ON(vop->event); ++ drm_crtc_vblank_off(crtc); ++ ++ mutex_lock(&vop->vop_lock); ++ vop->is_enabled = false; ++ mutex_unlock(&vop->vop_lock); ++ ++out: ++ if (crtc->state->event && !crtc->state->active) { ++ spin_lock_irq(&crtc->dev->event_lock); ++ drm_crtc_send_vblank_event(crtc, crtc->state->event); ++ spin_unlock_irq(&crtc->dev->event_lock); ++ crtc->state->event = NULL; ++ } ++} ++ ++static void vop_plane_destroy(struct drm_plane *plane) ++{ ++ drm_plane_cleanup(plane); ++} ++ ++static bool smart_mod_supported(struct drm_plane *plane, ++ u32 format, u64 modifier) ++{ ++ int i; ++ /* ++ * We always have to allow these modifiers: ++ * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. ++ * 2. Not passing any modifiers is the same as explicitly passing INVALID. ++ */ ++ if (modifier == DRM_FORMAT_MOD_LINEAR) { ++ return true; ++ } ++ /* Check that the modifier is on the list of the plane's supported modifiers. */ ++ for (i = 0; i < plane->modifier_count; i++) { ++ if (modifier == plane->modifiers[i]) ++ break; ++ } ++ if (i == plane->modifier_count) ++ return false; ++ return true; ++} ++ ++static int vop_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc_state *crtc_state; ++ int ret; ++ ++ if (!plane_state->fb || !plane_state->crtc) ++ return 0; ++ ++ ++ crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc); ++ if (IS_ERR(crtc_state)) ++ return PTR_ERR(crtc_state); ++ ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, ++ DRM_PLANE_NO_SCALING, ++ DRM_PLANE_NO_SCALING, ++ true, true); ++ ++ return ret; ++} ++ ++static void vop_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, ++ plane); ++ if (!old_state->crtc) ++ return; ++ ++} ++/* no ddr reg */ ++void hal_write_reg(unsigned int *address, unsigned int value) ++{ ++ if (address == NULL) { ++ return; ++ } ++ *(volatile unsigned int *)address = value; ++} ++ ++unsigned int hal_read_reg(const unsigned int *address) ++{ ++ if (address == NULL) { ++ return 0; ++ } ++ return *(volatile unsigned int *)(address); ++} ++ ++volatile vdp_regs_type *g_gfbg_reg = NULL; ++ ++static unsigned long fb_vou_get_gfx_abs_addr(hal_disp_layer layer, unsigned long reg) ++{ ++ volatile unsigned long reg_abs_addr; ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: ++ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GRF_REGS_LEN; ++ break; ++ default: ++ printk("Error layer id found in FUNC:%s,LINE:%d\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ ++ return reg_abs_addr; ++} ++ ++unsigned long vou_get_gfx_abs_addr(hal_disp_layer layer, unsigned long reg) ++{ ++ volatile unsigned long reg_abs_addr; ++ switch (layer) { ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GRF_REGS_LEN; ++ break; ++ ++ case HAL_DISP_LAYER_GFX3: ++ reg_abs_addr = reg + 3 * GRF_REGS_LEN; /* 3 lens */ ++ break; ++ ++ default: ++ printk("invalid layer %d!\n", layer); ++ reg_abs_addr = reg; ++ break; ++ } ++ ++ return reg_abs_addr; ++} ++ ++ ++bool fb_hal_graphic_set_gfx_ext(hal_disp_layer layer, hal_gfx_bitextend mode) ++{ ++ volatile u_gfx_out_ctrl gfx_out_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); ++ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_out_ctrl.bits.bitext = mode; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); ++ } else { ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ return true; ++} ++ ++bool fb_hal_graphic_set_gfx_palpha(hal_disp_layer layer, unsigned int alpha_en, unsigned int arange, ++ unsigned char alpha0, unsigned char alpha1) ++{ ++ volatile u_gfx_out_ctrl gfx_out_ctrl; ++ volatile u_gfx_1555_alpha gfx_1555_alpha; ++ volatile unsigned long addr_reg; ++ ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); ++ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_out_ctrl.bits.palpha_en = alpha_en; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); ++ ++ if (alpha_en == true) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); ++ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_1555_alpha.bits.alpha_1 = alpha1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); ++ ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); ++ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_1555_alpha.bits.alpha_0 = alpha0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); ++ } else { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); ++ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_1555_alpha.bits.alpha_1 = 0xff; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); ++ ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); ++ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_1555_alpha.bits.alpha_0 = 0xff; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); ++ } ++ } else { ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ return true; ++} ++/***************************************************************************** ++ Prototype : fb_vou_get_abs_addr ++ Description : Get the absolute address of the layer (video layer and graphics layer) ++*****************************************************************************/ ++static unsigned long fb_vou_get_abs_addr(hal_disp_layer layer, unsigned long reg) ++{ ++ unsigned long reg_abs_addr; ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: ++ reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_VHD0) * VHD_REGS_LEN; ++ break; ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: ++ reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_GFX0) * GFX_REGS_LEN; ++ break; ++ /* one wbc dev */ ++ case HAL_DISP_LAYER_WBC: ++ reg_abs_addr = (reg); ++ break; ++ default: ++ printk("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ return reg_abs_addr; ++} ++ ++unsigned long vou_get_abs_addr(hal_disp_layer layer, unsigned long reg) ++{ ++ volatile unsigned long reg_abs_addr; ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: ++ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_VHD0) * VHD_REGS_LEN; ++ break; ++ ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GFX_REGS_LEN; ++ break; ++ ++ case HAL_DISP_LAYER_GFX3: ++ reg_abs_addr = reg + 3 * GFX_REGS_LEN; /* 3 lens */ ++ break; ++ ++ default: ++ printk("invalid layer %d!\n", layer); ++ reg_abs_addr = reg; ++ break; ++ } ++ ++ return reg_abs_addr; ++} ++ ++/* ++ * Name : hal_layer_set_layer_galpha ++ * Desc : Set video/graphic layer's global alpha ++ */ ++bool fb_hal_layer_set_layer_galpha(hal_disp_layer layer, unsigned char alpha0) ++{ ++ volatile u_v0_ctrl v0_ctrl; ++ volatile u_g0_ctrl g0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->v0_ctrl.u32)); ++ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_ctrl.bits.galpha = alpha0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); ++ break; ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ctrl.u32)); ++ g0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ctrl.bits.galpha = alpha0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ctrl.u32); ++ break; ++ default: ++ printk("Error layer id %d found in %s: L%d\n", layer, __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++static void fb_hal_layer_csc_set_ck_gt_en(hal_disp_layer layer, bool ck_gt_en) ++{ ++ volatile u_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long )(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_ctrl.u32)); ++ g0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_ctrl.bits.ot_pp_csc_ck_gt_en = ck_gt_en; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_ctrl.u32); ++ } ++} ++ ++static void fb_hal_layer_csc_set_enable(hal_disp_layer layer, bool csc_en) ++{ ++ volatile u_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long )(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_ctrl.u32)); ++ g0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_ctrl.bits.ot_pp_csc_en = csc_en; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_ctrl.u32); ++ } ++} ++ ++bool fb_hal_layer_set_csc_en(hal_disp_layer layer, bool csc_en) ++{ ++ if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX4)) { ++ printk("Error, Wrong layer ID!%d\n", __LINE__); ++ return false; ++ } ++ fb_hal_layer_csc_set_ck_gt_en(layer, false); ++ fb_hal_layer_csc_set_enable(layer, csc_en); ++ ++ return true; ++} ++ ++/* for gfx decompress */ ++bool fb_hal_graphic_set_gfx_dcmp_enable(hal_disp_layer layer, unsigned int enable) ++{ ++ volatile u_gfx_src_info gfx_src_info; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_src_info.u32)); ++ ++ gfx_src_info.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_src_info.bits.dcmp_en = enable; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_src_info.u32); ++ } else { ++ printk("Error layer id %d not support dcmp in %s: L%d\n", (int)layer, __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* ++ * Name : fb_hal_layer_set_reg_up ++ * Desc : Set layer(video or graphic) register update. ++ */ ++bool fb_hal_layer_set_reg_up(hal_disp_layer layer) ++{ ++ volatile u_v0_upd v0_upd; ++ volatile u_g0_upd g0_upd; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->v0_upd.u32)); ++ v0_upd.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ /* video layer register update */ ++ v0_upd.bits.regup = 0x1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_upd.u32); ++ break; ++ } ++ ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_upd.u32)); ++ g0_upd.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ /* graphic layer register update */ ++ g0_upd.bits.regup = 0x1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_upd.u32); ++ break; ++ } ++ default: { ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ } ++ return true; ++} ++ ++/* layer stride */ ++bool fb_hal_graphic_set_gfx_stride(hal_disp_layer layer, unsigned short pitch) ++{ ++ volatile u_gfx_stride gfx_stride; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_stride.u32)); ++ gfx_stride.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_stride.bits.surface_stride = pitch; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_stride.u32); ++ } else { ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++bool fb_hal_layer_set_layer_out_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { ++ return true; ++ } else { ++ printk("Error:layer id not found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++} ++ ++bool fb_hal_layer_set_layer_in_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_gfx_ireso gfx_ireso; ++ volatile unsigned long addr_reg; ++ ++ if ((g_gfbg_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_ireso.u32)); ++ gfx_ireso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_ireso.bits.ireso_w = rect->width - 1; ++ gfx_ireso.bits.ireso_h = rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_ireso.u32); ++ } else { ++ printk("Error layer id found in %s, %d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* ++ * Name : fb_hal_set_layer_enable ++ * Desc : Set layer enable ++ */ ++bool fb_hal_set_layer_enable(hal_disp_layer layer, unsigned int enable) ++{ ++ volatile u_v0_ctrl v0_ctrl; ++ volatile u_g0_ctrl g0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->v0_ctrl.u32)); ++ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_ctrl.bits.surface_en = enable; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); ++ break; ++ } ++ ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ctrl.u32)); ++ g0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ctrl.bits.surface_en = enable; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ctrl.u32); ++ break; ++ default: ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* Desc : Set layer data type */ ++bool fb_hal_layer_set_layer_data_fmt(hal_disp_layer layer, hal_disp_pixel_format data_fmt) ++{ ++ volatile u_gfx_src_info gfx_src_info; ++ volatile unsigned long addr_reg; ++ ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_src_info.u32)); ++ gfx_src_info.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_src_info.bits.ifmt = data_fmt; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_src_info.u32); ++ } else { ++ printk("Error layer id%d found in %s: L%d\n", layer, __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++__inline static unsigned int get_low_addr(unsigned long long phys_addr) ++{ ++ return (unsigned int)phys_addr; ++} ++ ++__inline static unsigned int get_high_addr(unsigned long long phys_addr) ++{ ++ return (unsigned int)(phys_addr >> 32); /* 32bit low addr */ ++} ++ ++/* set layer addr */ ++bool fb_hal_graphic_set_gfx_addr(hal_disp_layer layer, phys_addr_t laddr) ++{ ++ volatile unsigned long gfx_addr_h; ++ volatile unsigned long gfx_addr_l; ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ /* Write low address to register. */ ++ gfx_addr_l = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_l)); ++ hal_write_reg((unsigned int *)(uintptr_t)gfx_addr_l, get_low_addr(laddr)); ++ ++ /* Write high address to register. */ ++ gfx_addr_h = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_h)); ++ hal_write_reg((unsigned int *)(uintptr_t)gfx_addr_h, get_high_addr(laddr)); ++ } else { ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ return true; ++} ++ ++bool fb_hal_layer_set_src_resolution(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_gfx_src_reso gfx_src_reso; ++ volatile unsigned long addr_reg; ++ ++ if ((g_gfbg_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_src_reso.u32)); ++ gfx_src_reso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_src_reso.bits.src_w = rect->width - 1; ++ gfx_src_reso.bits.src_h = rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_src_reso.u32); ++ } else { ++ printk("Error:layer id not found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++static unsigned int hal_get_addr_abs(volatile unsigned long *addr_reg, hal_disp_layer layer, const volatile unsigned int *value) ++{ ++ *addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)value); ++ return hal_read_reg((unsigned int *)(uintptr_t)(*addr_reg)); ++} ++ ++static void fb_hal_layer_csc_set_coef(hal_disp_layer layer, const vdp_csc_coef *coef) ++{ ++ volatile u_g0_ot_pp_csc_coef00 g0_ot_pp_csc_coef00; ++ volatile u_g0_ot_pp_csc_coef01 g0_ot_pp_csc_coef01; ++ volatile u_g0_ot_pp_csc_coef02 g0_ot_pp_csc_coef02; ++ volatile u_g0_ot_pp_csc_coef10 g0_ot_pp_csc_coef10; ++ volatile u_g0_ot_pp_csc_coef11 g0_ot_pp_csc_coef11; ++ volatile u_g0_ot_pp_csc_coef12 g0_ot_pp_csc_coef12; ++ volatile u_g0_ot_pp_csc_coef20 g0_ot_pp_csc_coef20; ++ volatile u_g0_ot_pp_csc_coef21 g0_ot_pp_csc_coef21; ++ volatile u_g0_ot_pp_csc_coef22 g0_ot_pp_csc_coef22; ++ volatile unsigned long addr_reg; ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { ++ g0_ot_pp_csc_coef00.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef00.u32)); ++ g0_ot_pp_csc_coef00.bits.ot_pp_csc_coef00 = coef->csc_coef00; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef00.u32); ++ ++ g0_ot_pp_csc_coef01.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef01.u32)); ++ g0_ot_pp_csc_coef01.bits.ot_pp_csc_coef01 = coef->csc_coef01; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef01.u32); ++ ++ g0_ot_pp_csc_coef02.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef02.u32)); ++ g0_ot_pp_csc_coef02.bits.ot_pp_csc_coef02 = coef->csc_coef02; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef02.u32); ++ ++ g0_ot_pp_csc_coef10.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef10.u32)); ++ g0_ot_pp_csc_coef10.bits.ot_pp_csc_coef10 = coef->csc_coef10; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef10.u32); ++ ++ g0_ot_pp_csc_coef11.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef11.u32)); ++ g0_ot_pp_csc_coef11.bits.ot_pp_csc_coef11 = coef->csc_coef11; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef11.u32); ++ ++ g0_ot_pp_csc_coef12.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef12.u32)); ++ g0_ot_pp_csc_coef12.bits.ot_pp_csc_coef12 = coef->csc_coef12; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef12.u32); ++ ++ g0_ot_pp_csc_coef20.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef20.u32)); ++ g0_ot_pp_csc_coef20.bits.ot_pp_csc_coef20 = coef->csc_coef20; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef20.u32); ++ ++ g0_ot_pp_csc_coef21.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef21.u32)); ++ g0_ot_pp_csc_coef21.bits.ot_pp_csc_coef21 = coef->csc_coef21; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef21.u32); ++ ++ g0_ot_pp_csc_coef22.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef22.u32)); ++ g0_ot_pp_csc_coef22.bits.ot_pp_csc_coef22 = coef->csc_coef22; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef22.u32); ++ } else { ++ printk("Error layer id found in %s, %d\n", __FUNCTION__, __LINE__); ++ } ++ return; ++} ++ ++static void fb_hal_layer_csc_set_dc_coef(hal_disp_layer layer, const vdp_csc_dc_coef *csc_dc_coef) ++{ ++ volatile u_g0_ot_pp_csc_idc0 g0_ot_pp_csc_idc0; ++ volatile u_g0_ot_pp_csc_idc1 g0_ot_pp_csc_idc1; ++ volatile u_g0_ot_pp_csc_idc2 g0_ot_pp_csc_idc2; ++ volatile u_g0_ot_pp_csc_odc0 g0_ot_pp_csc_odc0; ++ volatile u_g0_ot_pp_csc_odc1 g0_ot_pp_csc_odc1; ++ volatile u_g0_ot_pp_csc_odc2 g0_ot_pp_csc_odc2; ++ volatile unsigned long addr_reg; ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_idc0.u32)); ++ g0_ot_pp_csc_idc0.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_idc0.bits.ot_pp_csc_idc0 = csc_dc_coef->csc_in_dc0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_idc0.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_idc1.u32)); ++ g0_ot_pp_csc_idc1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_idc1.bits.ot_pp_csc_idc1 = csc_dc_coef->csc_in_dc1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_idc1.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_idc2.u32)); ++ g0_ot_pp_csc_idc2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_idc2.bits.ot_pp_csc_idc2 = csc_dc_coef->csc_in_dc2; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_idc2.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_odc0.u32)); ++ g0_ot_pp_csc_odc0.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_odc0.bits.ot_pp_csc_odc0 = csc_dc_coef->csc_out_dc0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_odc0.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_odc1.u32)); ++ g0_ot_pp_csc_odc1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_odc1.bits.ot_pp_csc_odc1 = csc_dc_coef->csc_out_dc1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_odc1.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_odc2.u32)); ++ g0_ot_pp_csc_odc2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_odc2.bits.ot_pp_csc_odc2 = csc_dc_coef->csc_out_dc2; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_odc2.u32); ++ } else { ++ printk("Error layer id found in %s, %d\n", __FUNCTION__, __LINE__); ++ } ++} ++ ++static void fb_hal_layer_csc_set_param(hal_disp_layer layer, const csc_coef_param *coef_param) ++{ ++ volatile u_g0_ot_pp_csc_scale g0_ot_pp_csc_scale; ++ volatile u_g0_ot_pp_csc_min_y g0_ot_pp_csc_min_y; ++ volatile u_g0_ot_pp_csc_min_c g0_ot_pp_csc_min_c; ++ volatile u_g0_ot_pp_csc_max_y g0_ot_pp_csc_max_y; ++ volatile u_g0_ot_pp_csc_max_c g0_ot_pp_csc_max_c; ++ volatile unsigned long addr_reg; ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_scale.u32)); ++ g0_ot_pp_csc_scale.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_scale.bits.ot_pp_csc_scale = coef_param->csc_scale2p; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_scale.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_min_y.u32)); ++ g0_ot_pp_csc_min_y.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_min_y.bits.ot_pp_csc_min_y = coef_param->csc_clip_min; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_min_y.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_min_c.u32)); ++ g0_ot_pp_csc_min_c.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_min_c.bits.ot_pp_csc_min_c = coef_param->csc_clip_min; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_min_c.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_max_y.u32)); ++ g0_ot_pp_csc_max_y.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_max_y.bits.ot_pp_csc_max_y = coef_param->csc_clip_max; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_max_y.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_max_c.u32)); ++ g0_ot_pp_csc_max_c.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ot_pp_csc_max_c.bits.ot_pp_csc_max_c = coef_param->csc_clip_max; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_max_c.u32); ++ } ++} ++ ++bool fb_hal_layer_set_csc_coef(hal_disp_layer layer, const csc_coef *coef) ++{ ++ if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX4)) { ++ printk("Error, Wrong layer ID!%d\n", __LINE__); ++ return false; ++ } ++ if (coef == NULL) { ++ printk("Error, null pointer\n"); ++ return false; ++ } ++ fb_hal_layer_csc_set_dc_coef(layer, (vdp_csc_dc_coef *)(&coef->csc_in_dc0)); ++ fb_hal_layer_csc_set_coef(layer, (vdp_csc_coef *)(&coef->csc_coef00)); ++ fb_hal_layer_csc_set_param(layer, (csc_coef_param *)(&coef->new_csc_scale2p)); ++ return true; ++} ++ ++//void *drm_gem_object_vmap(struct drm_gem_object *obj); ++const csc_coef g_csc_identity_limit = { ++ /* csc coef */ ++ 1024, 0, 0, 0, 1024, 0, 0, 0, 1024, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_identity_full = { ++ /* csc coef */ ++ 1024, 0, 0, 0, 1024, 0, 0, 0, 1024, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601full_to_yuv601limit = { ++ /* csc coef */ ++ 880, 0, 0, 0, 899, 0, 0, 0, 899, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv709limit_to_yuv601limit = { ++ /* csc coef */ ++ 1024, 102, 196, 0, 1014, -113, 0, -74, 1007, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv709full_to_yuv601limit = { ++ /* csc coef */ ++ 879, 89, 172, 0, 890, -100, 0, -65, 885, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601limit_to_yuv709limit = { ++ /* csc coef */ ++ 1024, -118, -213, 0, 1043, 117, 0, 77, 1050, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601full_to_yuv709limit = { ++ /* csc coef */ ++ 880, -103, -187, 0, 916, 102, 0, 67, 922, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv709full_to_yuv709limit = { ++ /* csc coef */ ++ 880, 0, 0, 0, 899, 0, 0, 0, 899, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601limit_to_yuv601full = { ++ /* csc coef */ ++ 1192, 0, 0, 0, 1165, 0, 0, 0, 1165, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv709limit_to_yuv601full = { ++ /* csc coef */ ++ 1192, 117, 222, 0, 1154, -128, 0, -84, 1146, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv709full_to_yuv601full = { ++ /* csc coef */ ++ 1024, 102, 196, 0, 1014, -113, 0, -74, 1007, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601limit_to_yuv709full = { ++ /* csc coef */ ++ 1192, -137, -248, 0, 1188, 133, 0, 87, 1194, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601full_to_yuv709full = { ++ /* csc coef */ ++ 1024, -118, -213, 0, 1043, 117, 0, 77, 1050, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv709limit_to_yuv709full = { ++ /* csc coef */ ++ 1192, 0, 0, 0, 1165, 0, 0, 0, 1165, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_yuv601limit_to_rgbfull = { ++ /* csc coef */ ++ 1192, 0, 1634, 1192, -400, -833, 1192, 2066, 0, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 0, 0, 0 ++}; ++ ++const csc_coef g_csc_yuv601full_to_rgbfull = { ++ /* csc coef */ ++ 1024, 0, 1436, 1024, -352, -731, 1024, 1815, 0, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 0, 0, 0 ++}; ++ ++const csc_coef g_csc_yuv709limit_to_rgbfull = { ++ /* csc coef */ ++ 1192, 0, 1836, 1192, -218, -547, 1192, 2166, 0, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 0, 0, 0 ++}; ++ ++const csc_coef g_csc_yuv709full_to_rgbfull = { ++ /* csc coef */ ++ 1024, 0, 1613, 1024, -192, -479, 1024, 1900, 0, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 0, 0, 0 ++}; ++ ++const csc_coef g_csc_yuv601limit_to_rgblimit = { ++ /* csc coef */ ++ 1024, 0, 1404, 1024, -344, -716, 1024, 1775, 0, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 16, 16, 16 ++}; ++ ++const csc_coef g_csc_yuv601full_to_rgblimit = { ++ /* csc coef */ ++ 880, 0, 1233, 880, -302, -629, 880, 1599, 0, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 16, 16, 16 ++}; ++ ++const csc_coef g_csc_yuv709limit_to_rgblimit = { ++ /* csc coef */ ++ 1024, 0, 1578, 1024, -187, -470, 1024, 1861, 0, ++ /* csc input dc */ ++ -16, -128, -128, ++ /* csc output dc */ ++ 16, 16, 16 ++}; ++ ++const csc_coef g_csc_yuv709full_to_rgblimit = { ++ /* csc coef */ ++ 880, 0, 1385, 880, -164, -413, 880, 1634, 0, ++ /* csc input dc */ ++ 0, -128, -128, ++ /* csc output dc */ ++ 16, 16, 16 ++}; ++ ++const csc_coef g_csc_rgbfull_to_yuv601limit = { ++ /* csc coef */ ++ 264, 516, 100, -152, -298, 450, 450, -377, -73, ++ /* csc input dc */ ++ 0, 0, 0, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_rgbfull_to_yuv601full = { ++ /* csc coef */ ++ 306, 601, 117, -173, -339, 512, 512, -429, -83, ++ /* csc input dc */ ++ 0, 0, 0, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++const csc_coef g_csc_rgbfull_to_yuv709limit = { ++ /* csc coef */ ++ 188, 629, 63, -103, -347, 450, 450, -409, -41, ++ /* csc input dc */ ++ 0, 0, 0, ++ /* csc output dc */ ++ 16, 128, 128 ++}; ++ ++const csc_coef g_csc_rgbfull_to_yuv709full = { ++ /* csc coef */ ++ 218, 732, 74, -117, -395, 512, 512, -465, -47, ++ /* csc input dc */ ++ 0, 0, 0, ++ /* csc output dc */ ++ 0, 128, 128 ++}; ++ ++/* sin table value, theta angle range[-30, 30], premultiplied by 1000 */ ++const int g_sin_table[61] = { /* 61 theta */ ++ -500, -485, -469, -454, -438, -422, -407, -391, -374, -358, ++ -342, -325, -309, -292, -276, -259, -242, -225, -208, -191, ++ -174, -156, -139, -122, -104, -87, -70, -52, -35, -17, ++ 0, 17, 35, 52, 70, 87, 104, 122, 139, 156, ++ 174, 191, 208, 225, 242, 259, 276, 292, 309, 325, ++ 342, 358, 374, 391, 407, 422, 438, 454, 469, 485, ++ 500 ++}; ++ ++/* cos table value, theta angle range[-30, 30], premultiplied by 1000 */ ++const int g_cos_table[61] = { /* 61 theta */ ++ 866, 875, 883, 891, 899, 906, 914, 921, 927, 934, ++ 940, 946, 951, 956, 961, 966, 970, 974, 978, 982, ++ 985, 988, 990, 993, 995, 996, 998, 999, 999, 1000, ++ 1000, 1000, 999, 999, 998, 996, 995, 993, 990, 988, ++ 985, 982, 978, 974, 970, 966, 961, 956, 951, 946, ++ 940, 934, 927, 921, 914, 906, 899, 891, 883, 875, ++ 866 ++}; ++ ++const csc_coef *g_csc_coef[OT_VO_CSC_MATRIX_BUTT] = { ++ &g_csc_identity_limit, ++ &g_csc_yuv601full_to_yuv601limit, ++ &g_csc_yuv709limit_to_yuv601limit, ++ &g_csc_yuv709full_to_yuv601limit, ++ &g_csc_yuv601limit_to_yuv709limit, ++ &g_csc_yuv601full_to_yuv709limit, ++ &g_csc_identity_limit, ++ &g_csc_yuv709full_to_yuv709limit, ++ &g_csc_yuv601limit_to_yuv601full, ++ &g_csc_identity_full, ++ &g_csc_yuv709limit_to_yuv601full, ++ &g_csc_yuv709full_to_yuv601full, ++ &g_csc_yuv601limit_to_yuv709full, ++ &g_csc_yuv601full_to_yuv709full, ++ &g_csc_yuv709limit_to_yuv709full, ++ &g_csc_identity_full, ++ &g_csc_yuv601limit_to_rgbfull, ++ &g_csc_yuv601full_to_rgbfull, ++ &g_csc_yuv709limit_to_rgbfull, ++ &g_csc_yuv709full_to_rgbfull, ++ &g_csc_yuv601limit_to_rgblimit, ++ &g_csc_yuv601full_to_rgblimit, ++ &g_csc_yuv709limit_to_rgblimit, ++ &g_csc_yuv709full_to_rgblimit, ++ &g_csc_rgbfull_to_yuv601limit, ++ &g_csc_rgbfull_to_yuv601full, ++ &g_csc_rgbfull_to_yuv709limit, ++ &g_csc_rgbfull_to_yuv709full, ++}; ++ ++bool fb_hal_graphic_set_gfx_key_mode(hal_disp_layer layer, unsigned int key_out) ++{ ++ volatile u_gfx_out_ctrl gfx_out_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); ++ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_out_ctrl.bits.key_mode = key_out; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); ++ } else { ++ printk("Error layer id %d not support colorkey mode in %s: L%d\n", ++ (int)layer, __FUNCTION__, __LINE__); ++ return false; ++ } ++ return true; ++} ++ ++bool fb_hal_graphic_set_gfx_key_en(hal_disp_layer layer, unsigned int key_enable) ++{ ++ volatile u_gfx_out_ctrl gfx_out_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); ++ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_out_ctrl.bits.enable = key_enable; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); ++ } else { ++ printk("Error layer id %d not support colorkey in %s: L%d\n", ++ (int)layer, __FUNCTION__, __LINE__); ++ return false; ++ } ++ return true; ++} ++/* ++ * Name : hal_graphic_get_gfx_addr ++ * Desc : get layer addr. ++ */ ++bool fb_hal_graphic_get_gfx_addr(hal_disp_layer layer, phys_addr_t *gfx_addr) ++{ ++ volatile unsigned long addr_reg; ++ volatile phys_addr_t addr_h = 0x0; ++ volatile phys_addr_t addr_l = 0x0; ++ ++ if ((g_gfbg_reg == NULL) || (gfx_addr == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ if (layer == HAL_DISP_LAYER_GFX0 || ++ layer == HAL_DISP_LAYER_GFX1 || ++ layer == HAL_DISP_LAYER_GFX2 || ++ layer == HAL_DISP_LAYER_GFX3 || ++ layer == HAL_DISP_LAYER_GFX4) { ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_l)); ++ addr_l = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_h)); ++ addr_h = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ } else { ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ *gfx_addr = addr_l + ((unsigned long long)addr_h << 32); /* 32 max address */ ++ return true; ++} ++ ++static void graphic_drv_cfg_zme_info(gf_zme_cfg *cfg) ++{ ++ cfg->ck_gt_en = 1; ++ cfg->out_pro = VDP_RMODE_PROGRESSIVE; ++ cfg->lhmid_en = 1; ++ cfg->ahmid_en = 1; ++ cfg->lhfir_mode = 1; ++ cfg->ahfir_mode = 1; ++ cfg->lvmid_en = 1; ++ cfg->avmid_en = 1; ++ cfg->lvfir_mode = 1; ++ cfg->avfir_mode = 1; ++} ++ ++/********************************************************************************** ++* Begin : Graphic layer ZME relative hal functions. ++**********************************************************************************/ ++void hal_g0_zme_set_ck_gt_en(unsigned int ck_gt_en) ++{ ++ volatile u_g0_zme_hinfo g0_zme_hinfo; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32)); ++ g0_zme_hinfo.bits.ck_gt_en = ck_gt_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32), g0_zme_hinfo.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_out_width(unsigned int out_width) ++{ ++ volatile u_g0_zme_hinfo g0_zme_hinfo; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32)); ++ g0_zme_hinfo.bits.out_width = out_width - 1; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32), g0_zme_hinfo.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_hfir_en(unsigned int hfir_en) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.hfir_en = hfir_en; ++ ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_ahfir_mid_en(unsigned int ahfir_mid_en) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.ahfir_mid_en = ahfir_mid_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_lhfir_mid_en(unsigned int lhfir_mid_en) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.lhfir_mid_en = lhfir_mid_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_chfir_mid_en(unsigned int chfir_mid_en) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.chfir_mid_en = chfir_mid_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_lhfir_mode(unsigned int lhfir_mode) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.lhfir_mode = lhfir_mode; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_ahfir_mode(unsigned int ahfir_mode) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.ahfir_mode = ahfir_mode; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_hfir_order(unsigned int hfir_order) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.hfir_order = hfir_order; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_hratio(unsigned int hratio) ++{ ++ volatile u_g0_zme_hsp g0_zme_hsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); ++ g0_zme_hsp.bits.hratio = hratio; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_lhfir_offset(unsigned int lhfir_offset) ++{ ++ volatile u_g0_zme_hloffset g0_zme_hloffset; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hloffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hloffset.u32)); ++ g0_zme_hloffset.bits.lhfir_offset = lhfir_offset; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hloffset.u32), g0_zme_hloffset.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_chfir_offset(unsigned int chfir_offset) ++{ ++ volatile u_g0_zme_hcoffset g0_zme_hcoffset; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_hcoffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hcoffset.u32)); ++ g0_zme_hcoffset.bits.chfir_offset = chfir_offset; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hcoffset.u32), g0_zme_hcoffset.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_out_pro(unsigned int out_pro) ++{ ++ volatile u_g0_zme_vinfo g0_zme_vinfo; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32)); ++ g0_zme_vinfo.bits.out_pro = out_pro; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32), g0_zme_vinfo.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_out_height(unsigned int out_height) ++{ ++ volatile u_g0_zme_vinfo g0_zme_vinfo; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32)); ++ g0_zme_vinfo.bits.out_height = out_height - 1; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32), g0_zme_vinfo.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_vfir_en(unsigned int vfir_en) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.vfir_en = vfir_en; ++ ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_avfir_mid_en(unsigned int avfir_mid_en) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.avfir_mid_en = avfir_mid_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_lvfir_mid_en(unsigned int lvfir_mid_en) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.lvfir_mid_en = lvfir_mid_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_cvfir_mid_en(unsigned int cvfir_mid_en) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.cvfir_mid_en = cvfir_mid_en; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_lvfir_mode(unsigned int lvfir_mode) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.lvfir_mode = lvfir_mode; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_vafir_mode(unsigned int vafir_mode) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.vafir_mode = vafir_mode; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_vratio(unsigned int vratio) ++{ ++ volatile u_g0_zme_vsp g0_zme_vsp; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); ++ g0_zme_vsp.bits.vratio = vratio; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_vtp_offset(unsigned int vtp_offset) ++{ ++ volatile u_g0_zme_voffset g0_zme_voffset; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_voffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32)); ++ g0_zme_voffset.bits.vtp_offset = vtp_offset; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32), g0_zme_voffset.u32); ++ ++ return; ++} ++ ++void hal_g0_zme_set_vbtm_offset(unsigned int vbtm_offset) ++{ ++ volatile u_g0_zme_voffset g0_zme_voffset; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ g0_zme_voffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32)); ++ g0_zme_voffset.bits.vbtm_offset = vbtm_offset; ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32), g0_zme_voffset.u32); ++ ++ return; ++} ++ ++void gf_func_set_g0zme_mode(unsigned int layer, gf_g0_zme_mode g0_zme_mode, const gf_zme_cfg *cfg) ++{ ++ /* filed declare */ ++ const unsigned int hfir_order = 1; ++ int lhfir_offset = 0; ++ int chfir_offset = 0; ++ int vtp_offset = 0; ++ int vbtm_offset = 0; ++ ++ const unsigned long zme_hprec = ZME_HPREC; ++ const unsigned long zme_vprec = ZME_VPREC; ++ unsigned int hratio, vratio; ++ ++ ++ if (cfg == NULL) { ++ return; ++ } ++ hratio = (cfg->in_width * zme_hprec) / cfg->out_width; ++ vratio = (cfg->in_height * zme_vprec) / cfg->out_height; ++ if (g0_zme_mode == VDP_G0_ZME_TYP) { ++ /* typ mode */ ++ lhfir_offset = 0; ++ chfir_offset = 0; ++ vtp_offset = 0; ++ vbtm_offset = (-1) * (long long)zme_vprec / 2; /* 2 alg data */ ++ } ++ /* drv transfer */ ++ hal_g0_zme_set_ck_gt_en(cfg->ck_gt_en); ++ hal_g0_zme_set_out_width(cfg->out_width); ++ hal_g0_zme_set_hfir_en(cfg->hfir_en); ++ hal_g0_zme_set_ahfir_mid_en(cfg->ahmid_en); ++ hal_g0_zme_set_lhfir_mid_en(cfg->lhmid_en); ++ hal_g0_zme_set_chfir_mid_en(cfg->lhmid_en); ++ hal_g0_zme_set_lhfir_mode(cfg->lhfir_mode); ++ hal_g0_zme_set_ahfir_mode(cfg->ahfir_mode); ++ hal_g0_zme_set_hfir_order(hfir_order); ++ hal_g0_zme_set_hratio(hratio); ++ hal_g0_zme_set_lhfir_offset(lhfir_offset); ++ hal_g0_zme_set_chfir_offset(chfir_offset); ++ hal_g0_zme_set_out_pro(cfg->out_pro); ++ hal_g0_zme_set_out_height(cfg->out_height); ++ hal_g0_zme_set_vfir_en(cfg->vfir_en); ++ hal_g0_zme_set_avfir_mid_en(cfg->avmid_en); ++ hal_g0_zme_set_lvfir_mid_en(cfg->lvmid_en); ++ hal_g0_zme_set_cvfir_mid_en(cfg->lvmid_en); ++ hal_g0_zme_set_lvfir_mode(cfg->lvfir_mode); ++ hal_g0_zme_set_vafir_mode(cfg->avfir_mode); ++ hal_g0_zme_set_vratio(vratio); ++ hal_g0_zme_set_vtp_offset(vtp_offset); ++ hal_g0_zme_set_vbtm_offset(vbtm_offset); ++} ++ ++bool fb_hal_video_set_layer_disp_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_g0_dfpos g0_dfpos; ++ volatile u_g0_dlpos g0_dlpos; ++ volatile unsigned long addr_reg; ++ ++ if ((g_gfbg_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_dfpos.u32)); ++ g0_dfpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_dfpos.bits.disp_xfpos = rect->x; ++ g0_dfpos.bits.disp_yfpos = rect->y; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_dfpos.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_dlpos.u32)); ++ g0_dlpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_dlpos.bits.disp_xlpos = rect->x + rect->width - 1; ++ g0_dlpos.bits.disp_ylpos = rect->y + rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_dlpos.u32); ++ break; ++ default: ++ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++bool fb_hal_video_set_layer_video_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_g0_vfpos g0_vfpos; ++ volatile u_g0_vlpos g0_vlpos; ++ volatile unsigned long addr_reg; ++ ++ if ((g_gfbg_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_GFX0: ++ case HAL_DISP_LAYER_GFX1: ++ case HAL_DISP_LAYER_GFX2: ++ case HAL_DISP_LAYER_GFX3: ++ case HAL_DISP_LAYER_GFX4: ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_vfpos.u32)); ++ g0_vfpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_vfpos.bits.video_xfpos = rect->x; ++ g0_vfpos.bits.video_yfpos = rect->y; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_vfpos.u32); ++ ++ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_vlpos.u32)); ++ g0_vlpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_vlpos.bits.video_xlpos = rect->x + rect->width - 1; ++ g0_vlpos.bits.video_ylpos = rect->y + rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_vlpos.u32); ++ break; ++ default: ++ printk("Error layer id %d# found in %s: L%d\n", layer, __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ return true; ++} ++ ++const csc_coef *vo_get_csc_coef(ot_vo_csc_matrix csc_matrix) ++{ ++ if ((csc_matrix >= OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT601LIMIT) && ++ (csc_matrix < OT_VO_CSC_MATRIX_BUTT)) { ++ return g_csc_coef[csc_matrix]; ++ } ++ ++ return NULL; ++} ++ ++int vo_drv_get_csc_matrix(ot_vo_csc_matrix csc_matrix, const csc_coef **csc_tmp) ++{ ++ *csc_tmp = vo_get_csc_coef(csc_matrix); ++ if (*csc_tmp == NULL) { ++ return -1; ++ } ++ return 0; ++} ++ ++static int graphic_drv_calc_csc_matrix(const vo_csc *csc, hal_csc_mode csc_mode, csc_coef *coef) ++{ ++ int luma, contrast, hue, satu; ++ ++ const csc_coef *csc_tmp = NULL; ++ int ret; ++ ++ luma = (int)csc->luma * 64 / 100 - 32; /* 64 100 32 alg data */ ++ contrast = ((int)csc->contrast - 50) * 2 + 100; /* 50 2 100 alg data */ ++ hue = (int)csc->hue * 60 / 100; /* 60 100 alg data */ ++ satu = ((int)csc->satuature - 50) * 2 + 100; /* 50 2 100 alg data */ ++ ++ ret = vo_drv_get_csc_matrix(csc_mode, &csc_tmp); ++ if (ret != 0) { ++ return ret; ++ } ++ coef->csc_in_dc0 = csc_tmp->csc_in_dc0; ++ coef->csc_in_dc1 = csc_tmp->csc_in_dc1; ++ coef->csc_in_dc2 = csc_tmp->csc_in_dc2; ++ coef->csc_out_dc0 = csc_tmp->csc_out_dc0; ++ coef->csc_out_dc1 = csc_tmp->csc_out_dc1; ++ coef->csc_out_dc2 = csc_tmp->csc_out_dc2; ++ /* ++ * C_ratio normally is 0~1.99, C_ratio=s32Contrast/100 ++ * S normally is 0~1.99,S=s32Satu/100 ++ * Hue -30~30, using the lut to get COS and SIN and then /1000 ++ */ ++ coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / 100; /* 100 alg data */ ++ coef->csc_coef01 = (contrast * csc_tmp->csc_coef01) / 100; /* 100 alg data */ ++ coef->csc_coef02 = (contrast * csc_tmp->csc_coef02) / 100; /* 100 alg data */ ++ if (hue >= GFX_MAX_CSC_TABLE) { ++ printk("hue(%u) is invalid!\n", (unsigned int)hue); ++ return -1; ++ } ++ coef->csc_coef10 = (contrast * satu * ((csc_tmp->csc_coef10 * g_cos_table[hue] + ++ csc_tmp->csc_coef20 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ ++ coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * g_cos_table[hue] + ++ csc_tmp->csc_coef21 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ ++ coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef12 * g_cos_table[hue] + ++ csc_tmp->csc_coef22 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ ++ coef->csc_coef20 = (contrast * satu * ((csc_tmp->csc_coef20 * g_cos_table[hue] - ++ csc_tmp->csc_coef10 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ ++ coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * g_cos_table[hue] - ++ csc_tmp->csc_coef11 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ ++ coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef22 * g_cos_table[hue] - ++ csc_tmp->csc_coef12 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ ++ coef->csc_out_dc0 += luma; ++ ++ return 0; ++} ++ ++int fb_graphic_drv_set_csc_coef(hal_disp_layer gfx_layer, const vo_csc *gfx_csc, const csc_coef_param *csc_param) ++{ ++ csc_coef coef; ++ hal_csc_mode csc_mode = gfx_csc->csc_matrix;//HAL_CSC_MODE_BT601FULL_TO_BT601FULL;//HAL_CSC_MODE_BT709FULL_TO_RGBFULL; ++ int ret; ++ const unsigned int dc_pre = 4; ++ unsigned int layer_index; ++ ++ if (gfx_csc == NULL || csc_param == NULL) { ++ return -1; ++ } ++ ++ /* cal CSC coef and CSC dc coef */ ++ ret = graphic_drv_calc_csc_matrix(gfx_csc, csc_mode, &coef); ++ if (ret != 0) { ++ printk("gfx_layer(%u) calculate CSC materix failed!\n", (unsigned int)gfx_layer); ++ return ret; ++ } ++ ++ coef.new_csc_clip_max = GFX_CSC_CLIP_MAX; ++ coef.new_csc_clip_min = GFX_CSC_CLIP_MIN; ++ coef.new_csc_scale2p = GFX_CSC_SCALE; ++ ++ coef.csc_in_dc0 = (int)dc_pre * coef.csc_in_dc0; ++ coef.csc_in_dc1 = (int)dc_pre * coef.csc_in_dc1; ++ coef.csc_in_dc2 = (int)dc_pre * coef.csc_in_dc2; ++ ++ coef.csc_out_dc0 = (int)dc_pre * coef.csc_out_dc0; ++ coef.csc_out_dc1 = (int)dc_pre * coef.csc_out_dc1; ++ coef.csc_out_dc2 = (int)dc_pre * coef.csc_out_dc2; ++ ++ /* set CSC coef and CSC dc coef */ ++ fb_hal_layer_set_csc_coef(gfx_layer, &coef); ++ ++ ++ return 0; ++} ++ ++void fb_hal_set_layer_ck_gt_en(hal_disp_layer layer, unsigned int ck_gt_en) ++{ ++ volatile u_voctrl voctrl; ++ volatile unsigned long addr_reg; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ addr_reg = (unsigned long)(uintptr_t)&(g_gfbg_reg->voctrl.u32); ++ voctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_GFX0: ++ voctrl.bits.g0_ck_gt_en = ck_gt_en; ++ break; ++ case HAL_DISP_LAYER_GFX1: ++ voctrl.bits.g1_ck_gt_en = ck_gt_en; ++ break; ++ case HAL_DISP_LAYER_GFX3: ++ voctrl.bits.g3_ck_gt_en = ck_gt_en; ++ break; ++ default: ++ /* Logic aren't configured for G2. Don't write the configuration to avoid affecting other layers. */ ++ return; ++ } ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, voctrl.u32); ++} ++ ++ ++extern int drm_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map); ++extern void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map); ++bool vo_hal_is_video_layer(hal_disp_layer layer) ++{ ++ if ((layer >= LAYER_VID_START) && (layer <= LAYER_VID_END)) { ++ return true; ++ } ++ ++ return false; ++} ++static volatile reg_vdp_regs *g_vo_reg = NULL; ++ ++volatile reg_vdp_regs *vo_hal_get_reg(void) ++{ ++ return g_vo_reg; ++} ++ ++void hal_video_set_layer_alpha(hal_disp_layer layer, unsigned int alpha) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_alpha v0_alpha; ++ volatile reg_g0_alpha g0_alpha; ++ volatile unsigned long addr_reg; ++ ++ ++ if (vo_hal_is_video_layer(layer)) { ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_alpha.u32)); ++ v0_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_alpha.bits.vbk_alpha = alpha; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_alpha.u32); ++ return; ++ } ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->g0_alpha.u32)); ++ g0_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_alpha.bits.vbk_alpha = alpha; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_alpha.u32); ++} ++ ++void hal_layer_set_layer_global_alpha(hal_disp_layer layer, unsigned char alpha0) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_ctrl v0_ctrl; ++ volatile reg_g0_ctrl g0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ if (vo_hal_is_video_layer(layer)) { ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_ctrl.u32)); ++ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_ctrl.bits.galpha = alpha0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); ++ return; ++ } ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->g0_ctrl.u32)); ++ g0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ g0_ctrl.bits.galpha = alpha0; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ctrl.u32); ++} ++ ++void hal_gfx_set_pixel_alpha_range(hal_disp_layer layer, unsigned int alpha_range) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_gfx_out_ctrl gfx_out_ctrl; ++ volatile unsigned long addr_reg; ++ addr_reg = vou_get_gfx_abs_addr(layer, (uintptr_t)&(vo_reg->gfx_out_ctrl.u32)); ++ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ gfx_out_ctrl.bits.palpha_range = alpha_range; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); ++} ++ ++void hal_video_hfir_set_hfir_mode(hal_disp_layer layer, unsigned int hfir_mode) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfir_ctrl.u32)); ++ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_ctrl.bits.hfir_mode = hfir_mode; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); ++} ++ ++void hal_video_hfir_set_coef(hal_disp_layer layer, const hfir_coef *coef) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_hfircoef01 v0_hfir_coef01; ++ volatile reg_v0_hfircoef23 v0_hfir_coef23; ++ volatile reg_v0_hfircoef45 v0_hfir_coef45; ++ volatile reg_v0_hfircoef67 v0_hfir_coef67; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef01.u32)); ++ v0_hfir_coef01.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_coef01.bits.coef0 = coef->coef0; ++ v0_hfir_coef01.bits.coef1 = coef->coef1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef01.u32); ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef23.u32)); ++ v0_hfir_coef23.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_coef23.bits.coef2 = coef->coef2; ++ v0_hfir_coef23.bits.coef3 = coef->coef3; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef23.u32); ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef45.u32)); ++ v0_hfir_coef45.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_coef45.bits.coef4 = coef->coef4; ++ v0_hfir_coef45.bits.coef5 = coef->coef5; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef45.u32); ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef67.u32)); ++ v0_hfir_coef67.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_coef67.bits.coef6 = coef->coef6; ++ v0_hfir_coef67.bits.coef7 = coef->coef7; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef67.u32); ++} ++ ++void hal_video_hfir_set_mid_en(hal_disp_layer layer, unsigned int mid_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; ++ volatile unsigned long addr_reg; ++ ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfir_ctrl.u32)); ++ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_ctrl.bits.mid_en = mid_en; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); ++} ++ ++unsigned long vou_get_chn_abs_addr(ot_vo_dev dev, unsigned long reg) ++{ ++ volatile unsigned long reg_abs_addr; ++ ++ switch (dev) { ++ case VO_DEV_DHD0: ++ case VO_DEV_DHD1: ++ reg_abs_addr = reg + (dev - VO_DEV_DHD0) * DHD_REGS_LEN; ++ break; ++ ++ default: ++ printk("invalid dev %d!\n", dev); ++ reg_abs_addr = reg; ++ break; ++ } ++ ++ return reg_abs_addr; ++} ++ ++void hal_disp_set_reg_up(ot_vo_dev dev) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_dhd0_ctrl dhd0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); ++ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_ctrl.bits.regup = 0x1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); ++} ++ ++void hal_video_hfir_set_ck_gt_en(hal_disp_layer layer, unsigned int ck_gt_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfir_ctrl.u32)); ++ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_hfir_ctrl.bits.ck_gt_en = ck_gt_en; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); ++} ++ ++void hal_layer_enable_layer(hal_disp_layer layer, unsigned int enable) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_v0_ctrl v0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_ctrl.u32)); ++ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_ctrl.bits.surface_en = enable; ++ v0_ctrl.bits.nosec_flag = 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); ++} ++ ++void hal_video_set_layer_ck_gt_en(hal_disp_layer layer, bool ck_gt_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_voctrl voctrl; ++ /* v3 not support to return */ ++ if (layer > HAL_DISP_LAYER_VHD2) { ++ return; ++ } ++ ++ voctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->voctrl.u32)); ++ if (layer == HAL_DISP_LAYER_VHD0) { ++ voctrl.bits.v0_ck_gt_en = ck_gt_en; ++ } else if (layer == HAL_DISP_LAYER_VHD1) { ++ voctrl.bits.v1_ck_gt_en = ck_gt_en; ++ } else { ++ voctrl.bits.v2_ck_gt_en = ck_gt_en; ++ } ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->voctrl.u32), voctrl.u32); ++} ++ ++unsigned long vou_get_vid_abs_addr(hal_disp_layer layer, unsigned long reg) ++{ ++ volatile unsigned long reg_abs_addr; ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: ++ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_VHD0) * VID_REGS_LEN; ++ break; ++ ++ default: ++ printk("invalid layer %d!\n", layer); ++ reg_abs_addr = reg; ++ break; ++ } ++ ++ return reg_abs_addr; ++} ++ ++void hal_layer_set_layer_data_fmt(hal_disp_layer layer, hal_disp_pixel_format data_fmt) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vid_src_info vid_src_info; ++ volatile unsigned long addr_reg; ++ ++ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(vo_reg->vid_src_info.u32)); ++ vid_src_info.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ vid_src_info.bits.data_type = data_fmt; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, vid_src_info.u32); ++} ++ ++bool hal_layer_set_src_resolution(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_vid_src_reso vid_src_reso; ++ volatile unsigned long addr_reg; ++ ++ if ((g_vo_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->vid_src_reso.u32); ++ vid_src_reso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ vid_src_reso.bits.src_w = rect->width - 1; ++ vid_src_reso.bits.src_h = rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, vid_src_reso.u32); ++ return true; ++} ++ ++bool hal_layer_set_layer_in_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_vid_in_reso vid_in_reso; ++ volatile unsigned long addr_reg; ++ ++ if ((g_vo_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ ++ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->vid_in_reso.u32); ++ vid_in_reso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ vid_in_reso.bits.ireso_w = rect->width - 1; ++ vid_in_reso.bits.ireso_h = rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, vid_in_reso.u32); ++ ++ return true; ++} ++ ++bool hal_video_set_layer_disp_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_v0_dfpos v0_dfpos; ++ volatile u_v0_dlpos v0_dlpos; ++ volatile unsigned long addr_reg; ++ ++ if ((g_vo_reg == NULL) || (rect == NULL)) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->v0_dfpos.u32); ++ v0_dfpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_dfpos.bits.disp_xfpos = rect->x; ++ v0_dfpos.bits.disp_yfpos = rect->y; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_dfpos.u32); ++ ++ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->v0_dlpos.u32); ++ v0_dlpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ v0_dlpos.bits.disp_xlpos = rect->x + rect->width - 1; ++ v0_dlpos.bits.disp_ylpos = rect->y + rect->height - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_dlpos.u32); ++ ++ return true; ++} ++ ++const int *vo_get_sin_table(void) ++{ ++ return g_sin_table; ++} ++ ++const int *vo_get_cos_table(void) ++{ ++ return g_cos_table; ++} ++ ++void vo_drv_calculate_yuv2rgb(const hal_csc_value *csc_value, const csc_coef *csc_tmp, csc_coef *coef) ++{ ++ int luma; ++ int contrast; ++ int hue; ++ int satu; ++ const int csc_value_times = 100; ++ const int table_times = 1000; ++ int square_cv_times = csc_value_times * csc_value_times; ++ const int *cos_table = vo_get_cos_table(); ++ const int *sin_table = vo_get_sin_table(); ++ ++ luma = csc_value->luma; ++ contrast = csc_value->cont; ++ hue = csc_value->hue; ++ satu = csc_value->satu; ++ ++ /* yuv->rgb */ ++ coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / csc_value_times; ++ coef->csc_coef01 = (contrast * satu * ((csc_tmp->csc_coef01 * cos_table[hue] - csc_tmp->csc_coef02 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef02 = (contrast * satu * ((csc_tmp->csc_coef01 * sin_table[hue] + csc_tmp->csc_coef02 * ++ cos_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef10 = (contrast * csc_tmp->csc_coef10) / csc_value_times; ++ coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * cos_table[hue] - csc_tmp->csc_coef12 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef11 * sin_table[hue] + csc_tmp->csc_coef12 * ++ cos_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef20 = (contrast * csc_tmp->csc_coef20) / csc_value_times; ++ coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * cos_table[hue] - csc_tmp->csc_coef22 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef21 * sin_table[hue] + csc_tmp->csc_coef22 * ++ cos_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_in_dc0 += ((contrast != 0) ? (luma * 100 / contrast) : (luma * 100)); /* 100 : trans coef */ ++} ++ ++void vo_drv_calculate_rgb2yuv(const hal_csc_value *csc_value, const csc_coef *csc_tmp, csc_coef *coef) ++{ ++ int luma; ++ int contrast; ++ int hue; ++ int satu; ++ const int csc_value_times = 100; ++ const int table_times = 1000; ++ int square_cv_times = csc_value_times * csc_value_times; ++ const int *cos_table = vo_get_cos_table(); ++ const int *sin_table = vo_get_sin_table(); ++ ++ luma = csc_value->luma; ++ contrast = csc_value->cont; ++ hue = csc_value->hue; ++ satu = csc_value->satu; ++ ++ /* rgb->yuv or yuv->yuv */ ++ coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / csc_value_times; ++ coef->csc_coef01 = (contrast * csc_tmp->csc_coef01) / csc_value_times; ++ coef->csc_coef02 = (contrast * csc_tmp->csc_coef02) / csc_value_times; ++ coef->csc_coef10 = (contrast * satu * ((csc_tmp->csc_coef10 * cos_table[hue] + csc_tmp->csc_coef20 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * cos_table[hue] + csc_tmp->csc_coef21 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef12 * cos_table[hue] + csc_tmp->csc_coef22 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef20 = (contrast * satu * ((csc_tmp->csc_coef20 * cos_table[hue] - csc_tmp->csc_coef10 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * cos_table[hue] - csc_tmp->csc_coef11 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef22 * cos_table[hue] - csc_tmp->csc_coef12 * ++ sin_table[hue]) / table_times)) / square_cv_times; ++ coef->csc_out_dc0 += luma; ++} ++ ++void vou_drv_calc_csc_matrix(const ot_vo_csc *csc, ot_vo_csc_matrix csc_matrix, csc_coef *coef) ++{ ++ int ret; ++ const csc_coef *csc_tmp = NULL; ++ hal_csc_value csc_value; ++ ++ if (csc->ex_csc_en == 0) { ++ csc_value.luma = (int)csc->luma * 64 / 100 - 32; /* 64: -32~32 100: trans coef */ ++ } else { ++ csc_value.luma = (int)csc->luma * 256 / 100 - 128; /* 256: -128~128 128 100 */ ++ } ++ ++ csc_value.cont = ((int)csc->contrast - 50) * 2 + 100; /* 50 2 100 trans coef */ ++ csc_value.hue = (int)csc->hue * 60 / 100; /* 60 100 trans coef */ ++ csc_value.satu = ((int)csc->saturation - 50) * 2 + 100; /* 50 2 100 trans coef */ ++ ++ ret = vo_drv_get_csc_matrix(csc_matrix, &csc_tmp); ++ if (ret != 0) { ++ return; ++ } ++ ++ coef->csc_in_dc0 = csc_tmp->csc_in_dc0; ++ coef->csc_in_dc1 = csc_tmp->csc_in_dc1; ++ coef->csc_in_dc2 = csc_tmp->csc_in_dc2; ++ coef->csc_out_dc0 = csc_tmp->csc_out_dc0; ++ coef->csc_out_dc1 = csc_tmp->csc_out_dc1; ++ coef->csc_out_dc2 = csc_tmp->csc_out_dc2; ++ ++ /* ++ * c_ratio的调节范围一般是0�?1.99, c_ratio=contrast/100 ++ * S的调节范围一般为0~1.99, S=satu/100 ++ * 色调调节参数的范围一般为-30°~30°, 通过查表法求得COS和SIN值并/1000 ++ */ ++ if ((csc_matrix >= OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBFULL) && ++ (csc_matrix <= OT_VO_CSC_MATRIX_BT709FULL_TO_RGBLIMIT)) { ++ vo_drv_calculate_yuv2rgb(&csc_value, csc_tmp, coef); ++ } else { ++ vo_drv_calculate_rgb2yuv(&csc_value, csc_tmp, coef); ++ } ++} ++ ++void vo_drv_csc_trans_to_register(csc_coef *coef) ++{ ++ const int dc_precision = 4; /* 4: reg precision is 10bit coef dc precision, need trans 10-8=2,2^2=4 */ ++ /* csc coef is 1024 precision, no need trans */ ++ coef->csc_in_dc0 = dc_precision * coef->csc_in_dc0; ++ coef->csc_in_dc1 = dc_precision * coef->csc_in_dc1; ++ coef->csc_in_dc2 = dc_precision * coef->csc_in_dc2; ++ ++ coef->csc_out_dc0 = dc_precision * coef->csc_out_dc0; ++ coef->csc_out_dc1 = dc_precision * coef->csc_out_dc1; ++ coef->csc_out_dc2 = dc_precision * coef->csc_out_dc2; ++} ++ ++void vo_hal_intf_set_hdmi_csc_dc_coef(const vdp_csc_dc_coef *csc_dc_coef); ++void vo_hal_intf_set_hdmi_csc_coef(const vdp_csc_coef *coef); ++ ++void vo_hal_intf_set_csc_cfg(ot_vo_intf_type intf, const csc_coef *csc_cfg) ++{ ++ const vdp_csc_dc_coef *csc_dc_coef = (vdp_csc_dc_coef *)(&csc_cfg->csc_in_dc0); ++ const vdp_csc_coef *coef = (vdp_csc_coef *)(&csc_cfg->csc_coef00); ++ ++ switch (intf) { ++ case OT_VO_INTF_HDMI: ++ vo_hal_intf_set_hdmi_csc_dc_coef(csc_dc_coef); ++ vo_hal_intf_set_hdmi_csc_coef(coef); ++ break; ++ default: ++ return; ++ } ++} ++ ++void vou_drv_intf_csc_config(ot_vo_intf_type intf, const ot_vo_csc *csc) ++{ ++ csc_coef coef; ++ (void)memset(&coef, 0x0, sizeof(csc_coef)); ++ vou_drv_calc_csc_matrix(csc, csc->csc_matrix, &coef); ++ vo_drv_csc_trans_to_register(&coef); ++ vo_hal_intf_set_csc_cfg(intf, &coef); ++} ++ ++void hal_disp_set_hdmi_mode(ot_vo_dev dev, unsigned int color_space) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_dhd0_ctrl dhd0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); ++ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_ctrl.bits.hdmi_mode = color_space; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); ++} ++ ++static void vo_drv_set_hdmi_mode(ot_vo_dev dev, const struct vop *hdmi_param) ++{ ++ if ((hdmi_param->csc.csc_matrix >= OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBFULL) && ++ (hdmi_param->csc.csc_matrix <= OT_VO_CSC_MATRIX_BT709FULL_TO_RGBLIMIT)) { ++ hal_disp_set_hdmi_mode(dev, 1); /* 1: RGB */ ++ } else { ++ hal_disp_set_hdmi_mode(dev, 0); /* 0: YUV */ ++ } ++} ++ ++bool hal_overlay_set_gfx_addr(hal_disp_layer layer, phys_addr_t laddr) ++{ ++ volatile unsigned long vid_addr_h; ++ volatile unsigned long vid_addr_l; ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ /* Write low address to register. */ ++ vid_addr_l = (unsigned long)(uintptr_t)&(g_gfbg_reg->vid_addr_l); ++ hal_write_reg((unsigned int *)(uintptr_t)vid_addr_l, get_low_addr(laddr)); ++ ++ /* Write high address to register. */ ++ vid_addr_h = (unsigned long)(uintptr_t)&(g_gfbg_reg->vid_addr_h); ++ hal_write_reg((unsigned int *)(uintptr_t)vid_addr_h, get_high_addr(laddr)); ++ ++ return true; ++} ++ ++bool hal_video_set_multi_area_l_addr(hal_disp_layer layer, unsigned int area_num, unsigned long l_addr, unsigned short stride) ++{ ++ volatile unsigned long vid_addr; ++ volatile unsigned long vid_addr_stride; ++ volatile u_vid_stride vid_stride; /* 0x10270 */ ++ ++ if ((layer == HAL_DISP_LAYER_VHD0) || (layer == HAL_DISP_LAYER_VHD1)) { ++ vid_addr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_addr_l)); ++ hal_write_reg((unsigned int*)(uintptr_t)vid_addr, get_low_addr(l_addr)); ++ ++ vid_addr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_addr_h)); ++ hal_write_reg((unsigned int*)(uintptr_t)vid_addr, get_high_addr(l_addr)); ++ ++ vid_addr_stride = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_stride)); ++ vid_stride.u32 = hal_read_reg((unsigned int*)(uintptr_t)vid_addr_stride); ++ vid_stride.bits.lm_stride = stride; ++ hal_write_reg((unsigned int*)(uintptr_t)vid_addr_stride, vid_stride.u32); ++ } else { ++ return false; ++ } ++ ++ return true; ++} ++ ++bool hal_video_set_multi_area_c_addr(hal_disp_layer layer, unsigned int area_num, unsigned long c_addr, unsigned short stride) ++{ ++ volatile unsigned long vid_caddr; /* 0x10258 */ ++ volatile unsigned long vid_addr_stride; ++ volatile u_vid_stride vid_stride; /* 0x10270 */ ++ ++ ++ ++ if ((layer == HAL_DISP_LAYER_VHD0) || (layer == HAL_DISP_LAYER_VHD1)) { ++ vid_caddr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_caddr_l)); ++ hal_write_reg((unsigned int*)(uintptr_t)vid_caddr, get_low_addr(c_addr)); ++ ++ vid_caddr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_caddr_h)); ++ hal_write_reg((unsigned int*)(uintptr_t)vid_caddr, get_high_addr(c_addr)); ++ ++ vid_addr_stride = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_stride.u32)); ++ vid_stride.u32 = hal_read_reg((unsigned int*)(uintptr_t)vid_addr_stride); ++ vid_stride.bits.chm_stride = stride; ++ hal_write_reg((unsigned int*)(uintptr_t)vid_addr_stride, vid_stride.u32); ++ } else { ++ return false; ++ } ++ ++ return true; ++} ++ ++/* vou zoom enable */ ++bool hal_layer_set_zme_enable(hal_disp_layer layer, ++ hal_disp_zmemode mode, ++ unsigned int enable) ++{ ++ ++ ++ ++ volatile u_v0_zme_hsp v0_zme_hsp; /* 0x1304 */ ++ volatile u_v0_zme_vsp v0_zme_vsp; /* 0x1404 */ ++ volatile u_v1_cvfir_vsp v1_cvfir_vsp; /* 0x2404 */ ++ ++ ++ volatile unsigned long addr_reg; ++ ++ if (layer == HAL_DISP_LAYER_VHD0) { ++ if ((mode == HAL_DISP_ZMEMODE_HORL) || (mode == HAL_DISP_ZMEMODE_HOR) || (mode == HAL_DISP_ZMEMODE_ALL)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_hsp.u32)); ++ v0_zme_hsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_zme_hsp.bits.lhfir_en = enable; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_hsp.u32); ++ } ++ ++ if ((mode == HAL_DISP_ZMEMODE_HORC) || (mode == HAL_DISP_ZMEMODE_HOR) || (mode == HAL_DISP_ZMEMODE_ALL)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_hsp.u32)); ++ v0_zme_hsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_zme_hsp.bits.chfir_en = enable; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_hsp.u32); ++ } ++ ++ if ((mode == HAL_DISP_ZMEMODE_VERL) || (mode == HAL_DISP_ZMEMODE_VER) || (mode == HAL_DISP_ZMEMODE_ALL)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_vsp.u32)); ++ v0_zme_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_zme_vsp.bits.lvfir_en = enable; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_vsp.u32); ++ } ++ ++ if ((mode == HAL_DISP_ZMEMODE_VERC) || (mode == HAL_DISP_ZMEMODE_VER) || (mode == HAL_DISP_ZMEMODE_ALL)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_vsp.u32)); ++ v0_zme_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_zme_vsp.bits.cvfir_en = enable; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_vsp.u32); ++ } ++ } else if (layer == HAL_DISP_LAYER_VHD1) { ++ if ((mode == HAL_DISP_ZMEMODE_VERL) || (mode == HAL_DISP_ZMEMODE_VER) || (mode == HAL_DISP_ZMEMODE_ALL)) { ++ addr_reg = (uintptr_t)&(g_vo_reg->v1_cvfir_vsp.u32); ++ v1_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v1_cvfir_vsp.bits.cvfir_en = enable; ++ v1_cvfir_vsp.bits.cvmid_en = enable; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v1_cvfir_vsp.u32); ++ } ++ } else { ++ return false; ++ } ++ return true; ++} ++ ++bool hal_video_set_layer_video_rect(hal_disp_layer layer, const ot_fb_rect *rect) ++{ ++ volatile u_v0_vfpos v0_vfpos;/* 0x1088 */ ++ volatile u_v0_vlpos v0_vlpos;/* 0x108c */ ++ volatile unsigned long addr_reg; ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: ++ case HAL_DISP_LAYER_VHD2: { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_vfpos.u32)); ++ v0_vfpos.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_vfpos.bits.video_xfpos = rect->x; ++ v0_vfpos.bits.video_yfpos = rect->y; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_vfpos.u32); ++ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_vlpos.u32)); ++ v0_vlpos.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_vlpos.bits.video_xlpos = rect->x + rect->width - 1; ++ v0_vlpos.bits.video_ylpos = rect->y + rect->height - 1; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_vlpos.u32); ++ ++ break; ++ } ++ ++ default: { ++ printk("error layer id,%s,%d\n",__func__,__LINE__); ++ return false; ++ } ++ } ++ ++ return true; ++} ++ ++bool hal_layer_set_zme_info(hal_disp_layer layer, unsigned int width, unsigned int height, ++ hal_disp_zme_outfmt zme_out_fmt) ++{ ++ volatile u_v0_zme_hinfo v0_zme_hinfo; /* 0x1300 */ ++ volatile u_v0_zme_vinfo v0_zme_vinfo; /* 0x1400 */ ++ volatile u_v1_cvfir_vinfo v1_cvfir_vinfo; /* 0x2400 */ ++ ++ volatile unsigned long addr_reg; ++ ++ if (layer == HAL_DISP_LAYER_VHD0) { ++ addr_reg = (uintptr_t)&(g_vo_reg->v0_zme_hinfo.u32); ++ v0_zme_hinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_zme_hinfo.bits.out_width = width - 1; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_hinfo.u32); ++ ++ addr_reg = (uintptr_t)&(g_vo_reg->v0_zme_vinfo.u32); ++ v0_zme_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_zme_vinfo.bits.out_pro = 1; ++ v0_zme_vinfo.bits.out_height = height - 1; ++ v0_zme_vinfo.bits.out_fmt = zme_out_fmt; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_vinfo.u32); ++ } else if (layer == HAL_DISP_LAYER_VHD1) { ++ addr_reg = (uintptr_t)&(g_vo_reg->v1_cvfir_vinfo.u32); ++ v1_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v1_cvfir_vinfo.bits.vzme_ck_gt_en = 1; ++ v1_cvfir_vinfo.bits.out_pro = 1; ++ v1_cvfir_vinfo.bits.out_height = height; ++ v1_cvfir_vinfo.bits.out_fmt = zme_out_fmt; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v1_cvfir_vinfo.u32); ++ } else { ++ return false; ++ } ++ ++ return true; ++} ++ ++void hal_layer_csc_set_enable(hal_disp_layer layer, bool csc_en) ++{ ++ volatile u_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; ++ ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_ot_pp_csc_ctrl.u32)); ++ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_en = csc_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); ++ } else if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->g0_ot_pp_csc_ctrl.u32)); ++ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_en = csc_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); ++ } ++} ++ ++void hal_layer_csc_set_ck_gt_en(hal_disp_layer layer, bool ck_gt_en) ++{ ++ volatile u_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; ++ ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_ot_pp_csc_ctrl.u32)); ++ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_ck_gt_en = ck_gt_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); ++ } else if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->g0_ot_pp_csc_ctrl.u32)); ++ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_ck_gt_en = ck_gt_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); ++ } ++} ++ ++ ++bool hal_layer_set_csc_en(hal_disp_layer layer, bool csc_en) ++{ ++ if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX3)) { ++ printk("error, wrong layer ID,%s,%d\n",__func__,__LINE__); ++ return false; ++ } ++ hal_layer_csc_set_ck_gt_en(layer, csc_en); ++ hal_layer_csc_set_enable(layer, csc_en); ++ return true; ++} ++ ++bool hal_video_set_hfir_mode(hal_disp_layer layer, hal_hfirmode mode) ++{ ++ volatile u_v0_hfir_ctrl v0_hfir_ctrl; ++ volatile u_wd_hpzme_ctrl wd_hpzme_ctrl; ++ volatile u_wd_hcds_ctrl wd_hcds_ctrl; ++ ++ volatile unsigned long addr_reg; ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfir_ctrl.u32)); ++ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_hfir_ctrl.bits.hfir_mode = mode; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); ++ break; ++ } ++ ++ case HAL_DISP_LAYER_WBC: { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->wd_hpzme_ctrl.u32)); ++ wd_hpzme_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ wd_hpzme_ctrl.bits.ck_gt_en = 1; ++ wd_hpzme_ctrl.bits.hfir_mode = mode; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, wd_hpzme_ctrl.u32); ++ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->wd_hcds_ctrl.u32)); ++ wd_hcds_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ wd_hcds_ctrl.bits.ck_gt_en = 1; ++ wd_hcds_ctrl.bits.hfir_en = 1; ++ wd_hcds_ctrl.bits.hfir_mode = 0x0; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, wd_hcds_ctrl.u32); ++ ++ break; ++ } ++ ++ default: { ++ return false; ++ } ++ } ++ ++ return true; ++} ++ ++bool hal_video_set_hfir_coef(hal_disp_layer layer, const int *coef) ++{ ++ volatile u_v0_hfircoef01 v0_hfircoef01; ++ volatile u_v0_hfircoef23 v0_hfircoef23; ++ volatile u_v0_hfircoef45 v0_hfircoef45; ++ volatile u_v0_hfircoef67 v0_hfircoef67; ++ volatile unsigned long addr_reg; ++ ++ switch (layer) { ++ case HAL_DISP_LAYER_VHD0: ++ case HAL_DISP_LAYER_VHD1: { ++ /* the number is to get the value from the coef array */ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef01.u32)); ++ v0_hfircoef01.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_hfircoef01.bits.coef0 = coef[0]; ++ v0_hfircoef01.bits.coef1 = coef[1]; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef01.u32); ++ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef23.u32)); ++ v0_hfircoef23.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_hfircoef23.bits.coef2 = coef[2]; ++ v0_hfircoef23.bits.coef3 = coef[3]; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef23.u32); ++ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef45.u32)); ++ v0_hfircoef45.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_hfircoef45.bits.coef4 = coef[4]; ++ v0_hfircoef45.bits.coef5 = coef[5]; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef45.u32); ++ ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef67.u32)); ++ v0_hfircoef67.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_hfircoef67.bits.coef6 = coef[6]; ++ v0_hfircoef67.bits.coef7 = coef[7]; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef67.u32); ++ break; ++ } ++ ++ default: { ++ return false; ++ } ++ } ++ ++ return true; ++} ++ ++void hal_video_cvfir_set_out_height(hal_disp_layer layer, unsigned int out_height) ++{ ++ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); ++ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vinfo.bits.out_height = out_height - 1; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_out_fmt(hal_disp_layer layer, unsigned int out_fmt) ++{ ++ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); ++ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vinfo.bits.out_fmt = out_fmt; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_out_pro(hal_disp_layer layer, unsigned int out_pro) ++{ ++ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); ++ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vinfo.bits.out_pro = out_pro; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_vzme_ck_gt_en(hal_disp_layer layer, bool vzme_ck_gt_en) ++{ ++ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); ++ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vinfo.bits.vzme_ck_gt_en = vzme_ck_gt_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_cvfir_en(hal_disp_layer layer, unsigned int cvfir_en) ++{ ++ volatile u_v0_cvfir_vsp v0_cvfir_vsp; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); ++ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vsp.bits.cvfir_en = cvfir_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_cvmid_en(hal_disp_layer layer, unsigned int cvmid_en) ++{ ++ volatile u_v0_cvfir_vsp v0_cvfir_vsp; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); ++ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vsp.bits.cvmid_en = cvmid_en; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_cvfir_mode(hal_disp_layer layer, unsigned int cvfir_mode) ++{ ++ volatile u_v0_cvfir_vsp v0_cvfir_vsp; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); ++ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vsp.bits.cvfir_mode = cvfir_mode; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_vratio(hal_disp_layer layer, unsigned int vratio) ++{ ++ volatile u_v0_cvfir_vsp v0_cvfir_vsp; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); ++ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vsp.bits.vratio = vratio; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); ++ } ++ ++ return; ++} ++ ++ ++void hal_video_cvfir_set_v_chroma_offset(hal_disp_layer layer, unsigned int vchroma_offset) ++{ ++ volatile u_v0_cvfir_voffset v0_cvfir_voffset; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_voffset.u32)); ++ v0_cvfir_voffset.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_voffset.bits.vchroma_offset = vchroma_offset; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_voffset.u32); ++ } ++ ++ return; ++} ++ ++void hal_video_cvfir_set_vb_chroma_offset(hal_disp_layer layer, unsigned int vbchroma_offset) ++{ ++ volatile u_v0_cvfir_vboffset v0_cvfir_vboffset; ++ volatile unsigned long addr_reg; ++ ++ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { ++ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vboffset.u32)); ++ v0_cvfir_vboffset.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); ++ v0_cvfir_vboffset.bits.vbchroma_offset = vbchroma_offset; ++ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vboffset.u32); ++ } ++ ++ return; ++} ++ ++void vo_drv_func_get_cvfir_pq_cfg(vo_zme_ds_info *ds_info, vo_zme_mode zme_mode, ++ vo_zme_comm_pq_cfg *comm_pq_cfg) ++{ ++ unsigned int zme_vprec; ++ /* the zme num is from algorithm, not magic num */ ++ if (zme_mode == VO_ZME_TYP) { ++ zme_vprec = ds_info->zme_vprec; ++ comm_pq_cfg->vluma_offset = 0; ++ comm_pq_cfg->vchroma_offset = 0; ++ comm_pq_cfg->vbluma_offset = MIN_OFFSET * (int)zme_vprec / 2; ++ comm_pq_cfg->vbchroma_offset = MIN_OFFSET * (int)zme_vprec / 2; ++ comm_pq_cfg->vl_flatdect_mode = 1; ++ comm_pq_cfg->vl_coringadj_en = 1; ++ comm_pq_cfg->vl_gain = 32; ++ comm_pq_cfg->vl_coring = 16; ++ comm_pq_cfg->vc_flatdect_mode = 1; ++ comm_pq_cfg->vc_coringadj_en = 1; ++ comm_pq_cfg->vc_gain = 32; ++ comm_pq_cfg->vc_coring = 16; ++ comm_pq_cfg->lhfir_offset = 0; ++ comm_pq_cfg->chfir_offset = 0; ++ comm_pq_cfg->hl_flatdect_mode = 1; ++ comm_pq_cfg->hl_coringadj_en = 1; ++ comm_pq_cfg->hl_gain = 32; ++ comm_pq_cfg->hl_coring = 16; ++ comm_pq_cfg->hc_flatdect_mode = 1; ++ comm_pq_cfg->hc_coringadj_en = 1; ++ comm_pq_cfg->hc_gain = 32; ++ comm_pq_cfg->hc_coring = 16; ++ } ++} ++ ++static void vo_drv_set_layer_cvfir_mode(unsigned int layer, vo_zme_mode zme_mode, const vdp_v1_cvfir_cfg *cfg) ++{ ++ unsigned int vzme_ck_gt_en; ++ unsigned int out_pro; ++ unsigned int out_fmt; ++ unsigned int out_height; ++ unsigned int cvfir_en; ++ unsigned int cvmid_en; ++ unsigned int cvfir_mode; ++ unsigned int vratio; ++ unsigned int vchroma_offset; ++ unsigned int vbchroma_offset; ++ vo_zme_ds_info ds_info = {0}; ++ vo_zme_comm_pq_cfg comm_pq_cfg = {0}; ++ ++ ds_info.zme_vprec = ZME_VPREC; ++ ds_info.zme_hprec = ZME_HPREC; ++ ++ vzme_ck_gt_en = cfg->ck_gt_en; ++ cvfir_en = cfg->cvfir_en; ++ cvfir_mode = cfg->cvfir_mode; ++ cvmid_en = cfg->cvmid_en; ++ out_pro = cfg->out_pro; ++ out_fmt = cfg->out_fmt; ++ out_height = (unsigned int)cfg->in_height; ++ vratio = ds_info.zme_vprec; ++ ++ vo_drv_func_get_cvfir_pq_cfg(&ds_info, zme_mode, &comm_pq_cfg); ++ ++ vchroma_offset = comm_pq_cfg.vchroma_offset; ++ vbchroma_offset = comm_pq_cfg.vbchroma_offset; ++ ++ hal_video_cvfir_set_out_height(layer, out_height); ++ hal_video_cvfir_set_out_fmt(layer, out_fmt); ++ hal_video_cvfir_set_out_pro(layer, out_pro); ++ hal_video_cvfir_set_vzme_ck_gt_en(layer, vzme_ck_gt_en); ++ ++ ++ hal_video_cvfir_set_cvfir_en(layer, cvfir_en); ++ hal_video_cvfir_set_cvmid_en(layer, cvmid_en); ++ hal_video_cvfir_set_cvfir_mode(layer, cvfir_mode); ++ hal_video_cvfir_set_vratio(layer, vratio); ++ ++ ++ hal_video_cvfir_set_v_chroma_offset(layer, vchroma_offset); ++ hal_video_cvfir_set_vb_chroma_offset(layer, vbchroma_offset); ++} ++ ++void vo_vid_set_zme_enable(unsigned int layer, const vdp_vid_ip_cfg *vid_cfg) ++{ ++ /* the numbers is from algorithm, not magic numbers */ ++ vdp_v1_cvfir_cfg cvfir_cfg; ++ cvfir_cfg.hfir_order = 0; ++ cvfir_cfg.lhfir_en = 0; ++ cvfir_cfg.chfir_en = 0; ++ cvfir_cfg.lhmid_en = 0; ++ cvfir_cfg.chmid_en = 0; ++ cvfir_cfg.lhfir_mode = 0; ++ cvfir_cfg.chfir_mode = 0; ++ cvfir_cfg.hl_shootctrl_en = 0; ++ cvfir_cfg.hl_shootctrl_mode = 0; ++ cvfir_cfg.hc_shootctrl_en = 0; ++ cvfir_cfg.hc_shootctrl_mode = 0; ++ cvfir_cfg.lvfir_en = 0; ++ cvfir_cfg.lvmid_en = 0; ++ cvfir_cfg.lvfir_mode = 0; ++ cvfir_cfg.vl_shootctrl_en = 0; ++ cvfir_cfg.vl_shootctrl_mode = 0; ++ cvfir_cfg.vc_shootctrl_en = 0; ++ cvfir_cfg.vc_shootctrl_mode = 0; ++ ++ /* CVFIR */ ++ cvfir_cfg.ck_gt_en = 0; ++ cvfir_cfg.cvfir_en = 1; ++ cvfir_cfg.cvmid_en = 0; ++ cvfir_cfg.cvfir_mode = 0; ++ cvfir_cfg.out_pro = VDP_RMODE_PROGRESSIVE; ++ cvfir_cfg.out_fmt = VDP_PROC_FMT_SP_422; ++ cvfir_cfg.in_width = vid_cfg->vid_iw; ++ cvfir_cfg.in_height = vid_cfg->vid_ih; ++ cvfir_cfg.out_width = vid_cfg->vid_ow; ++ cvfir_cfg.out_height = vid_cfg->vid_oh; ++ vo_drv_set_layer_cvfir_mode(layer, VO_ZME_TYP, &cvfir_cfg); ++} ++ ++static void video_layer_set_zme_cfg(unsigned int layer, const ot_fb_rect *disp_rect) ++{ ++ vdp_vid_ip_cfg vid_cfg = {0}; ++ vid_cfg.csc_en = 0; ++ vid_cfg.hfir_en = 1; ++ vid_cfg.vid_iw = disp_rect->width; ++ vid_cfg.vid_ih = disp_rect->height; ++ ++ vid_cfg.vid_ow = disp_rect->width; ++ vid_cfg.vid_oh = disp_rect->height; ++ vid_cfg.zme_en = false; ++ vo_vid_set_zme_enable(layer, &vid_cfg); ++} ++ ++void drm_overlay_update(ot_video_frame_info *p_frame_info) ++{ ++ int i = 0; ++ ot_fb_rect rect = {0}; ++ unsigned short stride = 0; ++ const int as32_hfir_coef[2][8] = { /* 2 8 hfir coef array */ ++ { 0x3f9, 0xc, 0x3ef, 0x19, 0x3da, 0x3a, 0x397, 0x148 }, ++ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a } ++ }; ++ hal_disp_layer disp_layer = HAL_DISP_LAYER_VHD0; ++ ++ rect.x = 0; ++ rect.y = 0; ++ rect.width = p_frame_info->video_frame.width; ++ rect.height = p_frame_info->video_frame.height; ++ stride = p_frame_info->video_frame.stride[0]; ++ hal_layer_set_layer_global_alpha(disp_layer, VO_ALPHA_OPACITY); /* global alpha max 255 */ ++ hal_video_set_layer_alpha(disp_layer, VO_ALPHA_OPACITY); /* alpha max 255 */ ++ //hal_layer_set_layer_data_fmt(disp_layer, HAL_INPUTFMT_YCBCR_SEMIPLANAR_420); ++ hal_layer_set_layer_data_fmt(disp_layer, VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_420); ++ hal_layer_set_csc_en(disp_layer, false); ++ for (i = 0; i <= HAL_DISP_LAYER_VHD1; i++) { ++ hal_video_set_hfir_mode(i, HAL_HFIRMODE_COPY); ++ hal_video_set_hfir_coef(i, as32_hfir_coef[i]); ++ } ++ hal_video_hfir_set_ck_gt_en(disp_layer, true); ++ hal_video_set_layer_disp_rect(disp_layer, &rect); ++ hal_video_set_layer_video_rect(disp_layer, &rect); ++ hal_layer_set_layer_in_rect(disp_layer, &rect); ++ fb_hal_layer_set_layer_galpha(disp_layer, GRAPHIC_ALPHA_OPACITY); ++ hal_layer_set_src_resolution(disp_layer, &rect); ++ ++ video_layer_set_zme_cfg(disp_layer, &rect); ++ ++ hal_layer_set_zme_enable(disp_layer, HAL_DISP_ZMEMODE_ALL, false); ++ hal_layer_set_zme_info(disp_layer, rect.width, rect.height, HAL_DISP_ZME_OUTFMT420); ++ ++ /* area 0 */ ++ hal_video_set_multi_area_l_addr(disp_layer, 0, p_frame_info->video_frame.phys_addr[0], stride); ++ hal_video_set_multi_area_c_addr(disp_layer, 0, p_frame_info->video_frame.phys_addr[1], stride); /* align 16 */ ++ ++ hal_layer_enable_layer(disp_layer, true); ++ hal_disp_set_reg_up(disp_layer); ++ fb_hal_layer_set_reg_up(disp_layer); ++ return; ++} ++ ++static void vop_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc *crtc = new_state->crtc; ++ struct vop *vop = to_vop(new_state->crtc); ++ struct drm_framebuffer *drm_fb = new_state->fb; ++ struct drm_rect *src = &new_state->src; ++ hal_disp_layer disp_layer = HAL_DISP_LAYER_GFX0; ++ ot_fb_rect rect = {0}; ++ size_t size = drm_fb->height * drm_fb->pitches[0]; ++ int ret = 0; ++ gf_zme_cfg cfg = {0}; ++ vo_csc gfx_csc = {0}; ++ csc_coef_param csc_param = {0}; ++ struct drm_gem_object *obj = drm_fb->obj[0]; ++ struct iosys_map map; ++ void *vaddr; ++ ++ rect.x = 0; ++ rect.y = 0; ++ rect.width = drm_fb->width; ++ rect.height = drm_fb->height; ++ ++ ret = drm_gem_vmap(obj, &map); ++ if (ret) { ++ printk("Failed to map GEM object: %d\n", ret); ++ return; ++ } ++ memcpy(vop->virt_addr, map.vaddr, size); ++ drm_gem_vunmap(obj, &map); ++ //gfbg_drv_layer_default_setting ++ spin_lock(&vop->reg_lock); ++ fb_hal_graphic_set_gfx_key_mode(disp_layer, FB_VOU_COLORKEY_IN); ++ fb_hal_graphic_set_gfx_key_en(disp_layer, false); ++ fb_hal_graphic_set_gfx_ext(disp_layer, FB_VOU_BITEXT_LOW_HIGHBITS); ++ fb_hal_graphic_set_gfx_palpha(disp_layer, true, true, 0, GRAPHIC_ALPHA_OPACITY); ++ fb_hal_layer_set_layer_galpha(disp_layer, GRAPHIC_ALPHA_OPACITY); ++ gfx_csc.csc_matrix = OT_VO_CSC_MATRIX_RGBFULL_TO_BT709LIMIT; ++ gfx_csc.luma = VO_CSC_DEF_VAL; ++ gfx_csc.contrast = VO_CSC_DEF_VAL; ++ gfx_csc.hue = VO_CSC_DEF_VAL; ++ gfx_csc.satuature = VO_CSC_DEF_VAL; ++ ++ /* CSC extra coef */ ++ csc_param.csc_scale2p = GFX_CSC_SCALE; ++ csc_param.csc_clip_min = GFX_CSC_CLIP_MIN; ++ csc_param.csc_clip_max = GFX_CSC_CLIP_MAX; ++ fb_graphic_drv_set_csc_coef(disp_layer, &gfx_csc, &csc_param); ++ fb_hal_layer_set_csc_en(disp_layer, true); ++ ++ //gfbg_drv_set_layer_alpha ++ fb_hal_layer_set_layer_data_fmt(disp_layer, HAL_INPUTFMT_ARGB_8888); ++ fb_hal_graphic_set_gfx_dcmp_enable(disp_layer, false); ++ //gfbg_drv_set_layer_rect ++ fb_hal_layer_set_layer_out_rect(disp_layer ,&rect); ++ fb_hal_layer_set_layer_in_rect(disp_layer ,&rect); ++ fb_hal_video_set_layer_disp_rect(disp_layer ,&rect); ++ fb_hal_video_set_layer_video_rect(disp_layer ,&rect); ++ //gfbg_drv_set_layer_src_image_reso ++ fb_hal_layer_set_src_resolution(disp_layer, &rect); ++ //graphic_drv_enable_zme ++ graphic_drv_cfg_zme_info(&cfg); ++ cfg.in_width = drm_fb->width; ++ cfg.in_height = drm_fb->height; ++ cfg.out_width = drm_fb->width; ++ cfg.out_height = drm_fb->height; ++ cfg.hfir_en = 0; ++ cfg.vfir_en = 0; ++ if (disp_layer == HAL_DISP_LAYER_GFX0) { ++ gf_func_set_g0zme_mode(disp_layer, VDP_G0_ZME_TYP, &cfg); ++ } ++ ++ fb_hal_graphic_set_gfx_stride(disp_layer, drm_fb->pitches[0]>>4);//gfbg_drv_set_layer_stride ++ fb_hal_graphic_set_gfx_addr(disp_layer, vop->phys_addr); ++ fb_hal_set_layer_enable(disp_layer, 1);//gfbg_drv_set_layer_enable ++ fb_hal_set_layer_ck_gt_en(disp_layer, 1); ++ fb_hal_graphic_set_gfx_dcmp_enable(disp_layer, false);//gfbg_drv_enable_dcmp ++ fb_hal_layer_set_reg_up(disp_layer); ++ spin_unlock(&vop->reg_lock); ++ ++ ++ /* ++ * can't update plane when vop is disabled. ++ */ ++ if (WARN_ON(!crtc)) ++ return; ++ ++ if (WARN_ON(!vop->is_enabled)) ++ return; ++ ++ if (!new_state->visible) { ++ vop_plane_atomic_disable(plane, state); ++ return; ++ } ++} ++ ++static int vop_plane_atomic_async_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ int min_scale = DRM_PLANE_NO_SCALING; ++ int max_scale = DRM_PLANE_NO_SCALING; ++ struct drm_crtc_state *crtc_state; ++ if (plane != new_plane_state->crtc->cursor) ++ return -EINVAL; ++ ++ if (!plane->state) ++ return -EINVAL; ++ ++ if (!plane->state->fb) ++ return -EINVAL; ++ ++ crtc_state = drm_atomic_get_existing_crtc_state(state, new_plane_state->crtc); ++ ++ /* Special case for asynchronous cursor updates. */ ++ if (!crtc_state) ++ crtc_state = plane->crtc->state; ++ ++ return drm_atomic_helper_check_plane_state(plane->state, crtc_state, ++ min_scale, max_scale, ++ true, true); ++} ++ ++static void vop_plane_atomic_async_update(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct vop *vop = to_vop(plane->state->crtc); ++ struct drm_framebuffer *old_fb = plane->state->fb; ++ ++ plane->state->crtc_x = new_state->crtc_x; ++ plane->state->crtc_y = new_state->crtc_y; ++ plane->state->crtc_h = new_state->crtc_h; ++ plane->state->crtc_w = new_state->crtc_w; ++ plane->state->src_x = new_state->src_x; ++ plane->state->src_y = new_state->src_y; ++ plane->state->src_h = new_state->src_h; ++ plane->state->src_w = new_state->src_w; ++ swap(plane->state->fb, new_state->fb); ++ ++ if (vop->is_enabled) { ++ vop_plane_atomic_update(plane, state); ++ } ++} ++ ++static const struct drm_plane_helper_funcs plane_helper_funcs = { ++ .atomic_check = vop_plane_atomic_check, ++ .atomic_update = vop_plane_atomic_update, ++ .atomic_disable = vop_plane_atomic_disable, ++ .atomic_async_check = vop_plane_atomic_async_check, ++ .atomic_async_update = vop_plane_atomic_async_update, ++}; ++ ++static const struct drm_plane_funcs vop_plane_funcs = { ++ .update_plane = drm_atomic_helper_update_plane, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .destroy = vop_plane_destroy, ++ .reset = drm_atomic_helper_plane_reset, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++ .format_mod_supported = smart_mod_supported, ++}; ++ ++static int vop_crtc_enable_vblank(struct drm_crtc *crtc) ++{ ++ struct vop *vop = to_vop(crtc); ++ unsigned long flags; ++ ++ if (WARN_ON(!vop->is_enabled)) ++ return -EPERM; ++ ++ spin_lock_irqsave(&vop->irq_lock, flags); ++ vop->vblank_enabled = true; ++ spin_unlock_irqrestore(&vop->irq_lock, flags); ++ return 0; ++} ++ ++static void vop_crtc_disable_vblank(struct drm_crtc *crtc) ++{ ++ ++ struct vop *vop = to_vop(crtc); ++ unsigned long flags; ++ ++ if (WARN_ON(!vop->is_enabled)) ++ return; ++ ++ spin_lock_irqsave(&vop->irq_lock, flags); ++ vop->vblank_enabled = false; ++ spin_unlock_irqrestore(&vop->irq_lock, flags); ++} ++ ++static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode) ++{ ++ struct vop *vop = to_vop(crtc); ++ return MODE_OK; ++} ++ ++static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct vop *vop = to_vop(crtc); ++ ++ return true; ++} ++ ++static void vop_crtc_atomic_begin(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vop *vop = to_vop(crtc); ++ ++ ++} ++ ++ ++void vo_hal_set_reg(volatile reg_vdp_regs *reg) ++{ ++ g_vo_reg = reg; ++} ++ ++void vo_hal_intf_set_dac_cablectr(ot_vo_intf_type intf_type, unsigned int cablectr) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vo_dac0_ctrl vo_dac0_ctrl; ++ volatile reg_vo_dac1_ctrl vo_dac1_ctrl; ++ volatile reg_vo_dac2_ctrl vo_dac2_ctrl; ++ volatile reg_vo_dac3_ctrl vo_dac3_ctrl; ++ if (intf_type == OT_VO_INTF_VGA) { ++ vo_dac0_ctrl.u32 = vo_reg->vo_dac0_ctrl.u32; ++ vo_dac1_ctrl.u32 = vo_reg->vo_dac1_ctrl.u32; ++ vo_dac2_ctrl.u32 = vo_reg->vo_dac2_ctrl.u32; ++ vo_dac0_ctrl.bits.cablectr = cablectr; ++ vo_dac1_ctrl.bits.cablectr = cablectr; ++ vo_dac2_ctrl.bits.cablectr = cablectr; ++ vo_reg->vo_dac0_ctrl.u32 = vo_dac0_ctrl.u32; ++ vo_reg->vo_dac1_ctrl.u32 = vo_dac1_ctrl.u32; ++ vo_reg->vo_dac2_ctrl.u32 = vo_dac2_ctrl.u32; ++ } else { /* dac3: CVBS */ ++ vo_dac3_ctrl.u32 = vo_reg->vo_dac3_ctrl.u32; ++ vo_dac3_ctrl.bits.cablectr = cablectr; ++ vo_reg->vo_dac3_ctrl.u32 = vo_dac3_ctrl.u32; ++ } ++} ++ ++static void vo_hal_intf_set_mux_sel_hd(ot_vo_dev dev, ot_vo_intf_type intf) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vo_mux vo_mux; ++ vo_mux.u32 = vo_reg->vo_mux.u32; ++ ++ switch (intf) { ++ case OT_VO_INTF_HDMI: ++ vo_mux.bits.hdmi_sel = dev; ++ break; ++ ++ case OT_VO_INTF_MIPI: ++ case OT_VO_INTF_MIPI_SLAVE: ++ vo_mux.bits.mipi_sel = dev; ++ break; ++ ++ case OT_VO_INTF_CVBS: ++ vo_mux.bits.sddate_sel = dev; ++ break; ++ ++ case OT_VO_INTF_BT1120: ++ vo_mux.bits.digital_sel = 0; ++ vo_mux.bits.bt_sel = dev; ++ break; ++ ++ case OT_VO_INTF_BT656: ++ vo_mux.bits.digital_sel = 0x1; ++ vo_mux.bits.bt_sel = dev; ++ break; ++ ++ case OT_VO_INTF_RGB_6BIT: ++ case OT_VO_INTF_RGB_8BIT: ++ case OT_VO_INTF_RGB_16BIT: ++ case OT_VO_INTF_RGB_18BIT: ++ case OT_VO_INTF_RGB_24BIT: ++ vo_mux.bits.digital_sel = 0x2; ++ vo_mux.bits.lcd_sel = dev; ++ break; ++ ++ default: ++ return; ++ } ++ ++ vo_reg->vo_mux.u32 = vo_mux.u32; ++} ++ ++void vo_hal_intf_set_hdmi_sync_inv(const hal_disp_syncinv *inv) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_intf_hdmi_sync_inv intf_hdmi_sync_inv; ++ ++ intf_hdmi_sync_inv.u32 = vo_reg->intf_hdmi_sync_inv.u32; ++ intf_hdmi_sync_inv.bits.dv_inv = inv->dv_inv; ++ intf_hdmi_sync_inv.bits.hs_inv = inv->hs_inv; ++ intf_hdmi_sync_inv.bits.vs_inv = inv->vs_inv; ++ intf_hdmi_sync_inv.bits.f_inv = inv->f_inv; ++ vo_reg->intf_hdmi_sync_inv.u32 = intf_hdmi_sync_inv.u32; ++} ++ ++void vo_hal_intf_set_sync_info_hvsync(ot_vo_dev dev, ++ const hal_disp_syncinfo *sync_info) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_dhd0_hsync1 dhd0_hsync1; ++ volatile reg_dhd0_hsync2 dhd0_hsync2; ++ volatile reg_dhd0_vsync1 dhd0_vsync1; ++ volatile reg_dhd0_vsync2 dhd0_vsync2; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_hsync1.u32)); ++ dhd0_hsync1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_hsync1.bits.hact = sync_info->hact - 1; ++ dhd0_hsync1.bits.hbb = (sync_info->hbb) - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_hsync1.u32); ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_hsync2.u32)); ++ dhd0_hsync2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_hsync2.bits.hmid = (sync_info->hmid == 0) ? 0 : (sync_info->hmid - 1); ++ dhd0_hsync2.bits.hfb = (sync_info->hfb) - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_hsync2.u32); ++ ++ /* config VHD interface vertical timing */ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_vsync1.u32)); ++ dhd0_vsync1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_vsync1.bits.vact = sync_info->vact - 1; ++ dhd0_vsync1.bits.vbb = sync_info->vbb - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vsync1.u32); ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_vsync2.u32)); ++ dhd0_vsync2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_vsync2.bits.vfb = sync_info->vfb - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vsync2.u32); ++} ++ ++void vo_hal_intf_set_sync_info_other(ot_vo_dev dev, ++ const hal_disp_syncinfo *sync_info) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_dhd0_ctrl dhd0_ctrl; ++ volatile reg_dhd0_vplus1 dhd0_vplus1; ++ volatile reg_dhd0_vplus2 dhd0_vplus2; ++ volatile reg_dhd0_pwr dhd0_pwr; ++ volatile unsigned long addr_reg; ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); ++ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_ctrl.bits.iop = sync_info->iop; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); ++ ++ /* config VHD interface vertical bottom timing, no use in progressive mode */ ++ addr_reg = vou_get_chn_abs_addr(dev, (unsigned long)(uintptr_t)&(vo_reg->dhd0_vplus1.u32)); ++ dhd0_vplus1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_vplus1.bits.bvact = sync_info->bvact - 1; ++ dhd0_vplus1.bits.bvbb = sync_info->bvbb - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vplus1.u32); ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_vplus2.u32)); ++ dhd0_vplus2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_vplus2.bits.bvfb = sync_info->bvfb - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vplus2.u32); ++ ++ /* config VHD interface vertical bottom timing, */ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_pwr.u32)); ++ dhd0_pwr.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_pwr.bits.hpw = sync_info->hpw - 1; ++ dhd0_pwr.bits.vpw = sync_info->vpw - 1; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_pwr.u32); ++} ++ ++hal_disp_syncinfo g_sync_timing[OT_VO_OUT_BUTT] = { ++/* ++ * |--INTFACE---||-----TOP-----||----HORIZON--------||----BOTTOM-----||-PULSE-||-INVERSE-| ++ * syncm,iop, itf, vact, vbb, vfb, hact, hbb, hfb, hmid,bvact,bvbb,bvfb, hpw, vpw,idv, ihs, ivs ++ */ ++ { 0, 0, 0, 288, 22, 2, 720, 132, 12, 1, 288, 23, 2, 126, 3, 0, 0, 0 }, /* 576I(PAL) */ ++ { 0, 0, 0, 240, 18, 4, 720, 119, 19, 1, 240, 19, 4, 124, 3, 0, 0, 0 }, /* 480I(NTSC) */ ++ { 0, 0, 0, 288, 22, 2, 960, 176, 16, 1, 288, 23, 2, 168, 3, 0, 0, 0 }, /* 960H(PAL) */ ++ { 0, 0, 0, 240, 18, 4, 960, 163, 21, 1, 240, 19, 4, 168, 3, 0, 0, 0 }, /* 960H(NTSC) */ ++ ++ { 1, 1, 2, 480, 35, 10, 640, 144, 16, 1, 1, 1, 1, 96, 2, 0, 1, 1 }, /* 640*480@60_hz CVT */ ++ { 1, 1, 1, 480, 36, 9, 720, 122, 16, 1, 1, 1, 1, 62, 6, 0, 0, 0 }, /* 480P@60_hz */ ++ { 1, 1, 1, 576, 44, 5, 720, 132, 12, 1, 1, 1, 1, 64, 5, 0, 0, 0 }, /* 576P@50_hz */ ++ { 1, 1, 2, 600, 27, 1, 800, 216, 40, 1, 1, 1, 1, 128, 4, 0, 0, 0 }, /* 800*600@60_hz VGA@60_hz */ ++ { 1, 1, 2, 768, 35, 3, 1024, 296, 24, 1, 1, 1, 1, 136, 6, 0, 1, 1 }, /* 1024x768@60_hz */ ++ { 0, 1, 1, 720, 25, 5, 1280, 260, 440, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@50_hz */ ++ { 0, 1, 1, 720, 25, 5, 1280, 260, 110, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@60_hz */ ++ { 1, 1, 2, 800, 28, 3, 1280, 328, 72, 1, 1, 1, 1, 128, 6, 0, 1, 0 }, /* 1280*800@60_hz VGA@60_hz */ ++ { 1, 1, 2, 1024, 41, 1, 1280, 360, 48, 1, 1, 1, 1, 112, 3, 0, 0, 0 }, /* 1280x1024@60_hz */ ++ { 1, 1, 2, 768, 27, 3, 1366, 356, 70, 1, 1, 1, 1, 143, 3, 0, 0, 0 }, /* 1366x768@60_hz */ ++ { 1, 1, 2, 1050, 36, 3, 1400, 376, 88, 1, 1, 1, 1, 144, 4, 0, 0, 0 }, /* 1400x1050@60_hz */ ++ { 1, 1, 2, 900, 31, 3, 1440, 384, 80, 1, 1, 1, 1, 152, 6, 0, 1, 0 }, /* 1440x900@60_hz */ ++ { 1, 1, 2, 1050, 36, 3, 1680, 456, 104, 1, 1, 1, 1, 176, 6, 0, 1, 0 }, /* 1680*1050@60_hz */ ++ ++ { 0, 1, 1, 1080, 41, 4, 1920, 192, 638, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@24_hz */ ++ { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@25_hz */ ++ { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@30_hz */ ++ { 0, 0, 1, 540, 20, 2, 1920, 192, 528, 1128, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@50_hz */ ++ { 0, 0, 1, 540, 20, 2, 1920, 192, 88, 908, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@60_hz */ ++ { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@50_hz */ ++ { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@60_hz */ ++ ++ { 1, 1, 2, 1200, 49, 1, 1600, 496, 64, 1, 1, 1, 1, 192, 3, 0, 0, 0 }, /* 1600*1200@60_hz */ ++ { 1, 1, 2, 1200, 32, 3, 1920, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 1920*1200@60_hz CVT (reduced blanking) */ ++ { 0, 1, 1, 2160, 72, 8, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1920*2160@30_hz */ ++ { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@30_hz */ ++ { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@60_hz */ ++ { 0, 1, 2, 1600, 43, 3, 2560, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 2560*1600@60_hz CVT (reduced blanking) */ ++ { 0, 1, 1, 2160, 82, 8, 3840, 384, 1276, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@24_hz */ ++ { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@25_hz */ ++ { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@30_hz */ ++ { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@50_hz */ ++ { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@60_hz */ ++ ++ { 0, 1, 1, 2160, 82, 8, 4096, 384, 1020, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@24 */ ++ { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@25 */ ++ { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@30 */ ++ { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@50 */ ++ { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@60 */ ++ { 0, 1, 1, 4320, 64, 16, 7680, 768, 552, 1, 1, 1, 1, 176, 20, 0, 0, 0 }, /* 7680x4320@30 */ ++ ++ { 0, 1, 1, 320, 10, 4, 240, 30, 10, 1, 1, 1, 1, 10, 2, 0, 0, 0 }, /* 240X320@50 6bit LCD */ ++ { 0, 1, 1, 240, 2, 2, 320, 5, 10, 1, 1, 1, 1, 10, 1, 0, 0, 0 }, /* 320X240@50 6bit LCD */ ++ { 0, 1, 1, 320, 4, 8, 240, 20, 10, 1, 1, 1, 1, 2, 2, 0, 0, 0 }, /* 240X320@60 16bit LCD */ ++ { 0, 1, 1, 240, 15, 9, 320, 65, 7, 1, 240, 14, 9, 1, 1, 0, 0, 0 }, /* 320X240@60 8bit LCD */ ++ { 0, 1, 1, 600, 23, 12, 800, 210, 46, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 800X600@60 24bit LCD */ ++ ++ { 0, 1, 1, 1280, 24, 8, 720, 123, 99, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* for MIPI DSI tx 720 x1280 at 60 hz */ ++ { 0, 1, 1, 1920, 36, 16, 1080, 28, 130, 1, 1, 1, 1, 8, 10, 0, 0, 0 }, /* for MIPI DSI tx 1080 x1920 at 60 hz */ ++ {} /* user sync info by user, empty configuration */ ++}; ++ ++hal_disp_syncinfo *vo_drv_comm_get_sync_timing(ot_vo_intf_sync sync) ++{ ++ return &g_sync_timing[sync]; ++} ++ ++void vo_drv_get_sync_info(ot_vo_dev dev, hal_disp_syncinfo *sync_info) ++{ ++ hal_disp_syncinfo *hal_sync = NULL; ++ ++ /* standard sync info */ ++ hal_sync = vo_drv_comm_get_sync_timing(OT_VO_OUT_1080P60); ++ memcpy(sync_info, hal_sync, sizeof(hal_disp_syncinfo)); ++} ++ ++static void vo_drv_get_sync_inv(ot_vo_dev dev, hal_disp_syncinv *inv) ++{ ++ hal_disp_syncinfo sync_info; ++ ot_vo_intf_type intf_type; ++ ot_vo_intf_sync intf_sync; ++ ++ intf_type = OT_VO_INTF_HDMI;//vo_drv_get_dev_intf_type(dev); ++ intf_sync = OT_VO_OUT_1080P60;//vo_drv_get_dev_intf_sync(dev); ++ ++ vo_drv_get_sync_info(dev, &sync_info); ++ ++ inv->hs_inv = sync_info.ihs ? 1 : 0; ++ inv->vs_inv = sync_info.ivs ? 1 : 0; ++ inv->dv_inv = sync_info.idv ? 1 : 0; ++ ++ if ((OT_VO_INTF_HDMI & intf_type) != 0) { ++ /* vsync/hsync should be 1 for hdmi test */ ++ if ((intf_sync == OT_VO_OUT_576P50) || (intf_sync == OT_VO_OUT_480P60)) { ++ inv->hs_inv = 1 - inv->hs_inv; ++ inv->vs_inv = 1 - inv->vs_inv; ++ } ++ } ++ ++ if ((OT_VO_INTF_BT656 & intf_type) != 0) { ++ inv->hs_inv = 1; ++ } ++ ++ if ((OT_VO_INTF_CVBS & intf_type) != 0) { ++ inv->hs_inv = 1; ++ } ++} ++ ++void vo_hal_intf_set_csc_enable(ot_vo_intf_type intf, bool enable) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_hdmi_csc_idc hdmi_csc_idc; ++ volatile reg_mipi_csc_idc mipi_csc_idc; ++ volatile reg_lcd_csc_idc rgb_csc_idc; ++ ++ switch (intf) { ++ case OT_VO_INTF_HDMI: ++ hdmi_csc_idc.u32 = vo_reg->hdmi_csc_idc.u32; ++ hdmi_csc_idc.bits.csc_en = enable; ++ vo_reg->hdmi_csc_idc.u32 = hdmi_csc_idc.u32; ++ break; ++ ++ case OT_VO_INTF_MIPI: ++ case OT_VO_INTF_MIPI_SLAVE: ++ mipi_csc_idc.u32 = vo_reg->mipi_csc_idc.u32; ++ mipi_csc_idc.bits.csc_en = enable; ++ vo_reg->mipi_csc_idc.u32 = mipi_csc_idc.u32; ++ break; ++ ++ case OT_VO_INTF_RGB_6BIT: ++ case OT_VO_INTF_RGB_8BIT: ++ case OT_VO_INTF_RGB_16BIT: ++ case OT_VO_INTF_RGB_18BIT: ++ case OT_VO_INTF_RGB_24BIT: ++ rgb_csc_idc.u32 = vo_reg->lcd_csc_idc.u32; ++ rgb_csc_idc.bits.csc_en = enable; ++ vo_reg->lcd_csc_idc.u32 = rgb_csc_idc.u32; ++ break; ++ ++ default: ++ return; ++ } ++} ++ ++void vo_hal_intf_set_hdmi_csc_dc_coef(const vdp_csc_dc_coef *csc_dc_coef) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_hdmi_csc_idc hdmi_csc_idc; ++ volatile reg_hdmi_csc_odc hdmi_csc_odc; ++ volatile reg_hdmi_csc_iodc hdmi_csc_iodc; ++ ++ ++ hdmi_csc_idc.u32 = vo_reg->hdmi_csc_idc.u32; ++ hdmi_csc_odc.u32 = vo_reg->hdmi_csc_odc.u32; ++ hdmi_csc_iodc.u32 = vo_reg->hdmi_csc_iodc.u32; ++ ++ /* the configuration is reversed. */ ++ hdmi_csc_idc.bits.cscidc0 = csc_dc_coef->csc_in_dc2; ++ hdmi_csc_idc.bits.cscidc1 = csc_dc_coef->csc_in_dc1; ++ hdmi_csc_iodc.bits.cscidc2 = csc_dc_coef->csc_in_dc0; ++ ++ hdmi_csc_odc.bits.cscodc0 = csc_dc_coef->csc_out_dc2; ++ ++ hdmi_csc_odc.bits.cscodc1 = csc_dc_coef->csc_out_dc1; ++ hdmi_csc_iodc.bits.cscodc2 = csc_dc_coef->csc_out_dc0; ++ ++ vo_reg->hdmi_csc_idc.u32 = hdmi_csc_idc.u32; ++ vo_reg->hdmi_csc_odc.u32 = hdmi_csc_odc.u32; ++ vo_reg->hdmi_csc_iodc.u32 = hdmi_csc_iodc.u32; ++} ++ ++void vo_hal_intf_set_hdmi_csc_coef(const vdp_csc_coef *coef) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_hdmi_csc_p0 hdmi_csc_p0; ++ volatile reg_hdmi_csc_p1 hdmi_csc_p1; ++ volatile reg_hdmi_csc_p2 hdmi_csc_p2; ++ volatile reg_hdmi_csc_p3 hdmi_csc_p3; ++ volatile reg_hdmi_csc_p4 hdmi_csc_p4; ++ ++ hdmi_csc_p0.u32 = vo_reg->hdmi_csc_p0.u32; ++ hdmi_csc_p1.u32 = vo_reg->hdmi_csc_p1.u32; ++ hdmi_csc_p2.u32 = vo_reg->hdmi_csc_p2.u32; ++ hdmi_csc_p3.u32 = vo_reg->hdmi_csc_p3.u32; ++ hdmi_csc_p4.u32 = vo_reg->hdmi_csc_p4.u32; ++ ++ hdmi_csc_p0.bits.cscp00 = coef->csc_coef00; ++ hdmi_csc_p0.bits.cscp01 = coef->csc_coef01; ++ hdmi_csc_p1.bits.cscp02 = coef->csc_coef02; ++ hdmi_csc_p1.bits.cscp10 = coef->csc_coef10; ++ hdmi_csc_p2.bits.cscp11 = coef->csc_coef11; ++ hdmi_csc_p2.bits.cscp12 = coef->csc_coef12; ++ hdmi_csc_p3.bits.cscp20 = coef->csc_coef20; ++ hdmi_csc_p3.bits.cscp21 = coef->csc_coef21; ++ hdmi_csc_p4.bits.cscp22 = coef->csc_coef22; ++ ++ vo_reg->hdmi_csc_p0.u32 = hdmi_csc_p0.u32; ++ vo_reg->hdmi_csc_p1.u32 = hdmi_csc_p1.u32; ++ vo_reg->hdmi_csc_p2.u32 = hdmi_csc_p2.u32; ++ vo_reg->hdmi_csc_p3.u32 = hdmi_csc_p3.u32; ++ vo_reg->hdmi_csc_p4.u32 = hdmi_csc_p4.u32; ++} ++ ++int vo_init(struct vop *vop); ++ ++static void vop_crtc_atomic_enable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ ++ struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, ++ crtc); ++ struct vop *vop = to_vop(crtc); ++ struct smart_crtc_state *s = to_smart_crtc_state(crtc->state); ++ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; ++ u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; ++ u16 hdisplay = adjusted_mode->hdisplay; ++ u16 htotal = adjusted_mode->htotal; ++ u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; ++ u16 hact_end = hact_st + hdisplay; ++ u16 vdisplay = adjusted_mode->vdisplay; ++ u16 vtotal = adjusted_mode->vtotal; ++ u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; ++ u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; ++ u16 vact_end = vact_st + vdisplay; ++ ot_vo_dev dev = vop->vo_dev; ++ ++ hal_disp_syncinfo sync_info; ++ hal_disp_syncinv inv = {0}; ++ uint32_t pin_pol, val; ++ int ret; ++ ++ if (old_state && old_state->self_refresh_active) { ++ drm_crtc_vblank_on(crtc); ++ return; ++ } ++ mutex_lock(&vop->vop_lock); ++ vo_init(vop); ++ WARN_ON(vop->event); ++ vop->is_enabled = true; ++ mutex_unlock(&vop->vop_lock); ++ drm_crtc_vblank_on(crtc); ++} ++ ++static int vop_crtc_atomic_check(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, ++ crtc); ++ struct vop *vop = to_vop(crtc); ++ struct drm_plane *plane; ++ struct drm_plane_state *plane_state; ++ struct smart_crtc_state *s; ++ int afbc_planes = 0; ++ ++ drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { ++ plane_state = ++ drm_atomic_get_plane_state(crtc_state->state, plane); ++ if (IS_ERR(plane_state)) { ++ printk("Cannot get plane state for plane %s\n", ++ plane->name); ++ return PTR_ERR(plane_state); ++ } ++ ++ if (drm_is_afbc(plane_state->fb->modifier)) ++ ++afbc_planes; ++ } ++ ++ ++ return 0; ++} ++ ++static void vop_crtc_atomic_flush(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct drm_pending_vblank_event *event = crtc->state->event; ++ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, ++ crtc); ++ struct drm_atomic_state *old_state = old_crtc_state->state; ++ struct drm_plane_state *old_plane_state, *new_plane_state; ++ struct vop *vop = to_vop(crtc); ++ struct drm_plane *plane; ++ struct smart_crtc_state *s; ++ int i; ++ ++ if (event) { ++ WARN_ON(drm_crtc_vblank_get(crtc) != 0); ++ ++ spin_lock_irq(&crtc->dev->event_lock); ++ drm_crtc_arm_vblank_event(crtc, event); ++ spin_unlock_irq(&crtc->dev->event_lock); ++ crtc->state->event = NULL; ++ } ++ ++ ++ for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, ++ new_plane_state, i) { ++ if (!old_plane_state->fb) ++ continue; ++ ++ if (old_plane_state->fb == new_plane_state->fb) ++ continue; ++ ++ drm_framebuffer_get(old_plane_state->fb); ++ WARN_ON(drm_crtc_vblank_get(crtc) != 0); ++ drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); ++ } ++} ++ ++static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { ++ .mode_valid = vop_crtc_mode_valid, ++ .mode_fixup = vop_crtc_mode_fixup, ++ .atomic_check = vop_crtc_atomic_check, ++ .atomic_begin = vop_crtc_atomic_begin, ++ .atomic_flush = vop_crtc_atomic_flush, ++ .atomic_enable = vop_crtc_atomic_enable, ++ .atomic_disable = vop_crtc_atomic_disable, ++}; ++ ++static void vop_crtc_destroy(struct drm_crtc *crtc) ++{ ++ drm_crtc_cleanup(crtc); ++} ++ ++static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) ++{ ++ struct smart_crtc_state *smart_state; ++ if (WARN_ON(!crtc->state)) ++ return NULL; ++ ++ smart_state = kmemdup(to_smart_crtc_state(crtc->state), ++ sizeof(*smart_state), GFP_KERNEL); ++ if (!smart_state) ++ return NULL; ++ ++ __drm_atomic_helper_crtc_duplicate_state(crtc, &smart_state->base); ++ return &smart_state->base; ++} ++ ++static void vop_crtc_destroy_state(struct drm_crtc *crtc, ++ struct drm_crtc_state *state) ++{ ++ struct smart_crtc_state *s = to_smart_crtc_state(state); ++ __drm_atomic_helper_crtc_destroy_state(&s->base); ++ kfree(s); ++} ++ ++static void vop_crtc_reset(struct drm_crtc *crtc) ++{ ++ struct smart_crtc_state *state; ++ if (crtc->state) { ++ __drm_atomic_helper_crtc_destroy_state(crtc->state); ++ state = to_smart_crtc_state(crtc->state); ++ kfree(state); ++ crtc->state = NULL; ++ } ++ ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (state == NULL) ++ return; ++ ++ __drm_atomic_helper_crtc_reset(crtc, &state->base); ++ state->intf_type = OT_VO_INTF_HDMI; ++ state->intf_sync = OT_VO_OUT_1080P60; ++ state->bg_color = COLOR_RGB_BLUE; ++ state->encoder_type = DRM_MODE_ENCODER_TMDS; ++} ++ ++static int vop_crtc_set_crc_source(struct drm_crtc *crtc, ++ const char *source_name) ++{ ++ ++ return -ENODEV; ++} ++ ++static int ++vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, ++ size_t *values_cnt) ++{ ++ ++ return -ENODEV; ++} ++ ++ ++static const struct drm_crtc_funcs vop_crtc_funcs = { ++ .set_config = drm_atomic_helper_set_config, ++ .page_flip = drm_atomic_helper_page_flip, ++ .destroy = vop_crtc_destroy, ++ .reset = vop_crtc_reset, ++ .atomic_duplicate_state = vop_crtc_duplicate_state, ++ .atomic_destroy_state = vop_crtc_destroy_state, ++ .enable_vblank = vop_crtc_enable_vblank, ++ .disable_vblank = vop_crtc_disable_vblank, ++ .set_crc_source = vop_crtc_set_crc_source, ++ .verify_crc_source = vop_crtc_verify_crc_source, ++}; ++ ++static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) ++{ ++ struct vop *vop = container_of(work, struct vop, fb_unref_work); ++ struct drm_framebuffer *fb = val; ++ drm_crtc_vblank_put(&vop->crtc); ++ drm_framebuffer_put(fb); ++} ++ ++void hal_disp_get_int_state_vblank(ot_vo_dev dev, bool *vblank) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_dhd0_state dhd0_state; ++ volatile unsigned long addr_reg; ++ ++ ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_state.u32)); ++ dhd0_state.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ *vblank = dhd0_state.bits.vblank; ++} ++ ++static const uint32_t formats_win_full[] = { ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_NV12, ++ DRM_FORMAT_YUYV, ++}; ++ ++const size_t formats_win_full_size = ARRAY_SIZE(formats_win_full); ++ ++static const uint32_t formats_win_overlay[] = { ++ DRM_FORMAT_NV12, ++ DRM_FORMAT_YUYV, ++ DRM_FORMAT_YUV420, /* Planar YUV420 */ ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_ABGR8888, ++}; ++ ++const size_t formats_win_overlay_size = ARRAY_SIZE(formats_win_overlay); ++ ++static const uint64_t format_modifiers_win_full[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ DRM_FORMAT_MOD_INVALID, ++}; ++ ++static int vop_create_crtc(struct vop *vop) ++{ ++ struct device *dev = vop->dev; ++ struct drm_device *drm_dev = vop->drm_dev; ++ struct drm_plane *plane, *tmp; ++ struct drm_crtc *crtc = &vop->crtc; ++ struct device_node *port; ++ int ret; ++ int i; ++ ++ /* ++ * Create drm_plane for primary and cursor planes first, since we need ++ * to pass them to drm_crtc_init_with_planes, which sets the ++ * "possible_crtcs" to the newly initialized crtc. ++ */ ++ plane = &vop->primary_plane; ++ ret = drm_universal_plane_init(vop->drm_dev, plane, ++ 1 << drm_crtc_index(crtc), &vop_plane_funcs, ++ formats_win_full, ++ formats_win_full_size, ++ format_modifiers_win_full, ++ DRM_PLANE_TYPE_PRIMARY, NULL); ++ ++ if (ret) { ++ printk("failed to init plane %d\n", ++ ret); ++ goto err_cleanup_planes; ++ } ++ ++ drm_plane_helper_add(plane, &plane_helper_funcs); ++ drm_plane_create_zpos_immutable_property(plane, 0); ++ drm_plane_create_alpha_property(plane); ++ drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, ++ DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | ++ DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y); ++ ++ ++ ++ ++ ret = drm_crtc_init_with_planes(drm_dev, crtc, &vop->primary_plane, NULL, ++ &vop_crtc_funcs, NULL); ++ if (ret) ++ goto err_cleanup_planes; ++ ++ drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); ++ ++ ++ port = of_get_child_by_name(dev->of_node, "port"); ++ if (!port) { ++ DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", ++ dev->of_node); ++ ret = -ENOENT; ++ goto err_cleanup_crtc; ++ } ++ drm_flip_work_init(&vop->fb_unref_work, "fb_unref", ++ vop_fb_unref_worker); ++ ++ crtc->port = port; ++ ++ ret = drm_self_refresh_helper_init(crtc); ++ if (ret) ++ DRM_DEV_DEBUG_KMS(vop->dev, ++ "Failed to init %s with SR helpers %d, ignoring\n", ++ crtc->name, ret); ++ return 0; ++ ++err_cleanup_crtc: ++ drm_crtc_cleanup(crtc); ++ ++err_cleanup_planes: ++ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, ++ head) ++ drm_plane_cleanup(plane); ++ printk("Failed to %s,ret:%d\n",__func__,ret); ++ return ret; ++} ++ ++static void vop_destroy_crtc(struct vop *vop) ++{ ++ struct drm_crtc *crtc = &vop->crtc; ++ struct drm_device *drm_dev = vop->drm_dev; ++ struct drm_plane *plane, *tmp; ++ ++ drm_self_refresh_helper_cleanup(crtc); ++ ++ of_node_put(crtc->port); ++ ++ /* ++ * We need to cleanup the planes now. Why? ++ * ++ * The planes are "&vop->win[i].base". That means the memory is ++ * all part of the big "struct vop" chunk of memory. That memory ++ * was devm allocated and associated with this component. We need to ++ * free it ourselves before vop_unbind() finishes. ++ */ ++ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, ++ head) ++ vop_plane_destroy(plane); ++ ++ /* ++ * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() ++ * references the CRTC. ++ */ ++ drm_crtc_cleanup(crtc); ++ drm_flip_work_cleanup(&vop->fb_unref_work); ++} ++ ++static void *g_reg_crg_base_addr = NULL; ++static void *g_reg_sys_base_addr = NULL; ++static void *g_reg_ddr0_base_addr = NULL; ++static void *g_reg_misc_base_addr = NULL; ++static void *g_reg_crg_pll_addr = NULL; ++static void *g_reg_otp_user_base_addr = NULL; ++ ++#define io_crg_address(x) ((uintptr_t)g_reg_crg_base_addr + ((x) - (CRG_REGS_ADDR) - (CRG_REGS_ADDR_OFFSET))) ++#define io_sys_address(x) ((uintptr_t)g_reg_sys_base_addr + ((x) - (SYS_REGS_ADDR))) ++#define io_ddr0_address(x) ((uintptr_t)g_reg_ddr0_base_addr + ((x) - (DDRC0_REG_ADDR))) ++#define io_misc_address(x) ((uintptr_t)g_reg_misc_base_addr + ((x) - (MISC_REGS_ADDR))) ++#define io_crg_pll_address(x) ((uintptr_t)g_reg_crg_pll_addr + ((x) - (CRG_REGS_ADDR))) ++#define io_otp_user_address(x) ((uintptr_t)g_reg_otp_user_base_addr + ((x) - (OTP_USER_REGS_ADDR))) ++ ++static inline int sys_hal_remap_reg(void **reg_ptr, phys_addr_t phys_addr, unsigned long size) ++{ ++ if (*reg_ptr == NULL) { ++ *reg_ptr = (void *)ioremap(phys_addr, size); ++ if (*reg_ptr == NULL) { ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++void sys_hal_exit(void) ++{ ++ if (g_reg_crg_base_addr != NULL) { ++ iounmap(g_reg_crg_base_addr); ++ g_reg_crg_base_addr = NULL; ++ } ++ ++ if (g_reg_sys_base_addr != NULL) { ++ iounmap(g_reg_sys_base_addr); ++ g_reg_sys_base_addr = NULL; ++ } ++ if (g_reg_ddr0_base_addr != NULL) { ++ iounmap(g_reg_ddr0_base_addr); ++ g_reg_ddr0_base_addr = NULL; ++ } ++ ++ if (g_reg_misc_base_addr != NULL) { ++ iounmap(g_reg_misc_base_addr); ++ g_reg_misc_base_addr = NULL; ++ } ++ ++ ++ if (g_reg_crg_pll_addr != NULL) { ++ iounmap((void *)g_reg_crg_pll_addr); ++ g_reg_crg_pll_addr = NULL; ++ } ++ ++ if (g_reg_otp_user_base_addr != NULL) { ++ iounmap(g_reg_otp_user_base_addr); ++ g_reg_otp_user_base_addr = NULL; ++ } ++ ++} ++ ++int sys_hal_init(void) ++{ ++ ++ if (sys_hal_remap_reg(&g_reg_crg_base_addr, CRG_REGS_ADDR + CRG_REGS_ADDR_OFFSET, CRG_REGS_SIZE) != 0) { ++ printk("remap crg reg fail, line: %d.\n", __LINE__); ++ goto sys_hal_fail; ++ } ++ ++ if (sys_hal_remap_reg(&g_reg_crg_pll_addr, CRG_REGS_ADDR, CRG_REGS_ADDR_OFFSET) != 0) { ++ printk("remap crg pll reg fail, line: %d.\n", __LINE__); ++ goto sys_hal_fail; ++ } ++ ++ if (sys_hal_remap_reg(&g_reg_sys_base_addr, SYS_REGS_ADDR, SYS_REGS_SIZE) != 0) { ++ printk("remap sys reg fail, line: %d.\n", __LINE__); ++ goto sys_hal_fail; ++ } ++ ++ if (sys_hal_remap_reg(&g_reg_ddr0_base_addr, DDRC0_REG_ADDR, DDRC_REGS_SIZE) != 0) { ++ printk("remap ddr0 reg fail, line: %d.\n", __LINE__); ++ goto sys_hal_fail; ++ } ++ ++ if (sys_hal_remap_reg(&g_reg_misc_base_addr, MISC_REGS_ADDR, MISC_REGS_SIZE) != 0) { ++ printk("remap MISC reg fail, line: %d.\n", __LINE__); ++ goto sys_hal_fail; ++ } ++ if (sys_hal_remap_reg(&g_reg_otp_user_base_addr, OTP_USER_REGS_ADDR, OTP_USER_REGS_SIZE) != 0) { ++ goto sys_hal_fail; ++ } ++ ++ return 0; ++ ++sys_hal_fail: ++ sys_hal_exit(); ++ return -1; ++} ++ ++static void ot_reg_set_bit(unsigned long value, unsigned long offset, unsigned long addr) ++{ ++ unsigned long t, mask; ++ unsigned long ul_flags; ++ ++ mask = 1 << offset; ++ t = readl((const volatile void *)(uintptr_t)addr); ++ t &= ~mask; ++ t |= (value << offset) & mask; ++ writel(t, (volatile void *)(uintptr_t)addr); ++} ++ ++int sys_hal_vo_bus_reset_sel(bool reset) ++{ ++ const unsigned int tmp = (reset == 1) ? 1 : 0; ++ const unsigned int bit = 0; /* 0: 0bit */ ++ ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8336_ADDR)); ++ return 0; ++} ++ ++void vo_lpw_bus_reset(bool reset) ++{ ++ sys_hal_vo_bus_reset_sel(reset); ++} ++ ++static void vo_init_set_sys_clk(void) ++{ ++ /* 撤销复位 */ ++ vo_lpw_bus_reset(0); ++} ++ ++int sys_hal_vo_cfg_clk_en(bool clk_en) ++{ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ const unsigned int bit = 6; /* 6: 6bit */ ++ ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8340_ADDR)); ++ ++ return 0; ++} ++ ++int sys_hal_vo_apb_clk_en(bool clk_en) ++{ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ const unsigned int bit = 8; /* 8: 8bit */ ++ ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8336_ADDR)); ++ ++ return 0; ++} ++ ++/* VO AXI BUS CLK */ ++int sys_hal_vo_bus_clk_en(bool clk_en) ++{ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ const unsigned int bit = 9; /* 9: 9bit */ ++ ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8336_ADDR)); ++ return 0; ++} ++ ++/* PPC */ ++int sys_hal_vo_core_clk_en(int dev, bool clk_en) ++{ ++ const unsigned int bit = 5; /* 5: 5bit */ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ unsigned long rval = 0; ++ ++ if ((dev == 0) || (dev == 1)) { ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8340_ADDR)); ++ return 0; ++ } ++ return -1; ++} ++ ++/* VO SD DATE */ ++int sys_hal_vo_sd_date_clk_en(int vo_dev, bool clk_en) ++{ ++ const unsigned int bit = 4; /* 4: 4bit */ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ ++ if (vo_dev != 1) { ++ return -1; ++ } ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8342_ADDR)); ++ return 0; ++} ++ ++void vo_drv_set_all_crg_clk(int vo_dev,bool clk_en) ++{ ++ sys_hal_vo_cfg_clk_en(clk_en); ++ sys_hal_vo_apb_clk_en(clk_en); ++ sys_hal_vo_bus_clk_en(clk_en); ++ sys_hal_vo_core_clk_en(vo_dev, clk_en); ++ ++ /* need open sd date crg */ ++ sys_hal_vo_sd_date_clk_en(vo_dev, clk_en); ++} ++ ++ ++static void vo_init_crg_clk(int vo_dev) ++{ ++ vo_drv_set_all_crg_clk(vo_dev,1); ++} ++ ++int sys_hal_vo_hdmi_clk_en(int vo_dev, bool hdmi_clk_en) ++{ ++ const unsigned int bit_pixel = 4; /* 4: 4bit */ ++ const unsigned int bit_vdp = 5; /* 5: 5bit */ ++ const unsigned int tmp = (hdmi_clk_en == 1) ? 1 : 0; ++ ++ ot_reg_set_bit(tmp, bit_pixel, io_crg_address(CRG_PERCTL8351_ADDR)); ++ ot_reg_set_bit(tmp, bit_vdp, io_crg_address(CRG_PERCTL8351_ADDR)); ++ ++ return 0; ++} ++ ++static void ot_reg_write32(unsigned long value, unsigned long mask, unsigned long addr) ++{ ++ unsigned long t; ++ ++ t = readl((const volatile void *)(uintptr_t)addr); ++ t &= ~mask; ++ t |= value & mask; ++ writel(t, (volatile void *)(uintptr_t)addr); ++} ++ ++int sys_hal_vo_hdmi_clk_sel(int vo_dev, unsigned int clk_ch_sel) ++{ ++ const unsigned int bit = 20; /* 20: 20bit */ ++ const unsigned int mask = 0x1; ++ ++ if (vo_dev == 0) { ++ ot_reg_write32(clk_ch_sel << bit, mask << bit, io_crg_address(CRG_PERCTL8351_ADDR)); ++ return 0; ++ } ++ return -1; ++} ++ ++static void vo_drv_set_intf_hdmi_cfg(ot_vo_dev dev) ++{ ++ bool hdmi_clk_en = 1; ++ bool hdmi_clk_sel = dev; ++ sys_hal_vo_hdmi_clk_en(dev, hdmi_clk_en); ++ sys_hal_vo_hdmi_clk_sel(dev, hdmi_clk_sel); ++ vo_hal_intf_set_mux_sel_hd(dev, OT_VO_INTF_HDMI); ++} ++void vo_drv_get_pll_cfg_no_div(ot_vo_intf_sync intf_sync, ot_vo_pll *pll) ++{ ++ vo_pll_param pll_init = {OT_VO_OUT_1080P60, {99, 0, 1, 4, 4}, 0}; ++ vo_pll_param *pll_ret = &pll_init; ++ pll->post_div2 = pll_ret->pll.post_div2; ++ pll->post_div1 = pll_ret->pll.post_div1; ++ pll->frac = pll_ret->pll.frac; ++ pll->fb_div = pll_ret->pll.fb_div; ++ pll->ref_div = pll_ret->pll.ref_div; ++} ++ ++void vo_drv_dev_get_pll_cfg(ot_vo_dev dev, ot_vo_pll *pll) ++{ ++ vo_drv_get_pll_cfg_no_div(OT_VO_OUT_1080P60, pll); ++} ++ ++int sys_hal_vo_set_pll_power_ctrl(int pll, bool power_down) ++{ ++ const unsigned int bit = 20; /* 20: 20bit */ ++ const unsigned int tmp = (power_down == 1) ? 1 : 0; ++ ++ if (pll != 0) { ++ return -1; ++ } ++ ++ ot_reg_set_bit(tmp, bit, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); ++ ++ return 0; ++} ++ ++static void vo_drv_dev_set_pll_power_down(ot_vo_dev dev, bool power_down) ++{ ++ sys_hal_vo_set_pll_power_ctrl(0, power_down); ++} ++ ++int sys_hal_vo_set_pll_fbdiv(int pll, unsigned int bits_set) ++{ ++ const unsigned int bit = 0; /* 0: 0bit */ ++ const unsigned int mask = 0xfff; ++ if (pll != 0) { ++ return -1; ++ } ++ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); ++ ++ return 0; ++} ++ ++int sys_hal_vo_set_pll_frac(int pll, unsigned int bits_set) ++{ ++ const unsigned int bit = 0; ++ const unsigned int bit_dsmpd = 25; /* 25: 25bit fractional or integer mode */ ++ const unsigned int mask = 0xffffff; ++ ++ if (pll != 0) { ++ return -1; ++ } ++ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL224_ADDR)); ++ if (bits_set == 0) { ++ ot_reg_set_bit(1, bit_dsmpd, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); /* 1: integer */ ++ } else { ++ ot_reg_set_bit(0, bit_dsmpd, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); /* 0: fractional */ ++ } ++ return 0; ++} ++ ++int sys_hal_vo_set_pll_refdiv(int pll, unsigned int bits_set) ++{ ++ const unsigned int bit = 12; /* 12: 12bit */ ++ const unsigned int mask = 0x3f; ++ ++ ++ if (pll != 0) { ++ return -1; ++ } ++ ++ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); ++ ++ return 0; ++} ++ ++int sys_hal_vo_set_pll_postdiv2(int pll, unsigned int bits_set) ++{ ++ const unsigned int bit = 28; /* 28: 28bit */ ++ const unsigned int mask = 0x7; ++ ++ ++ if (pll != 0) { ++ return -1; ++ } ++ ++ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL224_ADDR)); ++ ++ return 0; ++} ++ ++int sys_hal_vo_set_pll_postdiv1(int pll, unsigned int bits_set) ++{ ++ const unsigned int bit = 24; /* 24: 24bit */ ++ const unsigned int mask = 0x7; ++ ++ ++ if (pll != 0) { ++ return -1; ++ } ++ ++ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL224_ADDR)); ++ ++ ++ return 0; ++} ++ ++void vo_drv_dev_set_pll_cfg(ot_vo_dev dev, ot_vo_pll *pll) ++{ ++ vo_drv_dev_set_pll_power_down(dev, 1); ++ sys_hal_vo_set_pll_fbdiv(0, pll->fb_div); ++ sys_hal_vo_set_pll_frac(0, pll->frac); ++ sys_hal_vo_set_pll_refdiv(0, pll->ref_div); ++ sys_hal_vo_set_pll_postdiv1(0, pll->post_div1); ++ sys_hal_vo_set_pll_postdiv2(0, pll->post_div2); ++ vo_drv_dev_set_pll_power_down(dev, 0); ++} ++ ++static void vo_drv_set_hd_clk(ot_vo_dev dev) ++{ ++ ot_vo_pll pll = {0}; ++ if (dev == VO_DEV_DHD0) { ++ vo_drv_dev_get_pll_cfg(dev, &pll); ++ vo_drv_dev_set_pll_cfg(dev, &pll); ++ return; ++ } ++} ++ ++void vo_drv_set_dev_clk(ot_vo_dev dev) ++{ ++ vo_drv_set_hd_clk(dev); ++} ++ ++int sys_hal_vo_dev_clk_en(int vo_dev, bool clk_en) ++{ ++ const unsigned int bit = 4; /* 4: 4bit */ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ ++ if (vo_dev == 0) { ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8340_ADDR)); ++ } else if (vo_dev == 1) { ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8341_ADDR)); ++ } else { ++ return -1; ++ } ++ return 0; ++} ++ ++int sys_hal_vo_lcd_clk_en(int vo_dev, bool clk_en) ++{ ++ const unsigned int tmp = (clk_en == 1) ? 1 : 0; ++ const unsigned int bit = 27; /* 27: 27bit */ ++ ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8346_ADDR)); ++ ++ return 0; ++} ++ ++void vo_drv_set_dev_clk_en(ot_vo_dev dev, bool clk_en) ++{ ++ bool vo_clk_en = clk_en; ++ if ((dev == VO_DEV_DHD0) || (dev == VO_DEV_DHD1)) { ++ sys_hal_vo_dev_clk_en(dev, vo_clk_en); ++ } ++ if (dev == VO_DEV_DHD1) { ++ sys_hal_vo_lcd_clk_en(dev, vo_clk_en); ++ } ++} ++ ++int sys_hal_vo_hd_clk_sel(int dev, unsigned int clk_sel) ++{ ++ const unsigned int bit = 12; /* 12: 12bit */ ++ const unsigned int mask = 0xf; ++ ++ if (dev == 0) { ++ ot_reg_set_bit(clk_sel, bit, io_crg_address(CRG_PERCTL8340_ADDR)); ++ } else if (dev == 1) { ++ ot_reg_write32(clk_sel << bit, mask << bit, io_crg_address(CRG_PERCTL8341_ADDR)); ++ } else { ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++void vo_drv_set_dev_clk_sel(ot_vo_dev dev, unsigned int clk_sel) ++{ ++ unsigned int hd_clk_sel = clk_sel; /* hd0默认HPLL */ ++ ++ /* ++ * hd0选择时钟�? 注：hd1已经按照时序和接口在配置时钟大小的同时也配时钟源 ++ * 这里不能再配置hd1的时钟源，因为时钟源跟大小是绑定的�?? ++ */ ++ if (dev == VO_DEV_DHD0) { ++ sys_hal_vo_hd_clk_sel(dev, hd_clk_sel); ++ } ++} ++ ++/* rgbfull to yuv601full */ ++__inline static void rgb_to_yc_full(unsigned short r, unsigned short g, unsigned short b, unsigned short *y, unsigned short *cb, unsigned short *cr) ++{ ++ unsigned short y_tmp, cb_tmp, cr_tmp; ++ ++ y_tmp = (unsigned short)(((r * 76 + g * 150 + b * 29) >> 8) * 4); ++ cb_tmp = (unsigned short)(clip_min(((((b * 128 - r * 43) - g * 84) >> 8) + 128), 0) * 4); ++ cr_tmp = (unsigned short)(clip_min(((((r * 128 - g * 107) - b * 20) >> 8) + 128), 0) * 4); ++ ++ *y = MAX2(MIN2(y_tmp, 1023), 0); ++ *cb = MAX2(MIN2(cb_tmp, 1023), 0); ++ *cr = MAX2(MIN2(cr_tmp, 1023), 0); ++} ++ ++__inline static unsigned int rgb_to_yuv_full(unsigned int rgb) ++{ ++ unsigned short y, u, v; ++ ++ rgb_to_yc_full(RGB_R(rgb), RGB_G(rgb), RGB_B(rgb), &y, &u, &v); ++ ++ return YUV(y, u, v); ++} ++ ++void hal_cbm_set_cbm_bkg(hal_cbmmix mixer, const hal_disp_bkcolor *bkg) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_cbm_bkg1 cbm_bkg1; ++ volatile reg_cbm_bkg2 cbm_bkg2; ++ ++ if (mixer == HAL_CBMMIX1) { ++ cbm_bkg1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg1.u32)); ++ cbm_bkg1.bits.cbm_bkgy1 = (bkg->bkg_y); ++ cbm_bkg1.bits.cbm_bkgcb1 = (bkg->bkg_cb); ++ cbm_bkg1.bits.cbm_bkgcr1 = (bkg->bkg_cr); ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg1.u32), cbm_bkg1.u32); ++ } else if (mixer == HAL_CBMMIX2) { ++ cbm_bkg2.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg2.u32)); ++ cbm_bkg2.bits.cbm_bkgy2 = (bkg->bkg_y); ++ cbm_bkg2.bits.cbm_bkgcb2 = (bkg->bkg_cb); ++ cbm_bkg2.bits.cbm_bkgcr2 = (bkg->bkg_cr); ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg2.u32), cbm_bkg2.u32); ++ } ++} ++ ++static void vo_drv_set_cbm_bkg(ot_vo_dev dev) ++{ ++ hal_disp_bkcolor bkg; ++ unsigned int bg_color; ++ unsigned int yuv_bk_grd; ++ hal_cbmmix mixer = dev; ++ ++ /* bg_color only yuv output */ ++ bg_color = COLOR_RGB_RED;//vo_drv_get_dev_bg_color(dev); ++ yuv_bk_grd = rgb_to_yuv_full(bg_color); ++ bkg.bkg_y = YUV_Y(yuv_bk_grd); ++ bkg.bkg_cb = YUV_U(yuv_bk_grd); ++ bkg.bkg_cr = YUV_V(yuv_bk_grd); ++ ++ hal_cbm_set_cbm_bkg(mixer, &bkg); ++} ++ ++bool vo_drv_is_rgb_intf(ot_vo_intf_type intf_type) ++{ ++ if (((intf_type & OT_VO_INTF_RGB_6BIT) != 0) || ++ ((intf_type & OT_VO_INTF_RGB_8BIT) != 0) || ++ ((intf_type & OT_VO_INTF_RGB_16BIT) != 0) || ++ ((intf_type & OT_VO_INTF_RGB_18BIT) != 0) || ++ ((intf_type & OT_VO_INTF_RGB_24BIT) != 0)) { ++ return 1; ++ } ++ return 0; ++} ++ ++static void vo_drv_get_div_mod_by_rgb_intf(ot_vo_intf_type intf_type, unsigned int *div_mode) ++{ ++ if ((OT_VO_INTF_RGB_8BIT & intf_type) != 0) { ++ *div_mode = 3; /* 3: 4div */ ++ } else if ((OT_VO_INTF_RGB_6BIT & intf_type) != 0) { ++ *div_mode = 2; /* 2: 3div */ ++ } else if (((OT_VO_INTF_RGB_16BIT & intf_type) != 0) || ++ ((OT_VO_INTF_RGB_18BIT & intf_type) != 0) || ++ ((OT_VO_INTF_RGB_24BIT & intf_type) != 0)) { ++ *div_mode = 0; /* 0: 1div */ ++ } ++} ++ ++void vo_drv_get_div_mod(ot_vo_dev dev, unsigned int *div_mode) ++{ ++ ot_vo_intf_type intf_type = OT_VO_INTF_HDMI; ++ ++ if ((OT_VO_INTF_HDMI & intf_type) != 0) { ++ *div_mode = 0; /* 0: 1div */ ++ } ++ ++ if ((OT_VO_INTF_BT1120 & intf_type) != 0) { ++ *div_mode = 0; /* 0: 1div */ ++ } ++ ++ if ((OT_VO_INTF_BT656 & intf_type) != 0) { ++ *div_mode = 1; /* 1: 2div */ ++ } ++ ++ if ((OT_VO_INTF_CVBS & intf_type) != 0) { ++ *div_mode = 3; /* 0: 1div, 1: 2div, 2: 3div, 3: 4div */ ++ } ++ ++ if (vo_drv_is_rgb_intf(intf_type)) { ++ vo_drv_get_div_mod_by_rgb_intf(intf_type, div_mode); ++ } ++} ++ ++/* VO HD dev div_mode */ ++int sys_hal_vo_dev_div_mode(int vo_dev, unsigned int div_mod) ++{ ++ const unsigned int bit = 24; /* 24: 24bit */ ++ const unsigned int mask = 0x3; ++ ++ if (vo_dev == 0) { ++ ot_reg_write32(div_mod << bit, mask << bit, io_crg_address(CRG_PERCTL8340_ADDR)); ++ } else if (vo_dev == 1) { ++ ot_reg_write32(div_mod << bit, mask << bit, io_crg_address(CRG_PERCTL8341_ADDR)); ++ } else { ++ return -1; ++ } ++ return 0; ++} ++ ++static void vo_drv_set_div_mod(ot_vo_dev dev, unsigned int div_mode) ++{ ++ sys_hal_vo_dev_div_mode(dev, div_mode); ++} ++ ++bool vo_drv_is_bt_intf(ot_vo_intf_type intf_type) ++{ ++ if (((intf_type & OT_VO_INTF_BT1120) != 0) || ((intf_type & OT_VO_INTF_BT656) != 0)) { ++ return 1; ++ } ++ return 0; ++} ++ ++int sys_hal_vo_out_hd_phase_ctrl(int vo_dev, bool reverse) ++{ ++ const unsigned int tmp = (reverse == 1) ? 1 : 0; ++ const unsigned int bit = 20; /* 20: 20bit */ ++ ++ if ((vo_dev != 0) && (vo_dev != 1)) { ++ return -1; ++ } ++ ++ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8338_ADDR)); ++ return 0; ++} ++ ++void vo_drv_set_clk_reverse(ot_vo_dev dev, bool reverse) ++{ ++ ot_vo_intf_type intf_type = OT_VO_INTF_HDMI; ++ if ((vo_drv_is_rgb_intf(intf_type) != 1) && (vo_drv_is_bt_intf(intf_type) != 1)) { ++ return; ++ } ++ sys_hal_vo_out_hd_phase_ctrl(dev, reverse); ++} ++ ++static bool vo_drv_get_dev_clk_reverse(ot_vo_dev dev) ++{ ++ bool clk_reverse_en = 1; ++ ot_vo_intf_type intf_type = OT_VO_INTF_HDMI; ++ if ((intf_type & OT_VO_INTF_RGB_24BIT) != 0) { ++ clk_reverse_en = 0; ++ } ++ ++ return clk_reverse_en; ++} ++ ++static void vo_drv_set_dev_clk_reverse(ot_vo_dev dev) ++{ ++ ++ bool clk_reverse_en = vo_drv_get_dev_clk_reverse(dev); ++ vo_drv_set_clk_reverse(dev, clk_reverse_en); ++} ++ ++/* 打开、关闭中�? */ ++void hal_disp_set_int_mask(unsigned int mask_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vointmsk vo_intmsk; ++ /* display interrupt mask enable */ ++ vo_intmsk.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32)); ++ vo_intmsk.u32 = vo_intmsk.u32 | mask_en; ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32), vo_intmsk.u32); ++} ++ ++void hal_disp_clr_int_mask(unsigned int mask_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vointmsk vo_intmsk; ++ /* display interrupt mask enable */ ++ vo_intmsk.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32)); ++ vo_intmsk.u32 = vo_intmsk.u32 & (~mask_en); ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32), vo_intmsk.u32); ++} ++/* ++ * VTTHD1 : VO 垂直时序中断 ++ */ ++static unsigned int vo_drv_get_basic_int_type(ot_vo_dev dev) ++{ ++ unsigned int int_type = 0; ++ ++ if (dev == VO_DEV_DHD0) { ++ int_type = VO_INTMSK_DHD0_VTTHD1; ++ } else if (dev == VO_DEV_DHD1) { ++ int_type = VO_INTMSK_DHD1_VTTHD1 | VO_INTMSK_CVBS_VDAC; ++ } ++ return int_type; ++} ++ ++static void vo_drv_dev_vo_int_enable(ot_vo_dev dev, bool enable) ++{ ++ unsigned int int_type; ++ ++ int_type = vo_drv_get_basic_int_type(dev); ++ if (enable == 1) { ++ hal_disp_set_int_mask(int_type); ++ } else { ++ hal_disp_clr_int_mask(int_type); ++ } ++} ++/* ++ * VTTHD2 : gfbg 垂直时序中断 ++ * VTTHD3 : gfbg 帧起始中�? ++ */ ++static unsigned int vo_drv_get_gfbg_basic_int_type(ot_vo_dev dev) ++{ ++ unsigned int gfbg_int_type = 0; ++ ++ if (dev == VO_DEV_DHD0) { ++ gfbg_int_type = VO_INTMSK_DHD0_VTTHD2 | VO_INTMSK_DHD0_VTTHD3; ++ } else if (dev == VO_DEV_DHD1) { ++ gfbg_int_type = VO_INTMSK_DHD1_VTTHD2 | VO_INTMSK_DHD1_VTTHD3; ++ } ++ return gfbg_int_type; ++} ++ ++void hal_disp_set_int_mask1(unsigned int mask_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vointmsk1 vo_intmsk1; ++ /* display interrupt mask enable */ ++ vo_intmsk1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32)); ++ vo_intmsk1.u32 = vo_intmsk1.u32 | mask_en; ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32), vo_intmsk1.u32); ++} ++ ++void hal_disp_clr_int_mask1(unsigned int mask_en) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_vointmsk1 vo_intmsk1; ++ /* display interrupt mask enable */ ++ vo_intmsk1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32)); ++ vo_intmsk1.u32 = vo_intmsk1.u32 & (~mask_en); ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32), vo_intmsk1.u32); ++} ++ ++static void vo_drv_dev_gfbg_int_enable(ot_vo_dev dev, bool enable) ++{ ++ unsigned int gfbg_int_type; ++ gfbg_int_type = vo_drv_get_gfbg_basic_int_type(dev); ++ if (enable == 1) { ++ hal_disp_set_int_mask1(gfbg_int_type); ++ } else { ++ hal_disp_clr_int_mask1(gfbg_int_type); ++ } ++} ++ ++void vo_drv_dev_int_enable(ot_vo_dev dev, bool enable) ++{ ++ vo_drv_dev_vo_int_enable(dev, enable); ++ vo_drv_dev_gfbg_int_enable(dev, enable); ++} ++ ++static void vo_set_drv_dev_int_enable(void) ++{ ++ ot_vo_dev dev; ++ for (dev = 0; dev < OT_VO_MAX_PHYS_DEV_NUM; dev++) { ++ vo_drv_dev_int_enable(dev, 1); ++ } ++} ++ ++void hal_cbm_set_cbm_attr(hal_disp_layer layer, ot_vo_dev dev) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_link_ctrl link_ctrl; ++ link_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->link_ctrl.u32)); ++ if (layer == HAL_DISP_LAYER_VHD2) { ++ link_ctrl.bits.v2_link = dev; ++ } else if (layer == HAL_DISP_LAYER_GFX3) { ++ link_ctrl.bits.g3_link = dev; ++ } ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->link_ctrl.u32), link_ctrl.u32); ++} ++ ++bool hal_cbm_get_cbm_mixer_layer_id(const vo_hal_cbm_mixer *cbm_mixer, unsigned int cbm_len, ++ ot_vo_layer layer, unsigned char *layer_id) ++{ ++ unsigned int index; ++ for (index = 0; index < cbm_len; index++) { ++ if (layer == cbm_mixer[index].layer) { ++ *layer_id = cbm_mixer[index].layer_id; ++ return true; ++ } ++ } ++ ++ printk("error layer id %d found\n", layer); ++ return false; ++} ++ ++static bool hal_cbm_get_cbm1_mixer_layer_id(ot_vo_layer layer, unsigned char *layer_id) ++{ ++ const vo_hal_cbm_mixer cbm1_mixer[] = { ++ { OT_VO_LAYER_V0, 0x1 }, ++ { OT_VO_LAYER_V2, 0x3 }, ++ { OT_VO_LAYER_G0, 0x2 }, ++ { OT_VO_LAYER_G3, 0x4 }, ++ { VO_LAYER_BUTT, 0x0 } ++ }; ++ ++ unsigned int cbm1_len = sizeof(cbm1_mixer) / sizeof(vo_hal_cbm_mixer); ++ return hal_cbm_get_cbm_mixer_layer_id(cbm1_mixer, cbm1_len, layer, layer_id); ++} ++ ++static bool hal_cbm_get_cbm2_mixer_layer_id(ot_vo_layer layer, unsigned char *layer_id) ++{ ++ const vo_hal_cbm_mixer cbm2_mixer[] = { ++ { OT_VO_LAYER_V1, 0x1 }, ++ { OT_VO_LAYER_V2, 0x3 }, ++ { OT_VO_LAYER_G1, 0x2 }, ++ { OT_VO_LAYER_G3, 0x4 }, ++ { VO_LAYER_BUTT, 0x0 } ++ }; ++ ++ unsigned int cbm2_len = sizeof(cbm2_mixer) / sizeof(vo_hal_cbm_mixer); ++ return hal_cbm_get_cbm_mixer_layer_id(cbm2_mixer, cbm2_len, layer, layer_id); ++} ++ ++static void hal_cbm_set_cbm1_mixer_prio(ot_vo_layer layer, unsigned char prio) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_cbm_mix1 cbm_mix1; ++ unsigned char layer_id = 0; ++ ++ /* check layer availability */ ++ if (hal_cbm_get_cbm1_mixer_layer_id(layer, &layer_id) != true) { ++ return; ++ } ++ ++ /* set mixer prio */ ++ cbm_mix1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix1.u32)); ++ ++ switch (prio) { ++ case 0: /* 0: prio 0 */ ++ cbm_mix1.bits.mixer_prio0 = layer_id; ++ break; ++ ++ case 1: /* 1: prio 1 */ ++ cbm_mix1.bits.mixer_prio1 = layer_id; ++ break; ++ ++ case 2: /* 2: prio 2 */ ++ cbm_mix1.bits.mixer_prio2 = layer_id; ++ break; ++ ++ case 3: /* 3: prio 3 */ ++ cbm_mix1.bits.mixer_prio3 = layer_id; ++ break; ++ ++ default: ++ printk("error priority id %d found\n", prio); ++ return; ++ } ++ ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix1.u32), cbm_mix1.u32); ++} ++ ++static void hal_cbm_set_cbm2_mixer_prio(ot_vo_layer layer, unsigned char prio) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_cbm_mix2 cbm_mix2; ++ unsigned char layer_id = 0; ++ ++ /* check layer availability */ ++ if (hal_cbm_get_cbm2_mixer_layer_id(layer, &layer_id) != true) { ++ return; ++ } ++ ++ /* set mixer prio */ ++ cbm_mix2.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix2.u32)); ++ ++ switch (prio) { ++ case 0: /* 0: prio 0 */ ++ cbm_mix2.bits.mixer_prio0 = layer_id; ++ break; ++ ++ case 1: /* 1: prio 1 */ ++ cbm_mix2.bits.mixer_prio1 = layer_id; ++ break; ++ ++ case 2: /* 2: prio 2 */ ++ cbm_mix2.bits.mixer_prio2 = layer_id; ++ break; ++ ++ case 3: /* 3: prio 3 */ ++ cbm_mix2.bits.mixer_prio3 = layer_id; ++ break; ++ ++ default: ++ printk("error priority id %d found\n", prio); ++ return; ++ } ++ ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix2.u32), cbm_mix2.u32); ++} ++ ++void hal_cbm_set_cbm_mixer_prio(ot_vo_layer layer, unsigned char prio, unsigned char mixer_id) ++{ ++ if (mixer_id == HAL_CBMMIX1) { ++ hal_cbm_set_cbm1_mixer_prio(layer, prio); ++ } else if (mixer_id == HAL_CBMMIX2) { ++ hal_cbm_set_cbm2_mixer_prio(layer, prio); ++ } ++} ++ ++void vou_drv_set_layer_priority(ot_vo_dev dev, ot_vo_layer layer, unsigned int priority) ++{ ++ ++ hal_cbm_set_cbm_mixer_prio(layer, priority, dev); ++ ++ /* need regup */ ++ hal_disp_set_reg_up(dev); ++} ++ ++void vou_drv_def_layer_bind_dev(void) ++{ ++ /* default cbm */ ++ hal_cbm_set_cbm_attr(HAL_DISP_LAYER_VHD2, VO_DEV_DHD0); ++ hal_cbm_set_cbm_attr(HAL_DISP_LAYER_GFX3, VO_DEV_DHD0); ++ ++ /* default priority dhd0 */ ++ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_V0, VOU_MIX_PRIO0); ++ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_V2, VOU_MIX_PRIO1); ++ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_G0, VOU_MIX_PRIO2); ++ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_G3, VOU_MIX_PRIO3); ++ ++ /* default priority dhd1 */ ++ vou_drv_set_layer_priority(VO_DEV_DHD1, OT_VO_LAYER_V1, VOU_MIX_PRIO0); ++ vou_drv_set_layer_priority(VO_DEV_DHD1, OT_VO_LAYER_G1, VOU_MIX_PRIO2); ++ ++ /* need regup */ ++ hal_disp_set_reg_up(VO_DEV_DHD0); ++ hal_disp_set_reg_up(VO_DEV_DHD1); ++} ++ ++void hal_sys_set_outstanding(void) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_mac_outstanding mac_outstanding; ++ ++ mac_outstanding.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->mac_outstanding.u32)); ++ mac_outstanding.bits.mstr0_routstanding = 0xf; /* 0xf: master 0 read outstanding */ ++ mac_outstanding.bits.mstr0_woutstanding = 0x7; /* 0x7: master 0 write outstanding */ ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->mac_outstanding.u32), mac_outstanding.u32); ++} ++ ++void hal_disp_clear_int_status(unsigned int int_msk) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ ++ /* read interrupt status */ ++ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vomskintsta.u32), int_msk); ++} ++ ++ot_vo_layer vo_drv_get_hw_layer(ot_vo_layer layer) ++{ ++ return layer; ++} ++ ++void vou_drv_layer_enable(ot_vo_layer layer, bool enable) ++{ ++ ot_vo_layer hw_layer = vo_drv_get_hw_layer(layer); ++ hal_video_hfir_set_ck_gt_en(hw_layer, enable); ++ hal_layer_enable_layer(hw_layer, enable); ++ hal_video_set_layer_ck_gt_en(hw_layer, enable); ++} ++ ++hal_disp_layer vou_drv_convert_layer(ot_vo_layer layer) ++{ ++ hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT; ++ switch (layer) { ++ case VO_HAL_LAYER_VHD0: ++ disp_layer = HAL_DISP_LAYER_VHD0; ++ break; ++ ++ case VO_HAL_LAYER_VHD1: ++ disp_layer = HAL_DISP_LAYER_VHD1; ++ break; ++ ++ case VO_HAL_LAYER_VHD2: ++ disp_layer = HAL_DISP_LAYER_VHD2; ++ break; ++ ++ default: ++ break; ++ } ++ ++ return disp_layer; ++} ++ ++hal_disp_pixel_format vo_drv_convert_data_format(vou_layer_pixel_format data_fmt) ++{ ++ hal_disp_pixel_format pixel_format; ++ ++ if (data_fmt == VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_420) { ++ pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_420; ++ } else if (data_fmt == VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_422) { ++ pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_422; ++ } else { ++ pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_400; ++ } ++ ++ return pixel_format; ++} ++ ++void vou_drv_set_layer_data_fmt(ot_vo_layer layer, vou_layer_pixel_format data_fmt) ++{ ++ ot_vo_layer hw_layer = vo_drv_get_hw_layer(layer); ++ hal_disp_layer hal_layer; ++ hal_disp_pixel_format disp_data_fmt; ++ ++ hal_layer = vou_drv_convert_layer(hw_layer); ++ disp_data_fmt = vo_drv_convert_data_format(data_fmt); ++ hal_layer_set_layer_data_fmt(hal_layer, disp_data_fmt); ++} ++ ++void vo_drv_default_setting(void) ++{ ++ unsigned int i; ++ hfir_coef h_coef[LAYER_VID_END + 1] = { ++ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a }, ++ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a }, ++ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a } ++ }; ++ /* set dac default cablectr */ ++ vo_hal_intf_set_dac_cablectr(OT_VO_INTF_CVBS, VO_DAC_CABLE_CTR_DEF); ++ ++ /* set each video/graphic layer global alpha */ ++ for (i = LAYER_VID_START; i <= LAYER_GFX_END; i++) { ++ hal_layer_set_layer_global_alpha(i, VO_ALPHA_OPACITY); /* global alpha max 255 */ ++ hal_video_set_layer_alpha(i, VO_ALPHA_OPACITY); /* alpha max 255 */ ++ } ++ ++ /* select graphic layer's alpha range(0: 0~128,1:0~255) */ ++ for (i = LAYER_GFX_START; i <= LAYER_GFX_END; i++) { ++ hal_gfx_set_pixel_alpha_range(i, 1); ++ } ++ ++ /* set video layer hfir enable */ ++ for (i = LAYER_VID_START; i <= LAYER_VID_END; i++) { ++ hal_video_hfir_set_hfir_mode(i, HAL_HFIRMODE_COPY); ++ hal_video_hfir_set_coef(i, &h_coef[i]); ++ hal_video_hfir_set_mid_en(i, true); ++ } ++ ++ /* set each cross bar default PRI */ ++ vou_drv_def_layer_bind_dev(); ++ ++ /* outstanding */ ++ hal_sys_set_outstanding(); ++ ++ hal_disp_clear_int_status(VO_INTREPORT_ALL); ++ ++ /* only set video layer */ ++ for (i = LAYER_VID_START; i <= LAYER_VID_END; i++) { ++ vou_drv_layer_enable(i, false); ++ vou_drv_set_layer_data_fmt(i, VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_422); ++ } ++} ++ ++static void vo_init_default_setting(void) ++{ ++ vo_drv_default_setting(); ++} ++ ++void hal_disp_set_intf_enable(ot_vo_dev dev, bool intf) ++{ ++ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); ++ volatile reg_dhd0_ctrl dhd0_ctrl; ++ volatile unsigned long addr_reg; ++ ++ ++ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); ++ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); ++ dhd0_ctrl.bits.intf_en = intf; ++ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); ++} ++ ++int vo_init(struct vop *vop) ++{ ++ int vo_dev = vop->vo_dev; ++ hal_disp_syncinfo sync_info; ++ hal_disp_syncinv inv = {0}; ++ unsigned int div_mode = 0; ++ ++ ++ if(sys_hal_init() != 0) { ++ printk("sys_hal_init,%s,%d bad\n",__func__,__LINE__); ++ return -1; ++ } ++ ++ vo_init_set_sys_clk(); ++ ++ /* 使能时钟 */ ++ vo_init_crg_clk(vo_dev); ++ vo_drv_set_dev_clk(vo_dev); ++ vo_drv_set_dev_clk_en(vo_dev, 1); ++ vo_drv_set_dev_clk_sel(vo_dev, 0); ++ vo_drv_set_cbm_bkg(vo_dev); ++ vo_drv_set_intf_hdmi_cfg(vo_dev); ++ ++ vo_hal_intf_set_mux_sel_hd(vo_dev, OT_VO_INTF_HDMI); ++ vo_drv_get_sync_inv(vo_dev, &inv); ++ ++ //vo_drv_set_sync_inv ++ vo_hal_intf_set_hdmi_sync_inv(&inv); ++ vo_drv_get_sync_info(vo_dev, &sync_info); ++ vo_hal_intf_set_sync_info_hvsync(vo_dev,&sync_info); ++ vo_hal_intf_set_sync_info_other(vo_dev,&sync_info); ++ vo_drv_get_div_mod(vo_dev, &div_mode); ++ vo_drv_set_div_mod(vo_dev, div_mode); ++ vo_drv_set_dev_clk_reverse(vo_dev); ++ ++ //vo_drv_set_hdmi_param ++ vo_hal_intf_set_csc_enable(OT_VO_INTF_HDMI,1); ++ vou_drv_intf_csc_config(OT_VO_INTF_HDMI, &vop->csc); ++ vo_drv_set_hdmi_mode(vo_dev, vop); ++ hal_disp_set_reg_up(vo_dev); ++ ++ /* 默认硬件配置 */ ++ vo_init_default_setting(); ++ hal_disp_set_intf_enable(vo_dev, true); ++ vo_set_drv_dev_int_enable(); ++ hal_disp_set_reg_up(vo_dev); ++ return 0; ++} ++ ++unsigned int fb_hal_disp_get_int_status(unsigned int int_msk) ++{ ++ volatile u_vomskintsta1 vomskintsta1; ++ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ /* read interrupt status */ ++ vomskintsta1.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->vomskintsta1.u32)); ++ ++ return (vomskintsta1.u32 & int_msk); ++} ++/* ++ * Name : fb_hal_disp_clear_int_status ++ * Desc : Clear interrupt status. ++ */ ++bool fb_hal_disp_clear_int_status(unsigned int int_msk) ++{ ++ if (g_gfbg_reg == NULL) { ++ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); ++ return false; ++ } ++ ++ hal_write_reg((unsigned int *)&(g_gfbg_reg->vomskintsta1.u32), int_msk); ++ return true; ++} ++ ++enum irqreturn vop_isr(int irq, void *data) ++{ ++ struct vop *vop = data; ++ unsigned int int_status = fb_hal_disp_get_int_status(GFBG_INTREPORT_ALL); ++ ++ ++ if (int_status & GFBG_INTMSK_DHD0_VTTHD2) { ++ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD0_VTTHD2); ++ } else if (int_status & GFBG_INTMSK_DHD0_VTTHD3) { ++ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD0_VTTHD3); ++ } else if (int_status & GFBG_INTMSK_DHD1_VTTHD2) { ++ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD1_VTTHD2); ++ } else if (int_status & GFBG_INTMSK_DHD1_VTTHD3) { ++ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD1_VTTHD3); ++ } else if (int_status & GFBG_INTMSK_DSD_VTTHD2) { ++ fb_hal_disp_clear_int_status(GFBG_INTMSK_DSD_VTTHD2); ++ } else if (int_status & GFBG_INTMSK_DSD_VTTHD3) { ++ fb_hal_disp_clear_int_status(GFBG_INTMSK_DSD_VTTHD3); ++ } ++ ++ if (vop->vblank_enabled) { ++ drm_crtc_handle_vblank(&vop->crtc); ++ spin_lock(&vop->crtc.dev->event_lock); ++ if (vop->event) { ++ drm_crtc_send_vblank_event(&vop->crtc, vop->event); ++ drm_crtc_vblank_put(&vop->crtc); ++ vop->event = NULL; ++ } ++ spin_unlock(&vop->crtc.dev->event_lock); ++ } ++ return IRQ_HANDLED; ++} ++ ++static int vop_bind(struct device *dev, struct device *master, void *data) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct drm_device *drm_dev = data; ++ struct vop *vop; ++ struct resource *res; ++ ot_vo_dev vo_dev; ++ int ret; ++ vop = devm_kzalloc(dev, sizeof(*vop),GFP_KERNEL); ++ if (!vop) { ++ printk("devm_kzalloc,%s,%d error\n",__func__,__LINE__); ++ return -ENOMEM; ++ } ++ vop->size = 4 * 1920 * 1080; ++ vop->dev = dev; ++ vop->drm_dev = drm_dev; ++ vop->vo_dev = VO_DEV_DHD0; ++ vop->csc.csc_matrix = OT_VO_CSC_MATRIX_BT709FULL_TO_RGBFULL; ++ //vop->csc.csc_matrix = OT_VO_CSC_MATRIX_BT601FULL_TO_BT601FULL; ++ vop->csc.luma = VO_CSC_DEF_VAL; ++ vop->csc.contrast = VO_CSC_DEF_VAL; ++ vop->csc.hue = VO_CSC_DEF_VAL; ++ vop->csc.saturation = VO_CSC_DEF_VAL; ++ vop->csc.ex_csc_en = 0; ++ vop->is_enabled = false; ++ vop->vblank_enabled = false; ++ vop->irq = VOU1_IRQ_NR; ++ ++ vop->sgt = dma_alloc_noncontiguous(dev, vop->size, DMA_BIDIRECTIONAL, GFP_KERNEL, 0); ++ if (!vop->sgt) { ++ printk("CMA allocation of %zu bytes failed\n", vop->size); ++ return -ENOMEM; ++ } ++ ++ vop->phys_addr = (phys_addr_t)sg_dma_address(vop->sgt->sgl); ++ vop->virt_addr = dma_vmap_noncontiguous(dev, vop->size, vop->sgt); ++ if (!vop->virt_addr) { ++ printk("Failed to map DMA memory\n"); ++ ret = -ENOMEM; ++ goto err_free_main_sgt; ++ } ++ ++ spin_lock_init(&vop->reg_lock); ++ spin_lock_init(&vop->irq_lock); ++ mutex_init(&vop->vop_lock); ++ ++ dev_set_drvdata(dev, vop); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ vop->regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(vop->regs)) ++ return PTR_ERR(vop->regs); ++ vo_hal_set_reg(vop->regs); ++ g_gfbg_reg = (volatile vdp_regs_type *)vop->regs; ++ vop->len = resource_size(res); ++ vo_init(vop); ++ ret = vop_create_crtc(vop); ++ if (ret) ++ return ret; ++ ++ vop->irq = platform_get_irq_byname(pdev, "gfbg"); ++ ret = request_threaded_irq(vop->irq , vop_isr, NULL, IRQF_SHARED, "DRM Int", vop); ++ if (ret) ++ goto err_destroy_crtc; ++ printk("%s,%d OK\n",__func__,__LINE__); ++ return 0; ++ ++err_destroy_crtc: ++ vop_destroy_crtc(vop); ++err_unmap_main: ++ dma_vunmap_noncontiguous(dev, vop->virt_addr); ++err_free_main_sgt: ++ dma_free_noncontiguous(dev, vop->size, vop->sgt, DMA_BIDIRECTIONAL); ++ printk("%s,ret:%d\n",__func__,ret); ++ return ret; ++} ++ ++static void vop_unbind(struct device *dev, struct device *master, void *data) ++{ ++ struct vop *vop = dev_get_drvdata(dev); ++ free_irq(vop->irq , vop_isr); ++ ++ if (vop->virt_addr) { ++ dma_vunmap_noncontiguous(dev, vop->virt_addr); ++ vop->virt_addr = NULL; ++ } ++ ++ if (vop->sgt) { ++ dma_free_noncontiguous(dev, vop->size, vop->sgt, DMA_BIDIRECTIONAL); ++ vop->sgt = NULL; ++ } ++ ++ vop->phys_addr = 0; ++ vop_destroy_crtc(vop); ++} ++ ++const struct component_ops vop_component_ops = { ++ .bind = vop_bind, ++ .unbind = vop_unbind, ++}; ++ ++ ++static int vop_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ return component_add(dev, &vop_component_ops); ++} ++ ++static void vop_remove(struct platform_device *pdev) ++{ ++ component_del(&pdev->dev, &vop_component_ops); ++} ++EXPORT_SYMBOL_GPL(vop_component_ops); ++ ++static const struct of_device_id vop_driver_dt_match[] = { ++ { .compatible = "vendor,gfbg"}, ++ { /* sentinel */ }, ++}; ++struct platform_driver smart_vop_driver = { ++ .probe = vop_probe, ++ .remove_new = vop_remove, ++ .driver = { ++ .name = "hi3403v100-vop", ++ .of_match_table = vop_driver_dt_match, ++ }, ++}; +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.h b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.h +new file mode 100755 +index 000000000..f6c52671c +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.h +@@ -0,0 +1,1197 @@ ++ ++#ifndef _SMART_VOP_REG_H ++#define _SMART_VOP_REG_H ++ ++#include "smart_drm_drv.h" ++#include "hal_vo_reg.h" ++#include "hal_vo_def.h" ++#include "drv_vo_comm.h" ++ ++#include "gfbg_reg.h" ++ ++//bad ++/* AFBC supports a number of configurable modes. Relevant to us is block size ++ * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like ++ * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode ++ * could be enabled via the hreg_block_split register, but is not currently ++ * handled. The colourspace transform is implicitly always assumed by the ++ * decoder, so consumers must use this transform as well. ++ * ++ * Failure to match modifiers will cause errors displaying AFBC buffers ++ * produced by conformant AFBC producers, including Mesa. ++ */ ++ ++struct vop_rect { ++ int width; ++ int height; ++}; ++ ++struct vop_reg { ++ uint32_t mask; ++ uint16_t offset; ++ uint8_t shift; ++ bool write_mask; ++ bool relaxed; ++}; ++ ++struct vop_win_phy { ++ const uint32_t *data_formats; ++ uint32_t nformats; ++ const uint64_t *format_modifiers; ++ ++}; ++ ++struct vop_win_data { ++ uint32_t base; ++ const struct vop_win_phy *phy; ++ enum drm_plane_type type; ++}; ++ ++struct vop_data { ++ uint32_t version; ++ const struct vop_win_data *win; ++ unsigned int win_size; ++ unsigned int lut_size; ++ struct vop_rect max_output; ++ u64 feature; ++}; ++ ++/* VO video output interface type */ ++#define OT_VO_INTF_CVBS (0x01L << 0) ++#define OT_VO_INTF_VGA (0x01L << 1) ++#define OT_VO_INTF_BT656 (0x01L << 2) ++#define OT_VO_INTF_BT1120 (0x01L << 3) ++#define OT_VO_INTF_HDMI (0x01L << 4) ++#define OT_VO_INTF_RGB_6BIT (0x01L << 5) ++#define OT_VO_INTF_RGB_8BIT (0x01L << 6) ++#define OT_VO_INTF_RGB_16BIT (0x01L << 7) ++#define OT_VO_INTF_RGB_18BIT (0x01L << 8) ++#define OT_VO_INTF_RGB_24BIT (0x01L << 9) ++#define OT_VO_INTF_MIPI (0x01L << 10) ++#define OT_VO_INTF_MIPI_SLAVE (0x01L << 11) ++#define OT_VO_INTF_HDMI1 (0x01L << 12) ++ ++typedef enum { ++ OT_VO_OUT_PAL = 0, /* PAL standard */ ++ OT_VO_OUT_NTSC = 1, /* NTSC standard */ ++ OT_VO_OUT_960H_PAL = 2, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */ ++ OT_VO_OUT_960H_NTSC = 3, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */ ++ ++ OT_VO_OUT_640x480_60 = 4, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */ ++ OT_VO_OUT_480P60 = 5, /* 720 x 480 at 60 Hz. */ ++ OT_VO_OUT_576P50 = 6, /* 720 x 576 at 50 Hz. */ ++ OT_VO_OUT_800x600_60 = 7, /* VESA 800 x 600 at 60 Hz (non-interlaced) */ ++ OT_VO_OUT_1024x768_60 = 8, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */ ++ OT_VO_OUT_720P50 = 9, /* 1280 x 720 at 50 Hz. */ ++ OT_VO_OUT_720P60 = 10, /* 1280 x 720 at 60 Hz. */ ++ OT_VO_OUT_1280x800_60 = 11, /* 1280*800@60Hz VGA@60Hz */ ++ OT_VO_OUT_1280x1024_60 = 12, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */ ++ OT_VO_OUT_1366x768_60 = 13, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */ ++ OT_VO_OUT_1400x1050_60 = 14, /* VESA 1400 x 1050 at 60 Hz (non-interlaced) CVT */ ++ OT_VO_OUT_1440x900_60 = 15, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */ ++ OT_VO_OUT_1680x1050_60 = 16, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */ ++ ++ OT_VO_OUT_1080P24 = 17, /* 1920 x 1080 at 24 Hz. */ ++ OT_VO_OUT_1080P25 = 18, /* 1920 x 1080 at 25 Hz. */ ++ OT_VO_OUT_1080P30 = 19, /* 1920 x 1080 at 30 Hz. */ ++ OT_VO_OUT_1080I50 = 20, /* 1920 x 1080 at 50 Hz, interlaced. */ ++ OT_VO_OUT_1080I60 = 21, /* 1920 x 1080 at 60 Hz, interlaced. */ ++ OT_VO_OUT_1080P50 = 22, /* 1920 x 1080 at 50 Hz. */ ++ OT_VO_OUT_1080P60 = 23, /* 1920 x 1080 at 60 Hz. */ ++ ++ OT_VO_OUT_1600x1200_60 = 24, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */ ++ OT_VO_OUT_1920x1200_60 = 25, /* VESA 1920 x 1200 at 60 Hz (non-interlaced) CVT (Reduced Blanking) */ ++ OT_VO_OUT_1920x2160_30 = 26, /* 1920x2160_30 */ ++ OT_VO_OUT_2560x1440_30 = 27, /* 2560x1440_30 */ ++ OT_VO_OUT_2560x1440_60 = 28, /* 2560x1440_60 */ ++ OT_VO_OUT_2560x1600_60 = 29, /* 2560x1600_60 */ ++ ++ OT_VO_OUT_3840x2160_24 = 30, /* 3840x2160_24 */ ++ OT_VO_OUT_3840x2160_25 = 31, /* 3840x2160_25 */ ++ OT_VO_OUT_3840x2160_30 = 32, /* 3840x2160_30 */ ++ OT_VO_OUT_3840x2160_50 = 33, /* 3840x2160_50 */ ++ OT_VO_OUT_3840x2160_60 = 34, /* 3840x2160_60 */ ++ OT_VO_OUT_4096x2160_24 = 35, /* 4096x2160_24 */ ++ OT_VO_OUT_4096x2160_25 = 36, /* 4096x2160_25 */ ++ OT_VO_OUT_4096x2160_30 = 37, /* 4096x2160_30 */ ++ OT_VO_OUT_4096x2160_50 = 38, /* 4096x2160_50 */ ++ OT_VO_OUT_4096x2160_60 = 39, /* 4096x2160_60 */ ++ OT_VO_OUT_7680x4320_30 = 40, /* 7680x4320_30 */ ++ ++ OT_VO_OUT_240x320_50 = 41, /* 240x320_50 */ ++ OT_VO_OUT_320x240_50 = 42, /* 320x240_50 */ ++ OT_VO_OUT_240x320_60 = 43, /* 240x320_60 */ ++ OT_VO_OUT_320x240_60 = 44, /* 320x240_60 */ ++ OT_VO_OUT_800x600_50 = 45, /* 800x600_50 */ ++ ++ OT_VO_OUT_720x1280_60 = 46, /* For MIPI DSI Tx 720 x1280 at 60 Hz */ ++ OT_VO_OUT_1080x1920_60 = 47, /* For MIPI DSI Tx 1080x1920 at 60 Hz */ ++ ++ OT_VO_OUT_USER = 48, /* User timing. */ ++ ++ OT_VO_OUT_BUTT, ++} ot_vo_intf_sync; ++ ++typedef unsigned int ot_vo_intf_type; ++typedef int ot_vo_dev; ++#define VO_DAC_CABLE_CTR_DEF 3 ++typedef struct { ++ unsigned int syncm; ++ unsigned int iop; ++ unsigned char intfb; ++ ++ unsigned short vact; ++ unsigned short vbb; ++ unsigned short vfb; ++ ++ unsigned short hact; ++ unsigned short hbb; ++ unsigned short hfb; ++ unsigned short hmid; ++ ++ unsigned short bvact; ++ unsigned short bvbb; ++ unsigned short bvfb; ++ ++ unsigned short hpw; ++ unsigned short vpw; ++ ++ unsigned int idv; ++ unsigned int ihs; ++ unsigned int ivs; ++} hal_disp_syncinfo; ++ ++typedef struct { ++ unsigned int f_inv; ++ unsigned int vs_inv; ++ unsigned int hs_inv; ++ unsigned int dv_inv; ++} hal_disp_syncinv; ++ ++typedef enum { ++ VO_HD_HW_DEV = 0, /* HD dev */ ++ VO_SD_HW_DEV, /* SD dev */ ++ VO_UHD_HW_DEV, /* UHD dev */ ++ VO_CAS_DEV, /* cascade dev */ ++ VO_VIRT_DEV, /* virtual dev */ ++ VO_DEV_TYPE_BUTT, ++} vo_dev_type; ++ ++typedef struct { ++ vo_dev_type dev_type; /* dev type */ ++ bool support_wbc; /* WBC support or not */ ++} vo_dev_capability; ++ ++typedef struct { ++ /* 是否产生了VDAC中断,产生中断代表没有接负载 */ ++ bool int_ocurred; ++ bool detect_enabled; ++ bool is_connected; ++} vo_drv_load_detect_info; ++ ++typedef struct { ++ unsigned int bg_color; /* RW; background color of a device, in RGB format. */ ++ ot_vo_intf_type intf_type; /* RW; type of a VO interface */ ++ ot_vo_intf_sync intf_sync; /* RW; type of a VO interface timing */ ++ ot_vo_sync_info sync_info; /* RW; information about VO interface timing */ ++} ot_vo_pub_attr; ++ ++typedef struct { ++ bool vo_bypass_en; /* RW, range: [0, 1]; vo bypass enable */ ++} ot_vo_dev_param; ++ ++typedef enum { ++ OT_VO_CLK_EDGE_SINGLE = 0, /* single-edge mode */ ++ OT_VO_CLK_EDGE_DUAL, /* dual-edge mode */ ++ ++ OT_VO_CLK_EDGE_BUTT ++} ot_vo_clk_edge; ++typedef int ot_vo_layer; ++/* desc : device context, which contains device public attribute. */ ++typedef struct { ++ vo_dev_capability dev_cap; /* 设备能力级 */ ++ bool vo_enable; /* 设备使能标志 */ ++ bool config; /* 设备配置标志 */ ++ ot_vo_pub_attr vou_attr; /* 设备公共属性 */ ++ ++ unsigned int layer_num; /* 设备上包含层的数目 */ ++ unsigned int max_layer_num; /* 该设备上能包含的最多的层数，包括视频层和图形层 */ ++ ot_vo_layer layer[OT_VO_MAX_PRIORITY + 1]; /* 对应的优先级的层，如aen_layer[0]即该设备上优先级为0的层 */ ++ ++ unsigned int max_width; /* 设备分辨率最大宽度 */ ++ unsigned int max_height; /* 设备分辨率最大高度 */ ++ ++ bool less_buf_enable; /* 省BUF的标记 */ ++ bool user_notify_enable; /* 通知用户的标记 */ ++ unsigned int vtth; /* 提前完成中断垂直时序值 */ ++ unsigned int vtth2; /* 省BUF垂直时序值 */ ++ bool bt_param_config; /* bt_param配置标志，用于单双沿配置 */ ++ ot_vo_clk_edge clk_edge; /* 单双沿配置,默认单沿 */ ++ ++ bool dac_power_up; ++ vo_drv_load_detect_info load_detect_info; /* 负载检测 */ ++ unsigned int low_bandwidth_cnt; /* 统计VO低带宽信息 */ ++ unsigned long long bus_err; /* 统计VO bus err */ ++ unsigned int low_delay_err; /* 统计低延时错误 */ ++ ++ ot_vo_dev_param dev_param; ++} vo_drv_dev; ++ ++typedef enum { ++ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT601LIMIT = 0, /* Identity matrix. from BT.601 limit to BT.601 limit */ ++ OT_VO_CSC_MATRIX_BT601FULL_TO_BT601LIMIT = 1, /* Change color space from BT.601 full to BT.601 limit */ ++ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT601LIMIT = 2, /* Change color space from BT.709 limit to BT.601 limit */ ++ OT_VO_CSC_MATRIX_BT709FULL_TO_BT601LIMIT = 3, /* Change color space from BT.709 full to BT.601 limit */ ++ ++ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT709LIMIT = 4, /* Change color space from BT.601 limit to BT.709 limit */ ++ OT_VO_CSC_MATRIX_BT601FULL_TO_BT709LIMIT = 5, /* Change color space from BT.601 full to BT.709 limit */ ++ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT709LIMIT = 6, /* Identity matrix. from BT.709 limit to BT.709 limit */ ++ OT_VO_CSC_MATRIX_BT709FULL_TO_BT709LIMIT = 7, /* Change color space from BT.709 full to BT.709 limit */ ++ ++ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT601FULL = 8, /* Change color space from BT.601 limit to BT.601 full */ ++ OT_VO_CSC_MATRIX_BT601FULL_TO_BT601FULL = 9, /* Identity matrix. from BT.601 full to BT.601 full */ ++ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT601FULL = 10, /* Change color space from BT.709 limit to BT.601 full */ ++ OT_VO_CSC_MATRIX_BT709FULL_TO_BT601FULL = 11, /* Change color space from BT.709 full to BT.601 full */ ++ ++ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT709FULL = 12, /* Change color space from BT.601 limit to BT.709 full */ ++ OT_VO_CSC_MATRIX_BT601FULL_TO_BT709FULL = 13, /* Change color space from BT.601 full to BT.709 full */ ++ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT709FULL = 14, /* Change color space from BT.709 limit to BT.709 full */ ++ OT_VO_CSC_MATRIX_BT709FULL_TO_BT709FULL = 15, /* Identity matrix. from BT.709 full to BT.709 full */ ++ ++ OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBFULL = 16, /* Change color space from BT.601 limit to RGB full */ ++ OT_VO_CSC_MATRIX_BT601FULL_TO_RGBFULL = 17, /* Change color space from BT.601 full to RGB full */ ++ OT_VO_CSC_MATRIX_BT709LIMIT_TO_RGBFULL = 18, /* Change color space from BT.709 limit to RGB full */ ++ OT_VO_CSC_MATRIX_BT709FULL_TO_RGBFULL = 19, /* Change color space from BT.709 full to RGB full */ ++ ++ OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBLIMIT = 20, /* Change color space from BT.601 limit to RGB limit */ ++ OT_VO_CSC_MATRIX_BT601FULL_TO_RGBLIMIT = 21, /* Change color space from BT.709 full to RGB limit */ ++ OT_VO_CSC_MATRIX_BT709LIMIT_TO_RGBLIMIT = 22, /* Change color space from BT.601 limit to RGB limit */ ++ OT_VO_CSC_MATRIX_BT709FULL_TO_RGBLIMIT = 23, /* Change color space from BT.709 full to RGB limit */ ++ ++ OT_VO_CSC_MATRIX_RGBFULL_TO_BT601LIMIT = 24, /* Change color space from RGB full to BT.601 limit */ ++ OT_VO_CSC_MATRIX_RGBFULL_TO_BT601FULL = 25, /* Change color space from RGB full to BT.601 full */ ++ OT_VO_CSC_MATRIX_RGBFULL_TO_BT709LIMIT = 26, /* Change color space from RGB full to BT.709 limit */ ++ OT_VO_CSC_MATRIX_RGBFULL_TO_BT709FULL = 27, /* Change color space from RGB full to BT.709 full */ ++ ++ OT_VO_CSC_MATRIX_BUTT, ++} ot_vo_csc_matrix; ++ ++typedef struct { ++ ot_vo_csc_matrix csc_matrix; /* RW; CSC matrix */ ++ unsigned int luma; /* RW; range: [0, 100]; luminance, default: 50 */ ++ unsigned int contrast; /* RW; range: [0, 100]; contrast, default: 50 */ ++ unsigned int hue; /* RW; range: [0, 100]; hue, default: 50 */ ++ unsigned int saturation; /* RW; range: [0, 100]; saturation, default: 50 */ ++ bool ex_csc_en; /* RW; range: [0, 1]; extended csc switch for luminance, default: 0 */ ++} ot_vo_csc; ++ ++typedef struct { ++ int csc_coef00; ++ int csc_coef01; ++ int csc_coef02; ++ ++ int csc_coef10; ++ int csc_coef11; ++ int csc_coef12; ++ ++ int csc_coef20; ++ int csc_coef21; ++ int csc_coef22; ++} vdp_csc_coef; ++ ++typedef struct { ++ int csc_in_dc0; ++ int csc_in_dc1; ++ int csc_in_dc2; ++ ++ int csc_out_dc0; ++ int csc_out_dc1; ++ int csc_out_dc2; ++} vdp_csc_dc_coef; ++ ++typedef struct { ++ // for old version csc ++ int csc_coef00; ++ int csc_coef01; ++ int csc_coef02; ++ ++ int csc_coef10; ++ int csc_coef11; ++ int csc_coef12; ++ ++ int csc_coef20; ++ int csc_coef21; ++ int csc_coef22; ++ ++ int csc_in_dc0; ++ int csc_in_dc1; ++ int csc_in_dc2; ++ ++ int csc_out_dc0; ++ int csc_out_dc1; ++ int csc_out_dc2; ++ ++ int new_csc_scale2p; ++ int new_csc_clip_min; ++ int new_csc_clip_max; ++} csc_coef; ++ ++typedef struct { ++ int luma; ++ int cont; ++ int hue; ++ int satu; ++} hal_csc_value; ++ ++#define VO_CSC_DEF_VAL 50 ++#define VO_CSC_LUMA_MAX 100 ++#define VO_CSC_LUMA_MIN 0 ++#define VO_CSC_CONT_MAX 100 ++#define VO_CSC_CONT_MIN 0 ++#define VO_CSC_HUE_MAX 100 ++#define VO_CSC_HUE_MIN 0 ++#define VO_CSC_SAT_MAX 100 ++#define VO_CSC_SAT_MIN 0 ++ ++/* vou 的模块状态 */ ++#define VOU_STATE_STARTED 0 ++#define VOU_STATE_STOPPING 1 ++#define VOU_STATE_STOPPED 2 ++ ++typedef enum { ++ OT_ID_CMPI = 0, ++ OT_ID_VB = 1, ++ OT_ID_SYS = 2, ++ OT_ID_RGN = 3, ++ OT_ID_CHNL = 4, ++ OT_ID_VDEC = 5, ++ OT_ID_AVS = 6, ++ OT_ID_VPSS = 7, ++ OT_ID_VENC = 8, ++ OT_ID_SVP = 9, ++ OT_ID_H264E = 10, ++ OT_ID_JPEGE = 11, ++ OT_ID_H265E = 13, ++ OT_ID_JPEGD = 14, ++ OT_ID_VO = 15, ++ OT_ID_VI = 16, ++ OT_ID_DIS = 17, ++ OT_ID_VALG = 18, ++ OT_ID_RC = 19, ++ OT_ID_AIO = 20, ++ OT_ID_AI = 21, ++ OT_ID_AO = 22, ++ OT_ID_AENC = 23, ++ OT_ID_ADEC = 24, ++ OT_ID_VPU = 25, ++ OT_ID_PCIV = 26, ++ OT_ID_PCIVFMW = 27, ++ OT_ID_ISP = 28, ++ OT_ID_IVE = 29, ++ OT_ID_USER = 30, ++ OT_ID_PROC = 33, ++ OT_ID_LOG = 34, ++ OT_ID_VFMW = 35, ++ OT_ID_GDC = 37, ++ OT_ID_PHOTO = 38, ++ OT_ID_FB = 39, ++ OT_ID_HDMI = 40, ++ OT_ID_VOIE = 41, ++ OT_ID_TDE = 42, ++ OT_ID_HDR = 43, ++ OT_ID_PRORES = 44, ++ OT_ID_VGS = 45, ++ OT_ID_FD = 47, ++ OT_ID_OD = 48, ++ OT_ID_LPR = 50, ++ OT_ID_SVP_NNIE = 51, ++ OT_ID_SVP_DSP = 52, ++ OT_ID_DPU_RECT = 53, ++ OT_ID_DPU_MATCH = 54, ++ ++ OT_ID_MOTIONSENSOR = 55, ++ OT_ID_MOTIONFUSION = 56, ++ ++ OT_ID_GYRODIS = 57, ++ OT_ID_PM = 58, ++ OT_ID_SVP_ALG = 59, ++ OT_ID_IVP = 60, ++ OT_ID_MCF = 61, ++ OT_ID_SVP_MAU = 62, ++ OT_ID_VDA = 63, ++ OT_ID_VPP = 64, ++ OT_ID_KCF = 65, ++ OT_ID_PQP = 66, ++ ++ OT_ID_NPUDEV = 67, ++ OT_ID_AICPU = 68, ++ OT_ID_NPUDFX = 69, ++ OT_ID_TSFW = 70, ++ ++ OT_ID_CIPHER = 71, ++ OT_ID_KLAD = 72, ++ OT_ID_KEYSLOT = 73, ++ OT_ID_OTP = 74, ++ OT_ID_VDEC_ADAPT = 75, ++ OT_ID_DCC = 76, ++ OT_ID_VDEC_SERVER = 77, ++ OT_ID_VFMW_MDC = 78, ++ OT_ID_VB_LOG = 79, ++ OT_ID_MCF_CALIBRATION = 80, ++ OT_ID_SVP_NPU = 81, ++ OT_ID_HNR = 82, ++ OT_ID_SNAP = 83, ++ OT_ID_LOG_MDC = 84, ++ OT_ID_UVC = 85, ++ OT_ID_FISHEYE_CALIBRATION = 86, ++ OT_ID_SYNC = 87, ++ OT_ID_AIV = 88, ++ OT_ID_VO_DEV = 89, ++ OT_ID_IRQ = 90, ++ OT_ID_BUTT, ++} ot_mod_id; ++ ++typedef struct { ++ unsigned int fb_div; /* RW, range: [0, 0xfff]; frequency double division */ ++ unsigned int frac; /* RW, range: [0, 0xffffff]; fractional division */ ++ unsigned int ref_div; /* RW, range: (0, 0x3f]; reference clock division */ ++ unsigned int post_div1; /* RW, range: (0, 0x7]; level 1 post division */ ++ unsigned int post_div2; /* RW, range: (0, 0x7]; level 2 post division */ ++} ot_vo_pll; ++typedef enum { ++ SSC_VDP_DIV_340_TO_600 = 0, /* 340MHz~600MHz, 1div */ ++ SSC_VDP_DIV_200_TO_340 = 1, /* 200MHz~340MHz, 2div */ ++ SSC_VDP_DIV_100_TO_200 = 3, /* 100MHz~200MHz, 4div */ ++ SSC_VDP_DIV_50_TO_100 = 7, /* 50MHz~100MHz, 8div */ ++ SSC_VDP_DIV_25_TO_50 = 15, /* 25MHz~50MHz, 16div */ ++ ++ SSC_VDP_DIV_BUTT ++} vo_hdmi_ssc_vdp_div_mode; ++ ++typedef struct { ++ ot_vo_intf_sync index; ++ ot_vo_pll pll; ++ vo_hdmi_ssc_vdp_div_mode div; ++} vo_pll_param; ++ ++#define COLOR_RGB_RED 0xFF0000 ++#define COLOR_RGB_GREEN 0x00FF00 ++#define COLOR_RGB_BLUE 0x0000FF ++#define COLOR_RGB_BLACK 0x000000 ++#define COLOR_RGB_YELLOW 0xFFFF00 ++#define COLOR_RGB_CYN 0x00ffff ++#define COLOR_RGB_WHITE 0xffffff ++/* ++ * RGB(r,g,b) assemble the r,g,b to 24bit color ++ * RGB_R(c) get RED from 24bit color ++ * RGB_G(c) get GREEN from 24bit color ++ * RGB_B(c) get BLUE from 24bit color ++ */ ++#define RGB(r, g, b) ((((r) & 0xff) << 16) | (((g) & 0xff) << 8) | ((b) & 0xff)) ++#define RGB_R(c) (((c) & 0xff0000) >> 16) ++#define RGB_G(c) (((c) & 0xff00) >> 8) ++#define RGB_B(c) ((c) & 0xff) ++ ++/* ++ * YUV(y,u,v) assemble the y,u,v to 30bit color ++ * YUV_Y(c) get Y from 30bit color ++ * YUV_U(c) get U from 30bit color ++ * YUV_V(c) get V from 30bit color ++ */ ++#define YUV(y, u, v) ((((y) & 0x03ff) << 20) | (((u) & 0x03ff) << 10) | ((v) & 0x03ff)) ++#define YUV_Y(c) (((c) & 0x3ff00000) >> 20) ++#define YUV_U(c) (((c) & 0x000ffc00) >> 10) ++#define YUV_V(c) ((c) & 0x000003ff) ++/* ++ * MAX2(x,y) maximum of x and y ++ * MIN2(x,y) minimum of x and y ++ * MAX3(x,y,z) maximum of x, y and z ++ * MIN3(x,y,z) minimum of x, y and z ++ */ ++#define MAX2(x, y) ((x) > (y) ? (x) : (y)) ++#define MIN2(x, y) ((x) < (y) ? (x) : (y)) ++#define MAX3(x, y, z) ((x) > (y) ? MAX2(x, z) : MAX2(y, z)) ++#define MIN3(x, y, z) ((x) < (y) ? MIN2(x, z) : MIN2(y, z)) ++ ++/* ++ * CLIP3(x,min,max) clip x within [min,max] ++ * value_between(x,min.max) True if x is between [min,max] inclusively. ++ */ ++#define clip_min(x, min) (((x) >= (min)) ? (x) : (min)) ++#define clip3(x, min, max) ((x) < (min) ? (min) : ((x) > (max) ? (max) : (x))) ++#define clip_max(x, max) ((x) > (max) ? (max) : (x)) ++#define value_between(x, min, max) (((x) >= (min)) && ((x) <= (max))) ++ ++typedef struct { ++ unsigned short bkg_a; ++ unsigned short bkg_y; ++ unsigned short bkg_cb; ++ unsigned short bkg_cr; ++} hal_disp_bkcolor; ++ ++/* vou CBM MIXER */ ++typedef enum { ++ HAL_CBMMIX1 = 0, ++ HAL_CBMMIX2 = 1, ++ HAL_CBMMIX3 = 2, ++ ++ HAL_CBMMIX1_BUTT ++} hal_cbmmix; ++ ++/* vou mixer prio id */ ++typedef enum { ++ VOU_MIX_PRIO0 = 0, ++ VOU_MIX_PRIO1, ++ VOU_MIX_PRIO2, ++ VOU_MIX_PRIO3, ++ VOU_MIX_PRIO4, ++ VOU_MIX_BUTT ++} vou_mix_prio; ++#define OT_VO_MAX_PHYS_VIDEO_LAYER_NUM 3 /* max physical video layer num */ ++#define OT_VO_MAX_GFX_LAYER_NUM 3 /* max graphic layer num */ ++/* max physical layer num */ ++#define OT_VO_MAX_PHYS_LAYER_NUM (OT_VO_MAX_PHYS_VIDEO_LAYER_NUM + OT_VO_MAX_GFX_LAYER_NUM) ++#define VO_LAYER_BUTT OT_VO_MAX_PHYS_LAYER_NUM ++/* HFIR VCOEF */ ++typedef struct { ++ int coef0; ++ int coef1; ++ int coef2; ++ int coef3; ++ int coef4; ++ int coef5; ++ int coef6; ++ int coef7; ++} hfir_coef; ++typedef struct { ++ ot_vo_layer layer; ++ unsigned char layer_id; ++} vo_hal_cbm_mixer; ++typedef enum { ++ HAL_INPUTFMT_YCBCR_SEMIPLANAR_400 = 0x1, ++ HAL_INPUTFMT_YCBCR_SEMIPLANAR_420 = 0x2, ++ HAL_INPUTFMT_YCBCR_SEMIPLANAR_422 = 0x3, ++ HAL_INPUTFMT_YCBCR_SEMIPLANAR_444 = 0x4, ++ HAL_INPUTFMT_YCBCR_SEMIPLANAR_411_4X1 = 0x6, ++ HAL_INPUTFMT_YCBCR_SEMIPLANAR_422_2X1 = 0x7, ++ ++ HAL_INPUTFMT_CBYCRY_PACKAGE_422 = 0x9, ++ HAL_INPUTFMT_YCBYCR_PACKAGE_422 = 0xa, ++ HAL_INPUTFMT_YCRYCB_PACKAGE_422 = 0xb, ++ HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0x1000, ++ ++ HAL_INPUTFMT_CLUT_1BPP = 0x00, ++ HAL_INPUTFMT_CLUT_2BPP = 0x10, ++ HAL_INPUTFMT_CLUT_4BPP = 0x20, ++ HAL_INPUTFMT_CLUT_8BPP = 0x30, ++ HAL_INPUTFMT_ACLUT_44 = 0x38, ++ ++ HAL_INPUTFMT_RGB_444 = 0x40, ++ HAL_INPUTFMT_RGB_555 = 0x41, ++ HAL_INPUTFMT_RGB_565 = 0x42, ++ HAL_INPUTFMT_CBYCRY_PACKAGE_422_GRC = 0x43, ++ HAL_INPUTFMT_YCBYCR_PACKAGE_422_GRC = 0x44, ++ HAL_INPUTFMT_YCRYCB_PACKAGE_422_GRC = 0x45, ++ HAL_INPUTFMT_ACLUT_88 = 0x46, ++ HAL_INPUTFMT_ARGB_4444 = 0x48, ++ HAL_INPUTFMT_ARGB_1555 = 0x49, ++ ++ HAL_INPUTFMT_RGB_888 = 0x50, ++ HAL_INPUTFMT_YCBCR_888 = 0x51, ++ HAL_INPUTFMT_ARGB_8565 = 0x5a, ++ HAL_INPUTFMT_ARGB_6666 = 0x5b, ++ ++ HAL_INPUTFMT_KRGB_888 = 0x60, ++ HAL_INPUTFMT_ARGB_8888 = 0x68, ++ HAL_INPUTFMT_AYCBCR_8888 = 0x69, ++ ++ HAL_INPUTFMT_RGBA_4444 = 0xc8, ++ HAL_INPUTFMT_RGBA_5551 = 0xc9, ++ ++ HAL_INPUTFMT_RGBA_6666 = 0xd8, ++ HAL_INPUTFMT_RGBA_5658 = 0xda, ++ ++ HAL_INPUTFMT_RGBA_8888 = 0xe8, ++ HAL_INPUTFMT_YCBCRA_8888 = 0xe9, ++ ++ HAL_DISP_PIXELFORMAT_BUTT ++} hal_disp_pixel_format; ++#define VO_ALPHA_OPACITY 0xFF /* opacity alpha */ ++typedef enum { ++ HAL_HFIRMODE_MEDEN = 0, /* median filtering enable */ ++ HAL_HFIRMODE_COPY, /* chroma HFIR copy */ ++ HAL_HFIRMODE_DOUBLE, /* bilinear interpolation */ ++ HAL_HFIRMODE_6TAPFIR, /* 6 order FIR */ ++ ++ HAL_HFIRMODE_BUTT ++} hal_hfirmode; ++ ++/* vou graphic layer data extend mode */ ++typedef enum { ++ HAL_GFX_BITEXTEND_1ST = 0, ++ HAL_GFX_BITEXTEND_2ND = 0x2, ++ HAL_GFX_BITEXTEND_3RD = 0x3, ++ ++ HAL_GFX_BITEXTEND_BUTT ++} hal_gfx_bitextend; ++ ++typedef enum { ++ FB_VOU_BITEXT_LOW_ZERO = 0x0, ++ FB_VOU_BITEXT_LOW_HIGHBIT = 0x2, ++ FB_VOU_BITEXT_LOW_HIGHBITS = 0x3, ++ FB_VOU_BITEXT_BUTT ++} vou_bitext_mode; ++ ++typedef struct { ++ int x; ++ int y; ++ int width; ++ int height; ++} ot_fb_rect; ++#define GRAPHIC_ALPHA_OPACITY 0xff ++ ++/* vou interrupt mask type */ ++typedef enum { ++ GFBG_INTMSK_NONE = 0, ++ GFBG_INTMSK_DHD0_VTTHD1 = 0x1, ++ GFBG_INTMSK_DHD0_VTTHD2 = 0x2, ++ GFBG_INTMSK_DHD0_VTTHD3 = 0x4, ++ GFBG_INTMSK_DHD0_UFINT = 0x8, ++ ++ GFBG_INTMSK_DHD1_VTTHD1 = 0x10, ++ GFBG_INTMSK_DHD1_VTTHD2 = 0x20, ++ GFBG_INTMSK_DHD1_VTTHD3 = 0x40, ++ GFBG_INTMSK_DHD1_UFINT = 0x80, ++ ++ GFBG_INTMSK_DSD_VTTHD1 = 0x100, ++ GFBG_INTMSK_DSD_VTTHD2 = 0x200, ++ GFBG_INTMSK_DSD_VTTHD3 = 0x400, ++ GFBG_INTMSK_DSD_UFINT = 0x800, ++ ++ GFBG_INTMSK_B0_ERR = 0x1000, ++ GFBG_INTMSK_B1_ERR = 0x2000, ++ GFBG_INTMSK_B2_ERR = 0x4000, ++ ++ GFBG_INTMSK_WBC_DHDOVER = 0x8000, ++ GFBG_INTREPORT_ALL = 0xffffffff ++} gfbg_int_mask; ++ ++typedef struct { ++ int csc_scale2p; ++ int csc_clip_min; ++ int csc_clip_max; ++} csc_coef_param; ++ ++typedef enum { ++ FB_VOU_COLORKEY_IN = 0x0, ++ FB_VOU_COLORKEY_OUT = 0x1, ++ FB_VOU_COLORKEY_BUTT ++} vou_colorkey_mode; ++ ++typedef struct { ++ unsigned int ck_gt_en; ++ unsigned int in_width; ++ unsigned int out_width; ++ unsigned int out_pro; ++ ++ unsigned int hfir_en; ++ unsigned int lhmid_en; ++ unsigned int ahmid_en; ++ unsigned int lhfir_mode; ++ unsigned int ahfir_mode; ++ ++ unsigned int in_height; ++ unsigned int out_height; ++ ++ unsigned int vfir_en; ++ unsigned int lvmid_en; ++ unsigned int avmid_en; ++ unsigned int lvfir_mode; ++ unsigned int avfir_mode; ++} gf_zme_cfg; ++ ++typedef enum { ++ VDP_RMODE_INTERFACE = 0, ++ VDP_RMODE_INTERLACE = 0, ++ VDP_RMODE_PROGRESSIVE = 1, ++ VDP_RMODE_TOP = 2, ++ VDP_RMODE_BOTTOM = 3, ++ VDP_RMODE_PRO_TOP = 4, ++ VDP_RMODE_PRO_BOTTOM = 5, ++ VDP_RMODE_BUTT ++} vdp_data_rmode; ++ ++typedef enum { ++ VDP_G0_ZME_TYP = 0, ++ VDP_G0_ZME_TYP1, ++ VDP_G0_ZME_RAND, ++ VDP_G0_ZME_MAX, ++ VDP_G0_ZME_MIN, ++ VDP_G0_ZME_ZERO, ++ VDP_G0_ZME_BUTT ++} gf_g0_zme_mode; ++#define GFX_MAX_CSC_TABLE 61 ++typedef enum { ++ HAL_CSC_MODE_BT601LIMIT_TO_BT601LIMIT, /* BT601LIMIT to BT601LIMIT */ ++ HAL_CSC_MODE_BT601FULL_TO_BT601LIMIT, /* BT601FULL to BT601LIMIT */ ++ HAL_CSC_MODE_BT709LIMIT_TO_BT601LIMIT, /* BT709LIMIT to BT601LIMIT */ ++ HAL_CSC_MODE_BT709FULL_TO_BT601LIMIT, /* BT709FULL to BT601LIMIT */ ++ ++ HAL_CSC_MODE_BT601LIMIT_TO_BT709LIMIT, /* BT601LIMIT to BT709LIMIT */ ++ HAL_CSC_MODE_BT601FULL_TO_BT709LIMIT, /* BT601FULL to BT709LIMIT */ ++ HAL_CSC_MODE_BT709LIMIT_TO_BT709LIMIT, /* BT709LIMIT to BT709LIMIT */ ++ HAL_CSC_MODE_BT709FULL_TO_BT709LIMIT, /* BT709FULL to BT709LIMIT */ ++ ++ HAL_CSC_MODE_BT601LIMIT_TO_BT601FULL, /* BT601LIMIT to BT601FULL */ ++ HAL_CSC_MODE_BT601FULL_TO_BT601FULL, /* BT601FULL to BT601FULL */ ++ HAL_CSC_MODE_BT709LIMIT_TO_BT601FULL, /* BT709LIMIT to BT601FULL */ ++ HAL_CSC_MODE_BT709FULL_TO_BT601FULL, /* BT709FULL to BT601FULL */ ++ ++ HAL_CSC_MODE_BT601LIMIT_TO_BT709FULL, /* BT601LIMIT to BT709FULL */ ++ HAL_CSC_MODE_BT709LIMIT_TO_BT709FULL, /* BT709LIMIT to BT709FULL */ ++ HAL_CSC_MODE_BT601FULL_TO_BT709FULL, /* BT601FULL to BT709FULL */ ++ HAL_CSC_MODE_BT709FULL_TO_BT709FULL, /* BT709FULL to BT709FULL */ ++ ++ HAL_CSC_MODE_BT601LIMIT_TO_RGBFULL, /* BT601LIMIT to RGBFULL */ ++ HAL_CSC_MODE_BT601FULL_TO_RGBFULL, /* BT601FULL to RGBFULL */ ++ HAL_CSC_MODE_BT709LIMIT_TO_RGBFULL, /* BT709LIMIT to RGBFULL */ ++ HAL_CSC_MODE_BT709FULL_TO_RGBFULL, /* BT709FULL to RGBFULL */ ++ ++ HAL_CSC_MODE_BT601LIMIT_TO_RGBLIMIT, /* BT601LIMIT to RGBLIMIT */ ++ HAL_CSC_MODE_BT601FULL_TO_RGBLIMIT, /* BT601FULL to RGBLIMIT */ ++ HAL_CSC_MODE_BT709LIMIT_TO_RGBLIMIT, /* BT709LIMIT to RGBLIMIT */ ++ HAL_CSC_MODE_BT709FULL_TO_RGBLIMIT, /* BT709FULL to RGBLIMIT */ ++ ++ HAL_CSC_MODE_RGBFULL_TO_BT601LIMIT, /* RGBFULL to BT601LIMIT */ ++ HAL_CSC_MODE_RGBFULL_TO_BT601FULL, /* RGBFULL to BT601FULL */ ++ HAL_CSC_MODE_RGBFULL_TO_BT709LIMIT, /* RGBFULL to BT709LIMIT */ ++ HAL_CSC_MODE_RGBFULL_TO_BT709FULL, /* RGBFULL to BT709FULL */ ++ HAL_CSC_MODE_RGBFULL_TO_RGBFULL, /* RGBFULL to RGBFULL */ ++ HAL_CSC_MODE_RGBFULL_TO_RGBLIMIT, /* RGBFULLto RGBLIMIT */ ++ ++ HAL_CSC_MODE_BUTT ++} hal_csc_mode; ++ ++typedef struct { ++ ot_vo_csc_matrix csc_matrix; /* CSC matrix */ ++ unsigned int luma; /* RW Range: [0, 100] luminance, default: 50 */ ++ unsigned int contrast; /* RW Range: [0, 100] contrast, default: 50 */ ++ unsigned int hue; /* RW Range: [0, 100] hue, default: 50 */ ++ unsigned int satuature; /* RW Range: [0, 100] satuature, default: 50 */ ++} vo_csc; ++#define GFX_CSC_SCALE 0xa ++#define GFX_CSC_CLIP_MIN 0x0 ++#define GFX_CSC_CLIP_MAX 0x3ff ++#define VOU1_IRQ_NR 193 ++ ++typedef enum { ++ HAL_DISP_ZMEMODE_HORL = 0, ++ HAL_DISP_ZMEMODE_HORC, ++ HAL_DISP_ZMEMODE_VERL, ++ HAL_DISP_ZMEMODE_VERC, ++ ++ HAL_DISP_ZMEMODE_HOR, ++ HAL_DISP_ZMEMODE_VER, ++ HAL_DISP_ZMEMODE_ALPHA, ++ HAL_DISP_ZMEMODE_ALPHAV, ++ HAL_DISP_ZMEMODE_VERT, ++ HAL_DISP_ZMEMODE_VERB, ++ ++ HAL_DISP_ZMEMODE_ALL, ++ HAL_DISP_ZMEMODE_NONL, ++ HAL_DISP_ZMEMODE_BUTT ++} hal_disp_zmemode; ++ ++typedef enum { ++ HAL_DISP_ZME_OUTFMT420 = 0, ++ HAL_DISP_ZME_OUTFMT422, ++ HAL_DISP_ZME_OUTFMT444, ++ HAL_DISP_ZME_OUTFMT_BUTT ++} hal_disp_zme_outfmt; ++ ++typedef enum { ++ OT_VIDEO_FIELD_TOP = 1, /* even field */ ++ OT_VIDEO_FIELD_BOTTOM = 2, /* odd field */ ++ OT_VIDEO_FIELD_INTERLACED = 3, /* two interlaced fields */ ++ OT_VIDEO_FIELD_FRAME = 4, /* frame */ ++ ++ OT_VIDEO_FIELD_BUTT ++} ot_video_field; ++ ++/* we ONLY define picture format used, all unused will be deleted! */ ++typedef enum { ++ OT_PIXEL_FORMAT_RGB_444 = 0, ++ OT_PIXEL_FORMAT_RGB_555, ++ OT_PIXEL_FORMAT_RGB_565, ++ OT_PIXEL_FORMAT_RGB_888, ++ ++ OT_PIXEL_FORMAT_BGR_444, ++ OT_PIXEL_FORMAT_BGR_555, ++ OT_PIXEL_FORMAT_BGR_565, ++ OT_PIXEL_FORMAT_BGR_888, ++ ++ OT_PIXEL_FORMAT_ARGB_1555, ++ OT_PIXEL_FORMAT_ARGB_4444, ++ OT_PIXEL_FORMAT_ARGB_8565, ++ OT_PIXEL_FORMAT_ARGB_8888, ++ OT_PIXEL_FORMAT_ARGB_2BPP, ++ OT_PIXEL_FORMAT_ARGB_CLUT2, ++ OT_PIXEL_FORMAT_ARGB_CLUT4, ++ ++ OT_PIXEL_FORMAT_ABGR_1555, ++ OT_PIXEL_FORMAT_ABGR_4444, ++ OT_PIXEL_FORMAT_ABGR_8565, ++ OT_PIXEL_FORMAT_ABGR_8888, ++ ++ OT_PIXEL_FORMAT_RGB_BAYER_8BPP, ++ OT_PIXEL_FORMAT_RGB_BAYER_10BPP, ++ OT_PIXEL_FORMAT_RGB_BAYER_12BPP, ++ OT_PIXEL_FORMAT_RGB_BAYER_14BPP, ++ OT_PIXEL_FORMAT_RGB_BAYER_16BPP, ++ ++ OT_PIXEL_FORMAT_YVU_PLANAR_422, ++ OT_PIXEL_FORMAT_YVU_PLANAR_420, ++ OT_PIXEL_FORMAT_YVU_PLANAR_444, ++ ++ OT_PIXEL_FORMAT_YVU_SEMIPLANAR_422, ++ OT_PIXEL_FORMAT_YVU_SEMIPLANAR_420, ++ OT_PIXEL_FORMAT_YVU_SEMIPLANAR_444, ++ ++ OT_PIXEL_FORMAT_YUV_SEMIPLANAR_422, ++ OT_PIXEL_FORMAT_YUV_SEMIPLANAR_420, ++ OT_PIXEL_FORMAT_YUV_SEMIPLANAR_444, ++ ++ OT_PIXEL_FORMAT_YUYV_PACKAGE_422, ++ OT_PIXEL_FORMAT_YVYU_PACKAGE_422, ++ OT_PIXEL_FORMAT_UYVY_PACKAGE_422, ++ OT_PIXEL_FORMAT_VYUY_PACKAGE_422, ++ OT_PIXEL_FORMAT_YYUV_PACKAGE_422, ++ OT_PIXEL_FORMAT_YYVU_PACKAGE_422, ++ OT_PIXEL_FORMAT_UVYY_PACKAGE_422, ++ OT_PIXEL_FORMAT_VUYY_PACKAGE_422, ++ OT_PIXEL_FORMAT_VY1UY0_PACKAGE_422, ++ ++ OT_PIXEL_FORMAT_YUV_400, ++ OT_PIXEL_FORMAT_UV_420, ++ ++ /* SVP data format */ ++ OT_PIXEL_FORMAT_BGR_888_PLANAR, ++ OT_PIXEL_FORMAT_HSV_888_PACKAGE, ++ OT_PIXEL_FORMAT_HSV_888_PLANAR, ++ OT_PIXEL_FORMAT_LAB_888_PACKAGE, ++ OT_PIXEL_FORMAT_LAB_888_PLANAR, ++ OT_PIXEL_FORMAT_S8C1, ++ OT_PIXEL_FORMAT_S8C2_PACKAGE, ++ OT_PIXEL_FORMAT_S8C2_PLANAR, ++ OT_PIXEL_FORMAT_S8C3_PLANAR, ++ OT_PIXEL_FORMAT_S16C1, ++ OT_PIXEL_FORMAT_U8C1, ++ OT_PIXEL_FORMAT_U16C1, ++ OT_PIXEL_FORMAT_S32C1, ++ OT_PIXEL_FORMAT_U32C1, ++ OT_PIXEL_FORMAT_U64C1, ++ OT_PIXEL_FORMAT_S64C1, ++ ++ OT_PIXEL_FORMAT_BUTT ++} ot_pixel_format; ++ ++ ++typedef enum { ++ OT_VIDEO_FORMAT_LINEAR = 0, /* nature video line */ ++ OT_VIDEO_FORMAT_TILE_64x16, /* tile cell: 64pixel x 16line */ ++ OT_VIDEO_FORMAT_TILE_16x8, /* tile cell: 16pixel x 8line */ ++ OT_VIDEO_FORMAT_BUTT ++} ot_video_format; ++ ++typedef enum { ++ OT_COMPRESS_MODE_NONE = 0, /* no compress */ ++ OT_COMPRESS_MODE_SEG, /* compress unit is 256x1 bytes as a segment. */ ++ OT_COMPRESS_MODE_SEG_COMPACT, /* compact compress unit is 256x1 bytes as a segment. */ ++ OT_COMPRESS_MODE_TILE, /* compress unit is a tile. */ ++ OT_COMPRESS_MODE_LINE, /* compress unit is the whole line. */ ++ OT_COMPRESS_MODE_FRAME, /* compress unit is the whole frame. YUV for VPSS(3DNR) */ ++ ++ OT_COMPRESS_MODE_BUTT ++} ot_compress_mode; ++ ++typedef enum { ++ OT_DYNAMIC_RANGE_SDR8 = 0, ++ OT_DYNAMIC_RANGE_SDR10, ++ OT_DYNAMIC_RANGE_HDR10, ++ OT_DYNAMIC_RANGE_HLG, ++ OT_DYNAMIC_RANGE_SLF, ++ OT_DYNAMIC_RANGE_XDR, ++ OT_DYNAMIC_RANGE_BUTT ++} ot_dynamic_range; ++ ++ ++typedef enum { ++ OT_COLOR_GAMUT_BT601 = 0, ++ OT_COLOR_GAMUT_BT709, ++ OT_COLOR_GAMUT_BT2020, ++ OT_COLOR_GAMUT_USER, ++ OT_COLOR_GAMUT_BUTT ++} ot_color_gamut; ++#define OT_MAX_COLOR_COMPONENT 2 ++#define OT_ALIGN_NUM 8 ++#define ATTRIBUTE __attribute__((aligned(OT_ALIGN_NUM))) ++#define OT_MAX_USER_DATA_NUM 2 ++ ++typedef struct { ++ phys_addr_t misc_info_phys_addr; /* default allocated buffer */ ++ phys_addr_t jpeg_dcf_phys_addr; ++ phys_addr_t isp_info_phys_addr; ++ phys_addr_t low_delay_phys_addr; ++ phys_addr_t bnr_rnt_phys_addr; ++ phys_addr_t motion_data_phys_addr; ++ phys_addr_t frame_dng_phys_addr; ++ ++ void* ATTRIBUTE misc_info_virt_addr; /* misc info */ ++ void* ATTRIBUTE jpeg_dcf_virt_addr; /* jpeg_dcf, used in JPEG DCF */ ++ void* ATTRIBUTE isp_info_virt_addr; /* isp_frame_info, used in ISP debug, when get raw and send raw */ ++ void* ATTRIBUTE low_delay_virt_addr; /* used in low delay */ ++ void* ATTRIBUTE bnr_mot_virt_addr; /* used for 3dnr from bnr mot */ ++ void* ATTRIBUTE motion_data_virt_addr; /* vpss 3dnr use: gme motion data, filter motion data, gyro data. */ ++ void* ATTRIBUTE frame_dng_virt_addr; ++} ot_video_supplement; ++ ++typedef struct { ++ unsigned int width; ++ unsigned int height; ++ ot_video_field field; ++ ot_pixel_format pixel_format; ++ ot_video_format video_format; ++ ot_compress_mode compress_mode; ++ ot_dynamic_range dynamic_range; ++ ot_color_gamut color_gamut; ++ ++ unsigned int header_stride[OT_MAX_COLOR_COMPONENT]; ++ unsigned int stride[OT_MAX_COLOR_COMPONENT]; ++ ++ phys_addr_t header_phys_addr[OT_MAX_COLOR_COMPONENT]; ++ phys_addr_t phys_addr[OT_MAX_COLOR_COMPONENT]; ++ void* ATTRIBUTE header_virt_addr[OT_MAX_COLOR_COMPONENT]; ++ void* ATTRIBUTE virt_addr[OT_MAX_COLOR_COMPONENT]; ++ ++ unsigned int time_ref; ++ unsigned long long pts; ++ ++ unsigned long long user_data[OT_MAX_USER_DATA_NUM]; ++ unsigned int frame_flag; /* frame_flag, can be OR operation. */ ++ ot_video_supplement supplement; ++} ot_video_frame; ++ ++typedef struct { ++ ot_video_frame video_frame; ++ unsigned int pool_id; ++ ot_mod_id mod_id; ++} ot_video_frame_info; ++ ++#define MAX_OFFSET 3 ++#define MIN_OFFSET (-1) ++ ++typedef enum { ++ VO_ZME_TYP = 0, ++ VO_ZME_TYP1, ++ VO_ZME_RAND, ++ VO_ZME_MAX, ++ VO_ZME_MIN, ++ VO_ZME_ZERO, ++ VO_ZME_BUTT ++} vo_zme_mode; ++#if 0 ++typedef enum { ++ VO_INT_MODE_FRAME = 0x0, ++ VO_INT_MODE_FIELD = 0x1, ++ VO_INT_MODE_BUTT ++} vo_int_mode; ++#endif ++typedef struct { ++ unsigned int zme_vprec; ++ unsigned int zme_hprec; ++} vo_zme_ds_info; ++ ++typedef enum { ++ VDP_PROC_FMT_SP_420 = 0x0, ++ VDP_PROC_FMT_SP_422 = 0x1, ++ VDP_PROC_FMT_SP_444 = 0x2, ++ VDP_PROC_FMT_RGB_888 = 0x3, ++ VDP_PROC_FMT_RGB_444 = 0x4, ++ ++ VDP_PROC_FMT_BUTT ++} vdp_proc_fmt; ++ ++typedef struct { ++ unsigned int vluma_offset; ++ unsigned int vchroma_offset; ++ unsigned int vbluma_offset; ++ unsigned int vbchroma_offset; ++ unsigned int lhfir_offset; ++ unsigned int chfir_offset; ++ unsigned int vl_flatdect_mode; ++ unsigned int vl_coringadj_en; ++ unsigned int vl_gain; ++ unsigned int vl_coring; ++ unsigned int vc_flatdect_mode; ++ unsigned int vc_coringadj_en; ++ unsigned int vc_gain; ++ unsigned int vc_coring; ++ unsigned int hl_flatdect_mode; ++ unsigned int hl_coringadj_en; ++ unsigned int hl_gain; ++ unsigned int hl_coring; ++ unsigned int hc_flatdect_mode; ++ unsigned int hc_coringadj_en; ++ unsigned int hc_gain; ++ unsigned int hc_coring; ++} vo_zme_comm_pq_cfg; ++ ++typedef struct { ++ unsigned int ck_gt_en; ++ unsigned int out_pro; ++ unsigned int out_fmt; ++ unsigned long long in_height; ++ unsigned long long out_height; ++ unsigned long long in_width; ++ unsigned long long out_width; ++ unsigned int cvfir_en; ++ unsigned int cvmid_en; ++ unsigned int cvfir_mode; ++ ++ unsigned int hfir_order; ++ unsigned int lhfir_en; ++ unsigned int chfir_en; ++ unsigned int lhmid_en; ++ unsigned int chmid_en; ++ unsigned int non_lnr_en; ++ unsigned int lhfir_mode; ++ unsigned int chfir_mode; ++ unsigned int hl_shootctrl_en; ++ unsigned int hl_shootctrl_mode; ++ unsigned int hc_shootctrl_en; ++ unsigned int hc_shootctrl_mode; ++ ++ unsigned int in_pro; ++ unsigned int graphdet_en; ++ ++ unsigned int lvfir_en; ++ unsigned int lvmid_en; ++ unsigned int vfir_1tap_en; ++ unsigned int lvfir_mode; ++ unsigned int vl_shootctrl_en; ++ unsigned int vl_shootctrl_mode; ++ unsigned int vc_shootctrl_en; ++ unsigned int vc_shootctrl_mode; ++} vdp_v1_cvfir_cfg; ++ ++typedef struct { ++ unsigned int ck_gt_en; ++ unsigned int hfir_order; ++ unsigned int lhfir_en; ++ unsigned int chfir_en; ++ unsigned int lhmid_en; ++ unsigned int chmid_en; ++ unsigned int non_lnr_en; ++ unsigned int lhfir_mode; ++ unsigned int chfir_mode; ++ unsigned int hl_shootctrl_en; ++ unsigned int hl_shootctrl_mode; ++ unsigned int hc_shootctrl_en; ++ unsigned int hc_shootctrl_mode; ++ ++ unsigned int in_pro; ++ unsigned int out_pro; ++ unsigned int out_fmt; ++ unsigned long long in_height; ++ unsigned long long out_height; ++ unsigned long long in_width; ++ unsigned long long out_width; ++ unsigned int graphdet_en; ++ ++ unsigned int lvfir_en; ++ unsigned int cvfir_en; ++ unsigned int lvmid_en; ++ unsigned int cvmid_en; ++ unsigned int vfir_1tap_en; ++ unsigned int lvfir_mode; ++ unsigned int cvfir_mode; ++ unsigned int vl_shootctrl_en; ++ unsigned int vl_shootctrl_mode; ++ unsigned int vc_shootctrl_en; ++ unsigned int vc_shootctrl_mode; ++} vo_v0_zme_cfg; ++ ++typedef enum { ++ XDP_V0_HFIR_BYPASS = 0, ++ XDP_V0_HFIR_COPY, ++ XDP_V0_HFIR_BILT, ++ XDP_V0_HFIR_FILT, ++ XDP_V0_HFIR_BUTT ++} xdp_v0_hfir_mode; ++ ++typedef struct { ++ unsigned int ck_gt_en; ++ unsigned int mid_en; ++ xdp_v0_hfir_mode hfir_mode; ++} vo_v0_hfir_cfg; ++ ++typedef struct { ++ unsigned int ot_hdr_y2r_en; ++ unsigned int ot_hdr_y2r_ck_gt_en; ++ ++ unsigned int ot_hdr_v0_y2r_en; ++ unsigned int ot_hdr_v1_y2r_en; ++ unsigned int ot_hdr_v0_vhdr_en; ++ unsigned int ot_hdr_v1_vhdr_en; ++ unsigned int ot_hdr_v0_cl_en; ++ unsigned int ot_hdr_v1_cl_en; ++ ++ unsigned int ot_hdr_v_demo_en; ++ unsigned int ot_hdr_v_demo_mode; ++ unsigned int ot_hdr_v_demo_pos; ++} vo_csc_v0_cfg; ++ ++typedef struct { ++ unsigned int vhdr_en; ++ unsigned int vhdr_ck_gt_en; ++ unsigned int vhdr_degmm_en; ++ unsigned int vhdr_gamut_en; ++ unsigned int vhdr_tmap_en; ++ unsigned int vhdr_gmm_en; ++ unsigned int vhdr_dither_en; ++ unsigned int vhdr_r2y_en; ++ unsigned int vhdr_cadj_en; ++ unsigned int vhdr_gamut_bind; ++ ++ unsigned int vhdr_dither_round_unlim; ++ unsigned int vhdr_dither_round; ++ unsigned int vhdr_dither_domain_mode; ++ unsigned int vhdr_dither_tap_mode; ++} vo_ot_hdr_v_cfg; ++ ++typedef struct { ++ unsigned int vid_iw; ++ unsigned int vid_ih; ++ unsigned int vid_ow; ++ unsigned int vid_oh; ++ ++ unsigned int zme_en; ++ unsigned int hfir_en; ++ unsigned int csc_en; ++ unsigned int hdr_en; ++ ++ vo_v0_zme_cfg zme_cfg; ++ vo_v0_hfir_cfg hfir_cfg; ++ vo_csc_v0_cfg yuv2_rgb_cfg; ++ vo_ot_hdr_v_cfg v_ot_hdr_cfg; ++} vdp_vid_ip_cfg; ++ ++typedef struct { ++ int x; ++ int y; ++ unsigned int width; ++ unsigned int height; ++} ot_rect; ++ ++void drm_overlay_update(ot_video_frame_info *p_frame_info); ++#endif /* _SMART_VOP_REG_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include/drv_vo_comm.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include/drv_vo_comm.h +new file mode 100755 +index 000000000..55bc6e989 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include/drv_vo_comm.h +@@ -0,0 +1,168 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef DRV_VO_COMM_H ++#define DRV_VO_COMM_H ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++///test start ++#define VO_MAX_ZME_PHASE 17 ++#define VO_MAX_ZME_TAP 8 ++ ++/* ++ * 严重注意: ++ * 寄存器上获取的比率 ratio = 输入分辨率/输出分辨率 ++ * 而算法给出的比率 ratio = 输出分辨率/输入分辨率 (HERE USE) ++ */ ++typedef enum { ++ VOU_ZOOM_COEF_UP_1 = 0, ++ VOU_ZOOM_COEF_EQU_1, ++ VOU_ZOOM_COEF_075, ++ VOU_ZOOM_COEF_0666, ++ VOU_ZOOM_COEF_05, ++ VOU_ZOOM_COEF_04, ++ VOU_ZOOM_COEF_0375, ++ VOU_ZOOM_COEF_033, ++ VOU_ZOOM_COEF_0, ++ VOU_ZOOM_COEF_BUTT ++} vou_zoom_coef; ++ ++typedef enum { ++ VOU_ZOOM_TAP_6LH = 0, ++ VOU_ZOOM_TAP_4CH, ++ VOU_ZOOM_TAP_4LV, ++ VOU_ZOOM_TAP_4CV, ++ VOU_ZOOM_TAP_BUTT ++} vou_zoom_tap; ++///test end ++ ++typedef enum { ++ /* for video surface interface */ ++ VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_400 = 0x1, ++ VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_420 = 0x2, ++ VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_422 = 0x3, ++ VOU_LAYER_PIXEL_FORMAT_BUTT ++} vou_layer_pixel_format; ++ ++/* vou interrupt mask type */ ++typedef enum { ++ VO_INTMSK_NONE = 0, ++ VO_INTMSK_DHD0_VTTHD1 = 0x1, ++ VO_INTMSK_DHD0_VTTHD2 = 0x2, ++ VO_INTMSK_DHD0_VTTHD3 = 0x4, ++ VO_INTMSK_DHD0_UFINT = 0x8, ++ ++ VO_INTMSK_DHD1_VTTHD1 = 0x10, ++ VO_INTMSK_DHD1_VTTHD2 = 0x20, ++ VO_INTMSK_DHD1_VTTHD3 = 0x40, ++ VO_INTMSK_DHD1_UFINT = 0x80, ++ ++ VO_INTMSK_DSD_VTTHD1 = 0x100, ++ VO_INTMSK_DSD_VTTHD2 = 0x200, ++ VO_INTMSK_DSD_VTTHD3 = 0x400, ++ VO_INTMSK_DSD_UFINT = 0x800, ++ ++ VO_INTMSK_B0_ERR = 0x1000, ++ VO_INTMSK_B1_ERR = 0x2000, ++ VO_INTMSK_B2_ERR = 0x4000, ++ ++ VO_INTMSK_WBC_DHDOVER = 0x8000, ++ ++ VO_INTMSK_VGA_VDAC = 0x70000, /* INT VDAC0/VDAC1/VDAC2 */ ++ VO_INTMSK_CVBS_VDAC = 0x80000, /* INT VDAC3 */ ++ ++ VO_INTMSK_V0_TUNL_INT = 0x100000, ++ VO_INTMSK_V1_TUNL_INT = 0x200000, ++ ++ VO_INTREPORT_ALL = 0xffffffff ++} vo_int_mask; ++ ++typedef enum { ++ VO_INT_MODE_FRAME = 0x0, ++ VO_INT_MODE_FIELD = 0x1, ++ VO_INT_MODE_BUTT ++} vo_int_mode; ++ ++typedef struct vo_all_int_type { ++ int vtth_dev[OT_VO_MAX_PHYS_DEV_NUM]; ++ int vga_dev; ++ int cvbs_dev; ++} vo_int_type; ++ ++ ++typedef struct { ++ unsigned long long start_phys_addr; ++ void *start_vir_addr; ++ unsigned int size; ++} vo_mmz_buffer; ++ ++typedef struct { ++ vo_mmz_buffer buf_base_addr; ++ unsigned int u32size; ++ ++ unsigned char *coef_vir_addr[VO_COEF_BUF_BUTT]; ++ unsigned long long coef_phys_addr[VO_COEF_BUF_BUTT]; ++} vo_coef_addr; ++ ++typedef struct { ++ unsigned int data3; ++ unsigned int data2; ++ unsigned int data1; ++ unsigned int data0; ++ unsigned int depth; ++} vo_drv_u128; ++ ++typedef enum { ++ DRV_COEF_DATA_TYPE_U8 = 0, ++ DRV_COEF_DATA_TYPE_S8, ++ DRV_COEF_DATA_TYPE_U16, ++ DRV_COEF_DATA_TYPE_S16, ++ DRV_COEF_DATA_TYPE_U32, ++ DRV_COEF_DATA_TYPE_S32, ++ DRV_COEF_DATA_TYPE_BUTT ++} vo_drv_coef_data_type; ++ ++typedef enum { ++ VO_RM_COEF_MODE_TYP = 0x0, ++} vo_rm_coef_mode; ++ ++typedef struct { ++ vo_rm_coef_mode coef_mode; ++ unsigned int phase; ++ unsigned int tap; ++ short (*typ_lut)[VO_MAX_ZME_TAP]; ++ short (*gen_lut)[VO_MAX_ZME_TAP]; ++ short *max_val; ++ short *min_val; ++} vo_zme_coef_gen_info; ++ ++ ++ ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#endif /* end of DRV_VO_COMM_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo.h +new file mode 100755 +index 000000000..ec7a43539 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo.h +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HAL_VO_H ++#define HAL_VO_H ++ ++#include "hal_vo_reg.h" ++#include "hal_vo_def.h" ++#include "inner_vo.h" ++#include "sys_cmp.h" ++#include "hal_vo_comm.h" ++#include "hal_vo_dev.h" ++#include "hal_vo_video.h" ++#include "hal_vo_layer_comm.h" ++#include "hal_vo_gfx_comm.h" ++#include "mkp_vo.h" ++#include "ot_comm_irq.h" ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#if vo_desc("UBOOT_VO") ++ ++#if vo_desc("hal pub") ++volatile reg_vdp_regs *vo_hal_get_reg(td_void); ++td_void vo_hal_set_reg(volatile reg_vdp_regs *reg); ++#endif ++ ++#if vo_desc("get abs addr") ++td_ulong vou_get_abs_addr(hal_disp_layer layer, td_ulong reg); ++td_ulong vou_get_chn_abs_addr(ot_vo_dev dev, td_ulong reg); ++td_ulong vou_get_vid_abs_addr(hal_disp_layer layer, td_ulong reg); ++td_ulong vou_get_gfx_abs_addr(hal_disp_layer layer, td_ulong reg); ++#endif ++ ++#endif /* #if vo_desc("UBOOT_VO") */ ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#endif /* end of HAL_VO_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_def.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_def.h +new file mode 100755 +index 000000000..abc869af5 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_def.h +@@ -0,0 +1,235 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HAL_VO_DEF_H ++#define HAL_VO_DEF_H ++ ++#include "ot_defines.h" ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++ ++ ++#define VHD_REGS_LEN 0x1000 /* len of V0's regs */ ++#define GFX_REGS_LEN 0x800 ++#define DHD_REGS_LEN 0x1000 ++#define VID_REGS_LEN 0x200 /* len of VID regs */ ++#define GRF_REGS_LEN 0x200 /* len of GFX regs */ ++ ++/* offset define */ ++/* 0x200 bytes, 0x200/4 regs */ ++#define FDR_VID_OFFSET (0x200 / 4) ++ ++#define ZME_HPREC (1 << 20) ++#define ZME_VPREC (1 << 12) ++ ++#define VO_INPUT_BIT_WIDTH_10 10 ++ ++#define VO_OUTPUT_BIT_WIDTH_10 10 ++#define VO_OUTPUT_BIT_WIDTH_6 6 ++ ++typedef enum { ++ VO_DEV_DHD0 = 0, /* ultra high definition device */ ++ VO_DEV_DHD1 = 1, /* high definition device */ ++ VO_DEV_BUTT ++} vo_hal_dev; ++ ++typedef enum { ++ VO_HAL_LAYER_VHD0 = 0, /* V0 layer */ ++ VO_HAL_LAYER_VHD1 = 1, /* V1 layer */ ++ VO_HAL_LAYER_VHD2 = 2, /* V2 layer */ ++ ++ VO_HAL_LAYER_BUTT ++} vo_hal_layer; ++ ++typedef enum { ++ VO_SW_LAYER_VHD0 = 0, ++ VO_SW_LAYER_VHD1 = 1, ++ VO_SW_LAYER_VHD2 = 2, ++ ++ VO_SW_LAYER_VIRT0 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_0), ++ VO_SW_LAYER_VIRT1 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_1), ++ VO_SW_LAYER_VIRT2 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_2), ++ VO_SW_LAYER_VIRT3 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_3), ++ VO_SW_LAYER_VIRT31 = (VO_SW_LAYER_VIRT0 + OT_VO_MAX_VIRT_DEV_NUM), ++ ++ VOU_SW_LAYER_BUTT ++} vo_sw_layer; ++#if 0 ++typedef enum { ++ HAL_DISP_LAYER_VHD0 = 0, ++ HAL_DISP_LAYER_VHD1 = 1, ++ HAL_DISP_LAYER_VHD2 = 2, ++ ++ HAL_DISP_LAYER_GFX0 = 3, ++ HAL_DISP_LAYER_GFX1 = 4, ++ HAL_DISP_LAYER_GFX3 = 5, ++ HAL_DISP_LAYER_BUTT, ++} hal_disp_layer; ++#endif ++ ++typedef enum { ++ HAL_DISP_LAYER_VHD0 = 0, ++ HAL_DISP_LAYER_VHD1 = 1, ++ HAL_DISP_LAYER_VHD2 = 2, ++ HAL_DISP_LAYER_VSD0 = 3, ++ ++ HAL_DISP_LAYER_GFX0 = 4, ++ HAL_DISP_LAYER_GFX1 = 5, ++ HAL_DISP_LAYER_GFX2 = 6, ++ HAL_DISP_LAYER_GFX3 = 7, ++ HAL_DISP_LAYER_GFX4 = 8, ++ ++ HAL_DISP_LAYER_WBC = 9, ++ HAL_DISP_LAYER_BUTT, ++} hal_disp_layer; ++ ++ ++#define DEV_PHY_START VO_DEV_DHD0 ++#define DEV_PHY_END VO_DEV_DHD1 ++ ++#define LAYER_VID_START HAL_DISP_LAYER_VHD0 /* VHD0 */ ++#define LAYER_VID_END HAL_DISP_LAYER_VHD2 /* VHD2 */ ++#define LAYER_PHY_END VO_SW_LAYER_VHD2 ++ ++#define LAYER_GFX_START HAL_DISP_LAYER_GFX0 /* GFX0 */ ++#define LAYER_GFX_END HAL_DISP_LAYER_GFX2 /* GFX3 */ ++ ++typedef struct { ++ unsigned int dither_sed_y0; ++ unsigned int dither_sed_u0; ++ unsigned int dither_sed_v0; ++ unsigned int dither_sed_w0; ++ ++ unsigned int dither_sed_y1; ++ unsigned int dither_sed_u1; ++ unsigned int dither_sed_v1; ++ unsigned int dither_sed_w1; ++ ++ unsigned int dither_sed_y2; ++ unsigned int dither_sed_u2; ++ unsigned int dither_sed_v2; ++ unsigned int dither_sed_w2; ++ ++ unsigned int dither_sed_y3; ++ unsigned int dither_sed_u3; ++ unsigned int dither_sed_v3; ++ unsigned int dither_sed_w3; ++} vo_dihter_sed; ++ ++typedef enum { ++ DITHER_IO_MODE_12_10 = 1, ++ DITHER_IO_MODE_12_8 = 2, /* for rgb24bit */ ++ DITHER_IO_MODE_10_8 = 3, ++ DITHER_IO_MODE_10_6 = 4, /* for rgb16bit, rgb18bit */ ++ DITHER_IO_MODE_BUTT ++} dither_io_mode; ++ ++typedef enum { ++ DITHER_MODE_10BIT = 0, ++ DITHER_MODE_8BIT = 1, ++ DITHER_MODE_BUTT ++} dither_mode; ++ ++typedef enum { ++ DITHER_OWIDTH_MODE_5BIT = 0, ++ DITHER_OWIDTH_MODE_6BIT = 1, ++ DITHER_OWIDTH_MODE_7BIT = 2, ++ DITHER_OWIDTH_MODE_8BIT = 3, ++ DITHER_OWIDTH_MODE_9BIT = 4, ++ DITHER_OWIDTH_MODE_10BIT = 5, ++ DITHER_OWIDTH_MODE_BUTT ++} dither_owidth_mode; ++ ++typedef enum { ++ DITHER_IWIDTH_MODE_8BIT = 0, ++ DITHER_IWIDTH_MODE_9BIT = 1, ++ DITHER_IWIDTH_MODE_10BIT = 2, ++ DITHER_IWIDTH_MODE_11BIT = 3, ++ DITHER_IWIDTH_MODE_12BIT = 4, ++ DITHER_IWIDTH_MODE_BUTT ++} dither_iwidth_mode; ++ ++typedef struct { ++ dither_io_mode io_mode; ++ ++ unsigned int dither_en; ++ unsigned int dither_mode; ++ unsigned int dither_round; ++ unsigned int dither_round_unlim; ++ unsigned int i_data_width_dither; ++ unsigned int o_data_width_dither; ++ unsigned int dither_domain_mode; ++ unsigned int dither_tap_mode; ++ vo_dihter_sed dither_sed; ++ unsigned int dither_thr_max; ++ unsigned int dither_thr_min; ++} vdp_dither_cfg; ++ ++ ++ ++ ++ ++#define MAX_REGION_NUM 64 ++#define V0_REGION_NUM 64 ++#define V1_REGION_NUM 1 ++#define V2_REGION_NUM 1 ++#define VIRT_LAYER_REGION_NUM 64 ++ ++/* 提前6ms（预估值）上报VTTH */ ++#define VO_DEAULT_VTTH_TIME 6 ++ ++#define MRG_REGS_LEN 0xc00 /* len of v0 mrg regs */ ++ ++#define MRG_OFFSET_ADDR 0x12000 ++ ++/* for CMP and DCMP */ ++#define CMP_SEG_OFFSET (0x80 / 4) ++#define DCMP_SEG_OFFSET (0x20 / 4) ++ ++#define VO_DEV_DSD_START VO_DEV_DSD0 ++#define VO_DEV_DSD_END VO_DEV_DSD0 ++ ++#define VO_DEV_DHD_START VO_DEV_DHD0 ++#define VO_DEV_DHD_END VO_DEV_DHD1 ++ ++typedef enum { ++ VO_COEF_BUF_REGION_V0 = 8, ++ VO_COEF_BUF_REGION_V1 = 9, ++ ++ VO_COEF_BUF_BUTT = 10 ++} vo_coef_buf; ++ ++#define VO_ALL_COEF_SIZE COEF_SIZE_REGION_V0 ++#define COEF_SIZE_REGION_V0 (192 * 128 / 8) ++ ++#define LAYER_MRG_START HAL_DISP_LAYER_VHD0 ++#define LAYER_MRG_END HAL_DISP_LAYER_VHD1 ++ ++ ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif ++#endif /* end of #ifdef __cplusplus */ ++#endif /* end of HAL_VO_DEF_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_dev.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_dev.h +new file mode 100755 +index 000000000..fdee23fe6 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_dev.h +@@ -0,0 +1,76 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HAL_VO_DEV_H ++#define HAL_VO_DEV_H ++ ++#include "hal_vo_dev_comm.h" ++#include "inner_vo.h" ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#if vo_desc("UBOOT_VO") ++ ++td_void hal_sys_set_outstanding(td_void); ++ ++#if vo_desc("dev intf") ++#define VO_CVBS_DATE_PAL 0x628412dc ++#define VO_CVBS_DATE_NTSC 0x108412dc ++#define VO_CVBS_DATE_GAIN 0x8080958a ++#define VO_CVBS_DATE_PAL_GAIN VO_CVBS_DATE_GAIN ++#define VO_CVBS_DATE_NTSC_GAIN VO_CVBS_DATE_GAIN ++td_void vo_hal_intf_set_cvbs_dac_cfg(td_void); ++td_void vo_hal_intf_set_date_cvbs_gain(td_u32 data); ++td_void vo_hal_intf_set_date_cvbs_burst_start(td_void); ++td_void hal_disp_set_hdmi_mode(ot_vo_dev dev, td_u32 color_space); ++td_void vo_hal_intf_set_rgb_sync_inv(const hal_disp_syncinv *inv); ++td_void vo_hal_intf_set_mipi_sync_inv(const hal_disp_syncinv *inv); ++td_void vo_hal_intf_set_mux_sel(ot_vo_dev dev, ot_vo_intf_type intf); ++td_void vo_hal_intf_set_csc_enable(ot_vo_intf_type intf, td_bool enable); ++td_void vo_hal_intf_set_csc_cfg(ot_vo_intf_type intf, const csc_coef *csc_cfg); ++td_void vo_hal_set_intf_rgb_component_order(td_bool component_inverse_en); ++td_void vo_hal_set_intf_rgb_bit_inverse(td_bool bit_inverse_en); ++td_void hal_disp_set_lcd_serial_perd(td_u32 serial_perd); ++td_void vo_hal_set_intf_ctrl(ot_vo_intf_type intf, const td_u32 *ctrl_info); ++td_void vo_hal_set_dev_precharge_threshold(ot_vo_dev dev, td_bool te_enable); ++td_void vo_hal_intf_set_lcd_dither(const vdp_dither_cfg *cfg); ++#endif ++ ++#endif /* #if vo_desc("UBOOT_VO") */ ++ ++#if vo_desc("KERNEL_VO") ++ ++td_void hal_disp_set_int_mask1(td_u32 mask_en); ++td_void hal_disp_clr_int_mask1(td_u32 mask_en); ++td_void vo_hal_intf_set_dac_det_cable_en(ot_vo_dev dev, ot_vo_intf_type intf_type, td_bool enable); ++td_void vo_hal_intf_get_dec_det_high(ot_vo_intf_type intf_type, td_bool enable, ++ td_u32 *det_high); ++ ++#endif /* #if vo_desc("KERNEL_VO") */ ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#endif /* end of HAL_VO_DEV_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_reg.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_reg.h +new file mode 100755 +index 000000000..5106fb320 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_reg.h +@@ -0,0 +1,20459 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HAL_VO_REG_H ++#define HAL_VO_REG_H ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++/* define the union reg_voctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 23; /* [22..0] */ ++ unsigned int g3_ck_gt_en : 1; /* [23] */ ++ unsigned int v2_ck_gt_en : 1; /* [24] */ ++ unsigned int wbc_dhd_ck_gt_en : 1; /* [25] */ ++ unsigned int g1_ck_gt_en : 1; /* [26] */ ++ unsigned int g0_ck_gt_en : 1; /* [27] */ ++ unsigned int v1_ck_gt_en : 1; /* [28] */ ++ unsigned int v0_ck_gt_en : 1; /* [29] */ ++ unsigned int chk_sum_en : 1; /* [30] */ ++ unsigned int vo_ck_gt_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_voctrl; ++ ++/* define the union reg_vointsta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_int : 1; /* [0] */ ++ unsigned int dhd0vtthd2_int : 1; /* [1] */ ++ unsigned int dhd0vtthd3_int : 1; /* [2] */ ++ unsigned int dhd0uf_int : 1; /* [3] */ ++ unsigned int dhd1vtthd1_int : 1; /* [4] */ ++ unsigned int dhd1vtthd2_int : 1; /* [5] */ ++ unsigned int dhd1vtthd3_int : 1; /* [6] */ ++ unsigned int dhd1uf_int : 1; /* [7] */ ++ unsigned int dsdvtthd1_int : 1; /* [8] */ ++ unsigned int dsdvtthd2_int : 1; /* [9] */ ++ unsigned int dsdvtthd3_int : 1; /* [10] */ ++ unsigned int dsduf_int : 1; /* [11] */ ++ unsigned int b0_err_int : 1; /* [12] */ ++ unsigned int b1_err_int : 1; /* [13] */ ++ unsigned int b2_err_int : 1; /* [14] */ ++ unsigned int wbc_dhd_over_int : 1; /* [15] */ ++ unsigned int vdac0_int : 1; /* [16] */ ++ unsigned int vdac1_int : 1; /* [17] */ ++ unsigned int vdac2_int : 1; /* [18] */ ++ unsigned int vdac3_int : 1; /* [19] */ ++ unsigned int v0_tunl_int : 1; /* [20] */ ++ unsigned int v1_tunl_int : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vointsta; ++ ++/* define the union reg_vomskintsta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_clr : 1; /* [0] */ ++ unsigned int dhd0vtthd2_clr : 1; /* [1] */ ++ unsigned int dhd0vtthd3_clr : 1; /* [2] */ ++ unsigned int dhd0uf_clr : 1; /* [3] */ ++ unsigned int dhd1vtthd1_clr : 1; /* [4] */ ++ unsigned int dhd1vtthd2_clr : 1; /* [5] */ ++ unsigned int dhd1vtthd3_clr : 1; /* [6] */ ++ unsigned int dhd1uf_clr : 1; /* [7] */ ++ unsigned int dsdvtthd1_clr : 1; /* [8] */ ++ unsigned int dsdvtthd2_clr : 1; /* [9] */ ++ unsigned int dsdvtthd3_clr : 1; /* [10] */ ++ unsigned int dsduf_clr : 1; /* [11] */ ++ unsigned int b0_err_clr : 1; /* [12] */ ++ unsigned int b1_err_clr : 1; /* [13] */ ++ unsigned int b2_err_clr : 1; /* [14] */ ++ unsigned int wbc_dhd_over_clr : 1; /* [15] */ ++ unsigned int vdac0_clr : 1; /* [16] */ ++ unsigned int vdac1_clr : 1; /* [17] */ ++ unsigned int vdac2_clr : 1; /* [18] */ ++ unsigned int vdac3_clr : 1; /* [19] */ ++ unsigned int v0_tunl_clr : 1; /* [20] */ ++ unsigned int v1_tunl_clr : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vomskintsta; ++ ++/* define the union reg_vointmsk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ ++ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ ++ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ ++ unsigned int dhd0uf_intmask : 1; /* [3] */ ++ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ ++ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ ++ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ ++ unsigned int dhd1uf_intmask : 1; /* [7] */ ++ unsigned int dsdvtthd1_intmask : 1; /* [8] */ ++ unsigned int dsdvtthd2_intmask : 1; /* [9] */ ++ unsigned int dsdvtthd3_intmask : 1; /* [10] */ ++ unsigned int dsduf_intmask : 1; /* [11] */ ++ unsigned int b0_err_intmask : 1; /* [12] */ ++ unsigned int b1_err_intmask : 1; /* [13] */ ++ unsigned int b2_err_intmask : 1; /* [14] */ ++ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ ++ unsigned int vdac0_intmask : 1; /* [16] */ ++ unsigned int vdac1_intmask : 1; /* [17] */ ++ unsigned int vdac2_intmask : 1; /* [18] */ ++ unsigned int vdac3_intmask : 1; /* [19] */ ++ unsigned int v0_tunl_intmask : 1; /* [20] */ ++ unsigned int v1_tunl_intmask : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vointmsk; ++ ++/* define the union reg_vodebug */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rm_en_chn : 4; /* [3..0] */ ++ unsigned int dhd0_ff_info : 2; /* [5..4] */ ++ unsigned int dhd1_ff_info : 2; /* [7..6] */ ++ unsigned int dsd0_ff_info : 2; /* [9..8] */ ++ unsigned int bfm_vga_en : 1; /* [10] */ ++ unsigned int bfm_cvbs_en : 1; /* [11] */ ++ unsigned int bfm_lcd_en : 1; /* [12] */ ++ unsigned int bfm_bt1120_en : 1; /* [13] */ ++ unsigned int wbc2_ff_info : 2; /* [15..14] */ ++ unsigned int wbc_mode : 4; /* [19..16] */ ++ unsigned int node_num : 4; /* [23..20] */ ++ unsigned int wbc_cmp_mode : 2; /* [25..24] */ ++ unsigned int bfm_mode : 3; /* [28..26] */ ++ unsigned int bfm_clk_sel : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vodebug; ++ ++/* define the union reg_vointsta1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_int : 1; /* [0] */ ++ unsigned int dhd0vtthd2_int : 1; /* [1] */ ++ unsigned int dhd0vtthd3_int : 1; /* [2] */ ++ unsigned int dhd0uf_int : 1; /* [3] */ ++ unsigned int dhd1vtthd1_int : 1; /* [4] */ ++ unsigned int dhd1vtthd2_int : 1; /* [5] */ ++ unsigned int dhd1vtthd3_int : 1; /* [6] */ ++ unsigned int dhd1uf_int : 1; /* [7] */ ++ unsigned int dsdvtthd1_int : 1; /* [8] */ ++ unsigned int dsdvtthd2_int : 1; /* [9] */ ++ unsigned int dsdvtthd3_int : 1; /* [10] */ ++ unsigned int dsduf_int : 1; /* [11] */ ++ unsigned int b0_err_int : 1; /* [12] */ ++ unsigned int b1_err_int : 1; /* [13] */ ++ unsigned int b2_err_int : 1; /* [14] */ ++ unsigned int wbc_dhd_over_int : 1; /* [15] */ ++ unsigned int vdac0_int : 1; /* [16] */ ++ unsigned int vdac1_int : 1; /* [17] */ ++ unsigned int vdac2_int : 1; /* [18] */ ++ unsigned int vdac3_int : 1; /* [19] */ ++ unsigned int v0_tunl_int : 1; /* [20] */ ++ unsigned int v1_tunl_int : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vointsta1; ++ ++/* define the union reg_vomskintsta1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_clr : 1; /* [0] */ ++ unsigned int dhd0vtthd2_clr : 1; /* [1] */ ++ unsigned int dhd0vtthd3_clr : 1; /* [2] */ ++ unsigned int dhd0uf_clr : 1; /* [3] */ ++ unsigned int dhd1vtthd1_clr : 1; /* [4] */ ++ unsigned int dhd1vtthd2_clr : 1; /* [5] */ ++ unsigned int dhd1vtthd3_clr : 1; /* [6] */ ++ unsigned int dhd1uf_clr : 1; /* [7] */ ++ unsigned int dsdvtthd1_clr : 1; /* [8] */ ++ unsigned int dsdvtthd2_clr : 1; /* [9] */ ++ unsigned int dsdvtthd3_clr : 1; /* [10] */ ++ unsigned int dsduf_clr : 1; /* [11] */ ++ unsigned int b0_err_clr : 1; /* [12] */ ++ unsigned int b1_err_clr : 1; /* [13] */ ++ unsigned int b2_err_clr : 1; /* [14] */ ++ unsigned int wbc_dhd_over_clr : 1; /* [15] */ ++ unsigned int vdac0_clr : 1; /* [16] */ ++ unsigned int vdac1_clr : 1; /* [17] */ ++ unsigned int vdac2_clr : 1; /* [18] */ ++ unsigned int vdac3_clr : 1; /* [19] */ ++ unsigned int v0_tunl_clr : 1; /* [20] */ ++ unsigned int v1_tunl_clr : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vomskintsta1; ++ ++/* define the union reg_vointmsk1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ ++ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ ++ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ ++ unsigned int dhd0uf_intmask : 1; /* [3] */ ++ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ ++ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ ++ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ ++ unsigned int dhd1uf_intmask : 1; /* [7] */ ++ unsigned int dsdvtthd1_intmask : 1; /* [8] */ ++ unsigned int dsdvtthd2_intmask : 1; /* [9] */ ++ unsigned int dsdvtthd3_intmask : 1; /* [10] */ ++ unsigned int dsduf_intmask : 1; /* [11] */ ++ unsigned int b0_err_intmask : 1; /* [12] */ ++ unsigned int b1_err_intmask : 1; /* [13] */ ++ unsigned int b2_err_intmask : 1; /* [14] */ ++ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ ++ unsigned int vdac0_intmask : 1; /* [16] */ ++ unsigned int vdac1_intmask : 1; /* [17] */ ++ unsigned int vdac2_intmask : 1; /* [18] */ ++ unsigned int vdac3_intmask : 1; /* [19] */ ++ unsigned int v0_tunl_intmask : 1; /* [20] */ ++ unsigned int v1_tunl_intmask : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vointmsk1; ++ ++/* define the union reg_volowpower_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rasehd_twac : 2; /* [1..0] */ ++ unsigned int rasehd_twa : 2; /* [3..2] */ ++ unsigned int rashd_tselw : 2; /* [5..4] */ ++ unsigned int rashd_tselr : 3; /* [8..6] */ ++ unsigned int rfshd_tselw : 2; /* [10..9] */ ++ unsigned int rfshd_tselr : 3; /* [13..11] */ ++ unsigned int rfsehd_tselw : 2; /* [15..14] */ ++ unsigned int rfsehd_tselr : 3; /* [18..16] */ ++ unsigned int rasehd_tselw : 2; /* [20..19] */ ++ unsigned int rasehd_tselr : 3; /* [23..21] */ ++ unsigned int rfthd_tselw : 2; /* [25..24] */ ++ unsigned int rfthd_tselr : 2; /* [27..26] */ ++ unsigned int rftehd_tselw : 2; /* [29..28] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_volowpower_ctrl; ++ ++/* define the union reg_voufsta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_uf_sta : 1; /* [0] */ ++ unsigned int v1_uf_sta : 1; /* [1] */ ++ unsigned int reserved_0 : 1; /* [2] */ ++ unsigned int v3_uf_sta : 1; /* [3] */ ++ unsigned int reserved_1 : 4; /* [7..4] */ ++ unsigned int g0_uf_sta : 1; /* [8] */ ++ unsigned int g1_uf_sta : 1; /* [9] */ ++ unsigned int g2_uf_sta : 1; /* [10] */ ++ unsigned int g3_uf_sta : 1; /* [11] */ ++ unsigned int g4_uf_sta : 1; /* [12] */ ++ unsigned int reserved_2 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_voufsta; ++ ++/* define the union reg_voufclr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_uf_clr : 1; /* [0] */ ++ unsigned int v1_uf_clr : 1; /* [1] */ ++ unsigned int reserved_0 : 1; /* [2] */ ++ unsigned int v3_uf_clr : 1; /* [3] */ ++ unsigned int reserved_1 : 4; /* [7..4] */ ++ unsigned int g0_uf_clr : 1; /* [8] */ ++ unsigned int g1_uf_clr : 1; /* [9] */ ++ unsigned int g2_uf_clr : 1; /* [10] */ ++ unsigned int g3_uf_clr : 1; /* [11] */ ++ unsigned int g4_uf_clr : 1; /* [12] */ ++ unsigned int reserved_2 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_voufclr; ++ ++/* define the union reg_vointproc_tim */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vointproc_time : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vointproc_tim; ++ ++/* define the union reg_volowpower_ctrl1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rftehd_tselr : 3; /* [2..0] */ ++ unsigned int rftehd_tselm : 2; /* [4..3] */ ++ unsigned int rasehd_test : 3; /* [7..5] */ ++ unsigned int rashd_test : 3; /* [10..8] */ ++ unsigned int rfsehd_test : 3; /* [13..11] */ ++ unsigned int rfshd_test : 3; /* [16..14] */ ++ unsigned int rftehd_test : 3; /* [19..17] */ ++ unsigned int rfthd_test : 3; /* [22..20] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_volowpower_ctrl1; ++ ++/* define the union reg_vofpgadef */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_hdr_v_def : 1; /* [0] */ ++ unsigned int ot_hdr_g_def : 1; /* [1] */ ++ unsigned int ot_hdr_wd_def : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vofpgadef; ++ ++/* define the union reg_volowpower_ctrl2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int s14_rfshd_rm : 4; /* [3..0] */ ++ unsigned int s14_rfshs_rm : 4; /* [7..4] */ ++ unsigned int s14_rasehd_rm : 4; /* [11..8] */ ++ unsigned int s14_rashd_rm : 4; /* [15..12] */ ++ unsigned int s14_rfshd_rme : 1; /* [16] */ ++ unsigned int s14_rfshs_rme : 1; /* [17] */ ++ unsigned int s14_rasehd_rme : 1; /* [18] */ ++ unsigned int s14_rashd_rme : 1; /* [19] */ ++ unsigned int s14_rfthd_rma : 4; /* [23..20] */ ++ unsigned int s14_rfthd_rmb : 4; /* [27..24] */ ++ unsigned int s14_rfthd_rmea : 1; /* [28] */ ++ unsigned int s14_rfthd_rmeb : 1; /* [29] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_volowpower_ctrl2; ++ ++/* define the union reg_volowpower_ctrl3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int s14_rom_rm : 4; /* [3..0] */ ++ unsigned int s14_rom_rme : 1; /* [4] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_volowpower_ctrl3; ++ ++/* define the union reg_vomux_dac */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dac0_sel : 4; /* [3..0] */ ++ unsigned int dac1_sel : 4; /* [7..4] */ ++ unsigned int dac2_sel : 4; /* [11..8] */ ++ unsigned int dac3_sel : 4; /* [15..12] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vomux_dac; ++ ++/* define the union reg_vomux_testsync */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int test_dv : 1; /* [0] */ ++ unsigned int test_hsync : 1; /* [1] */ ++ unsigned int test_vsync : 1; /* [2] */ ++ unsigned int test_field : 1; /* [3] */ ++ unsigned int reserved_0 : 27; /* [30..4] */ ++ unsigned int vo_test_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vomux_testsync; ++ ++/* define the union reg_vomux_testdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int test_data : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vomux_testdata; ++ ++/* define the union reg_vo_dac_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dac_reg_rev : 4; /* [3..0] */ ++ unsigned int dac_reg_rev1 : 6; /* [9..4] */ ++ unsigned int dac_reg_dac3_cable_en : 1; /* [10] */ ++ unsigned int dac_reg_rev2 : 3; /* [13..11] */ ++ unsigned int dac_reg_vref_cable : 1; /* [14] */ ++ unsigned int dac_reg_res_sel : 1; /* [15] */ ++ unsigned int enctr : 4; /* [19..16] */ ++ unsigned int enextref : 1; /* [20] */ ++ unsigned int pdchopper : 1; /* [21] */ ++ unsigned int envbg : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac_ctrl; ++ ++/* define the union reg_vo_dac_otp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dac_otp_rev0 : 3; /* [2..0] */ ++ unsigned int dac_otp_poly_step : 6; /* [8..3] */ ++ unsigned int dac_otp_rev1 : 5; /* [13..9] */ ++ unsigned int dac_otp_ch3_itrim : 1; /* [14] */ ++ unsigned int dac_otp_24k_12k_sel : 1; /* [15] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac_otp; ++ ++/* define the union reg_vo_dac0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac0_ctrl; ++ ++/* define the union reg_vo_dac1_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac1_ctrl; ++ ++/* define the union reg_vo_dac2_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac2_ctrl; ++ ++/* define the union reg_vo_dac3_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cablectr : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int dacgc : 6; /* [9..4] */ ++ unsigned int reserved_1 : 21; /* [30..10] */ ++ unsigned int dac_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac3_ctrl; ++ ++/* define the union reg_vo_dac_stat0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cableout0 : 1; /* [0] */ ++ unsigned int cableout1 : 1; /* [1] */ ++ unsigned int cableout2 : 1; /* [2] */ ++ unsigned int cableout3 : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_dac_stat0; ++ ++/* define the union reg_cbm_bkg1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cbm_bkgcr1 : 10; /* [9..0] */ ++ unsigned int cbm_bkgcb1 : 10; /* [19..10] */ ++ unsigned int cbm_bkgy1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_cbm_bkg1; ++ ++/* define the union reg_cbm_mix1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int mixer_prio4 : 4; /* [19..16] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_cbm_mix1; ++ ++/* define the union reg_wbc_bmp_thd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_bmp_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_bmp_thd; ++ ++/* define the union reg_cbm_bkg2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cbm_bkgcr2 : 10; /* [9..0] */ ++ unsigned int cbm_bkgcb2 : 10; /* [19..10] */ ++ unsigned int cbm_bkgy2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_cbm_bkg2; ++ ++/* define the union reg_cbm_mix2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int mixer_prio4 : 4; /* [19..16] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_cbm_mix2; ++ ++/* define the union reg_hc_bmp_thd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hc_bmp_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hc_bmp_thd; ++ ++/* define the union reg_cbm_bkg3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cbm_bkgcr3 : 10; /* [9..0] */ ++ unsigned int cbm_bkgcb3 : 10; /* [19..10] */ ++ unsigned int cbm_bkgy3 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_cbm_bkg3; ++ ++/* define the union reg_cbm_mix3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_cbm_mix3; ++ ++/* define the union reg_mixv0_bkg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_bkgcr : 10; /* [9..0] */ ++ unsigned int mixer_bkgcb : 10; /* [19..10] */ ++ unsigned int mixer_bkgy : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mixv0_bkg; ++ ++/* define the union reg_mixv0_mix */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mixv0_mix; ++ ++/* define the union reg_mixg0_bkg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_bkgcr : 10; /* [9..0] */ ++ unsigned int mixer_bkgcb : 10; /* [19..10] */ ++ unsigned int mixer_bkgy : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mixg0_bkg; ++ ++/* define the union reg_mixg0_bkalpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mixg0_bkalpha; ++ ++/* define the union reg_mixg0_mix */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mixer_prio0 : 4; /* [3..0] */ ++ unsigned int mixer_prio1 : 4; /* [7..4] */ ++ unsigned int mixer_prio2 : 4; /* [11..8] */ ++ unsigned int mixer_prio3 : 4; /* [15..12] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mixg0_mix; ++ ++/* define the union reg_link_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v2_link : 2; /* [1..0] */ ++ unsigned int g3_link : 2; /* [3..2] */ ++ unsigned int g2_link : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_link_ctrl; ++ ++/* define the union reg_vpss_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vpss_en : 1; /* [0] */ ++ unsigned int chk_sum_en : 1; /* [1] */ ++ unsigned int dei_en : 1; /* [2] */ ++ unsigned int mcdi_en : 1; /* [3] */ ++ unsigned int nx2_vc1_en : 1; /* [4] */ ++ unsigned int rgme_en : 1; /* [5] */ ++ unsigned int meds_en : 1; /* [6] */ ++ unsigned int hsp_en : 1; /* [7] */ ++ unsigned int snr_en : 1; /* [8] */ ++ unsigned int tnr_en : 1; /* [9] */ ++ unsigned int rfr_en : 1; /* [10] */ ++ unsigned int ifmd_en : 1; /* [11] */ ++ unsigned int igbm_en : 1; /* [12] */ ++ unsigned int cue_en : 1; /* [13] */ ++ unsigned int scd_en : 1; /* [14] */ ++ unsigned int blk_det_en : 1; /* [15] */ ++ unsigned int reserved_0 : 7; /* [22..16] */ ++ unsigned int vpss_node_init : 1; /* [23] */ ++ unsigned int ram_bank : 4; /* [27..24] */ ++ unsigned int dei_debug_en : 1; /* [28] */ ++ unsigned int dei_repeat_mode : 1; /* [29] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vpss_ctrl; ++ ++/* define the union reg_vpss_miscellaneous */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 4; /* [3..0] */ ++ unsigned int reserved_1 : 4; /* [7..4] */ ++ unsigned int reserved_2 : 16; /* [23..8] */ ++ unsigned int ck_gt_en : 1; /* [24] */ ++ unsigned int ck_gt_en_calc : 1; /* [25] */ ++ unsigned int reserved_3 : 2; /* [27..26] */ ++ unsigned int reserved_4 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vpss_miscellaneous; ++ ++/* define the union reg_vpss_ftconfig */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int node_rst_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vpss_ftconfig; ++ ++/* define the union reg_para_up_vhd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_up_vhd_chn00 : 1; /* [0] */ ++ unsigned int para_up_vhd_chn01 : 1; /* [1] */ ++ unsigned int para_up_vhd_chn02 : 1; /* [2] */ ++ unsigned int para_up_vhd_chn03 : 1; /* [3] */ ++ unsigned int para_up_vhd_chn04 : 1; /* [4] */ ++ unsigned int para_up_vhd_chn05 : 1; /* [5] */ ++ unsigned int para_up_vhd_chn06 : 1; /* [6] */ ++ unsigned int para_up_vhd_chn07 : 1; /* [7] */ ++ unsigned int para_up_vhd_chn08 : 1; /* [8] */ ++ unsigned int para_up_vhd_chn09 : 1; /* [9] */ ++ unsigned int para_up_vhd_chn10 : 1; /* [10] */ ++ unsigned int para_up_vhd_chn11 : 1; /* [11] */ ++ unsigned int para_up_vhd_chn12 : 1; /* [12] */ ++ unsigned int para_up_vhd_chn13 : 1; /* [13] */ ++ unsigned int para_up_vhd_chn14 : 1; /* [14] */ ++ unsigned int para_up_vhd_chn15 : 1; /* [15] */ ++ unsigned int para_up_vhd_chn16 : 1; /* [16] */ ++ unsigned int para_up_vhd_chn17 : 1; /* [17] */ ++ unsigned int para_up_vhd_chn18 : 1; /* [18] */ ++ unsigned int para_up_vhd_chn19 : 1; /* [19] */ ++ unsigned int para_up_vhd_chn20 : 1; /* [20] */ ++ unsigned int para_up_vhd_chn21 : 1; /* [21] */ ++ unsigned int para_up_vhd_chn22 : 1; /* [22] */ ++ unsigned int para_up_vhd_chn23 : 1; /* [23] */ ++ unsigned int para_up_vhd_chn24 : 1; /* [24] */ ++ unsigned int para_up_vhd_chn25 : 1; /* [25] */ ++ unsigned int para_up_vhd_chn26 : 1; /* [26] */ ++ unsigned int para_up_vhd_chn27 : 1; /* [27] */ ++ unsigned int para_up_vhd_chn28 : 1; /* [28] */ ++ unsigned int para_up_vhd_chn29 : 1; /* [29] */ ++ unsigned int para_up_vhd_chn30 : 1; /* [30] */ ++ unsigned int para_up_vhd_chn31 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_para_up_vhd; ++ ++/* define the union reg_para_up_vsd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_up_vsd_chn00 : 1; /* [0] */ ++ unsigned int para_up_vsd_chn01 : 1; /* [1] */ ++ unsigned int para_up_vsd_chn02 : 1; /* [2] */ ++ unsigned int para_up_vsd_chn03 : 1; /* [3] */ ++ unsigned int para_up_vsd_chn04 : 1; /* [4] */ ++ unsigned int para_up_vsd_chn05 : 1; /* [5] */ ++ unsigned int para_up_vsd_chn06 : 1; /* [6] */ ++ unsigned int para_up_vsd_chn07 : 1; /* [7] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_para_up_vsd; ++ ++/* define the union reg_para_conflict_clr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_conflict_clr_hd : 1; /* [0] */ ++ unsigned int para_conflict_clr_sd : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_para_conflict_clr; ++ ++/* define the union reg_para_conflict_sta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_conflict_hd : 1; /* [0] */ ++ unsigned int para_conflict_sd : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_para_conflict_sta; ++ ++/* define the union reg_v0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int mir_en : 1; /* [8] */ ++ unsigned int reserved_0 : 19; /* [27..9] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ctrl; ++ ++/* define the union reg_v0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_upd; ++ ++/* define the union reg_v0_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_0reso_read; ++ ++/* define the union reg_v0_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ireso; ++ ++/* define the union reg_v0_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_dfpos; ++ ++/* define the union reg_v0_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_dlpos; ++ ++/* define the union reg_v0_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_vfpos; ++ ++/* define the union reg_v0_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_vlpos; ++ ++/* define the union reg_v0_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_bk; ++ ++/* define the union reg_v0_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_alpha; ++ ++/* define the union reg_v0_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mute_bk; ++ ++/* define the union reg_v0_rimwidth */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_width : 5; /* [4..0] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_rimwidth; ++ ++/* define the union reg_v0_rimcol0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_v0 : 10; /* [9..0] */ ++ unsigned int v0_rim_u0 : 10; /* [19..10] */ ++ unsigned int v0_rim_y0 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_rimcol0; ++ ++/* define the union reg_v0_rimcol1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_v1 : 10; /* [9..0] */ ++ unsigned int v0_rim_u1 : 10; /* [19..10] */ ++ unsigned int v0_rim_y1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_rimcol1; ++ ++/* define the union reg_v0_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_ctrl; ++ ++/* define the union reg_v0_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef00; ++ ++/* define the union reg_v0_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef01; ++ ++/* define the union reg_v0_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef02; ++ ++/* define the union reg_v0_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef10; ++ ++/* define the union reg_v0_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef11; ++ ++/* define the union reg_v0_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef12; ++ ++/* define the union reg_v0_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef20; ++ ++/* define the union reg_v0_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef21; ++ ++/* define the union reg_v0_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_coef22; ++ ++/* define the union reg_v0_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_scale; ++ ++/* define the union reg_v0_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_idc0; ++ ++/* define the union reg_v0_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_idc1; ++ ++/* define the union reg_v0_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_idc2; ++ ++/* define the union reg_v0_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_odc0; ++ ++/* define the union reg_v0_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_odc1; ++ ++/* define the union reg_v0_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_odc2; ++ ++/* define the union reg_v0_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_min_y; ++ ++/* define the union reg_v0_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_min_c; ++ ++/* define the union reg_v0_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_max_y; ++ ++/* define the union reg_v0_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_max_c; ++ ++/* define the union reg_v0_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef00; ++ ++/* define the union reg_v0_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef01; ++ ++/* define the union reg_v0_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef02; ++ ++/* define the union reg_v0_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef10; ++ ++/* define the union reg_v0_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef11; ++ ++/* define the union reg_v0_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef12; ++ ++/* define the union reg_v0_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef20; ++ ++/* define the union reg_v0_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef21; ++ ++/* define the union reg_v0_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_coef22; ++ ++/* define the union reg_v0_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_scale; ++ ++/* define the union reg_v0_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_idc0; ++ ++/* define the union reg_v0_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_idc1; ++ ++/* define the union reg_v0_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_idc2; ++ ++/* define the union reg_v0_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_odc0; ++ ++/* define the union reg_v0_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_odc1; ++ ++/* define the union reg_v0_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_odc2; ++ ++/* define the union reg_v0_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_min_y; ++ ++/* define the union reg_v0_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_min_c; ++ ++/* define the union reg_v0_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_max_y; ++ ++/* define the union reg_v0_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc2_max_c; ++ ++/* define the union reg_v0_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_v0_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_ot_pp_csc_ink_pos; ++ ++/* define the union reg_v0_cvfir_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_vinfo; ++ ++/* define the union reg_v0_cvfir_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_vsp; ++ ++/* define the union reg_v0_cvfir_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_voffset; ++ ++/* define the union reg_v0_cvfir_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_vboffset; ++ ++/* define the union reg_v0_cvfir_vcoef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_vcoef0; ++ ++/* define the union reg_v0_cvfir_vcoef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_vcoef1; ++ ++/* define the union reg_v0_cvfir_vcoef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_cvfir_vcoef2; ++ ++/* define the union reg_v0_hfir_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_hfir_ctrl; ++ ++/* define the union reg_v0_hfircoef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_hfircoef01; ++ ++/* define the union reg_v0_hfircoef23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_hfircoef23; ++ ++/* define the union reg_v0_hfircoef45 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_hfircoef45; ++ ++/* define the union reg_v0_hfircoef67 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_hfircoef67; ++ ++/* define the union reg_v1_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ctrl; ++ ++/* define the union reg_v1_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_upd; ++ ++/* define the union reg_v1_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_0reso_read; ++ ++/* define the union reg_v1_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ireso; ++ ++/* define the union reg_v1_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_dfpos; ++ ++/* define the union reg_v1_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_dlpos; ++ ++/* define the union reg_v1_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_vfpos; ++ ++/* define the union reg_v1_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_vlpos; ++ ++/* define the union reg_v1_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_bk; ++ ++/* define the union reg_v1_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_alpha; ++ ++/* define the union reg_v1_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mute_bk; ++ ++/* define the union reg_v1_rimwidth */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_width : 5; /* [4..0] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_rimwidth; ++ ++/* define the union reg_v1_rimcol0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_v0 : 10; /* [9..0] */ ++ unsigned int v0_rim_u0 : 10; /* [19..10] */ ++ unsigned int v0_rim_y0 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_rimcol0; ++ ++/* define the union reg_v1_rimcol1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_v1 : 10; /* [9..0] */ ++ unsigned int v0_rim_u1 : 10; /* [19..10] */ ++ unsigned int v0_rim_y1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_rimcol1; ++ ++/* define the union reg_v1_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_ctrl; ++ ++/* define the union reg_v1_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef00; ++ ++/* define the union reg_v1_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef01; ++ ++/* define the union reg_v1_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef02; ++ ++/* define the union reg_v1_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef10; ++ ++/* define the union reg_v1_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef11; ++ ++/* define the union reg_v1_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef12; ++ ++/* define the union reg_v1_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef20; ++ ++/* define the union reg_v1_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef21; ++ ++/* define the union reg_v1_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_coef22; ++ ++/* define the union reg_v1_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_scale; ++ ++/* define the union reg_v1_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_idc0; ++ ++/* define the union reg_v1_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_idc1; ++ ++/* define the union reg_v1_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_idc2; ++ ++/* define the union reg_v1_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_odc0; ++ ++/* define the union reg_v1_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_odc1; ++ ++/* define the union reg_v1_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_odc2; ++ ++/* define the union reg_v1_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_min_y; ++ ++/* define the union reg_v1_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_min_c; ++ ++/* define the union reg_v1_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_max_y; ++ ++/* define the union reg_v1_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_max_c; ++ ++/* define the union reg_v1_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef00; ++ ++/* define the union reg_v1_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef01; ++ ++/* define the union reg_v1_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef02; ++ ++/* define the union reg_v1_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef10; ++ ++/* define the union reg_v1_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef11; ++ ++/* define the union reg_v1_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef12; ++ ++/* define the union reg_v1_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef20; ++ ++/* define the union reg_v1_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef21; ++ ++/* define the union reg_v1_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_coef22; ++ ++/* define the union reg_v1_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_scale; ++ ++/* define the union reg_v1_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_idc0; ++ ++/* define the union reg_v1_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_idc1; ++ ++/* define the union reg_v1_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_idc2; ++ ++/* define the union reg_v1_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_odc0; ++ ++/* define the union reg_v1_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_odc1; ++ ++/* define the union reg_v1_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_odc2; ++ ++/* define the union reg_v1_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_min_y; ++ ++/* define the union reg_v1_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_min_c; ++ ++/* define the union reg_v1_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_max_y; ++ ++/* define the union reg_v1_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc2_max_c; ++ ++/* define the union reg_v1_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_v1_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_ot_pp_csc_ink_pos; ++ ++/* define the union reg_v1_cvfir_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_vinfo; ++ ++/* define the union reg_v1_cvfir_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_vsp; ++ ++/* define the union reg_v1_cvfir_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_voffset; ++ ++/* define the union reg_v1_cvfir_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_vboffset; ++ ++/* define the union reg_v1_cvfir_vcoef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_vcoef0; ++ ++/* define the union reg_v1_cvfir_vcoef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_vcoef1; ++ ++/* define the union reg_v1_cvfir_vcoef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_cvfir_vcoef2; ++ ++/* define the union reg_v1_hfir_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_hfir_ctrl; ++ ++/* define the union reg_v1_hfircoef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_hfircoef01; ++ ++/* define the union reg_v1_hfircoef23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_hfircoef23; ++ ++/* define the union reg_v1_hfircoef45 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_hfircoef45; ++ ++/* define the union reg_v1_hfircoef67 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_hfircoef67; ++ ++/* define the union reg_v2_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ctrl; ++ ++/* define the union reg_v2_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_upd; ++ ++/* define the union reg_v2_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_0reso_read; ++ ++/* define the union reg_v2_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ireso; ++ ++/* define the union reg_v2_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_dfpos; ++ ++/* define the union reg_v2_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_dlpos; ++ ++/* define the union reg_v2_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_vfpos; ++ ++/* define the union reg_v2_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_vlpos; ++ ++/* define the union reg_v2_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_bk; ++ ++/* define the union reg_v2_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_alpha; ++ ++/* define the union reg_v2_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_mute_bk; ++ ++/* define the union reg_v2_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_ctrl; ++ ++/* define the union reg_v2_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef00; ++ ++/* define the union reg_v2_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef01; ++ ++/* define the union reg_v2_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef02; ++ ++/* define the union reg_v2_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef10; ++ ++/* define the union reg_v2_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef11; ++ ++/* define the union reg_v2_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef12; ++ ++/* define the union reg_v2_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef20; ++ ++/* define the union reg_v2_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef21; ++ ++/* define the union reg_v2_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_coef22; ++ ++/* define the union reg_v2_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_scale; ++ ++/* define the union reg_v2_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_idc0; ++ ++/* define the union reg_v2_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_idc1; ++ ++/* define the union reg_v2_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_idc2; ++ ++/* define the union reg_v2_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_odc0; ++ ++/* define the union reg_v2_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_odc1; ++ ++/* define the union reg_v2_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_odc2; ++ ++/* define the union reg_v2_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_min_y; ++ ++/* define the union reg_v2_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_min_c; ++ ++/* define the union reg_v2_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_max_y; ++ ++/* define the union reg_v2_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_max_c; ++ ++/* define the union reg_v2_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef00; ++ ++/* define the union reg_v2_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef01; ++ ++/* define the union reg_v2_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef02; ++ ++/* define the union reg_v2_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef10; ++ ++/* define the union reg_v2_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef11; ++ ++/* define the union reg_v2_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef12; ++ ++/* define the union reg_v2_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef20; ++ ++/* define the union reg_v2_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef21; ++ ++/* define the union reg_v2_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_coef22; ++ ++/* define the union reg_v2_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_scale; ++ ++/* define the union reg_v2_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_idc0; ++ ++/* define the union reg_v2_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_idc1; ++ ++/* define the union reg_v2_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_idc2; ++ ++/* define the union reg_v2_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_odc0; ++ ++/* define the union reg_v2_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_odc1; ++ ++/* define the union reg_v2_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_odc2; ++ ++/* define the union reg_v2_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_min_y; ++ ++/* define the union reg_v2_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_min_c; ++ ++/* define the union reg_v2_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_max_y; ++ ++/* define the union reg_v2_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc2_max_c; ++ ++/* define the union reg_v2_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_v2_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_ot_pp_csc_ink_pos; ++ ++/* define the union reg_v2_cvfir_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_vinfo; ++ ++/* define the union reg_v2_cvfir_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_vsp; ++ ++/* define the union reg_v2_cvfir_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_voffset; ++ ++/* define the union reg_v2_cvfir_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_vboffset; ++ ++/* define the union reg_v2_cvfir_vcoef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_vcoef0; ++ ++/* define the union reg_v2_cvfir_vcoef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_vcoef1; ++ ++/* define the union reg_v2_cvfir_vcoef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_cvfir_vcoef2; ++ ++/* define the union reg_v2_hfir_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_hfir_ctrl; ++ ++/* define the union reg_v2_hfircoef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_hfircoef01; ++ ++/* define the union reg_v2_hfircoef23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_hfircoef23; ++ ++/* define the union reg_v2_hfircoef45 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_hfircoef45; ++ ++/* define the union reg_v2_hfircoef67 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_hfircoef67; ++ ++/* define the union reg_v3_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 20; /* [27..8] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ctrl; ++ ++/* define the union reg_v3_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_upd; ++ ++/* define the union reg_v3_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_0reso_read; ++ ++/* define the union reg_v3_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ireso; ++ ++/* define the union reg_v3_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_dfpos; ++ ++/* define the union reg_v3_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_dlpos; ++ ++/* define the union reg_v3_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_vfpos; ++ ++/* define the union reg_v3_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_vlpos; ++ ++/* define the union reg_v3_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_bk; ++ ++/* define the union reg_v3_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_alpha; ++ ++/* define the union reg_v3_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_mute_bk; ++ ++/* define the union reg_v3_rimwidth */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_width : 5; /* [4..0] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_rimwidth; ++ ++/* define the union reg_v3_rimcol0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_v0 : 10; /* [9..0] */ ++ unsigned int v0_rim_u0 : 10; /* [19..10] */ ++ unsigned int v0_rim_y0 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_rimcol0; ++ ++/* define the union reg_v3_rimcol1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v0_rim_v1 : 10; /* [9..0] */ ++ unsigned int v0_rim_u1 : 10; /* [19..10] */ ++ unsigned int v0_rim_y1 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_rimcol1; ++ ++/* define the union reg_v3_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_ctrl; ++ ++/* define the union reg_v3_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef00; ++ ++/* define the union reg_v3_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef01; ++ ++/* define the union reg_v3_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef02; ++ ++/* define the union reg_v3_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef10; ++ ++/* define the union reg_v3_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef11; ++ ++/* define the union reg_v3_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef12; ++ ++/* define the union reg_v3_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef20; ++ ++/* define the union reg_v3_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef21; ++ ++/* define the union reg_v3_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_coef22; ++ ++/* define the union reg_v3_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_scale; ++ ++/* define the union reg_v3_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_idc0; ++ ++/* define the union reg_v3_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_idc1; ++ ++/* define the union reg_v3_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_idc2; ++ ++/* define the union reg_v3_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_odc0; ++ ++/* define the union reg_v3_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_odc1; ++ ++/* define the union reg_v3_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_odc2; ++ ++/* define the union reg_v3_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_min_y; ++ ++/* define the union reg_v3_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_min_c; ++ ++/* define the union reg_v3_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_max_y; ++ ++/* define the union reg_v3_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_max_c; ++ ++/* define the union reg_v3_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef00; ++ ++/* define the union reg_v3_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef01; ++ ++/* define the union reg_v3_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef02; ++ ++/* define the union reg_v3_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef10; ++ ++/* define the union reg_v3_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef11; ++ ++/* define the union reg_v3_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef12; ++ ++/* define the union reg_v3_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef20; ++ ++/* define the union reg_v3_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef21; ++ ++/* define the union reg_v3_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_coef22; ++ ++/* define the union reg_v3_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_scale; ++ ++/* define the union reg_v3_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_idc0; ++ ++/* define the union reg_v3_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_idc1; ++ ++/* define the union reg_v3_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_idc2; ++ ++/* define the union reg_v3_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_odc0; ++ ++/* define the union reg_v3_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_odc1; ++ ++/* define the union reg_v3_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_odc2; ++ ++/* define the union reg_v3_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_min_y; ++ ++/* define the union reg_v3_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_min_c; ++ ++/* define the union reg_v3_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_max_y; ++ ++/* define the union reg_v3_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc2_max_c; ++ ++/* define the union reg_v3_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_v3_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_ot_pp_csc_ink_pos; ++ ++/* define the union reg_v3_cvfir_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_vinfo; ++ ++/* define the union reg_v3_cvfir_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int reserved_2 : 1; /* [26] */ ++ unsigned int reserved_3 : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int reserved_4 : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int reserved_5 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_vsp; ++ ++/* define the union reg_v3_cvfir_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_voffset; ++ ++/* define the union reg_v3_cvfir_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_vboffset; ++ ++/* define the union reg_v3_cvfir_vcoef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef02 : 10; /* [9..0] */ ++ unsigned int vccoef01 : 10; /* [19..10] */ ++ unsigned int vccoef00 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_vcoef0; ++ ++/* define the union reg_v3_cvfir_vcoef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef11 : 10; /* [9..0] */ ++ unsigned int vccoef10 : 10; /* [19..10] */ ++ unsigned int vccoef03 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_vcoef1; ++ ++/* define the union reg_v3_cvfir_vcoef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vccoef13 : 10; /* [9..0] */ ++ unsigned int vccoef12 : 10; /* [19..10] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_cvfir_vcoef2; ++ ++/* define the union reg_v3_hfir_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_1 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_hfir_ctrl; ++ ++/* define the union reg_v3_hfircoef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_hfircoef01; ++ ++/* define the union reg_v3_hfircoef23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_hfircoef23; ++ ++/* define the union reg_v3_hfircoef45 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_hfircoef45; ++ ++/* define the union reg_v3_hfircoef67 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef7 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v3_hfircoef67; ++ ++/* define the union reg_vp0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_upd; ++ ++/* define the union reg_vp0_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_ireso; ++ ++/* define the union reg_vp0_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_lbox_ctrl; ++ ++/* define the union reg_vp0_galpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_galpha; ++ ++/* define the union reg_vp0_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 12; /* [11..0] */ ++ unsigned int disp_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_dfpos; ++ ++/* define the union reg_vp0_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 12; /* [11..0] */ ++ unsigned int disp_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_dlpos; ++ ++/* define the union reg_vp0_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 12; /* [11..0] */ ++ unsigned int video_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_vfpos; ++ ++/* define the union reg_vp0_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 12; /* [11..0] */ ++ unsigned int video_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_vlpos; ++ ++/* define the union reg_vp0_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_bk; ++ ++/* define the union reg_vp0_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_alpha; ++ ++/* define the union reg_vp0_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vp0_mute_bk; ++ ++/* define the union reg_g0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g0_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ctrl; ++ ++/* define the union reg_g0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_upd; ++ ++/* define the union reg_g0_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_0reso_read; ++ ++/* define the union reg_g0_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ireso; ++ ++/* define the union reg_g0_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_dfpos; ++ ++/* define the union reg_g0_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_dlpos; ++ ++/* define the union reg_g0_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_vfpos; ++ ++/* define the union reg_g0_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_vlpos; ++ ++/* define the union reg_g0_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_bk; ++ ++/* define the union reg_g0_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_alpha; ++ ++/* define the union reg_g0_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_mute_bk; ++ ++/* define the union reg_g0_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_lbox_ctrl; ++ ++/* define the union reg_g0_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_ctrl; ++ ++/* define the union reg_g0_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef00; ++ ++/* define the union reg_g0_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef01; ++ ++/* define the union reg_g0_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef02; ++ ++/* define the union reg_g0_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef10; ++ ++/* define the union reg_g0_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef11; ++ ++/* define the union reg_g0_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef12; ++ ++/* define the union reg_g0_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef20; ++ ++/* define the union reg_g0_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef21; ++ ++/* define the union reg_g0_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_coef22; ++ ++/* define the union reg_g0_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_scale; ++ ++/* define the union reg_g0_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_idc0; ++ ++/* define the union reg_g0_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_idc1; ++ ++/* define the union reg_g0_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_idc2; ++ ++/* define the union reg_g0_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_odc0; ++ ++/* define the union reg_g0_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_odc1; ++ ++/* define the union reg_g0_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_odc2; ++ ++/* define the union reg_g0_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_min_y; ++ ++/* define the union reg_g0_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_min_c; ++ ++/* define the union reg_g0_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_max_y; ++ ++/* define the union reg_g0_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_max_c; ++ ++/* define the union reg_g0_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef00; ++ ++/* define the union reg_g0_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef01; ++ ++/* define the union reg_g0_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef02; ++ ++/* define the union reg_g0_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef10; ++ ++/* define the union reg_g0_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef11; ++ ++/* define the union reg_g0_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef12; ++ ++/* define the union reg_g0_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef20; ++ ++/* define the union reg_g0_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef21; ++ ++/* define the union reg_g0_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_coef22; ++ ++/* define the union reg_g0_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_scale; ++ ++/* define the union reg_g0_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_idc0; ++ ++/* define the union reg_g0_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_idc1; ++ ++/* define the union reg_g0_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_idc2; ++ ++/* define the union reg_g0_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_odc0; ++ ++/* define the union reg_g0_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_odc1; ++ ++/* define the union reg_g0_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_odc2; ++ ++/* define the union reg_g0_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_min_y; ++ ++/* define the union reg_g0_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_min_c; ++ ++/* define the union reg_g0_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_max_y; ++ ++/* define the union reg_g0_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc2_max_c; ++ ++/* define the union reg_g0_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_g0_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_ot_pp_csc_ink_pos; ++ ++/* define the union reg_osb_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_v : 10; /* [9..0] */ ++ unsigned int osb_bk_u : 10; /* [19..10] */ ++ unsigned int osb_bk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int osb_mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_osb_mute_bk; ++ ++/* define the union reg_osb_bk_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_osb_bk_alpha; ++ ++/* define the union reg_osb_coef_rd_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_osb_coef_rd_en; ++ ++/* define the union reg_g0_zme_hinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_hinfo; ++ ++/* define the union reg_g0_zme_hsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int ahfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int chfir_mid_en : 1; /* [28] */ ++ unsigned int lhfir_mid_en : 1; /* [29] */ ++ unsigned int ahfir_mid_en : 1; /* [30] */ ++ unsigned int hfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_hsp; ++ ++/* define the union reg_g0_zme_hloffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_hloffset; ++ ++/* define the union reg_g0_zme_hcoffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_hcoffset; ++ ++/* define the union reg_g0_zme_coef_ren */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int apb_g0_vf_lren : 1; /* [1] */ ++ unsigned int reserved_1 : 1; /* [2] */ ++ unsigned int apb_g0_hf_lren : 1; /* [3] */ ++ unsigned int reserved_2 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_coef_ren; ++ ++/* define the union reg_g0_zme_coef_rdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_coef_rdata; ++ ++/* define the union reg_g0_zme_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int reserved_0 : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_vinfo; ++ ++/* define the union reg_g0_zme_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 9; /* [24..16] */ ++ unsigned int vafir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int reserved_1 : 1; /* [27] */ ++ unsigned int cvfir_mid_en : 1; /* [28] */ ++ unsigned int lvfir_mid_en : 1; /* [29] */ ++ unsigned int avfir_mid_en : 1; /* [30] */ ++ unsigned int vfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_vsp; ++ ++/* define the union reg_g0_zme_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbtm_offset : 16; /* [15..0] */ ++ unsigned int vtp_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g0_zme_voffset; ++ ++/* define the union reg_g1_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ctrl; ++ ++/* define the union reg_g1_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_upd; ++ ++/* define the union reg_g1_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_0reso_read; ++ ++/* define the union reg_g1_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ireso; ++ ++/* define the union reg_g1_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_dfpos; ++ ++/* define the union reg_g1_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_dlpos; ++ ++/* define the union reg_g1_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_vfpos; ++ ++/* define the union reg_g1_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_vlpos; ++ ++/* define the union reg_g1_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_bk; ++ ++/* define the union reg_g1_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_alpha; ++ ++/* define the union reg_g1_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_mute_bk; ++ ++/* define the union reg_g1_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_lbox_ctrl; ++ ++/* define the union reg_g1_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_ctrl; ++ ++/* define the union reg_g1_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef00; ++ ++/* define the union reg_g1_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef01; ++ ++/* define the union reg_g1_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef02; ++ ++/* define the union reg_g1_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef10; ++ ++/* define the union reg_g1_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef11; ++ ++/* define the union reg_g1_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef12; ++ ++/* define the union reg_g1_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef20; ++ ++/* define the union reg_g1_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef21; ++ ++/* define the union reg_g1_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_coef22; ++ ++/* define the union reg_g1_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_scale; ++ ++/* define the union reg_g1_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_idc0; ++ ++/* define the union reg_g1_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_idc1; ++ ++/* define the union reg_g1_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_idc2; ++ ++/* define the union reg_g1_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_odc0; ++ ++/* define the union reg_g1_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_odc1; ++ ++/* define the union reg_g1_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_odc2; ++ ++/* define the union reg_g1_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_min_y; ++ ++/* define the union reg_g1_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_min_c; ++ ++/* define the union reg_g1_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_max_y; ++ ++/* define the union reg_g1_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_max_c; ++ ++/* define the union reg_g1_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef00; ++ ++/* define the union reg_g1_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef01; ++ ++/* define the union reg_g1_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef02; ++ ++/* define the union reg_g1_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef10; ++ ++/* define the union reg_g1_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef11; ++ ++/* define the union reg_g1_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef12; ++ ++/* define the union reg_g1_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef20; ++ ++/* define the union reg_g1_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef21; ++ ++/* define the union reg_g1_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_coef22; ++ ++/* define the union reg_g1_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_scale; ++ ++/* define the union reg_g1_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_idc0; ++ ++/* define the union reg_g1_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_idc1; ++ ++/* define the union reg_g1_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_idc2; ++ ++/* define the union reg_g1_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_odc0; ++ ++/* define the union reg_g1_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_odc1; ++ ++/* define the union reg_g1_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_odc2; ++ ++/* define the union reg_g1_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_min_y; ++ ++/* define the union reg_g1_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_min_c; ++ ++/* define the union reg_g1_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_max_y; ++ ++/* define the union reg_g1_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc2_max_c; ++ ++/* define the union reg_g1_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_g1_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_ot_pp_csc_ink_pos; ++ ++/* define the union reg_g1_osb_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_v : 10; /* [9..0] */ ++ unsigned int osb_bk_u : 10; /* [19..10] */ ++ unsigned int osb_bk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int osb_mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_osb_mute_bk; ++ ++/* define the union reg_g1_osb_bk_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_osb_bk_alpha; ++ ++/* define the union reg_g1_osb_coef_rd_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_osb_coef_rd_en; ++ ++/* define the union reg_g1_zme_hinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_hinfo; ++ ++/* define the union reg_g1_zme_hsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int ahfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int chfir_mid_en : 1; /* [28] */ ++ unsigned int lhfir_mid_en : 1; /* [29] */ ++ unsigned int ahfir_mid_en : 1; /* [30] */ ++ unsigned int hfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_hsp; ++ ++/* define the union reg_g1_zme_hloffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_hloffset; ++ ++/* define the union reg_g1_zme_hcoffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 24; /* [23..0] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_hcoffset; ++ ++/* define the union reg_g1_zme_coef_ren */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int apb_g1_vf_lren : 1; /* [1] */ ++ unsigned int reserved_1 : 1; /* [2] */ ++ unsigned int apb_g1_hf_lren : 1; /* [3] */ ++ unsigned int reserved_2 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_coef_ren; ++ ++/* define the union reg_g1_zme_coef_rdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_coef_rdata; ++ ++/* define the union reg_g1_zme_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int reserved_0 : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_vinfo; ++ ++/* define the union reg_g1_zme_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 9; /* [24..16] */ ++ unsigned int vafir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int reserved_1 : 1; /* [27] */ ++ unsigned int cvfir_mid_en : 1; /* [28] */ ++ unsigned int lvfir_mid_en : 1; /* [29] */ ++ unsigned int avfir_mid_en : 1; /* [30] */ ++ unsigned int vfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_vsp; ++ ++/* define the union reg_g1_zme_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbtm_offset : 16; /* [15..0] */ ++ unsigned int vtp_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_zme_voffset; ++ ++/* define the union reg_g2_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ctrl; ++ ++/* define the union reg_g2_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_upd; ++ ++/* define the union reg_g2_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_0reso_read; ++ ++/* define the union reg_g2_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ireso; ++ ++/* define the union reg_g2_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_dfpos; ++ ++/* define the union reg_g2_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_dlpos; ++ ++/* define the union reg_g2_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_vfpos; ++ ++/* define the union reg_g2_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_vlpos; ++ ++/* define the union reg_g2_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_bk; ++ ++/* define the union reg_g2_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_alpha; ++ ++/* define the union reg_g2_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_mute_bk; ++ ++/* define the union reg_g2_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_lbox_ctrl; ++ ++/* define the union reg_g2_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_ctrl; ++ ++/* define the union reg_g2_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef00; ++ ++/* define the union reg_g2_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef01; ++ ++/* define the union reg_g2_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef02; ++ ++/* define the union reg_g2_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef10; ++ ++/* define the union reg_g2_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef11; ++ ++/* define the union reg_g2_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef12; ++ ++/* define the union reg_g2_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef20; ++ ++/* define the union reg_g2_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef21; ++ ++/* define the union reg_g2_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_coef22; ++ ++/* define the union reg_g2_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_scale; ++ ++/* define the union reg_g2_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_idc0; ++ ++/* define the union reg_g2_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_idc1; ++ ++/* define the union reg_g2_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_idc2; ++ ++/* define the union reg_g2_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_odc0; ++ ++/* define the union reg_g2_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_odc1; ++ ++/* define the union reg_g2_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_odc2; ++ ++/* define the union reg_g2_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_min_y; ++ ++/* define the union reg_g2_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_min_c; ++ ++/* define the union reg_g2_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_max_y; ++ ++/* define the union reg_g2_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_max_c; ++ ++/* define the union reg_g2_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef00; ++ ++/* define the union reg_g2_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef01; ++ ++/* define the union reg_g2_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef02; ++ ++/* define the union reg_g2_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef10; ++ ++/* define the union reg_g2_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef11; ++ ++/* define the union reg_g2_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef12; ++ ++/* define the union reg_g2_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef20; ++ ++/* define the union reg_g2_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef21; ++ ++/* define the union reg_g2_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_coef22; ++ ++/* define the union reg_g2_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_scale; ++ ++/* define the union reg_g2_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_idc0; ++ ++/* define the union reg_g2_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_idc1; ++ ++/* define the union reg_g2_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_idc2; ++ ++/* define the union reg_g2_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_odc0; ++ ++/* define the union reg_g2_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_odc1; ++ ++/* define the union reg_g2_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_odc2; ++ ++/* define the union reg_g2_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_min_y; ++ ++/* define the union reg_g2_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_min_c; ++ ++/* define the union reg_g2_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_max_y; ++ ++/* define the union reg_g2_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc2_max_c; ++ ++/* define the union reg_g2_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_g2_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g2_ot_pp_csc_ink_pos; ++ ++/* define the union reg_g3_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ctrl; ++ ++/* define the union reg_g3_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_upd; ++ ++/* define the union reg_g3_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_0reso_read; ++ ++/* define the union reg_g3_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ireso; ++ ++/* define the union reg_g3_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_dfpos; ++ ++/* define the union reg_g3_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_dlpos; ++ ++/* define the union reg_g3_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_vfpos; ++ ++/* define the union reg_g3_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_vlpos; ++ ++/* define the union reg_g3_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_bk; ++ ++/* define the union reg_g3_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_alpha; ++ ++/* define the union reg_g3_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_mute_bk; ++ ++/* define the union reg_g3_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_lbox_ctrl; ++ ++/* define the union reg_g3_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_ctrl; ++ ++/* define the union reg_g3_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef00; ++ ++/* define the union reg_g3_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef01; ++ ++/* define the union reg_g3_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef02; ++ ++/* define the union reg_g3_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef10; ++ ++/* define the union reg_g3_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef11; ++ ++/* define the union reg_g3_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef12; ++ ++/* define the union reg_g3_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef20; ++ ++/* define the union reg_g3_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef21; ++ ++/* define the union reg_g3_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_coef22; ++ ++/* define the union reg_g3_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_scale; ++ ++/* define the union reg_g3_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_idc0; ++ ++/* define the union reg_g3_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_idc1; ++ ++/* define the union reg_g3_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_idc2; ++ ++/* define the union reg_g3_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_odc0; ++ ++/* define the union reg_g3_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_odc1; ++ ++/* define the union reg_g3_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_odc2; ++ ++/* define the union reg_g3_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_min_y; ++ ++/* define the union reg_g3_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_min_c; ++ ++/* define the union reg_g3_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_max_y; ++ ++/* define the union reg_g3_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_max_c; ++ ++/* define the union reg_g3_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef00; ++ ++/* define the union reg_g3_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef01; ++ ++/* define the union reg_g3_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef02; ++ ++/* define the union reg_g3_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef10; ++ ++/* define the union reg_g3_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef11; ++ ++/* define the union reg_g3_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef12; ++ ++/* define the union reg_g3_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef20; ++ ++/* define the union reg_g3_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef21; ++ ++/* define the union reg_g3_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_coef22; ++ ++/* define the union reg_g3_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_scale; ++ ++/* define the union reg_g3_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_idc0; ++ ++/* define the union reg_g3_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_idc1; ++ ++/* define the union reg_g3_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_idc2; ++ ++/* define the union reg_g3_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_odc0; ++ ++/* define the union reg_g3_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_odc1; ++ ++/* define the union reg_g3_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_odc2; ++ ++/* define the union reg_g3_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_min_y; ++ ++/* define the union reg_g3_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_min_c; ++ ++/* define the union reg_g3_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_max_y; ++ ++/* define the union reg_g3_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc2_max_c; ++ ++/* define the union reg_g3_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_g3_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_ot_pp_csc_ink_pos; ++ ++/* define the union reg_g3_osb_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_v : 10; /* [9..0] */ ++ unsigned int osb_bk_u : 10; /* [19..10] */ ++ unsigned int osb_bk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int osb_mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_osb_mute_bk; ++ ++/* define the union reg_g3_osb_bk_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_osb_bk_alpha; ++ ++/* define the union reg_g3_osb_coef_rd_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_osb_coef_rd_en; ++ ++/* define the union reg_g4_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 19; /* [26..8] */ ++ unsigned int g1_depremult : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int surface_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ctrl; ++ ++/* define the union reg_g4_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_upd; ++ ++/* define the union reg_g4_0reso_read */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_0reso_read; ++ ++/* define the union reg_g4_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ireso; ++ ++/* define the union reg_g4_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 16; /* [15..0] */ ++ unsigned int disp_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_dfpos; ++ ++/* define the union reg_g4_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 16; /* [15..0] */ ++ unsigned int disp_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_dlpos; ++ ++/* define the union reg_g4_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 16; /* [15..0] */ ++ unsigned int video_yfpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_vfpos; ++ ++/* define the union reg_g4_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 16; /* [15..0] */ ++ unsigned int video_ylpos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_vlpos; ++ ++/* define the union reg_g4_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_bk; ++ ++/* define the union reg_g4_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_alpha; ++ ++/* define the union reg_g4_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_mute_bk; ++ ++/* define the union reg_g4_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_lbox_ctrl; ++ ++/* define the union reg_g4_ot_pp_csc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_en : 1; /* [0] */ ++ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ ++ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_ctrl; ++ ++/* define the union reg_g4_ot_pp_csc_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef00; ++ ++/* define the union reg_g4_ot_pp_csc_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef01; ++ ++/* define the union reg_g4_ot_pp_csc_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef02; ++ ++/* define the union reg_g4_ot_pp_csc_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef10; ++ ++/* define the union reg_g4_ot_pp_csc_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef11; ++ ++/* define the union reg_g4_ot_pp_csc_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef12; ++ ++/* define the union reg_g4_ot_pp_csc_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef20; ++ ++/* define the union reg_g4_ot_pp_csc_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef21; ++ ++/* define the union reg_g4_ot_pp_csc_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_coef22; ++ ++/* define the union reg_g4_ot_pp_csc_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_scale; ++ ++/* define the union reg_g4_ot_pp_csc_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_idc0; ++ ++/* define the union reg_g4_ot_pp_csc_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_idc1; ++ ++/* define the union reg_g4_ot_pp_csc_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_idc2; ++ ++/* define the union reg_g4_ot_pp_csc_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_odc0; ++ ++/* define the union reg_g4_ot_pp_csc_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_odc1; ++ ++/* define the union reg_g4_ot_pp_csc_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_odc2; ++ ++/* define the union reg_g4_ot_pp_csc_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_min_y; ++ ++/* define the union reg_g4_ot_pp_csc_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_min_c; ++ ++/* define the union reg_g4_ot_pp_csc_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_max_y; ++ ++/* define the union reg_g4_ot_pp_csc_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_max_c; ++ ++/* define the union reg_g4_ot_pp_csc2_coef00 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef00; ++ ++/* define the union reg_g4_ot_pp_csc2_coef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef01; ++ ++/* define the union reg_g4_ot_pp_csc2_coef02 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef02; ++ ++/* define the union reg_g4_ot_pp_csc2_coef10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef10; ++ ++/* define the union reg_g4_ot_pp_csc2_coef11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef11; ++ ++/* define the union reg_g4_ot_pp_csc2_coef12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef12; ++ ++/* define the union reg_g4_ot_pp_csc2_coef20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef20; ++ ++/* define the union reg_g4_ot_pp_csc2_coef21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef21; ++ ++/* define the union reg_g4_ot_pp_csc2_coef22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_coef22; ++ ++/* define the union reg_g4_ot_pp_csc2_scale */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_scale; ++ ++/* define the union reg_g4_ot_pp_csc2_idc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_idc0; ++ ++/* define the union reg_g4_ot_pp_csc2_idc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_idc1; ++ ++/* define the union reg_g4_ot_pp_csc2_idc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_idc2; ++ ++/* define the union reg_g4_ot_pp_csc2_odc0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_odc0; ++ ++/* define the union reg_g4_ot_pp_csc2_odc1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_odc1; ++ ++/* define the union reg_g4_ot_pp_csc2_odc2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_odc2; ++ ++/* define the union reg_g4_ot_pp_csc2_min_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_min_y; ++ ++/* define the union reg_g4_ot_pp_csc2_min_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_min_c; ++ ++/* define the union reg_g4_ot_pp_csc2_max_y */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_max_y; ++ ++/* define the union reg_g4_ot_pp_csc2_max_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc2_max_c; ++ ++/* define the union reg_g4_ot_pp_csc_ink_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ink_en : 1; /* [0] */ ++ unsigned int ink_sel : 1; /* [1] */ ++ unsigned int data_fmt : 1; /* [2] */ ++ unsigned int cross_enable : 1; /* [3] */ ++ unsigned int color_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_ink_ctrl; ++ ++/* define the union reg_g4_ot_pp_csc_ink_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_pos : 16; /* [15..0] */ ++ unsigned int y_pos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_ot_pp_csc_ink_pos; ++ ++/* define the union reg_g4_osb_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_v : 10; /* [9..0] */ ++ unsigned int osb_bk_u : 10; /* [19..10] */ ++ unsigned int osb_bk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int osb_mute_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_osb_mute_bk; ++ ++/* define the union reg_g4_osb_bk_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_bk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_osb_bk_alpha; ++ ++/* define the union reg_g4_osb_coef_rd_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int osb_rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_osb_coef_rd_en; ++ ++/* define the union reg_gp0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_upd; ++ ++/* define the union reg_gp0_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int iw : 16; /* [15..0] */ ++ unsigned int ih : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_ireso; ++ ++/* define the union reg_gp0_lbox_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_lbox_ctrl; ++ ++/* define the union reg_gp0_galpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int galpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_galpha; ++ ++/* define the union reg_gp0_dfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xfpos : 12; /* [11..0] */ ++ unsigned int disp_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_dfpos; ++ ++/* define the union reg_gp0_dlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int disp_xlpos : 12; /* [11..0] */ ++ unsigned int disp_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_dlpos; ++ ++/* define the union reg_gp0_vfpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xfpos : 12; /* [11..0] */ ++ unsigned int video_yfpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_vfpos; ++ ++/* define the union reg_gp0_vlpos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_xlpos : 12; /* [11..0] */ ++ unsigned int video_ylpos : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_vlpos; ++ ++/* define the union reg_gp0_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_cr : 10; /* [9..0] */ ++ unsigned int vbk_cb : 10; /* [19..10] */ ++ unsigned int vbk_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_bk; ++ ++/* define the union reg_gp0_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbk_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_alpha; ++ ++/* define the union reg_gp0_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_mute_bk; ++ ++/* define the union reg_gp0_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_idc; ++ ++/* define the union reg_gp0_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_odc; ++ ++/* define the union reg_gp0_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_iodc; ++ ++/* define the union reg_gp0_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_p0; ++ ++/* define the union reg_gp0_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_p1; ++ ++/* define the union reg_gp0_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_p2; ++ ++/* define the union reg_gp0_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_p3; ++ ++/* define the union reg_gp0_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gp0_csc_p4; ++ ++/* define the union reg_wbc_g0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int auto_stop_en : 1; /* [10] */ ++ unsigned int reserved_0 : 15; /* [25..11] */ ++ unsigned int format_out : 2; /* [27..26] */ ++ unsigned int reserved_1 : 3; /* [30..28] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_ctrl; ++ ++/* define the union reg_wbc_g0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_upd; ++ ++/* define the union reg_wbc_g0_cmp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cmp_lossy_en : 1; /* [0] */ ++ unsigned int reserved_0 : 3; /* [3..1] */ ++ unsigned int cmp_drr : 4; /* [7..4] */ ++ unsigned int reserved_1 : 23; /* [30..8] */ ++ unsigned int cmp_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_cmp; ++ ++/* define the union reg_wbc_g0_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbcstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_stride; ++ ++/* define the union reg_wbc_g0_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_oreso; ++ ++/* define the union reg_wbc_g0_fcrop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wfcrop : 12; /* [11..0] */ ++ unsigned int hfcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_fcrop; ++ ++/* define the union reg_wbc_g0_lcrop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wlcrop : 12; /* [11..0] */ ++ unsigned int hlcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_g0_lcrop; ++ ++/* define the union reg_wbc_gp0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int auto_stop_en : 1; /* [10] */ ++ unsigned int reserved_0 : 1; /* [11] */ ++ unsigned int wbc_vtthd_mode : 1; /* [12] */ ++ unsigned int reserved_1 : 5; /* [17..13] */ ++ unsigned int three_d_mode : 2; /* [19..18] */ ++ unsigned int reserved_2 : 3; /* [22..20] */ ++ unsigned int flip_en : 1; /* [23] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int mode_out : 2; /* [29..28] */ ++ unsigned int reserved_3 : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_ctrl; ++ ++/* define the union reg_wbc_gp0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_upd; ++ ++/* define the union reg_wbc_gp0_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbclstride : 16; /* [15..0] */ ++ unsigned int wbccstride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_stride; ++ ++/* define the union reg_wbc_gp0_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_oreso; ++ ++/* define the union reg_wbc_gp0_fcrop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wfcrop : 12; /* [11..0] */ ++ unsigned int hfcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_fcrop; ++ ++/* define the union reg_wbc_gp0_lcrop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wlcrop : 12; /* [11..0] */ ++ unsigned int hlcrop : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_lcrop; ++ ++/* define the union reg_wbc_gp0_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int dither_round : 1; /* [29] */ ++ unsigned int dither_mode : 1; /* [30] */ ++ unsigned int dither_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_dither_ctrl; ++ ++/* define the union reg_wbc_gp0_dither_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_coef0 : 8; /* [7..0] */ ++ unsigned int dither_coef1 : 8; /* [15..8] */ ++ unsigned int dither_coef2 : 8; /* [23..16] */ ++ unsigned int dither_coef3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_dither_coef0; ++ ++/* define the union reg_wbc_gp0_dither_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_coef4 : 8; /* [7..0] */ ++ unsigned int dither_coef5 : 8; /* [15..8] */ ++ unsigned int dither_coef6 : 8; /* [23..16] */ ++ unsigned int dither_coef7 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_dither_coef1; ++ ++/* define the union reg_wbc_gp0_hpzme */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int hpzme_mode : 1; /* [29] */ ++ unsigned int hpzme_mid_en : 1; /* [30] */ ++ unsigned int hpzme_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_gp0_hpzme; ++ ++/* define the union reg_wbc_me_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 10; /* [19..10] */ ++ unsigned int ofl_master : 1; /* [20] */ ++ unsigned int reserved_1 : 2; /* [22..21] */ ++ unsigned int mad_data_mode : 1; /* [23] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int reserved_2 : 1; /* [28] */ ++ unsigned int c_wbc_en : 1; /* [29] */ ++ unsigned int reserved_3 : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_ctrl; ++ ++/* define the union reg_wbc_me_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_upd; ++ ++/* define the union reg_wbc_me_wlen_sel */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wlen_sel : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_wlen_sel; ++ ++/* define the union reg_wbc_me_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbclstride : 16; /* [15..0] */ ++ unsigned int wbccstride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_stride; ++ ++/* define the union reg_wbc_me_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_oreso; ++ ++/* define the union reg_wbc_me_smmu_bypass */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int l_bypass : 1; /* [0] */ ++ unsigned int c_bypass : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_smmu_bypass; ++ ++/* define the union reg_wbc_me_paraup */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_hlcoef_upd : 1; /* [0] */ ++ unsigned int wbc_hccoef_upd : 1; /* [1] */ ++ unsigned int wbc_vlcoef_upd : 1; /* [2] */ ++ unsigned int wbc_vccoef_upd : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_paraup; ++ ++/* define the union reg_wbc_me_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int dither_round : 1; /* [29] */ ++ unsigned int dither_mode : 1; /* [30] */ ++ unsigned int dither_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_dither_ctrl; ++ ++/* define the union reg_wbc_me_dither_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_coef0 : 8; /* [7..0] */ ++ unsigned int dither_coef1 : 8; /* [15..8] */ ++ unsigned int dither_coef2 : 8; /* [23..16] */ ++ unsigned int dither_coef3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_dither_coef0; ++ ++/* define the union reg_wbc_me_dither_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_coef4 : 8; /* [7..0] */ ++ unsigned int dither_coef5 : 8; /* [15..8] */ ++ unsigned int dither_coef6 : 8; /* [23..16] */ ++ unsigned int dither_coef7 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_dither_coef1; ++ ++/* define the union reg_wbc_me_zme_hsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int hchfir_en : 1; /* [25] */ ++ unsigned int hlfir_en : 1; /* [26] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int hchmid_en : 1; /* [28] */ ++ unsigned int hlmid_en : 1; /* [29] */ ++ unsigned int hchmsc_en : 1; /* [30] */ ++ unsigned int hlmsc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_hsp; ++ ++/* define the union reg_wbc_me_zme_hloffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hor_loffset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_hloffset; ++ ++/* define the union reg_wbc_me_zme_hcoffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hor_coffset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_hcoffset; ++ ++/* define the union reg_wbc_me_zme_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 19; /* [18..0] */ ++ unsigned int zme_in_fmt : 2; /* [20..19] */ ++ unsigned int zme_out_fmt : 2; /* [22..21] */ ++ unsigned int vchfir_en : 1; /* [23] */ ++ unsigned int vlfir_en : 1; /* [24] */ ++ unsigned int reserved_1 : 3; /* [27..25] */ ++ unsigned int vchmid_en : 1; /* [28] */ ++ unsigned int vlmid_en : 1; /* [29] */ ++ unsigned int vchmsc_en : 1; /* [30] */ ++ unsigned int vlmsc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_vsp; ++ ++/* define the union reg_wbc_me_zme_vsr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_vsr; ++ ++/* define the union reg_wbc_me_zme_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int vluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_voffset; ++ ++/* define the union reg_wbc_me_zme_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int vbluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_me_zme_vboffset; ++ ++/* define the union reg_wbc_fi_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 3; /* [12..10] */ ++ unsigned int addr_mode : 1; /* [13] */ ++ unsigned int fsize_mode : 1; /* [14] */ ++ unsigned int tnr_nrds_en : 1; /* [15] */ ++ unsigned int reserved_1 : 4; /* [19..16] */ ++ unsigned int ofl_master : 1; /* [20] */ ++ unsigned int data_width : 1; /* [21] */ ++ unsigned int reserved_2 : 2; /* [23..22] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int reserved_3 : 2; /* [29..28] */ ++ unsigned int cmp_en : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_ctrl; ++ ++/* define the union reg_wbc_fi_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_upd; ++ ++/* define the union reg_wbc_fi_wlen_sel */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wlen_sel : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_wlen_sel; ++ ++/* define the union reg_wbc_fi_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbclstride : 16; /* [15..0] */ ++ unsigned int wbccstride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_stride; ++ ++/* define the union reg_wbc_fi_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_oreso; ++ ++/* define the union reg_wbc_fi_smmu_bypass */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int l_bypass : 1; /* [0] */ ++ unsigned int c_bypass : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_smmu_bypass; ++ ++/* define the union reg_wbc_fi_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_size : 23; /* [22..0] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_frame_size; ++ ++/* define the union reg_wbc_fi_hcds */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 29; /* [28..0] */ ++ unsigned int hchfir_en : 1; /* [29] */ ++ unsigned int hchmid_en : 1; /* [30] */ ++ unsigned int hcds_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_hcds; ++ ++/* define the union reg_wbc_fi_hcds_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int coef1 : 10; /* [19..10] */ ++ unsigned int coef2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_hcds_coef0; ++ ++/* define the union reg_wbc_fi_hcds_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef3 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_hcds_coef1; ++ ++/* define the union reg_wbc_fi_cmp_mb */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mb_bits : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_mb; ++ ++/* define the union reg_wbc_fi_cmp_max_min */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int min_bits_cnt : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int max_bits_cnt : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_max_min; ++ ++/* define the union reg_wbc_fi_cmp_adj_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int adj_sad_thr : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int adj_sad_bit_thr : 8; /* [23..16] */ ++ unsigned int adj_spec_bit_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_adj_thr; ++ ++/* define the union reg_wbc_fi_cmp_big_grad */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int big_grad_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int big_grad_num_thr : 5; /* [12..8] */ ++ unsigned int reserved_1 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_big_grad; ++ ++/* define the union reg_wbc_fi_cmp_blk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smth_thr : 6; /* [5..0] */ ++ unsigned int reserved_0 : 2; /* [7..6] */ ++ unsigned int blk_comp_thr : 3; /* [10..8] */ ++ unsigned int reserved_1 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_blk; ++ ++/* define the union reg_wbc_fi_cmp_graphic_judge */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int graphic_en : 1; /* [0] */ ++ unsigned int reserved_0 : 15; /* [15..1] */ ++ unsigned int video_sad_thr : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_graphic_judge; ++ ++/* define the union reg_wbc_fi_cmp_rc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int sadbits_ngain : 3; /* [2..0] */ ++ unsigned int reserved_0 : 5; /* [7..3] */ ++ unsigned int rc_smth_gain : 3; /* [10..8] */ ++ unsigned int reserved_1 : 5; /* [15..11] */ ++ unsigned int max_trow_bits : 6; /* [21..16] */ ++ unsigned int reserved_2 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_rc; ++ ++/* define the union reg_wbc_fi_cmp_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_size : 21; /* [20..0] */ ++ unsigned int reserved_0 : 11; /* [31..21] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_fi_cmp_frame_size; ++ ++/* define the union reg_wbc_cmp_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int is_lossless : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int dw_mode : 1; /* [2] */ ++ unsigned int sep_cmp_en : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_glb_info; ++ ++/* define the union reg_wbc_cmp_framesize */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int frame_height : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_framesize; ++ ++/* define the union reg_wbc_cmp_rc_cfg0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mb_bits_y : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int min_mb_bits_y : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg0; ++ ++/* define the union reg_wbc_cmp_rc_cfg2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_qp_y : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int sad_bits_ngain : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int rc_smth_ngain : 3; /* [18..16] */ ++ unsigned int reserved_2 : 5; /* [23..19] */ ++ unsigned int max_trow_bits : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg2; ++ ++/* define the union reg_wbc_cmp_rc_cfg3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_sad_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int min_sad_thr : 7; /* [22..16] */ ++ unsigned int reserved_1 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg3; ++ ++/* define the union reg_wbc_cmp_rc_cfg4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smth_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int still_thr : 7; /* [14..8] */ ++ unsigned int reserved_1 : 1; /* [15] */ ++ unsigned int big_grad_thr : 10; /* [25..16] */ ++ unsigned int reserved_2 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg4; ++ ++/* define the union reg_wbc_cmp_rc_cfg5 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smth_pix_num_thr : 6; /* [5..0] */ ++ unsigned int reserved_0 : 2; /* [7..6] */ ++ unsigned int still_pix_num_thr : 6; /* [13..8] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_2 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg5; ++ ++/* define the union reg_wbc_cmp_rc_cfg6 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int noise_sad : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int pix_diff_thr : 9; /* [24..16] */ ++ unsigned int reserved_1 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg6; ++ ++/* define the union reg_wbc_cmp_rc_cfg7 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg7; ++ ++/* define the union reg_wbc_cmp_rc_cfg8 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr_y : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr_y : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr_y : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr_y : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg8; ++ ++/* define the union reg_wbc_cmp_rc_cfg10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int est_err_gain : 5; /* [4..0] */ ++ unsigned int reserved_0 : 11; /* [15..5] */ ++ unsigned int max_est_err_level : 9; /* [24..16] */ ++ unsigned int max_vbv_buf_loss_thr : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_rc_cfg10; ++ ++/* define the union reg_wbc_cmp_outsize0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_size0_reg : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_outsize0; ++ ++/* define the union reg_wbc_cmp_max_row */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_size1_reg : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_max_row; ++ ++/* define the union reg_wbc_bmp_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 10; /* [19..10] */ ++ unsigned int ofl_master : 1; /* [20] */ ++ unsigned int data_width : 1; /* [21] */ ++ unsigned int reserved_1 : 2; /* [23..22] */ ++ unsigned int format_out : 4; /* [27..24] */ ++ unsigned int reserved_2 : 3; /* [30..28] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_bmp_ctrl; ++ ++/* define the union reg_wbc_bmp_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_bmp_upd; ++ ++/* define the union reg_wbc_bmp_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_bmp_oreso; ++ ++/* define the union reg_wbc_bmp_sum */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bmp_sum : 25; /* [24..0] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_bmp_sum; ++ ++/* define the union reg_wbc_dhd0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int p2i_en : 1; /* [0] */ ++ unsigned int root_path : 2; /* [2..1] */ ++ unsigned int reserved_0 : 19; /* [21..3] */ ++ unsigned int mode_out : 2; /* [23..22] */ ++ unsigned int three_d_mode : 2; /* [25..24] */ ++ unsigned int auto_stop_en : 1; /* [26] */ ++ unsigned int wbc_vtthd_mode : 1; /* [27] */ ++ unsigned int rupd_field : 1; /* [28] */ ++ unsigned int rgup_mode : 1; /* [29] */ ++ unsigned int nosec_flag : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_dhd0_ctrl; ++ ++/* define the union reg_wbc_dhd0_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_dhd0_upd; ++ ++/* define the union reg_wbc_dhd0_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 16; /* [15..0] */ ++ unsigned int oh : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_dhd0_oreso; ++ ++/* define the union reg_wd_hpzme_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_en : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hpzme_ctrl; ++ ++/* define the union reg_wd_hpzmecoef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hpzmecoef01; ++ ++/* define the union reg_wd_hpzmecoef23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hpzmecoef23; ++ ++/* define the union reg_wd_hpzmecoef45 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hpzmecoef45; ++ ++/* define the union reg_wd_hpzmecoef67 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hpzmecoef67; ++ ++/* define the union reg_wd_hcds_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_en : 1; /* [0] */ ++ unsigned int hfir_mode : 2; /* [2..1] */ ++ unsigned int mid_en : 1; /* [3] */ ++ unsigned int ck_gt_en : 1; /* [4] */ ++ unsigned int reserved_0 : 27; /* [31..5] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hcds_ctrl; ++ ++/* define the union reg_wd_hcdscoef01 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hcdscoef01; ++ ++/* define the union reg_wd_hcdscoef23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hcdscoef23; ++ ++/* define the union reg_wd_hcdscoef45 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hcdscoef45; ++ ++/* define the union reg_wd_hcdscoef67 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 10; /* [9..0] */ ++ unsigned int reserved_1 : 6; /* [15..10] */ ++ unsigned int reserved_2 : 10; /* [25..16] */ ++ unsigned int reserved_3 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_hcdscoef67; ++ ++/* define the union reg_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_ctrl; ++ ++/* define the union reg_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_y0; ++ ++/* define the union reg_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_u0; ++ ++/* define the union reg_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_v0; ++ ++/* define the union reg_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_w0; ++ ++/* define the union reg_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_y1; ++ ++/* define the union reg_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_u1; ++ ++/* define the union reg_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_v1; ++ ++/* define the union reg_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_w1; ++ ++/* define the union reg_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_y2; ++ ++/* define the union reg_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_u2; ++ ++/* define the union reg_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_v2; ++ ++/* define the union reg_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_w2; ++ ++/* define the union reg_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_y3; ++ ++/* define the union reg_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_u3; ++ ++/* define the union reg_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_v3; ++ ++/* define the union reg_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_sed_w3; ++ ++/* define the union reg_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dither_thr; ++ ++/* define the union reg_wd_zme_hinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int hzme_ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hinfo; ++ ++/* define the union reg_wd_zme_hsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int chfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int non_lnr_en : 1; /* [27] */ ++ unsigned int chmid_en : 1; /* [28] */ ++ unsigned int lhmid_en : 1; /* [29] */ ++ unsigned int chfir_en : 1; /* [30] */ ++ unsigned int lhfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hsp; ++ ++/* define the union reg_wd_zme_hloffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hloffset; ++ ++/* define the union reg_wd_zme_hcoffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hcoffset; ++ ++/* define the union reg_wd_zme_hcoef_ren */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_hf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hcoef_ren; ++ ++/* define the union reg_wd_zme_hcoef_rdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hcoef_rdata; ++ ++/* define the union reg_wd_zme_hdraw */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hdraw_mode : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hdraw; ++ ++/* define the union reg_wd_zme_hratio */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hratio : 27; /* [26..0] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_hratio; ++ ++/* define the union reg_wd_zme_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vinfo; ++ ++/* define the union reg_wd_zme_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 16; /* [15..0] */ ++ unsigned int graphdet_en : 1; /* [16] */ ++ unsigned int reserved_1 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int vfir_1tap_en : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int lvmid_en : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int lvfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vsp; ++ ++/* define the union reg_wd_zme_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int vluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_voffset; ++ ++/* define the union reg_wd_zme_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int vbluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vboffset; ++ ++/* define the union reg_wd_zme_vcoef_ren */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_vf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vcoef_ren; ++ ++/* define the union reg_wd_zme_vcoef_rdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vcoef_rdata; ++ ++/* define the union reg_wd_zme_vdraw */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vdraw_mode : 2; /* [1..0] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vdraw; ++ ++/* define the union reg_wd_zme_vratio */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 19; /* [18..0] */ ++ unsigned int reserved_0 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wd_zme_vratio; ++ ++/* define the union reg_dhd0_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int disp_mode : 3; /* [3..1] */ ++ unsigned int iop : 1; /* [4] */ ++ unsigned int intf_ivs : 1; /* [5] */ ++ unsigned int intf_ihs : 1; /* [6] */ ++ unsigned int intf_idv : 1; /* [7] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int hdmi420c_sel : 1; /* [9] */ ++ unsigned int hdmi420_en : 1; /* [10] */ ++ unsigned int uf_offline_en : 1; /* [11] */ ++ unsigned int reserved_1 : 2; /* [13..12] */ ++ unsigned int hdmi_mode : 1; /* [14] */ ++ unsigned int twochn_debug : 1; /* [15] */ ++ unsigned int twochn_en : 1; /* [16] */ ++ unsigned int reserved_2 : 1; /* [17] */ ++ unsigned int cbar_mode : 1; /* [18] */ ++ unsigned int sin_en : 1; /* [19] */ ++ unsigned int fpga_lmt_width : 7; /* [26..20] */ ++ unsigned int fpga_lmt_en : 1; /* [27] */ ++ unsigned int p2i_en : 1; /* [28] */ ++ unsigned int cbar_sel : 1; /* [29] */ ++ unsigned int cbar_en : 1; /* [30] */ ++ unsigned int intf_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ctrl; ++ ++/* define the union reg_dhd0_vsync1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vact : 16; /* [15..0] */ ++ unsigned int vbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vsync1; ++ ++/* define the union reg_dhd0_vsync2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vsync2; ++ ++/* define the union reg_dhd0_hsync1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hact : 16; /* [15..0] */ ++ unsigned int hbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_hsync1; ++ ++/* define the union reg_dhd0_hsync2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfb : 16; /* [15..0] */ ++ unsigned int hmid : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_hsync2; ++ ++/* define the union reg_dhd0_vplus1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvact : 16; /* [15..0] */ ++ unsigned int bvbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vplus1; ++ ++/* define the union reg_dhd0_vplus2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vplus2; ++ ++/* define the union reg_dhd0_pwr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hpw : 16; /* [15..0] */ ++ unsigned int vpw : 8; /* [23..16] */ ++ unsigned int reserved_0 : 3; /* [26..24] */ ++ unsigned int multichn_en : 2; /* [28..27] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_pwr; ++ ++/* define the union reg_dhd0_vtthd3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vtmgthd3 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd3_mode : 1; /* [15] */ ++ unsigned int vtmgthd4 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd4_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vtthd3; ++ ++/* define the union reg_dhd0_vtthd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vtmgthd1 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd1_mode : 1; /* [15] */ ++ unsigned int vtmgthd2 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd2_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vtthd; ++ ++/* define the union reg_dhd0_parathd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int dfs_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_parathd; ++ ++/* define the union reg_dhd0_precharge_thd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tcon_precharge_thd : 17; /* [16..0] */ ++ unsigned int reserved_0 : 3; /* [19..17] */ ++ unsigned int vsync_te_mode : 1; /* [20] */ ++ unsigned int reserved_1 : 10; /* [30..21] */ ++ unsigned int dneed_en_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_precharge_thd; ++ ++/* define the union reg_dhd0_start_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int start_pos : 8; /* [7..0] */ ++ unsigned int timing_start_pos : 8; /* [15..8] */ ++ unsigned int fi_start_pos : 4; /* [19..16] */ ++ unsigned int req_start_pos : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_start_pos; ++ ++/* define the union reg_dhd0_start_pos1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_start_pos1 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_start_pos1; ++ ++/* define the union reg_dhd0_paraup */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int paraup_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_paraup; ++ ++/* define the union reg_dhd0_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lcd_dv_inv : 1; /* [0] */ ++ unsigned int lcd_hs_inv : 1; /* [1] */ ++ unsigned int lcd_vs_inv : 1; /* [2] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int vga_dv_inv : 1; /* [4] */ ++ unsigned int vga_hs_inv : 1; /* [5] */ ++ unsigned int vga_vs_inv : 1; /* [6] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int hdmi_dv_inv : 1; /* [8] */ ++ unsigned int hdmi_hs_inv : 1; /* [9] */ ++ unsigned int hdmi_vs_inv : 1; /* [10] */ ++ unsigned int hdmi_f_inv : 1; /* [11] */ ++ unsigned int date_dv_inv : 1; /* [12] */ ++ unsigned int date_hs_inv : 1; /* [13] */ ++ unsigned int date_vs_inv : 1; /* [14] */ ++ unsigned int date_f_inv : 1; /* [15] */ ++ unsigned int reserved_2 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_sync_inv; ++ ++/* define the union reg_dhd0_clk_dv_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_clk_mux : 1; /* [0] */ ++ unsigned int intf_dv_mux : 1; /* [1] */ ++ unsigned int no_active_area_pos : 16; /* [17..2] */ ++ unsigned int reserved_0 : 14; /* [31..18] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_clk_dv_ctrl; ++ ++/* define the union reg_dhd0_rgb_fix_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fix_b : 10; /* [9..0] */ ++ unsigned int fix_g : 10; /* [19..10] */ ++ unsigned int fix_r : 10; /* [29..20] */ ++ unsigned int rgb_fix_mux : 1; /* [30] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_rgb_fix_ctrl; ++ ++/* define the union reg_dhd0_lockcfg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int measure_en : 1; /* [0] */ ++ unsigned int lock_cnt_en : 1; /* [1] */ ++ unsigned int vdp_measure_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_lockcfg; ++ ++/* define the union reg_dhd0_intf_chksum_high1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int r0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_intf_chksum_high1; ++ ++/* define the union reg_dhd0_intf_chksum_high2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int r1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_intf_chksum_high2; ++ ++/* define the union reg_dhd0_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vback_blank : 1; /* [0] */ ++ unsigned int vblank : 1; /* [1] */ ++ unsigned int bottom_field : 1; /* [2] */ ++ unsigned int vcnt : 13; /* [15..3] */ ++ unsigned int count_int : 8; /* [23..16] */ ++ unsigned int dhd_even : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_state; ++ ++/* define the union reg_dhd0_uf_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ud_first_cnt : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int start_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_uf_state; ++ ++/* define the union reg_vo_mux */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mipi_sel : 4; /* [3..0] */ ++ unsigned int lcd_sel : 4; /* [7..4] */ ++ unsigned int bt_sel : 4; /* [11..8] */ ++ unsigned int sddate_sel : 4; /* [15..12] */ ++ unsigned int hdmi_sel : 4; /* [19..16] */ ++ unsigned int hdmi1_sel : 4; /* [23..20] */ ++ unsigned int vga_sel : 4; /* [27..24] */ ++ unsigned int digital_sel : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_mux; ++ ++/* define the union reg_vo_mux_sync */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int sync_dv : 1; /* [0] */ ++ unsigned int sync_hsync : 1; /* [1] */ ++ unsigned int sync_vsync : 1; /* [2] */ ++ unsigned int sync_field : 1; /* [3] */ ++ unsigned int reserved_0 : 27; /* [30..4] */ ++ unsigned int sync_test_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_mux_sync; ++ ++/* define the union reg_vo_mux_data */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vomux_data : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vo_mux_data; ++ ++/* define the union reg_dhd0_vsync_te_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vsync_te_start_sta : 8; /* [7..0] */ ++ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ ++ unsigned int vsync_te_end_sta : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vsync_te_state; ++ ++/* define the union reg_dhd0_vsync_te_state1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vsync_te_vfb : 16; /* [15..0] */ ++ unsigned int vsync_te_width : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_vsync_te_state1; ++ ++/* define the union reg_dhd0_ccdoimgmod */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int img_mode : 7; /* [6..0] */ ++ unsigned int img_right : 1; /* [7] */ ++ unsigned int img_id : 2; /* [9..8] */ ++ unsigned int slave_mode : 1; /* [10] */ ++ unsigned int ccd_en : 1; /* [11] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int vbi_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ccdoimgmod; ++ ++/* define the union reg_dhd0_ccdoposmskh */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int p32_en : 1; /* [0] */ ++ unsigned int p33_en : 1; /* [1] */ ++ unsigned int p34_en : 1; /* [2] */ ++ unsigned int p35_en : 1; /* [3] */ ++ unsigned int p36_en : 1; /* [4] */ ++ unsigned int p37_en : 1; /* [5] */ ++ unsigned int p38_en : 1; /* [6] */ ++ unsigned int p39_en : 1; /* [7] */ ++ unsigned int p40_en : 1; /* [8] */ ++ unsigned int p41_en : 1; /* [9] */ ++ unsigned int p42_en : 1; /* [10] */ ++ unsigned int p43_en : 1; /* [11] */ ++ unsigned int p44_en : 1; /* [12] */ ++ unsigned int p45_en : 1; /* [13] */ ++ unsigned int p46_en : 1; /* [14] */ ++ unsigned int p47_en : 1; /* [15] */ ++ unsigned int p48_en : 1; /* [16] */ ++ unsigned int p49_en : 1; /* [17] */ ++ unsigned int p50_en : 1; /* [18] */ ++ unsigned int p51_en : 1; /* [19] */ ++ unsigned int p52_en : 1; /* [20] */ ++ unsigned int p53_en : 1; /* [21] */ ++ unsigned int p54_en : 1; /* [22] */ ++ unsigned int p55_en : 1; /* [23] */ ++ unsigned int p56_en : 1; /* [24] */ ++ unsigned int p57_en : 1; /* [25] */ ++ unsigned int p58_en : 1; /* [26] */ ++ unsigned int p59_en : 1; /* [27] */ ++ unsigned int p60_en : 1; /* [28] */ ++ unsigned int p61_en : 1; /* [29] */ ++ unsigned int p62_en : 1; /* [30] */ ++ unsigned int p63_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ccdoposmskh; ++ ++/* define the union reg_dhd0_ccdoposmskl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int p0_en : 1; /* [0] */ ++ unsigned int p1_en : 1; /* [1] */ ++ unsigned int p2_en : 1; /* [2] */ ++ unsigned int p3_en : 1; /* [3] */ ++ unsigned int p4_en : 1; /* [4] */ ++ unsigned int p5_en : 1; /* [5] */ ++ unsigned int p6_en : 1; /* [6] */ ++ unsigned int p7_en : 1; /* [7] */ ++ unsigned int p8_en : 1; /* [8] */ ++ unsigned int p9_en : 1; /* [9] */ ++ unsigned int p10_en : 1; /* [10] */ ++ unsigned int p11_en : 1; /* [11] */ ++ unsigned int p12_en : 1; /* [12] */ ++ unsigned int p13_en : 1; /* [13] */ ++ unsigned int p14_en : 1; /* [14] */ ++ unsigned int p15_en : 1; /* [15] */ ++ unsigned int p16_en : 1; /* [16] */ ++ unsigned int p17_en : 1; /* [17] */ ++ unsigned int p18_en : 1; /* [18] */ ++ unsigned int p19_en : 1; /* [19] */ ++ unsigned int p20_en : 1; /* [20] */ ++ unsigned int p21_en : 1; /* [21] */ ++ unsigned int p22_en : 1; /* [22] */ ++ unsigned int p23_en : 1; /* [23] */ ++ unsigned int p24_en : 1; /* [24] */ ++ unsigned int p25_en : 1; /* [25] */ ++ unsigned int p26_en : 1; /* [26] */ ++ unsigned int p27_en : 1; /* [27] */ ++ unsigned int p28_en : 1; /* [28] */ ++ unsigned int p29_en : 1; /* [29] */ ++ unsigned int p30_en : 1; /* [30] */ ++ unsigned int p31_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ccdoposmskl; ++ ++/* define the union reg_dhd0_dacdet1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vdac_det_high : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int det_line : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_dacdet1; ++ ++/* define the union reg_dhd0_dacdet2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int det_pixel_sta : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int det_pixel_wid : 11; /* [26..16] */ ++ unsigned int reserved_1 : 4; /* [30..27] */ ++ unsigned int vdac_det_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_dacdet2; ++ ++/* define the union reg_dhd0_ccd_info1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int img_mode : 7; /* [6..0] */ ++ unsigned int img_right : 1; /* [7] */ ++ unsigned int img_id : 2; /* [9..8] */ ++ unsigned int reserved_0 : 1; /* [10] */ ++ unsigned int ccd_en : 1; /* [11] */ ++ unsigned int reserved_1 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ccd_info1; ++ ++/* define the union reg_dhd0_ccd_info2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int p32_en : 1; /* [0] */ ++ unsigned int p33_en : 1; /* [1] */ ++ unsigned int p34_en : 1; /* [2] */ ++ unsigned int p35_en : 1; /* [3] */ ++ unsigned int p36_en : 1; /* [4] */ ++ unsigned int p37_en : 1; /* [5] */ ++ unsigned int p38_en : 1; /* [6] */ ++ unsigned int p39_en : 1; /* [7] */ ++ unsigned int p40_en : 1; /* [8] */ ++ unsigned int p41_en : 1; /* [9] */ ++ unsigned int p42_en : 1; /* [10] */ ++ unsigned int p43_en : 1; /* [11] */ ++ unsigned int p44_en : 1; /* [12] */ ++ unsigned int p45_en : 1; /* [13] */ ++ unsigned int p46_en : 1; /* [14] */ ++ unsigned int p47_en : 1; /* [15] */ ++ unsigned int p48_en : 1; /* [16] */ ++ unsigned int p49_en : 1; /* [17] */ ++ unsigned int p50_en : 1; /* [18] */ ++ unsigned int p51_en : 1; /* [19] */ ++ unsigned int p52_en : 1; /* [20] */ ++ unsigned int p53_en : 1; /* [21] */ ++ unsigned int p54_en : 1; /* [22] */ ++ unsigned int p55_en : 1; /* [23] */ ++ unsigned int p56_en : 1; /* [24] */ ++ unsigned int p57_en : 1; /* [25] */ ++ unsigned int p58_en : 1; /* [26] */ ++ unsigned int p59_en : 1; /* [27] */ ++ unsigned int p60_en : 1; /* [28] */ ++ unsigned int p61_en : 1; /* [29] */ ++ unsigned int p62_en : 1; /* [30] */ ++ unsigned int p63_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ccd_info2; ++ ++/* define the union reg_dhd0_ccd_info3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int p0_en : 1; /* [0] */ ++ unsigned int p1_en : 1; /* [1] */ ++ unsigned int p2_en : 1; /* [2] */ ++ unsigned int p3_en : 1; /* [3] */ ++ unsigned int p4_en : 1; /* [4] */ ++ unsigned int p5_en : 1; /* [5] */ ++ unsigned int p6_en : 1; /* [6] */ ++ unsigned int p7_en : 1; /* [7] */ ++ unsigned int p8_en : 1; /* [8] */ ++ unsigned int p9_en : 1; /* [9] */ ++ unsigned int p10_en : 1; /* [10] */ ++ unsigned int p11_en : 1; /* [11] */ ++ unsigned int p12_en : 1; /* [12] */ ++ unsigned int p13_en : 1; /* [13] */ ++ unsigned int p14_en : 1; /* [14] */ ++ unsigned int p15_en : 1; /* [15] */ ++ unsigned int p16_en : 1; /* [16] */ ++ unsigned int p17_en : 1; /* [17] */ ++ unsigned int p18_en : 1; /* [18] */ ++ unsigned int p19_en : 1; /* [19] */ ++ unsigned int p20_en : 1; /* [20] */ ++ unsigned int p21_en : 1; /* [21] */ ++ unsigned int p22_en : 1; /* [22] */ ++ unsigned int p23_en : 1; /* [23] */ ++ unsigned int p24_en : 1; /* [24] */ ++ unsigned int p25_en : 1; /* [25] */ ++ unsigned int p26_en : 1; /* [26] */ ++ unsigned int p27_en : 1; /* [27] */ ++ unsigned int p28_en : 1; /* [28] */ ++ unsigned int p29_en : 1; /* [29] */ ++ unsigned int p30_en : 1; /* [30] */ ++ unsigned int p31_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd0_ccd_info3; ++ ++/* define the union reg_intf_hdmi_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int hdmi_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_hdmi_ctrl; ++ ++/* define the union reg_intf_hdmi_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_hdmi_upd; ++ ++/* define the union reg_intf_hdmi_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_hdmi_sync_inv; ++ ++/* define the union reg_hdmi_intf_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int r0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_intf_chksum_high; ++ ++/* define the union reg_hdmi_intf1_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int r1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_intf1_chksum_high; ++ ++/* define the union reg_hdmi_hfir_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_hfir_coef0; ++ ++/* define the union reg_hdmi_hfir_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_hfir_coef1; ++ ++/* define the union reg_hdmi_hfir_coef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_hfir_coef2; ++ ++/* define the union reg_hdmi_hfir_coef3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_hfir_coef3; ++ ++/* define the union reg_hdmi_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_idc; ++ ++/* define the union reg_hdmi_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_odc; ++ ++/* define the union reg_hdmi_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_iodc; ++ ++/* define the union reg_hdmi_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_p0; ++ ++/* define the union reg_hdmi_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_p1; ++ ++/* define the union reg_hdmi_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_p2; ++ ++/* define the union reg_hdmi_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_p3; ++ ++/* define the union reg_hdmi_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi_csc_p4; ++ ++/* define the union reg_intf_mipi_del_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_mipi_del_ctrl; ++ ++/* define the union reg_intf_mipi_del_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_mipi_del_upd; ++ ++/* define the union reg_intf_mipi_del_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_mipi_del_sync_inv; ++ ++/* define the union reg_mipi_del_intf_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int b0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int r0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_intf_chksum_high; ++ ++/* define the union reg_mipi_del_intf1_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int b1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int r1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_intf1_chksum_high; ++ ++/* define the union reg_mipi_del_hfir_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_hfir_coef0; ++ ++/* define the union reg_mipi_del_hfir_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_hfir_coef1; ++ ++/* define the union reg_mipi_del_hfir_coef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_hfir_coef2; ++ ++/* define the union reg_mipi_del_hfir_coef3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_hfir_coef3; ++ ++/* define the union reg_mipi_del_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_idc; ++ ++/* define the union reg_mipi_del_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_odc; ++ ++/* define the union reg_mipi_del_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_iodc; ++ ++/* define the union reg_mipi_del_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_p0; ++ ++/* define the union reg_mipi_del_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_p1; ++ ++/* define the union reg_mipi_del_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_p2; ++ ++/* define the union reg_mipi_del_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_p3; ++ ++/* define the union reg_mipi_del_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_del_csc_p4; ++ ++/* define the union reg_intf_bt_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 16; /* [15..0] */ ++ unsigned int data_width : 1; /* [16] */ ++ unsigned int bit_inv : 1; /* [17] */ ++ unsigned int uv_mode : 1; /* [18] */ ++ unsigned int yc_mode : 1; /* [19] */ ++ unsigned int reserved_1 : 10; /* [29..20] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_bt_ctrl; ++ ++/* define the union reg_intf_bt_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_bt_upd; ++ ++/* define the union reg_intf_bt_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_bt_sync_inv; ++ ++/* define the union reg_bt_clip0_l */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int clip_cl0 : 10; /* [9..0] */ ++ unsigned int clip_cl1 : 10; /* [19..10] */ ++ unsigned int clip_cl2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int clip_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_clip0_l; ++ ++/* define the union reg_bt_clip0_h */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int clip_ch0 : 10; /* [9..0] */ ++ unsigned int clip_ch1 : 10; /* [19..10] */ ++ unsigned int clip_ch2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_clip0_h; ++ ++/* define the union reg_bt_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_ctrl; ++ ++/* define the union reg_bt_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_y0; ++ ++/* define the union reg_bt_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_u0; ++ ++/* define the union reg_bt_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_v0; ++ ++/* define the union reg_bt_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_w0; ++ ++/* define the union reg_bt_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_y1; ++ ++/* define the union reg_bt_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_u1; ++ ++/* define the union reg_bt_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_v1; ++ ++/* define the union reg_bt_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_w1; ++ ++/* define the union reg_bt_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_y2; ++ ++/* define the union reg_bt_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_u2; ++ ++/* define the union reg_bt_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_v2; ++ ++/* define the union reg_bt_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_w2; ++ ++/* define the union reg_bt_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_y3; ++ ++/* define the union reg_bt_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_u3; ++ ++/* define the union reg_bt_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_v3; ++ ++/* define the union reg_bt_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_sed_w3; ++ ++/* define the union reg_bt_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_bt_dither_thr; ++ ++/* define the union reg_intf_lcd_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 20; /* [19..0] */ ++ unsigned int lcd_format : 4; /* [23..20] */ ++ unsigned int lcd_bit_inv : 1; /* [24] */ ++ unsigned int lcd_comp_order : 1; /* [25] */ ++ unsigned int lcd_serial_perd : 1; /* [26] */ ++ unsigned int reserved_1 : 3; /* [29..27] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_lcd_ctrl; ++ ++/* define the union reg_intf_lcd_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_lcd_upd; ++ ++/* define the union reg_intf_lcd_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_lcd_sync_inv; ++ ++/* define the union reg_lcd_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_idc; ++ ++/* define the union reg_lcd_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_odc; ++ ++/* define the union reg_lcd_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_iodc; ++ ++/* define the union reg_lcd_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_p0; ++ ++/* define the union reg_lcd_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_p1; ++ ++/* define the union reg_lcd_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_p2; ++ ++/* define the union reg_lcd_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_p3; ++ ++/* define the union reg_lcd_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_csc_p4; ++ ++/* define the union reg_lcd_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_ctrl; ++ ++/* define the union reg_lcd_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_y0; ++ ++/* define the union reg_lcd_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_u0; ++ ++/* define the union reg_lcd_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_v0; ++ ++/* define the union reg_lcd_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_w0; ++ ++/* define the union reg_lcd_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_y1; ++ ++/* define the union reg_lcd_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_u1; ++ ++/* define the union reg_lcd_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_v1; ++ ++/* define the union reg_lcd_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_w1; ++ ++/* define the union reg_lcd_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_y2; ++ ++/* define the union reg_lcd_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_u2; ++ ++/* define the union reg_lcd_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_v2; ++ ++/* define the union reg_lcd_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_w2; ++ ++/* define the union reg_lcd_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_y3; ++ ++/* define the union reg_lcd_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_u3; ++ ++/* define the union reg_lcd_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_v3; ++ ++/* define the union reg_lcd_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_sed_w3; ++ ++/* define the union reg_lcd_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_lcd_dither_thr; ++ ++/* define the union reg_intf_hdmi1_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int hdmi_mode : 2; /* [5..4] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_hdmi1_ctrl; ++ ++/* define the union reg_intf_hdmi1_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_hdmi1_upd; ++ ++/* define the union reg_intf_hdmi1_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_hdmi1_sync_inv; ++ ++/* define the union reg_hdmi1_intf_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int r0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi1_intf_chksum_high; ++ ++/* define the union reg_hdmi1_intf1_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int r1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi1_intf1_chksum_high; ++ ++/* define the union reg_hdmi1_hfir_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi1_hfir_coef0; ++ ++/* define the union reg_hdmi1_hfir_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi1_hfir_coef1; ++ ++/* define the union reg_hdmi1_hfir_coef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi1_hfir_coef2; ++ ++/* define the union reg_hdmi1_hfir_coef3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_hdmi1_hfir_coef3; ++ ++/* define the union reg_intf_vga_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 24; /* [23..0] */ ++ unsigned int yc_mode : 1; /* [24] */ ++ unsigned int lcd_parallel_mode : 1; /* [25] */ ++ unsigned int lcd_data_inv : 1; /* [26] */ ++ unsigned int lcd_parallel_order : 1; /* [27] */ ++ unsigned int lcd_serial_perd : 1; /* [28] */ ++ unsigned int lcd_serial_mode : 1; /* [29] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_vga_ctrl; ++ ++/* define the union reg_intf_vga_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_vga_upd; ++ ++/* define the union reg_intf_vga_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_vga_sync_inv; ++ ++/* define the union reg_vga_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_idc; ++ ++/* define the union reg_vga_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_odc; ++ ++/* define the union reg_vga_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_iodc; ++ ++/* define the union reg_vga_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_p0; ++ ++/* define the union reg_vga_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_p1; ++ ++/* define the union reg_vga_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_p2; ++ ++/* define the union reg_vga_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_p3; ++ ++/* define the union reg_vga_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_csc_p4; ++ ++/* define the union reg_vga_hspcfg0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_tmp0 : 8; /* [7..0] */ ++ unsigned int hsp_hf0_tmp1 : 8; /* [15..8] */ ++ unsigned int hsp_hf0_tmp2 : 8; /* [23..16] */ ++ unsigned int hsp_hf0_tmp3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg0; ++ ++/* define the union reg_vga_hspcfg1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_coring : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int hsp_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg1; ++ ++/* define the union reg_vga_hspcfg5 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_gainpos : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int hsp_hf0_gainneg : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg5; ++ ++/* define the union reg_vga_hspcfg6 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf0_overth : 8; /* [7..0] */ ++ unsigned int hsp_hf0_underth : 8; /* [15..8] */ ++ unsigned int hsp_hf0_mixratio : 8; /* [23..16] */ ++ unsigned int reserved_0 : 4; /* [27..24] */ ++ unsigned int hsp_hf0_winsize : 3; /* [30..28] */ ++ unsigned int hsp_hf0_adpshoot_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg6; ++ ++/* define the union reg_vga_hspcfg7 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_tmp0 : 8; /* [7..0] */ ++ unsigned int hsp_hf1_tmp1 : 8; /* [15..8] */ ++ unsigned int hsp_hf1_tmp2 : 8; /* [23..16] */ ++ unsigned int hsp_hf1_tmp3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg7; ++ ++/* define the union reg_vga_hspcfg8 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_coring : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg8; ++ ++/* define the union reg_vga_hspcfg12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_gainpos : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int hsp_hf1_gainneg : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg12; ++ ++/* define the union reg_vga_hspcfg13 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_hf1_overth : 8; /* [7..0] */ ++ unsigned int hsp_hf1_underth : 8; /* [15..8] */ ++ unsigned int hsp_hf1_mixratio : 8; /* [23..16] */ ++ unsigned int reserved_0 : 4; /* [27..24] */ ++ unsigned int hsp_hf1_winsize : 3; /* [30..28] */ ++ unsigned int hsp_hf1_adpshoot_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg13; ++ ++/* define the union reg_vga_hspcfg14 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_cdti_gain : 8; /* [7..0] */ ++ unsigned int hsp_ldti_gain : 8; /* [15..8] */ ++ unsigned int hsp_lti_ratio : 8; /* [23..16] */ ++ unsigned int hsp_hf_shootdiv : 3; /* [26..24] */ ++ unsigned int reserved_0 : 1; /* [27] */ ++ unsigned int hsp_ctih_en : 1; /* [28] */ ++ unsigned int hsp_ltih_en : 1; /* [29] */ ++ unsigned int hsp_h1_en : 1; /* [30] */ ++ unsigned int hsp_h0_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg14; ++ ++/* define the union reg_vga_hspcfg15 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hsp_glb_underth : 9; /* [8..0] */ ++ unsigned int reserved_0 : 1; /* [9] */ ++ unsigned int hsp_glb_overth : 9; /* [18..10] */ ++ unsigned int reserved_1 : 1; /* [19] */ ++ unsigned int hsp_peak_ratio : 8; /* [27..20] */ ++ unsigned int reserved_2 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vga_hspcfg15; ++ ++/* define the union reg_intf_date_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 23; /* [22..0] */ ++ unsigned int uv_mode : 1; /* [23] */ ++ unsigned int yc_mode : 1; /* [24] */ ++ unsigned int lcd_parallel_mode : 1; /* [25] */ ++ unsigned int lcd_data_inv : 1; /* [26] */ ++ unsigned int lcd_parallel_order : 1; /* [27] */ ++ unsigned int lcd_serial_perd : 1; /* [28] */ ++ unsigned int lcd_serial_mode : 1; /* [29] */ ++ unsigned int dfir_en : 1; /* [30] */ ++ unsigned int hdmi_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_date_ctrl; ++ ++/* define the union reg_intf_date_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_date_upd; ++ ++/* define the union reg_intf_date_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_date_sync_inv; ++ ++/* define the union reg_date_clip0_l */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int clip_cl0 : 10; /* [9..0] */ ++ unsigned int clip_cl1 : 10; /* [19..10] */ ++ unsigned int clip_cl2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 1; /* [30] */ ++ unsigned int clip_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_clip0_l; ++ ++/* define the union reg_date_clip0_h */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int clip_ch0 : 10; /* [9..0] */ ++ unsigned int clip_ch1 : 10; /* [19..10] */ ++ unsigned int clip_ch2 : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_clip0_h; ++ ++/* define the union reg_intf0_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_ctrl; ++ ++/* define the union reg_intf0_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_y0; ++ ++/* define the union reg_intf0_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_u0; ++ ++/* define the union reg_intf0_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_v0; ++ ++/* define the union reg_intf0_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_w0; ++ ++/* define the union reg_intf0_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_y1; ++ ++/* define the union reg_intf0_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_u1; ++ ++/* define the union reg_intf0_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_v1; ++ ++/* define the union reg_intf0_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_w1; ++ ++/* define the union reg_intf0_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_y2; ++ ++/* define the union reg_intf0_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_u2; ++ ++/* define the union reg_intf0_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_v2; ++ ++/* define the union reg_intf0_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_w2; ++ ++/* define the union reg_intf0_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_y3; ++ ++/* define the union reg_intf0_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_u3; ++ ++/* define the union reg_intf0_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_v3; ++ ++/* define the union reg_intf0_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_sed_w3; ++ ++/* define the union reg_intf0_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf0_dither_thr; ++ ++/* define the union reg_intf_mipi_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_422_en : 1; /* [0] */ ++ unsigned int intf_420_en : 1; /* [1] */ ++ unsigned int intf_420_mode : 2; /* [3..2] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_mipi_ctrl; ++ ++/* define the union reg_intf_mipi_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_mipi_upd; ++ ++/* define the union reg_intf_mipi_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dv_inv : 1; /* [0] */ ++ unsigned int hs_inv : 1; /* [1] */ ++ unsigned int vs_inv : 1; /* [2] */ ++ unsigned int f_inv : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf_mipi_sync_inv; ++ ++/* define the union reg_mipi_intf_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int b0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int r0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_intf_chksum_high; ++ ++/* define the union reg_mipi_intf1_chksum_high */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int b1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int r1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_intf1_chksum_high; ++ ++/* define the union reg_mipi_hfir_coef0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef0 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef1 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_hfir_coef0; ++ ++/* define the union reg_mipi_hfir_coef1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef2 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef3 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_hfir_coef1; ++ ++/* define the union reg_mipi_hfir_coef2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef4 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int hfir_coef5 : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_hfir_coef2; ++ ++/* define the union reg_mipi_hfir_coef3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfir_coef6 : 10; /* [9..0] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_hfir_coef3; ++ ++/* define the union reg_mipi_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_idc; ++ ++/* define the union reg_mipi_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_odc; ++ ++/* define the union reg_mipi_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_iodc; ++ ++/* define the union reg_mipi_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_p0; ++ ++/* define the union reg_mipi_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_p1; ++ ++/* define the union reg_mipi_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_p2; ++ ++/* define the union reg_mipi_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_p3; ++ ++/* define the union reg_mipi_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_csc_p4; ++ ++/* define the union reg_mipi_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_ctrl; ++ ++/* define the union reg_mipi_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_y0; ++ ++/* define the union reg_mipi_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_u0; ++ ++/* define the union reg_mipi_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_v0; ++ ++/* define the union reg_mipi_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_w0; ++ ++/* define the union reg_mipi_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_y1; ++ ++/* define the union reg_mipi_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_u1; ++ ++/* define the union reg_mipi_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_v1; ++ ++/* define the union reg_mipi_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_w1; ++ ++/* define the union reg_mipi_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_y2; ++ ++/* define the union reg_mipi_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_u2; ++ ++/* define the union reg_mipi_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_v2; ++ ++/* define the union reg_mipi_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_w2; ++ ++/* define the union reg_mipi_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_y3; ++ ++/* define the union reg_mipi_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_u3; ++ ++/* define the union reg_mipi_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_v3; ++ ++/* define the union reg_mipi_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_sed_w3; ++ ++/* define the union reg_mipi_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mipi_dither_thr; ++ ++/* define the union reg_dhd1_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int disp_mode : 3; /* [3..1] */ ++ unsigned int iop : 1; /* [4] */ ++ unsigned int intf_ivs : 1; /* [5] */ ++ unsigned int intf_ihs : 1; /* [6] */ ++ unsigned int intf_idv : 1; /* [7] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int hdmi420c_sel : 1; /* [9] */ ++ unsigned int hdmi420_en : 1; /* [10] */ ++ unsigned int uf_offline_en : 1; /* [11] */ ++ unsigned int reserved_1 : 2; /* [13..12] */ ++ unsigned int hdmi_mode : 1; /* [14] */ ++ unsigned int twochn_debug : 1; /* [15] */ ++ unsigned int twochn_en : 1; /* [16] */ ++ unsigned int reserved_2 : 1; /* [17] */ ++ unsigned int cbar_mode : 1; /* [18] */ ++ unsigned int sin_en : 1; /* [19] */ ++ unsigned int fpga_lmt_width : 7; /* [26..20] */ ++ unsigned int fpga_lmt_en : 1; /* [27] */ ++ unsigned int p2i_en : 1; /* [28] */ ++ unsigned int cbar_sel : 1; /* [29] */ ++ unsigned int cbar_en : 1; /* [30] */ ++ unsigned int intf_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_ctrl; ++ ++/* define the union reg_dhd1_vsync1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vact : 16; /* [15..0] */ ++ unsigned int vbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vsync1; ++ ++/* define the union reg_dhd1_vsync2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vsync2; ++ ++/* define the union reg_dhd1_hsync1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hact : 16; /* [15..0] */ ++ unsigned int hbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_hsync1; ++ ++/* define the union reg_dhd1_hsync2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfb : 16; /* [15..0] */ ++ unsigned int hmid : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_hsync2; ++ ++/* define the union reg_dhd1_vplus1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvact : 16; /* [15..0] */ ++ unsigned int bvbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vplus1; ++ ++/* define the union reg_dhd1_vplus2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vplus2; ++ ++/* define the union reg_dhd1_pwr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hpw : 16; /* [15..0] */ ++ unsigned int vpw : 8; /* [23..16] */ ++ unsigned int reserved_0 : 3; /* [26..24] */ ++ unsigned int multichn_en : 2; /* [28..27] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_pwr; ++ ++/* define the union reg_dhd1_vtthd3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vtmgthd3 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd3_mode : 1; /* [15] */ ++ unsigned int vtmgthd4 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd4_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vtthd3; ++ ++/* define the union reg_dhd1_vtthd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vtmgthd1 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd1_mode : 1; /* [15] */ ++ unsigned int vtmgthd2 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd2_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vtthd; ++ ++/* define the union reg_dhd1_parathd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int dfs_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_parathd; ++ ++/* define the union reg_dhd1_precharge_thd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tcon_precharge_thd : 17; /* [16..0] */ ++ unsigned int reserved_0 : 3; /* [19..17] */ ++ unsigned int vsync_te_mode : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_precharge_thd; ++ ++/* define the union reg_dhd1_start_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int start_pos : 8; /* [7..0] */ ++ unsigned int timing_start_pos : 8; /* [15..8] */ ++ unsigned int fi_start_pos : 4; /* [19..16] */ ++ unsigned int req_start_pos : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_start_pos; ++ ++/* define the union reg_dhd1_start_pos1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_start_pos1 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_start_pos1; ++ ++/* define the union reg_dhd1_paraup */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int paraup_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_paraup; ++ ++/* define the union reg_dhd1_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lcd_dv_inv : 1; /* [0] */ ++ unsigned int lcd_hs_inv : 1; /* [1] */ ++ unsigned int lcd_vs_inv : 1; /* [2] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int vga_dv_inv : 1; /* [4] */ ++ unsigned int vga_hs_inv : 1; /* [5] */ ++ unsigned int vga_vs_inv : 1; /* [6] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int hdmi_dv_inv : 1; /* [8] */ ++ unsigned int hdmi_hs_inv : 1; /* [9] */ ++ unsigned int hdmi_vs_inv : 1; /* [10] */ ++ unsigned int hdmi_f_inv : 1; /* [11] */ ++ unsigned int date_dv_inv : 1; /* [12] */ ++ unsigned int date_hs_inv : 1; /* [13] */ ++ unsigned int date_vs_inv : 1; /* [14] */ ++ unsigned int date_f_inv : 1; /* [15] */ ++ unsigned int reserved_2 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_sync_inv; ++ ++/* define the union reg_dhd1_clk_dv_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_clk_mux : 1; /* [0] */ ++ unsigned int intf_dv_mux : 1; /* [1] */ ++ unsigned int no_active_area_pos : 16; /* [17..2] */ ++ unsigned int reserved_0 : 14; /* [31..18] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_clk_dv_ctrl; ++ ++/* define the union reg_dhd1_rgb_fix_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fix_b : 10; /* [9..0] */ ++ unsigned int fix_g : 10; /* [19..10] */ ++ unsigned int fix_r : 10; /* [29..20] */ ++ unsigned int rgb_fix_mux : 1; /* [30] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_rgb_fix_ctrl; ++ ++/* define the union reg_dhd1_lockcfg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int measure_en : 1; /* [0] */ ++ unsigned int lock_cnt_en : 1; /* [1] */ ++ unsigned int vdp_measure_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_lockcfg; ++ ++/* define the union reg_dhd1_intf_chksum_high1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int y0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_intf_chksum_high1; ++ ++/* define the union reg_dhd1_intf_chksum_high2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int y1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_intf_chksum_high2; ++ ++/* define the union reg_dhd1_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vback_blank : 1; /* [0] */ ++ unsigned int vblank : 1; /* [1] */ ++ unsigned int bottom_field : 1; /* [2] */ ++ unsigned int vcnt : 13; /* [15..3] */ ++ unsigned int count_int : 8; /* [23..16] */ ++ unsigned int dhd_even : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_state; ++ ++/* define the union reg_dhd1_uf_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ud_first_cnt : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int start_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_uf_state; ++ ++/* define the union reg_dhd1_vsync_te_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vsync_te_start_sta : 8; /* [7..0] */ ++ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ ++ unsigned int vsync_te_end_sta : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vsync_te_state; ++ ++/* define the union reg_dhd1_vsync_te_state1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vsync_te_vfb : 16; /* [15..0] */ ++ unsigned int vsync_te_width : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd1_vsync_te_state1; ++ ++/* define the union reg_intf1_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_ctrl; ++ ++/* define the union reg_intf1_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_y0; ++ ++/* define the union reg_intf1_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_u0; ++ ++/* define the union reg_intf1_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_v0; ++ ++/* define the union reg_intf1_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_w0; ++ ++/* define the union reg_intf1_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_y1; ++ ++/* define the union reg_intf1_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_u1; ++ ++/* define the union reg_intf1_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_v1; ++ ++/* define the union reg_intf1_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_w1; ++ ++/* define the union reg_intf1_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_y2; ++ ++/* define the union reg_intf1_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_u2; ++ ++/* define the union reg_intf1_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_v2; ++ ++/* define the union reg_intf1_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_w2; ++ ++/* define the union reg_intf1_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_y3; ++ ++/* define the union reg_intf1_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_u3; ++ ++/* define the union reg_intf1_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_v3; ++ ++/* define the union reg_intf1_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_sed_w3; ++ ++/* define the union reg_intf1_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf1_dither_thr; ++ ++/* define the union reg_dhd2_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int disp_mode : 3; /* [3..1] */ ++ unsigned int iop : 1; /* [4] */ ++ unsigned int intf_ivs : 1; /* [5] */ ++ unsigned int intf_ihs : 1; /* [6] */ ++ unsigned int intf_idv : 1; /* [7] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int hdmi420c_sel : 1; /* [9] */ ++ unsigned int hdmi420_en : 1; /* [10] */ ++ unsigned int uf_offline_en : 1; /* [11] */ ++ unsigned int reserved_1 : 2; /* [13..12] */ ++ unsigned int hdmi_mode : 1; /* [14] */ ++ unsigned int twochn_debug : 1; /* [15] */ ++ unsigned int twochn_en : 1; /* [16] */ ++ unsigned int reserved_2 : 1; /* [17] */ ++ unsigned int cbar_mode : 1; /* [18] */ ++ unsigned int sin_en : 1; /* [19] */ ++ unsigned int fpga_lmt_width : 7; /* [26..20] */ ++ unsigned int fpga_lmt_en : 1; /* [27] */ ++ unsigned int p2i_en : 1; /* [28] */ ++ unsigned int cbar_sel : 1; /* [29] */ ++ unsigned int cbar_en : 1; /* [30] */ ++ unsigned int intf_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_ctrl; ++ ++/* define the union reg_dhd2_vsync1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vact : 16; /* [15..0] */ ++ unsigned int vbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vsync1; ++ ++/* define the union reg_dhd2_vsync2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vsync2; ++ ++/* define the union reg_dhd2_hsync1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hact : 16; /* [15..0] */ ++ unsigned int hbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_hsync1; ++ ++/* define the union reg_dhd2_hsync2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hfb : 16; /* [15..0] */ ++ unsigned int hmid : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_hsync2; ++ ++/* define the union reg_dhd2_vplus1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvact : 16; /* [15..0] */ ++ unsigned int bvbb : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vplus1; ++ ++/* define the union reg_dhd2_vplus2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvfb : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vplus2; ++ ++/* define the union reg_dhd2_pwr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hpw : 16; /* [15..0] */ ++ unsigned int vpw : 8; /* [23..16] */ ++ unsigned int reserved_0 : 3; /* [26..24] */ ++ unsigned int multichn_en : 2; /* [28..27] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_pwr; ++ ++/* define the union reg_dhd2_vtthd3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vtmgthd3 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd3_mode : 1; /* [15] */ ++ unsigned int vtmgthd4 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd4_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vtthd3; ++ ++/* define the union reg_dhd2_vtthd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vtmgthd1 : 13; /* [12..0] */ ++ unsigned int reserved_0 : 2; /* [14..13] */ ++ unsigned int thd1_mode : 1; /* [15] */ ++ unsigned int vtmgthd2 : 13; /* [28..16] */ ++ unsigned int reserved_1 : 2; /* [30..29] */ ++ unsigned int thd2_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vtthd; ++ ++/* define the union reg_dhd2_parathd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_thd : 8; /* [7..0] */ ++ unsigned int reserved_0 : 23; /* [30..8] */ ++ unsigned int dfs_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_parathd; ++ ++/* define the union reg_dhd2_precharge_thd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tcon_precharge_thd : 17; /* [16..0] */ ++ unsigned int reserved_0 : 3; /* [19..17] */ ++ unsigned int vsync_te_mode : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_precharge_thd; ++ ++/* define the union reg_dhd2_start_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int start_pos : 8; /* [7..0] */ ++ unsigned int timing_start_pos : 8; /* [15..8] */ ++ unsigned int fi_start_pos : 4; /* [19..16] */ ++ unsigned int req_start_pos : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_start_pos; ++ ++/* define the union reg_dhd2_start_pos1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_start_pos1 : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_start_pos1; ++ ++/* define the union reg_dhd2_paraup */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int paraup_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_paraup; ++ ++/* define the union reg_dhd2_sync_inv */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lcd_dv_inv : 1; /* [0] */ ++ unsigned int lcd_hs_inv : 1; /* [1] */ ++ unsigned int lcd_vs_inv : 1; /* [2] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int vga_dv_inv : 1; /* [4] */ ++ unsigned int vga_hs_inv : 1; /* [5] */ ++ unsigned int vga_vs_inv : 1; /* [6] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int hdmi_dv_inv : 1; /* [8] */ ++ unsigned int hdmi_hs_inv : 1; /* [9] */ ++ unsigned int hdmi_vs_inv : 1; /* [10] */ ++ unsigned int hdmi_f_inv : 1; /* [11] */ ++ unsigned int date_dv_inv : 1; /* [12] */ ++ unsigned int date_hs_inv : 1; /* [13] */ ++ unsigned int date_vs_inv : 1; /* [14] */ ++ unsigned int date_f_inv : 1; /* [15] */ ++ unsigned int reserved_2 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_sync_inv; ++ ++/* define the union reg_dhd2_clk_dv_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int intf_clk_mux : 1; /* [0] */ ++ unsigned int intf_dv_mux : 1; /* [1] */ ++ unsigned int no_active_area_pos : 16; /* [17..2] */ ++ unsigned int reserved_0 : 14; /* [31..18] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_clk_dv_ctrl; ++ ++/* define the union reg_dhd2_rgb_fix_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fix_b : 10; /* [9..0] */ ++ unsigned int fix_g : 10; /* [19..10] */ ++ unsigned int fix_r : 10; /* [29..20] */ ++ unsigned int rgb_fix_mux : 1; /* [30] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_rgb_fix_ctrl; ++ ++/* define the union reg_dhd2_lockcfg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int measure_en : 1; /* [0] */ ++ unsigned int lock_cnt_en : 1; /* [1] */ ++ unsigned int vdp_measure_en : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_lockcfg; ++ ++/* define the union reg_dhd2_intf_chksum_high1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int y0_sum_high : 8; /* [7..0] */ ++ unsigned int g0_sum_high : 8; /* [15..8] */ ++ unsigned int b0_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_intf_chksum_high1; ++ ++/* define the union reg_dhd2_intf_chksum_high2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int y1_sum_high : 8; /* [7..0] */ ++ unsigned int g1_sum_high : 8; /* [15..8] */ ++ unsigned int b1_sum_high : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_intf_chksum_high2; ++ ++/* define the union reg_dhd2_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vback_blank : 1; /* [0] */ ++ unsigned int vblank : 1; /* [1] */ ++ unsigned int bottom_field : 1; /* [2] */ ++ unsigned int vcnt : 13; /* [15..3] */ ++ unsigned int count_int : 8; /* [23..16] */ ++ unsigned int dhd_even : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_state; ++ ++/* define the union reg_dhd2_uf_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ud_first_cnt : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int start_pos : 8; /* [23..16] */ ++ unsigned int reserved_1 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_uf_state; ++ ++/* define the union reg_dhd2_vsync_te_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vsync_te_start_sta : 8; /* [7..0] */ ++ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ ++ unsigned int vsync_te_end_sta : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vsync_te_state; ++ ++/* define the union reg_dhd2_vsync_te_state1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vsync_te_vfb : 16; /* [15..0] */ ++ unsigned int vsync_te_width : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_dhd2_vsync_te_state1; ++ ++/* define the union reg_intf2_dither_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_tap_mode : 2; /* [1..0] */ ++ unsigned int dither_domain_mode : 1; /* [2] */ ++ unsigned int dither_round : 1; /* [3] */ ++ unsigned int dither_mode : 1; /* [4] */ ++ unsigned int dither_en : 1; /* [5] */ ++ unsigned int dither_round_unlim : 1; /* [6] */ ++ unsigned int i_data_width_dither : 3; /* [9..7] */ ++ unsigned int o_data_width_dither : 3; /* [12..10] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_ctrl; ++ ++/* define the union reg_intf2_dither_sed_y0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_y0; ++ ++/* define the union reg_intf2_dither_sed_u0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_u0; ++ ++/* define the union reg_intf2_dither_sed_v0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_v0; ++ ++/* define the union reg_intf2_dither_sed_w0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w0 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_w0; ++ ++/* define the union reg_intf2_dither_sed_y1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_y1; ++ ++/* define the union reg_intf2_dither_sed_u1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_u1; ++ ++/* define the union reg_intf2_dither_sed_v1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_v1; ++ ++/* define the union reg_intf2_dither_sed_w1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w1 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_w1; ++ ++/* define the union reg_intf2_dither_sed_y2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_y2; ++ ++/* define the union reg_intf2_dither_sed_u2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_u2; ++ ++/* define the union reg_intf2_dither_sed_v2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_v2; ++ ++/* define the union reg_intf2_dither_sed_w2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w2 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_w2; ++ ++/* define the union reg_intf2_dither_sed_y3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_y3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_y3; ++ ++/* define the union reg_intf2_dither_sed_u3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_u3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_u3; ++ ++/* define the union reg_intf2_dither_sed_v3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_v3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_v3; ++ ++/* define the union reg_intf2_dither_sed_w3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_sed_w3 : 31; /* [30..0] */ ++ unsigned int reserved_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_sed_w3; ++ ++/* define the union reg_intf2_dither_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dither_thr_min : 16; /* [15..0] */ ++ unsigned int dither_thr_max : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_intf2_dither_thr; ++ ++/* define the union reg_date_coeff0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt_seq : 1; /* [0] */ ++ unsigned int chgain_en : 1; /* [1] */ ++ unsigned int sylp_en : 1; /* [2] */ ++ unsigned int chlp_en : 1; /* [3] */ ++ unsigned int oversam2_en : 1; /* [4] */ ++ unsigned int lunt_en : 1; /* [5] */ ++ unsigned int oversam_en : 2; /* [7..6] */ ++ unsigned int reserved_0 : 1; /* [8] */ ++ unsigned int luma_dl : 4; /* [12..9] */ ++ unsigned int agc_amp_sel : 1; /* [13] */ ++ unsigned int length_sel : 1; /* [14] */ ++ unsigned int sync_mode_scart : 1; /* [15] */ ++ unsigned int sync_mode_sel : 2; /* [17..16] */ ++ unsigned int style_sel : 4; /* [21..18] */ ++ unsigned int fm_sel : 1; /* [22] */ ++ unsigned int vbi_lpf_en : 1; /* [23] */ ++ unsigned int rgb_en : 1; /* [24] */ ++ unsigned int scanline : 1; /* [25] */ ++ unsigned int pbpr_lpf_en : 1; /* [26] */ ++ unsigned int pal_half_en : 1; /* [27] */ ++ unsigned int reserved_1 : 1; /* [28] */ ++ unsigned int dis_ire : 1; /* [29] */ ++ unsigned int clpf_sel : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff0; ++ ++/* define the union reg_date_coeff1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dac_test : 10; /* [9..0] */ ++ unsigned int date_test_mode : 2; /* [11..10] */ ++ unsigned int date_test_en : 1; /* [12] */ ++ unsigned int amp_outside : 10; /* [22..13] */ ++ unsigned int c_limit_en : 1; /* [23] */ ++ unsigned int cc_seq : 1; /* [24] */ ++ unsigned int cgms_seq : 1; /* [25] */ ++ unsigned int vps_seq : 1; /* [26] */ ++ unsigned int wss_seq : 1; /* [27] */ ++ unsigned int cvbs_limit_en : 1; /* [28] */ ++ unsigned int c_gain : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff1; ++ ++/* define the union reg_date_coeff3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef03 : 26; /* [25..0] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff3; ++ ++/* define the union reg_date_coeff4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef04 : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff4; ++ ++/* define the union reg_date_coeff5 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef05 : 29; /* [28..0] */ ++ unsigned int reserved_0 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff5; ++ ++/* define the union reg_date_coeff6 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int coef06_1 : 23; /* [22..0] */ ++ unsigned int reserved_0 : 8; /* [30..23] */ ++ unsigned int coef06_0 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff6; ++ ++/* define the union reg_date_coeff7 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt07_enf2 : 1; /* [0] */ ++ unsigned int tt08_enf2 : 1; /* [1] */ ++ unsigned int tt09_enf2 : 1; /* [2] */ ++ unsigned int tt10_enf2 : 1; /* [3] */ ++ unsigned int tt11_enf2 : 1; /* [4] */ ++ unsigned int tt12_enf2 : 1; /* [5] */ ++ unsigned int tt13_enf2 : 1; /* [6] */ ++ unsigned int tt14_enf2 : 1; /* [7] */ ++ unsigned int tt15_enf2 : 1; /* [8] */ ++ unsigned int tt16_enf2 : 1; /* [9] */ ++ unsigned int tt17_enf2 : 1; /* [10] */ ++ unsigned int tt18_enf2 : 1; /* [11] */ ++ unsigned int tt19_enf2 : 1; /* [12] */ ++ unsigned int tt20_enf2 : 1; /* [13] */ ++ unsigned int tt21_enf2 : 1; /* [14] */ ++ unsigned int tt22_enf2 : 1; /* [15] */ ++ unsigned int tt07_enf1 : 1; /* [16] */ ++ unsigned int tt08_enf1 : 1; /* [17] */ ++ unsigned int tt09_enf1 : 1; /* [18] */ ++ unsigned int tt10_enf1 : 1; /* [19] */ ++ unsigned int tt11_enf1 : 1; /* [20] */ ++ unsigned int tt12_enf1 : 1; /* [21] */ ++ unsigned int tt13_enf1 : 1; /* [22] */ ++ unsigned int tt14_enf1 : 1; /* [23] */ ++ unsigned int tt15_enf1 : 1; /* [24] */ ++ unsigned int tt16_enf1 : 1; /* [25] */ ++ unsigned int tt17_enf1 : 1; /* [26] */ ++ unsigned int tt18_enf1 : 1; /* [27] */ ++ unsigned int tt19_enf1 : 1; /* [28] */ ++ unsigned int tt20_enf1 : 1; /* [29] */ ++ unsigned int tt21_enf1 : 1; /* [30] */ ++ unsigned int tt22_enf1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff7; ++ ++/* define the union reg_date_coeff10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt_pktoff : 8; /* [7..0] */ ++ unsigned int tt_mode : 2; /* [9..8] */ ++ unsigned int tt_highest : 1; /* [10] */ ++ unsigned int full_page : 1; /* [11] */ ++ unsigned int nabts_100ire : 1; /* [12] */ ++ unsigned int reserved_0 : 18; /* [30..13] */ ++ unsigned int tt_ready : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff10; ++ ++/* define the union reg_date_coeff11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int date_clf2 : 10; /* [9..0] */ ++ unsigned int date_clf1 : 10; /* [19..10] */ ++ unsigned int cc_enf2 : 1; /* [20] */ ++ unsigned int cc_enf1 : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff11; ++ ++/* define the union reg_date_coeff12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cc_f2data : 16; /* [15..0] */ ++ unsigned int cc_f1data : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff12; ++ ++/* define the union reg_date_coeff13 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cg_f1data : 20; /* [19..0] */ ++ unsigned int cg_enf2 : 1; /* [20] */ ++ unsigned int cg_enf1 : 1; /* [21] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff13; ++ ++/* define the union reg_date_coeff14 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cg_f2data : 20; /* [19..0] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff14; ++ ++/* define the union reg_date_coeff15 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wss_data : 14; /* [13..0] */ ++ unsigned int wss_en : 1; /* [14] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff15; ++ ++/* define the union reg_date_coeff16 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vps_data : 24; /* [23..0] */ ++ unsigned int vps_en : 1; /* [24] */ ++ unsigned int reserved_0 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff16; ++ ++/* define the union reg_date_coeff19 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vps_data : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff19; ++ ++/* define the union reg_date_coeff20 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt05_enf2 : 1; /* [0] */ ++ unsigned int tt06_enf2 : 1; /* [1] */ ++ unsigned int tt06_enf1 : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff20; ++ ++/* define the union reg_date_coeff21 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dac0_in_sel : 3; /* [2..0] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int dac1_in_sel : 3; /* [6..4] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int dac2_in_sel : 3; /* [10..8] */ ++ unsigned int reserved_2 : 1; /* [11] */ ++ unsigned int dac3_in_sel : 3; /* [14..12] */ ++ unsigned int reserved_3 : 1; /* [15] */ ++ unsigned int dac4_in_sel : 3; /* [18..16] */ ++ unsigned int reserved_4 : 1; /* [19] */ ++ unsigned int dac5_in_sel : 3; /* [22..20] */ ++ unsigned int reserved_5 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff21; ++ ++/* define the union reg_date_coeff22 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int video_phase_delta : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff22; ++ ++/* define the union reg_date_coeff23 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dac0_out_dly : 3; /* [2..0] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int dac1_out_dly : 3; /* [6..4] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int dac2_out_dly : 3; /* [10..8] */ ++ unsigned int reserved_2 : 1; /* [11] */ ++ unsigned int dac3_out_dly : 3; /* [14..12] */ ++ unsigned int reserved_3 : 1; /* [15] */ ++ unsigned int dac4_out_dly : 3; /* [18..16] */ ++ unsigned int reserved_4 : 1; /* [19] */ ++ unsigned int dac5_out_dly : 3; /* [22..20] */ ++ unsigned int reserved_5 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff23; ++ ++/* define the union reg_date_coeff25 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_n_coef : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int x_n_1_coef : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff25; ++ ++/* define the union reg_date_coeff26 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int x_n_1_coef : 13; /* [12..0] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff26; ++ ++/* define the union reg_date_coeff27 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int y_n_coef : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int y_n_1_coef : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff27; ++ ++/* define the union reg_date_coeff28 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int pixel_begin1 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int pixel_begin2 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff28; ++ ++/* define the union reg_date_coeff29 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int pixel_end : 11; /* [10..0] */ ++ unsigned int reserved_0 : 21; /* [31..11] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff29; ++ ++/* define the union reg_date_coeff30 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int g_secam : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff30; ++ ++/* define the union reg_date_isrmask */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt_mask : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_isrmask; ++ ++/* define the union reg_date_isrstate */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt_status : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_isrstate; ++ ++/* define the union reg_date_isr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tt_int : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_isr; ++ ++/* define the union reg_date_coeff37 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fir_y1_coeff0 : 8; /* [7..0] */ ++ unsigned int fir_y1_coeff1 : 8; /* [15..8] */ ++ unsigned int fir_y1_coeff2 : 8; /* [23..16] */ ++ unsigned int fir_y1_coeff3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff37; ++ ++/* define the union reg_date_coeff38 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fir_y2_coeff0 : 16; /* [15..0] */ ++ unsigned int fir_y2_coeff1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff38; ++ ++/* define the union reg_date_coeff39 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fir_y2_coeff2 : 16; /* [15..0] */ ++ unsigned int fir_y2_coeff3 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff39; ++ ++/* define the union reg_date_coeff40 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fir_c1_coeff0 : 8; /* [7..0] */ ++ unsigned int fir_c1_coeff1 : 8; /* [15..8] */ ++ unsigned int fir_c1_coeff2 : 8; /* [23..16] */ ++ unsigned int fir_c1_coeff3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff40; ++ ++/* define the union reg_date_coeff41 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fir_c2_coeff0 : 16; /* [15..0] */ ++ unsigned int fir_c2_coeff1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff41; ++ ++/* define the union reg_date_coeff42 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int fir_c2_coeff2 : 16; /* [15..0] */ ++ unsigned int fir_c2_coeff3 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff42; ++ ++/* define the union reg_date_dacdet1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vdac_det_high : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int det_line : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_dacdet1; ++ ++/* define the union reg_date_dacdet2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int det_pixel_sta : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int det_pixel_wid : 11; /* [26..16] */ ++ unsigned int reserved_1 : 4; /* [30..27] */ ++ unsigned int vdac_det_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_dacdet2; ++ ++/* define the union reg_date_coeff50 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff50; ++ ++/* define the union reg_date_coeff51 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff51; ++ ++/* define the union reg_date_coeff52 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff52; ++ ++/* define the union reg_date_coeff53 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff53; ++ ++/* define the union reg_date_coeff54 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff54; ++ ++/* define the union reg_date_coeff55 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ovs_coeff0 : 11; /* [10..0] */ ++ unsigned int reserved_0 : 5; /* [15..11] */ ++ unsigned int ovs_coeff1 : 11; /* [26..16] */ ++ unsigned int reserved_1 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff55; ++ ++/* define the union reg_date_coeff57 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int v_gain : 8; /* [7..0] */ ++ unsigned int reg_gain : 8; /* [15..8] */ ++ unsigned int ycvbs_gain : 8; /* [23..16] */ ++ unsigned int reserved_0 : 7; /* [30..24] */ ++ unsigned int cvbs_gain_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_date_coeff57; ++ ++/* define the union reg_mac_outstanding */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mstr0_routstanding : 4; /* [3..0] */ ++ unsigned int mstr0_woutstanding : 4; /* [7..4] */ ++ unsigned int mstr1_routstanding : 4; /* [11..8] */ ++ unsigned int mstr1_woutstanding : 4; /* [15..12] */ ++ unsigned int mstr2_routstanding : 4; /* [19..16] */ ++ unsigned int mstr2_woutstanding : 4; /* [23..20] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_outstanding; ++ ++/* define the union reg_mac_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int split_mode : 4; /* [3..0] */ ++ unsigned int arb_mode : 4; /* [7..4] */ ++ unsigned int mid_enable : 1; /* [8] */ ++ unsigned int reserved_0 : 3; /* [11..9] */ ++ unsigned int wport_sel : 4; /* [15..12] */ ++ unsigned int reserved_1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_ctrl; ++ ++/* define the union reg_mac_rchn_prio */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_prio : 1; /* [0] */ ++ unsigned int v0_prio : 1; /* [1] */ ++ unsigned int v0h_prio : 1; /* [2] */ ++ unsigned int v0t_prio : 1; /* [3] */ ++ unsigned int v1_prio : 1; /* [4] */ ++ unsigned int v1t_prio : 1; /* [5] */ ++ unsigned int v2_prio : 1; /* [6] */ ++ unsigned int g0_prio : 1; /* [7] */ ++ unsigned int g1_prio : 1; /* [8] */ ++ unsigned int g3_prio : 1; /* [9] */ ++ unsigned int rchn31_prio : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_rchn_prio; ++ ++/* define the union reg_mac_wchn_prio */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wchn_prio : 1; /* [0] */ ++ unsigned int wchnh_prio : 1; /* [1] */ ++ unsigned int wchn31_prio : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_wchn_prio; ++ ++/* define the union reg_mac_rchn_sel0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int para_sel : 2; /* [1..0] */ ++ unsigned int v0_sel : 2; /* [3..2] */ ++ unsigned int v1_sel : 2; /* [5..4] */ ++ unsigned int v2_sel : 2; /* [7..6] */ ++ unsigned int v3_sel : 2; /* [9..8] */ ++ unsigned int g0_sel : 2; /* [11..10] */ ++ unsigned int g1_sel : 2; /* [13..12] */ ++ unsigned int g2_sel : 2; /* [15..14] */ ++ unsigned int g3_sel : 2; /* [17..16] */ ++ unsigned int g4_sel : 2; /* [19..18] */ ++ unsigned int rchn10_sel : 2; /* [21..20] */ ++ unsigned int rchn11_sel : 2; /* [23..22] */ ++ unsigned int rchn12_sel : 2; /* [25..24] */ ++ unsigned int rchn13_sel : 2; /* [27..26] */ ++ unsigned int rchn14_sel : 2; /* [29..28] */ ++ unsigned int rchn15_sel : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_rchn_sel0; ++ ++/* define the union reg_mac_wchn_sel0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wchn0_sel : 2; /* [1..0] */ ++ unsigned int wchn15_sel : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_wchn_sel0; ++ ++/* define the union reg_mac_bus_err_clr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bus_error_clr : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_bus_err_clr; ++ ++/* define the union reg_mac_bus_err */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mst0_r_error : 1; /* [0] */ ++ unsigned int mst0_w_error : 1; /* [1] */ ++ unsigned int mst1_r_error : 1; /* [2] */ ++ unsigned int mst1_w_error : 1; /* [3] */ ++ unsigned int mst2_r_error : 1; /* [4] */ ++ unsigned int mst2_w_error : 1; /* [5] */ ++ unsigned int reserved_0 : 26; /* [31..6] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_bus_err; ++ ++/* define the union reg_mac_debug_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int axi_det_enable : 1; /* [0] */ ++ unsigned int reserved_0 : 3; /* [3..1] */ ++ unsigned int fifo_det_mode : 4; /* [7..4] */ ++ unsigned int reserved_1 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_debug_ctrl; ++ ++/* define the union reg_mac_debug_clr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int axi_det_clr : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_debug_clr; ++ ++/* define the union reg_mac_axi_press0_ctrl0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int awvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int awvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 14; /* [30..17] */ ++ unsigned int bypass_flag : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press0_ctrl0; ++ ++/* define the union reg_mac_axi_press0_ctrl1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int arvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int arvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press0_ctrl1; ++ ++/* define the union reg_mac_axi_press0_ctrl2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int wvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press0_ctrl2; ++ ++/* define the union reg_mac_axi_press0_ctrl3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int rvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press0_ctrl3; ++ ++/* define the union reg_mac_axi_press0_ctrl4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int bvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press0_ctrl4; ++ ++/* define the union reg_mac_axi_press0_ctrl5 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int axi_press_st : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press0_ctrl5; ++ ++/* define the union reg_mac_axi_press1_ctrl0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int awvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int awvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 14; /* [30..17] */ ++ unsigned int bypass_flag : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press1_ctrl0; ++ ++/* define the union reg_mac_axi_press1_ctrl1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int arvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int arvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press1_ctrl1; ++ ++/* define the union reg_mac_axi_press1_ctrl2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int wvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press1_ctrl2; ++ ++/* define the union reg_mac_axi_press1_ctrl3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int rvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press1_ctrl3; ++ ++/* define the union reg_mac_axi_press1_ctrl4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int bvalid_delay_cfg : 16; /* [15..0] */ ++ unsigned int bvalid_delay_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press1_ctrl4; ++ ++/* define the union reg_mac_axi_press1_ctrl5 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int axi_press_st : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_mac_axi_press1_ctrl5; ++ ++/* define the union reg_vid_read_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int chm_rmode : 3; /* [2..0] */ ++ unsigned int reserved_0 : 1; /* [3] */ ++ unsigned int lm_rmode : 3; /* [6..4] */ ++ unsigned int reserved_1 : 1; /* [7] */ ++ unsigned int chm_draw_mode : 2; /* [9..8] */ ++ unsigned int lm_draw_mode : 2; /* [11..10] */ ++ unsigned int flip_en : 1; /* [12] */ ++ unsigned int chm_copy_en : 1; /* [13] */ ++ unsigned int reserved_2 : 2; /* [15..14] */ ++ unsigned int mute_en : 1; /* [16] */ ++ unsigned int mute_req_en : 1; /* [17] */ ++ unsigned int vicap_mute_en : 1; /* [18] */ ++ unsigned int mrg_enable : 1; /* [19] */ ++ unsigned int mrg_mute_mode : 1; /* [20] */ ++ unsigned int fdr_ck_gt_en : 1; /* [21] */ ++ unsigned int reserved_3 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_read_ctrl; ++ ++/* define the union reg_vid_mac_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_ctrl : 2; /* [1..0] */ ++ unsigned int req_len : 2; /* [3..2] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int ofl_master : 1; /* [8] */ ++ unsigned int reserved_1 : 22; /* [30..9] */ ++ unsigned int pre_rd_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_mac_ctrl; ++ ++/* define the union reg_vid_out_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int draw_pixel_mode : 3; /* [2..0] */ ++ unsigned int draw_pixel_en : 1; /* [3] */ ++ unsigned int uv_order_en : 1; /* [4] */ ++ unsigned int single_port_mode : 1; /* [5] */ ++ unsigned int testpattern_en : 1; /* [6] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_out_ctrl; ++ ++/* define the union reg_vid_mute_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_mute_alpha; ++ ++/* define the union reg_vid_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_mute_bk; ++ ++/* define the union reg_vid_src_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int data_type : 3; /* [2..0] */ ++ unsigned int data_fmt : 2; /* [4..3] */ ++ unsigned int reserved_0 : 3; /* [7..5] */ ++ unsigned int data_width : 2; /* [9..8] */ ++ unsigned int reserved_1 : 2; /* [11..10] */ ++ unsigned int field_type : 1; /* [12] */ ++ unsigned int reserved_2 : 3; /* [15..13] */ ++ unsigned int disp_mode : 4; /* [19..16] */ ++ unsigned int dcmp_en : 2; /* [21..20] */ ++ unsigned int compact_en : 1; /* [22] */ ++ unsigned int compact_req_mode : 1; /* [23] */ ++ unsigned int reserved_3 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_src_info; ++ ++/* define the union reg_vid_src_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int src_w : 16; /* [15..0] */ ++ unsigned int src_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_src_reso; ++ ++/* define the union reg_vid_src_crop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int src_crop_x : 16; /* [15..0] */ ++ unsigned int src_crop_y : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_src_crop; ++ ++/* define the union reg_vid_in_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ireso_w : 16; /* [15..0] */ ++ unsigned int ireso_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_in_reso; ++ ++/* define the union reg_vid_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lm_stride : 16; /* [15..0] */ ++ unsigned int chm_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_stride; ++ ++/* define the union reg_vid_2bit_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lm_tile_stride : 16; /* [15..0] */ ++ unsigned int chm_tile_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_2bit_stride; ++ ++/* define the union reg_vid_head_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lm_head_stride : 16; /* [15..0] */ ++ unsigned int chm_head_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_head_stride; ++ ++/* define the union reg_vid_smmu_bypass */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lm_bypass_2d : 1; /* [0] */ ++ unsigned int chm_bypass_2d : 1; /* [1] */ ++ unsigned int lm_bypass_3d : 1; /* [2] */ ++ unsigned int chm_bypass_3d : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_smmu_bypass; ++ ++/* define the union reg_vid_testpat_cfg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tp_speed : 10; /* [9..0] */ ++ unsigned int reserved_0 : 2; /* [11..10] */ ++ unsigned int tp_line_w : 1; /* [12] */ ++ unsigned int tp_color_mode : 1; /* [13] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int tp_mode : 2; /* [17..16] */ ++ unsigned int reserved_2 : 14; /* [31..18] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_testpat_cfg; ++ ++/* define the union reg_vid_testpat_seed */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tp_seed : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_testpat_seed; ++ ++/* define the union reg_vid_tunl_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tunl_interval : 8; /* [7..0] */ ++ unsigned int tunl_thd : 16; /* [23..8] */ ++ unsigned int reserved_0 : 6; /* [29..24] */ ++ unsigned int tunl_uf : 1; /* [30] */ ++ unsigned int rtunl_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_tunl_ctrl; ++ ++/* define the union reg_vid_tunl_crop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tunl_crop_line : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_tunl_crop; ++ ++/* define the union reg_vid_tunl_errsta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int l_tunl_err : 1; /* [0] */ ++ unsigned int c_tunl_err : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_tunl_errsta; ++ ++/* define the union reg_vid_tunl_debug */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int l_tunl_err_num : 16; /* [15..0] */ ++ unsigned int c_tunl_err_num : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_tunl_debug; ++ ++/* define the union reg_vid_dcmp_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int c_is_lossless : 1; /* [0] */ ++ unsigned int l_is_lossless : 1; /* [1] */ ++ unsigned int c_cmp_mode : 1; /* [2] */ ++ unsigned int l_cmp_mode : 1; /* [3] */ ++ unsigned int c_cmp_rate : 2; /* [5..4] */ ++ unsigned int l_cmp_rate : 2; /* [7..6] */ ++ unsigned int mem_mode : 1; /* [8] */ ++ unsigned int reserved_0 : 23; /* [31..9] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vid_dcmp_ctrl; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int is_lossless : 1; /* [1] */ ++ unsigned int cmp_mode : 1; /* [2] */ ++ unsigned int max_mb_qp_y : 3; /* [5..3] */ ++ unsigned int reserved_0 : 10; /* [15..6] */ ++ unsigned int max_mb_qp_c : 3; /* [18..16] */ ++ unsigned int seg_en : 1; /* [19] */ ++ unsigned int bit_depth : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_glb_info; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_height : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_width : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_frame_size; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_error_sta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dcmp_error : 1; /* [0] */ ++ unsigned int forgive : 1; /* [1] */ ++ unsigned int consume : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_error_sta; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_glb_info_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int is_lossless : 1; /* [1] */ ++ unsigned int cmp_mode : 1; /* [2] */ ++ unsigned int max_mb_qp_y : 3; /* [5..3] */ ++ unsigned int reserved_0 : 10; /* [15..6] */ ++ unsigned int max_mb_qp_c : 3; /* [18..16] */ ++ unsigned int seg_en : 1; /* [19] */ ++ unsigned int bit_depth : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_glb_info_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_frame_size_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_height : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_width : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_frame_size_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_dcmp_error_sta_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dcmp_error : 1; /* [0] */ ++ unsigned int forgive : 1; /* [1] */ ++ unsigned int consume : 1; /* [2] */ ++ unsigned int reserved_0 : 29; /* [31..3] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_dcmp_error_sta_c; ++ ++/* define the union reg_gfx_read_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int read_mode : 2; /* [1..0] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int draw_mode : 2; /* [5..4] */ ++ unsigned int reserved_1 : 2; /* [7..6] */ ++ unsigned int flip_en : 1; /* [8] */ ++ unsigned int reserved_2 : 1; /* [9] */ ++ unsigned int mute_en : 1; /* [10] */ ++ unsigned int mute_req_en : 1; /* [11] */ ++ unsigned int fdr_ck_gt_en : 1; /* [12] */ ++ unsigned int reserved_3 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_read_ctrl; ++ ++/* define the union reg_gfx_mac_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_ctrl : 2; /* [1..0] */ ++ unsigned int req_len : 2; /* [3..2] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int ofl_master : 1; /* [8] */ ++ unsigned int dcmp_thd_close : 1; /* [9] */ ++ unsigned int dcmp_mute_ctrl : 1; /* [10] */ ++ unsigned int reserved_1 : 13; /* [23..11] */ ++ unsigned int req_ld_mode : 2; /* [25..24] */ ++ unsigned int reserved_2 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_mac_ctrl; ++ ++/* define the union reg_gfx_out_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int palpha_range : 1; /* [0] */ ++ unsigned int palpha_en : 1; /* [1] */ ++ unsigned int reserved_0 : 2; /* [3..2] */ ++ unsigned int key_mode : 1; /* [4] */ ++ unsigned int key_en : 1; /* [5] */ ++ unsigned int reserved_1 : 2; /* [7..6] */ ++ unsigned int bitext : 2; /* [9..8] */ ++ unsigned int premulti_en : 1; /* [10] */ ++ unsigned int testpattern_en : 1; /* [11] */ ++ unsigned int reserved_2 : 20; /* [31..12] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_out_ctrl; ++ ++/* define the union reg_gfx_mute_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_alpha : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_mute_alpha; ++ ++/* define the union reg_gfx_mute_bk */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mute_cr : 10; /* [9..0] */ ++ unsigned int mute_cb : 10; /* [19..10] */ ++ unsigned int mute_y : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_mute_bk; ++ ++/* define the union reg_gfx_smmu_bypass */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smmu_bypass_2d : 1; /* [0] */ ++ unsigned int smmu_bypass_3d : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_smmu_bypass; ++ ++/* define the union reg_gfx_1555_alpha */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int alpha_0 : 8; /* [7..0] */ ++ unsigned int alpha_1 : 8; /* [15..8] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_1555_alpha; ++ ++/* define the union reg_gfx_src_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ifmt : 8; /* [7..0] */ ++ unsigned int reserved_0 : 8; /* [15..8] */ ++ unsigned int disp_mode : 4; /* [19..16] */ ++ unsigned int dcmp_en : 1; /* [20] */ ++ unsigned int reserved_1 : 11; /* [31..21] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_src_info; ++ ++/* define the union reg_gfx_src_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int src_w : 16; /* [15..0] */ ++ unsigned int src_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_src_reso; ++ ++/* define the union reg_gfx_src_crop */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int src_crop_x : 16; /* [15..0] */ ++ unsigned int src_crop_y : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_src_crop; ++ ++/* define the union reg_gfx_ireso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ireso_w : 16; /* [15..0] */ ++ unsigned int ireso_h : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ireso; ++ ++/* define the union reg_gfx_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int surface_stride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_stride; ++ ++/* define the union reg_gfx_ckey_max */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int key_b_max : 8; /* [7..0] */ ++ unsigned int key_g_max : 8; /* [15..8] */ ++ unsigned int key_r_max : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ckey_max; ++ ++/* define the union reg_gfx_ckey_min */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int key_b_min : 8; /* [7..0] */ ++ unsigned int key_g_min : 8; /* [15..8] */ ++ unsigned int key_r_min : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ckey_min; ++ ++/* define the union reg_gfx_ckey_mask */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int key_b_msk : 8; /* [7..0] */ ++ unsigned int key_g_msk : 8; /* [15..8] */ ++ unsigned int key_r_msk : 8; /* [23..16] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ckey_mask; ++ ++/* define the union reg_gfx_testpat_cfg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tp_speed : 10; /* [9..0] */ ++ unsigned int reserved_0 : 2; /* [11..10] */ ++ unsigned int tp_line_w : 1; /* [12] */ ++ unsigned int tp_color_mode : 1; /* [13] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int tp_mode : 2; /* [17..16] */ ++ unsigned int reserved_2 : 14; /* [31..18] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_testpat_cfg; ++ ++/* define the union reg_gfx_testpat_seed */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int tp_seed : 30; /* [29..0] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_testpat_seed; ++ ++/* define the union reg_gfx_ld_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 1; /* [0] */ ++ unsigned int hw_mute_clr : 1; /* [1] */ ++ unsigned int ld_mute_en : 1; /* [2] */ ++ unsigned int ld_err_mute_en : 1; /* [3] */ ++ unsigned int reserved_1 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ld_ctrl; ++ ++/* define the union reg_gfx_ld_smute_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int sw_mute_clr : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ld_smute_ctrl; ++ ++/* define the union reg_gfx_ld_err_sta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ld_err_clr : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_ld_err_sta; ++ ++/* define the union reg_vdp_v3r2_line_osd_dcmp_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int conv_en : 1; /* [2] */ ++ unsigned int is_lossless : 1; /* [3] */ ++ unsigned int osd_mode : 2; /* [5..4] */ ++ unsigned int max_mb_qp : 3; /* [8..6] */ ++ unsigned int excess_err_mask : 1; /* [9] */ ++ unsigned int rw_reg_add : 6; /* [15..10] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_line_osd_dcmp_glb_info; ++ ++/* define the union reg_vdp_v3r2_line_osd_dcmp_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_height : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_line_osd_dcmp_frame_size; ++ ++/* define the union reg_vdp_v3r2_line_osd_dcmp_error_sta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dcmp_error : 1; /* [0] */ ++ unsigned int o_pix_forgive : 1; /* [1] */ ++ unsigned int o_pix_consume : 1; /* [2] */ ++ unsigned int o_mb_qp_error : 1; /* [3] */ ++ unsigned int o_dcmp_excess_err : 1; /* [4] */ ++ unsigned int o_dcmp_err_add : 5; /* [9..5] */ ++ unsigned int o_dcmp_debug : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_line_osd_dcmp_error_sta; ++ ++/* define the union reg_wbc_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 4; /* [3..0] */ ++ unsigned int data_width : 1; /* [4] */ ++ unsigned int reserved_1 : 3; /* [7..5] */ ++ unsigned int uv_order : 1; /* [8] */ ++ unsigned int flip_en : 1; /* [9] */ ++ unsigned int align_mode : 1; /* [10] */ ++ unsigned int reserved_2 : 3; /* [13..11] */ ++ unsigned int cap_ck_gt_en : 1; /* [14] */ ++ unsigned int reserved_3 : 14; /* [28..15] */ ++ unsigned int wbc_cmp_en : 1; /* [29] */ ++ unsigned int reserved_4 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_ctrl; ++ ++/* define the union reg_wbc_mac_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 2; /* [11..10] */ ++ unsigned int wbc_len : 2; /* [13..12] */ ++ unsigned int reserved_1 : 18; /* [31..14] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_mac_ctrl; ++ ++/* define the union reg_wbc_smmu_bypass */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int l_bypass : 1; /* [0] */ ++ unsigned int c_bypass : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_smmu_bypass; ++ ++/* define the union reg_wbc_lowdlyctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wb_per_line_num : 12; /* [11..0] */ ++ unsigned int partfns_line_num : 12; /* [23..12] */ ++ unsigned int reserved_0 : 6; /* [29..24] */ ++ unsigned int lowdly_test : 1; /* [30] */ ++ unsigned int lowdly_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_lowdlyctrl; ++ ++/* define the union reg_wbc_lowdlysta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 31; /* [30..0] */ ++ unsigned int part_finish : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_lowdlysta; ++ ++/* define the union reg_wbc_ystride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_ystride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_ystride; ++ ++/* define the union reg_wbc_cstride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_cstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cstride; ++ ++/* define the union reg_wbc_ynstride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_ynstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_ynstride; ++ ++/* define the union reg_wbc_cnstride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_cnstride : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cnstride; ++ ++/* define the union reg_wbc_sta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_l_busy : 1; /* [0] */ ++ unsigned int wbc_c_busy : 1; /* [1] */ ++ unsigned int wbc_lh_busy : 1; /* [2] */ ++ unsigned int wbc_ch_busy : 1; /* [3] */ ++ unsigned int reserved_0 : 28; /* [31..4] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_sta; ++ ++/* define the union reg_wbc_line_num */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int wbc_l_linenum : 16; /* [15..0] */ ++ unsigned int wbc_c_linenum : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_line_num; ++ ++/* define the union reg_wbc_cap_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cap_width : 16; /* [15..0] */ ++ unsigned int cap_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cap_reso; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int is_lossless : 1; /* [2] */ ++ unsigned int chroma_en : 1; /* [3] */ ++ unsigned int esl_qp : 3; /* [6..4] */ ++ unsigned int bit_depth : 1; /* [7] */ ++ unsigned int mirror_en : 1; /* [8] */ ++ unsigned int seg_en : 1; /* [9] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_glb_info; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_height : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_frame_size; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int big_grad_thr : 8; /* [7..0] */ ++ unsigned int diff_thr : 8; /* [15..8] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg0; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg1; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int buffer_init_bits : 16; /* [15..0] */ ++ unsigned int buffer_size : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg12; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg13 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int budget_mb_bits : 10; /* [9..0] */ ++ unsigned int budget_mb_bits_last : 10; /* [19..10] */ ++ unsigned int min_mb_bits : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg13; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg16 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smooth_status_thr : 4; /* [3..0] */ ++ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ ++ unsigned int max_mb_qp : 3; /* [14..12] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg16; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_glb_st */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_left_bits_buffer : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_glb_st; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_glb_info_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ice_en : 1; /* [0] */ ++ unsigned int cmp_mode : 1; /* [1] */ ++ unsigned int is_lossless : 1; /* [2] */ ++ unsigned int chroma_en : 1; /* [3] */ ++ unsigned int esl_qp : 3; /* [6..4] */ ++ unsigned int bit_depth : 1; /* [7] */ ++ unsigned int mirror_en : 1; /* [8] */ ++ unsigned int seg_en : 1; /* [9] */ ++ unsigned int reserved_0 : 22; /* [31..10] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_glb_info_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_frame_size_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 14; /* [13..0] */ ++ unsigned int reserved_0 : 2; /* [15..14] */ ++ unsigned int frame_height : 14; /* [29..16] */ ++ unsigned int reserved_1 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_frame_size_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg0_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int big_grad_thr : 8; /* [7..0] */ ++ unsigned int diff_thr : 8; /* [15..8] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg0_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg1_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg1_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg12_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int buffer_init_bits : 16; /* [15..0] */ ++ unsigned int buffer_size : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg12_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg13_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int budget_mb_bits : 10; /* [9..0] */ ++ unsigned int budget_mb_bits_last : 10; /* [19..10] */ ++ unsigned int min_mb_bits : 10; /* [29..20] */ ++ unsigned int reserved_0 : 2; /* [31..30] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg13_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg16_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smooth_status_thr : 4; /* [3..0] */ ++ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ ++ unsigned int max_mb_qp : 3; /* [14..12] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_rc_cfg16_c; ++ ++/* define the union reg_vdp_v3r2_lineseg_cmp_glb_st_c */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_left_bits_buffer : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_vdp_v3r2_lineseg_cmp_glb_st_c; ++ ++/* define the union reg_wbc_cmp_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int req_interval : 10; /* [9..0] */ ++ unsigned int reserved_0 : 17; /* [26..10] */ ++ unsigned int mem_mode : 1; /* [27] */ ++ unsigned int data_width : 1; /* [28] */ ++ unsigned int reserved_1 : 1; /* [29] */ ++ unsigned int l_cmp_en : 1; /* [30] */ ++ unsigned int wbc_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_ctrl; ++ ++/* define the union reg_wbc_cmp_upd */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int regup : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_upd; ++ ++/* define the union reg_wbc_cmp_height */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int c_max_height : 13; /* [12..0] */ ++ unsigned int l_max_height : 13; /* [25..13] */ ++ unsigned int addr_mode : 1; /* [26] */ ++ unsigned int fsize_mode : 1; /* [27] */ ++ unsigned int rgb_cmp_mode : 2; /* [29..28] */ ++ unsigned int pause_mode : 1; /* [30] */ ++ unsigned int buffer_mode : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_height; ++ ++/* define the union reg_wbc_cmp_oreso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int ow : 12; /* [11..0] */ ++ unsigned int oh : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_cmp_oreso; ++ ++/* define the union reg_wbc_od_state */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int addr_err : 1; /* [0] */ ++ unsigned int he_addr_err0 : 1; /* [1] */ ++ unsigned int he_addr_err1 : 1; /* [2] */ ++ unsigned int he_addr_err2 : 1; /* [3] */ ++ unsigned int w_addr_err : 1; /* [4] */ ++ unsigned int he_fsize_err0 : 1; /* [5] */ ++ unsigned int he_fsize_err1 : 1; /* [6] */ ++ unsigned int he_fsize_err2 : 1; /* [7] */ ++ unsigned int w_fsize_err : 1; /* [8] */ ++ unsigned int he_fsize_war0 : 1; /* [9] */ ++ unsigned int he_fsize_war1 : 1; /* [10] */ ++ unsigned int he_fsize_war2 : 1; /* [11] */ ++ unsigned int w_fsize_war : 1; /* [12] */ ++ unsigned int reserved_0 : 19; /* [31..13] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_wbc_od_state; ++ ++/* define the union reg_od_pic_osd_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int is_lossless : 1; /* [0] */ ++ unsigned int is_lossless_a : 1; /* [1] */ ++ unsigned int cmp_mode : 1; /* [2] */ ++ unsigned int source_mode : 3; /* [5..3] */ ++ unsigned int part_cmp_en : 1; /* [6] */ ++ unsigned int top_pred_en : 1; /* [7] */ ++ unsigned int graphic_en : 1; /* [8] */ ++ unsigned int reserved_0 : 23; /* [31..9] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_glb_info; ++ ++/* define the union reg_od_pic_osd_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int frame_height : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_frame_size; ++ ++/* define the union reg_od_pic_osd_rc_cfg0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mb_bits : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int min_mb_bits : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg0; ++ ++/* define the union reg_od_pic_osd_rc_cfg1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_qp : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int sad_bits_gain : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int rc_smth_ngain : 3; /* [18..16] */ ++ unsigned int reserved_2 : 5; /* [23..19] */ ++ unsigned int max_trow_bits : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg1; ++ ++/* define the union reg_od_pic_osd_rc_cfg2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_sad_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int min_sad_thr : 7; /* [22..16] */ ++ unsigned int reserved_1 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg2; ++ ++/* define the union reg_od_pic_osd_rc_cfg3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smth_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int still_thr : 7; /* [14..8] */ ++ unsigned int reserved_1 : 1; /* [15] */ ++ unsigned int big_grad_thr : 10; /* [25..16] */ ++ unsigned int reserved_2 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg3; ++ ++/* define the union reg_od_pic_osd_rc_cfg4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int smth_pix_num_thr : 6; /* [5..0] */ ++ unsigned int reserved_0 : 2; /* [7..6] */ ++ unsigned int still_pix_num_thr : 6; /* [13..8] */ ++ unsigned int reserved_1 : 2; /* [15..14] */ ++ unsigned int noise_pix_num_thr : 6; /* [21..16] */ ++ unsigned int reserved_2 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg4; ++ ++/* define the union reg_od_pic_osd_rc_cfg5 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int noise_sad : 7; /* [6..0] */ ++ unsigned int reserved_0 : 9; /* [15..7] */ ++ unsigned int pix_diff_thr : 10; /* [25..16] */ ++ unsigned int reserved_1 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg5; ++ ++/* define the union reg_od_pic_osd_rc_cfg6 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg6; ++ ++/* define the union reg_od_pic_osd_rc_cfg7 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ ++ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ ++ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ ++ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg7; ++ ++/* define the union reg_od_pic_osd_rc_cfg8 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int est_err_gain : 5; /* [4..0] */ ++ unsigned int reserved_0 : 11; /* [15..5] */ ++ unsigned int max_est_err_level : 9; /* [24..16] */ ++ unsigned int reserved_1 : 7; /* [31..25] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg8; ++ ++/* define the union reg_od_pic_osd_rc_cfg9 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 16; /* [15..0] */ ++ unsigned int vbv_buf_loss1_thr : 7; /* [22..16] */ ++ unsigned int reserved_1 : 1; /* [23] */ ++ unsigned int vbv_buf_loss2_thr : 7; /* [30..24] */ ++ unsigned int reserved_2 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg9; ++ ++/* define the union reg_od_pic_osd_rc_cfg10 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int qp_thr0 : 3; /* [2..0] */ ++ unsigned int reserved_0 : 5; /* [7..3] */ ++ unsigned int qp_thr1 : 3; /* [10..8] */ ++ unsigned int reserved_1 : 5; /* [15..11] */ ++ unsigned int qp_thr2 : 3; /* [18..16] */ ++ unsigned int reserved_2 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg10; ++ ++/* define the union reg_od_pic_osd_rc_cfg11 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int grph_bias_bit_thr0 : 8; /* [7..0] */ ++ unsigned int grph_bias_bit_thr1 : 8; /* [15..8] */ ++ unsigned int grph_ideal_bit_thr : 10; /* [25..16] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg11; ++ ++/* define the union reg_od_pic_osd_rc_cfg12 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int force_rc_en : 1; /* [0] */ ++ unsigned int reserved_0 : 7; /* [7..1] */ ++ unsigned int forcerc_bits_diff_thr : 8; /* [15..8] */ ++ unsigned int reserved_1 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg12; ++ ++/* define the union reg_od_pic_osd_rc_cfg13 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int maxdiff_ctrl_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg13; ++ ++/* define the union reg_od_pic_osd_rc_cfg14 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mb_bits_cap : 10; /* [9..0] */ ++ unsigned int reserved_0 : 6; /* [15..10] */ ++ unsigned int init_buf_bits_cap : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg14; ++ ++/* define the union reg_od_pic_osd_rc_cfg15 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lfw_mb_len : 7; /* [6..0] */ ++ unsigned int reserved_0 : 1; /* [7] */ ++ unsigned int cmplx_sad_thr : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int err_thr0 : 4; /* [19..16] */ ++ unsigned int reserved_2 : 4; /* [23..20] */ ++ unsigned int err_thr1 : 4; /* [27..24] */ ++ unsigned int reserved_3 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg15; ++ ++/* define the union reg_od_pic_osd_rc_cfg16 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int sim_num_thr : 3; /* [2..0] */ ++ unsigned int reserved_0 : 5; /* [7..3] */ ++ unsigned int sum_y_err_thr : 7; /* [14..8] */ ++ unsigned int reserved_1 : 1; /* [15] */ ++ unsigned int sum_c_err_thr : 7; /* [22..16] */ ++ unsigned int reserved_2 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg16; ++ ++/* define the union reg_od_pic_osd_rc_cfg17 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cpmlx_sad_thr_y : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int smpl_sad_thr_c : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int smpl_sumsad_thr_y : 8; /* [23..16] */ ++ unsigned int smpl_sumsad_thr_c : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg17; ++ ++/* define the union reg_od_pic_osd_rc_cfg18 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int future_sad_y_thr0 : 4; /* [3..0] */ ++ unsigned int reserved_0 : 4; /* [7..4] */ ++ unsigned int future_sad_c_thr0 : 4; /* [11..8] */ ++ unsigned int reserved_1 : 4; /* [15..12] */ ++ unsigned int future_sad_y_thr1 : 4; /* [19..16] */ ++ unsigned int reserved_2 : 4; /* [23..20] */ ++ unsigned int future_sad_c_thr1 : 4; /* [27..24] */ ++ unsigned int reserved_3 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg18; ++ ++/* define the union reg_od_pic_osd_rc_cfg19 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cmplx_sumsad_thr_y : 8; /* [7..0] */ ++ unsigned int cmplx_sumsad_thr_c : 8; /* [15..8] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_rc_cfg19; ++ ++/* define the union reg_od_pic_osd_stat_thr */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_gap_bw_row_len_thr : 7; /* [6..0] */ ++ unsigned int reserved_0 : 25; /* [31..7] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_stat_thr; ++ ++/* define the union reg_od_pic_osd_pcmp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int pcmp_start_hpos : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int pcmp_end_hpos : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_pcmp; ++ ++/* define the union reg_od_pic_osd_bs_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_size_reg : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_bs_size; ++ ++/* define the union reg_od_pic_osd_worst_row */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_frm_row_len : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_worst_row; ++ ++/* define the union reg_od_pic_osd_best_row */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int min_frm_row_len : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_best_row; ++ ++/* define the union reg_od_pic_osd_stat_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int max_gap_bw_row_len_cnt : 16; /* [15..0] */ ++ unsigned int reserved_0 : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_od_pic_osd_stat_info; ++ ++/* define the union reg_v0_mrg_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ ++ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ ++ unsigned int reserved_0 : 12; /* [19..8] */ ++ unsigned int mrg_edge_en : 1; /* [20] */ ++ unsigned int reserved_1 : 4; /* [24..21] */ ++ unsigned int mrg_edge_typ : 1; /* [25] */ ++ unsigned int reserved_2 : 2; /* [27..26] */ ++ unsigned int mrg_crop_en : 1; /* [28] */ ++ unsigned int mrg_dcmp_en : 1; /* [29] */ ++ unsigned int mrg_mute_en : 1; /* [30] */ ++ unsigned int mrg_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_ctrl; ++ ++/* define the union reg_v0_mrg_disp_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_xpos : 16; /* [15..0] */ ++ unsigned int mrg_ypos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_disp_pos; ++ ++/* define the union reg_v0_mrg_disp_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_width : 16; /* [15..0] */ ++ unsigned int mrg_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_disp_reso; ++ ++/* define the union reg_v0_mrg_src_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_src_width : 16; /* [15..0] */ ++ unsigned int mrg_src_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_src_reso; ++ ++/* define the union reg_v0_mrg_src_offset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_src_hoffset : 16; /* [15..0] */ ++ unsigned int mrg_src_voffset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_src_offset; ++ ++/* define the union reg_v0_mrg_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_c_stride : 16; /* [15..0] */ ++ unsigned int mrg_y_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_stride; ++ ++/* define the union reg_v0_mrg_hstride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_ch_stride : 16; /* [15..0] */ ++ unsigned int mrg_yh_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_hstride; ++ ++/* define the union reg_v0_mrg_read_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rd_region : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_read_ctrl; ++ ++/* define the union reg_v0_mrg_read_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_mrg_read_en; ++ ++/* define the union reg_v1_mrg_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ ++ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ ++ unsigned int reserved_0 : 12; /* [19..8] */ ++ unsigned int mrg_edge_en : 1; /* [20] */ ++ unsigned int reserved_1 : 4; /* [24..21] */ ++ unsigned int mrg_edge_typ : 1; /* [25] */ ++ unsigned int reserved_2 : 2; /* [27..26] */ ++ unsigned int mrg_crop_en : 1; /* [28] */ ++ unsigned int mrg_dcmp_en : 1; /* [29] */ ++ unsigned int mrg_mute_en : 1; /* [30] */ ++ unsigned int mrg_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_ctrl; ++ ++/* define the union reg_v1_mrg_disp_pos */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_xpos : 16; /* [15..0] */ ++ unsigned int mrg_ypos : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_disp_pos; ++ ++/* define the union reg_v1_mrg_disp_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_width : 16; /* [15..0] */ ++ unsigned int mrg_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_disp_reso; ++ ++/* define the union reg_v1_mrg_src_reso */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_src_width : 16; /* [15..0] */ ++ unsigned int mrg_src_height : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_src_reso; ++ ++/* define the union reg_v1_mrg_src_offset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_src_hoffset : 16; /* [15..0] */ ++ unsigned int mrg_src_voffset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_src_offset; ++ ++/* define the union reg_v1_mrg_stride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_c_stride : 16; /* [15..0] */ ++ unsigned int mrg_y_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_stride; ++ ++/* define the union reg_v1_mrg_hstride */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mrg_ch_stride : 16; /* [15..0] */ ++ unsigned int mrg_yh_stride : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_hstride; ++ ++/* define the union reg_v1_mrg_read_ctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rd_region : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_read_ctrl; ++ ++/* define the union reg_v1_mrg_read_en */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int rd_en : 1; /* [0] */ ++ unsigned int reserved_0 : 31; /* [31..1] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_mrg_read_en; ++ ++/* define the union reg_g1_osb_ctrl1_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mode_0 : 2; /* [1..0] */ ++ unsigned int thick_w_0 : 6; /* [7..2] */ ++ unsigned int arm_w_0 : 8; /* [15..8] */ ++ unsigned int edge_v_0 : 4; /* [19..16] */ ++ unsigned int edge_u_0 : 4; /* [23..20] */ ++ unsigned int edge_y_0 : 4; /* [27..24] */ ++ unsigned int edge_alpha_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_osb_ctrl1_box_0; ++ ++/* define the union reg_g1_osb_ctrl2_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int hend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_osb_ctrl2_box_0; ++ ++/* define the union reg_g1_osb_ctrl3_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int vend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_osb_ctrl3_box_0; ++ ++/* define the union reg_g3_osb_ctrl1_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mode_0 : 2; /* [1..0] */ ++ unsigned int thick_w_0 : 6; /* [7..2] */ ++ unsigned int arm_w_0 : 8; /* [15..8] */ ++ unsigned int edge_v_0 : 4; /* [19..16] */ ++ unsigned int edge_u_0 : 4; /* [23..20] */ ++ unsigned int edge_y_0 : 4; /* [27..24] */ ++ unsigned int edge_alpha_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_osb_ctrl1_box_0; ++ ++/* define the union reg_g3_osb_ctrl2_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int hend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_osb_ctrl2_box_0; ++ ++/* define the union reg_g3_osb_ctrl3_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int vend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_osb_ctrl3_box_0; ++ ++/* define the union reg_g4_osb_ctrl1_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int mode_0 : 2; /* [1..0] */ ++ unsigned int thick_w_0 : 6; /* [7..2] */ ++ unsigned int arm_w_0 : 8; /* [15..8] */ ++ unsigned int edge_v_0 : 4; /* [19..16] */ ++ unsigned int edge_u_0 : 4; /* [23..20] */ ++ unsigned int edge_y_0 : 4; /* [27..24] */ ++ unsigned int edge_alpha_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_osb_ctrl1_box_0; ++ ++/* define the union reg_g4_osb_ctrl2_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int hend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_osb_ctrl2_box_0; ++ ++/* define the union reg_g4_osb_ctrl3_box_0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vstr_pos_0 : 12; /* [11..0] */ ++ unsigned int reserved_0 : 4; /* [15..12] */ ++ unsigned int vend_pos_0 : 12; /* [27..16] */ ++ unsigned int reserved_1 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g4_osb_ctrl3_box_0; ++ ++/* define the union reg_v1_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_idc; ++ ++/* define the union reg_v1_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_odc; ++ ++/* define the union reg_v1_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_iodc; ++ ++/* define the union reg_v1_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_p0; ++ ++/* define the union reg_v1_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_p1; ++ ++/* define the union reg_v1_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_p2; ++ ++/* define the union reg_v1_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_p3; ++ ++/* define the union reg_v1_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc_p4; ++ ++/* define the union reg_v1_csc1_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_idc; ++ ++/* define the union reg_v1_csc1_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_odc; ++ ++/* define the union reg_v1_csc1_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_iodc; ++ ++/* define the union reg_v1_csc1_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_p0; ++ ++/* define the union reg_v1_csc1_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_p1; ++ ++/* define the union reg_v1_csc1_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_p2; ++ ++/* define the union reg_v1_csc1_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_p3; ++ ++/* define the union reg_v1_csc1_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v1_csc1_p4; ++ ++/* define the union reg_v2_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_idc; ++ ++/* define the union reg_v2_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_odc; ++ ++/* define the union reg_v2_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_iodc; ++ ++/* define the union reg_v2_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_p0; ++ ++/* define the union reg_v2_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_p1; ++ ++/* define the union reg_v2_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_p2; ++ ++/* define the union reg_v2_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_p3; ++ ++/* define the union reg_v2_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc_p4; ++ ++/* define the union reg_v2_csc1_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_idc; ++ ++/* define the union reg_v2_csc1_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_odc; ++ ++/* define the union reg_v2_csc1_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_iodc; ++ ++/* define the union reg_v2_csc1_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_p0; ++ ++/* define the union reg_v2_csc1_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_p1; ++ ++/* define the union reg_v2_csc1_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_p2; ++ ++/* define the union reg_v2_csc1_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_p3; ++ ++/* define the union reg_v2_csc1_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v2_csc1_p4; ++ ++/* define the union reg_g1_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_idc; ++ ++/* define the union reg_g1_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_odc; ++ ++/* define the union reg_g1_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_iodc; ++ ++/* define the union reg_g1_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_p0; ++ ++/* define the union reg_g1_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_p1; ++ ++/* define the union reg_g1_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_p2; ++ ++/* define the union reg_g1_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_p3; ++ ++/* define the union reg_g1_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc_p4; ++ ++/* define the union reg_g1_csc1_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_idc; ++ ++/* define the union reg_g1_csc1_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_odc; ++ ++/* define the union reg_g1_csc1_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_iodc; ++ ++/* define the union reg_g1_csc1_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_p0; ++ ++/* define the union reg_g1_csc1_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_p1; ++ ++/* define the union reg_g1_csc1_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_p2; ++ ++/* define the union reg_g1_csc1_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_p3; ++ ++/* define the union reg_g1_csc1_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g1_csc1_p4; ++ ++/* define the union reg_g3_csc_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int csc_ck_gt_en : 1; /* [26] */ ++ unsigned int reserved_0 : 5; /* [31..27] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_idc; ++ ++/* define the union reg_g3_csc_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_odc; ++ ++/* define the union reg_g3_csc_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_iodc; ++ ++/* define the union reg_g3_csc_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_p0; ++ ++/* define the union reg_g3_csc_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_p1; ++ ++/* define the union reg_g3_csc_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_p2; ++ ++/* define the union reg_g3_csc_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_p3; ++ ++/* define the union reg_g3_csc_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc_p4; ++ ++/* define the union reg_g3_csc1_idc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc0 : 11; /* [10..0] */ ++ unsigned int cscidc1 : 11; /* [21..11] */ ++ unsigned int csc_en : 1; /* [22] */ ++ unsigned int csc_mode : 3; /* [25..23] */ ++ unsigned int reserved_0 : 6; /* [31..26] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_idc; ++ ++/* define the union reg_g3_csc1_odc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscodc0 : 11; /* [10..0] */ ++ unsigned int cscodc1 : 11; /* [21..11] */ ++ unsigned int csc_sign_mode : 1; /* [22] */ ++ unsigned int reserved_0 : 9; /* [31..23] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_odc; ++ ++/* define the union reg_g3_csc1_iodc */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscidc2 : 11; /* [10..0] */ ++ unsigned int cscodc2 : 11; /* [21..11] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_iodc; ++ ++/* define the union reg_g3_csc1_p0 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp00 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp01 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_p0; ++ ++/* define the union reg_g3_csc1_p1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp02 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp10 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_p1; ++ ++/* define the union reg_g3_csc1_p2 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp11 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp12 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_p2; ++ ++/* define the union reg_g3_csc1_p3 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp20 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 1; /* [15] */ ++ unsigned int cscp21 : 15; /* [30..16] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_p3; ++ ++/* define the union reg_g3_csc1_p4 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int cscp22 : 15; /* [14..0] */ ++ unsigned int reserved_0 : 17; /* [31..15] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_g3_csc1_p4; ++ ++/* define the union reg_v0_zme_hinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_width : 16; /* [15..0] */ ++ unsigned int hzme_ck_gt_en : 1; /* [16] */ ++ unsigned int reserved_0 : 15; /* [31..17] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hinfo; ++ ++/* define the union reg_v0_zme_hsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hratio : 24; /* [23..0] */ ++ unsigned int hfir_order : 1; /* [24] */ ++ unsigned int chfir_mode : 1; /* [25] */ ++ unsigned int lhfir_mode : 1; /* [26] */ ++ unsigned int non_lnr_en : 1; /* [27] */ ++ unsigned int chmid_en : 1; /* [28] */ ++ unsigned int lhmid_en : 1; /* [29] */ ++ unsigned int chfir_en : 1; /* [30] */ ++ unsigned int lhfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hsp; ++ ++/* define the union reg_v0_zme_hloffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int lhfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hloffset; ++ ++/* define the union reg_v0_zme_hcoffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int chfir_offset : 28; /* [27..0] */ ++ unsigned int reserved_0 : 4; /* [31..28] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hcoffset; ++ ++/* define the union reg_v0_zme_hzone0delta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int zone0_delta : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hzone0delta; ++ ++/* define the union reg_v0_zme_hzone2delta */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int zone2_delta : 22; /* [21..0] */ ++ unsigned int reserved_0 : 10; /* [31..22] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hzone2delta; ++ ++/* define the union reg_v0_zme_hzoneend */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int zone0_end : 12; /* [11..0] */ ++ unsigned int zone1_end : 12; /* [23..12] */ ++ unsigned int reserved_0 : 8; /* [31..24] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hzoneend; ++ ++/* define the union reg_v0_zme_hl_shootctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hl_coring : 8; /* [7..0] */ ++ unsigned int hl_gain : 6; /* [13..8] */ ++ unsigned int hl_coringadj_en : 1; /* [14] */ ++ unsigned int hl_flatdect_mode : 1; /* [15] */ ++ unsigned int hl_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int hl_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hl_shootctrl; ++ ++/* define the union reg_v0_zme_hc_shootctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int hc_coring : 8; /* [7..0] */ ++ unsigned int hc_gain : 6; /* [13..8] */ ++ unsigned int hc_coringadj_en : 1; /* [14] */ ++ unsigned int hc_flatdect_mode : 1; /* [15] */ ++ unsigned int hc_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int hc_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hc_shootctrl; ++ ++/* define the union reg_v0_zme_hcoef_ren */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_hf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hcoef_ren; ++ ++/* define the union reg_v0_zme_hcoef_rdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_hcoef_rdata; ++ ++/* define the union reg_v0_zme_vinfo */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int out_height : 16; /* [15..0] */ ++ unsigned int out_fmt : 2; /* [17..16] */ ++ unsigned int out_pro : 1; /* [18] */ ++ unsigned int vzme_ck_gt_en : 1; /* [19] */ ++ unsigned int reserved_0 : 12; /* [31..20] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vinfo; ++ ++/* define the union reg_v0_zme_vsp */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vratio : 16; /* [15..0] */ ++ unsigned int graphdet_en : 1; /* [16] */ ++ unsigned int reserved_0 : 8; /* [24..17] */ ++ unsigned int cvfir_mode : 1; /* [25] */ ++ unsigned int lvfir_mode : 1; /* [26] */ ++ unsigned int vfir_1tap_en : 1; /* [27] */ ++ unsigned int cvmid_en : 1; /* [28] */ ++ unsigned int lvmid_en : 1; /* [29] */ ++ unsigned int cvfir_en : 1; /* [30] */ ++ unsigned int lvfir_en : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vsp; ++ ++/* define the union reg_v0_zme_voffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vchroma_offset : 16; /* [15..0] */ ++ unsigned int vluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_voffset; ++ ++/* define the union reg_v0_zme_vboffset */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vbchroma_offset : 16; /* [15..0] */ ++ unsigned int vbluma_offset : 16; /* [31..16] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vboffset; ++ ++/* define the union reg_v0_zme_vl_shootctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vl_coring : 8; /* [7..0] */ ++ unsigned int vl_gain : 6; /* [13..8] */ ++ unsigned int vl_coringadj_en : 1; /* [14] */ ++ unsigned int vl_flatdect_mode : 1; /* [15] */ ++ unsigned int vl_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int vl_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vl_shootctrl; ++ ++/* define the union reg_v0_zme_vc_shootctrl */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int vc_coring : 8; /* [7..0] */ ++ unsigned int vc_gain : 6; /* [13..8] */ ++ unsigned int vc_coringadj_en : 1; /* [14] */ ++ unsigned int vc_flatdect_mode : 1; /* [15] */ ++ unsigned int vc_shootctrl_mode : 1; /* [16] */ ++ unsigned int reserved_0 : 1; /* [17] */ ++ unsigned int vc_shootctrl_en : 1; /* [18] */ ++ unsigned int reserved_1 : 13; /* [31..19] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vc_shootctrl; ++ ++/* define the union reg_v0_zme_vcoef_ren */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vf_cren : 1; /* [0] */ ++ unsigned int apb_vhd_vf_lren : 1; /* [1] */ ++ unsigned int reserved_0 : 30; /* [31..2] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vcoef_ren; ++ ++/* define the union reg_v0_zme_vcoef_rdata */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_v0_zme_vcoef_rdata; ++ ++/* define the union reg_gfx_osd_glb_info */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int dcmp_en : 1; /* [0] */ ++ unsigned int is_lossless : 1; /* [1] */ ++ unsigned int is_lossless_a : 1; /* [2] */ ++ unsigned int cmp_mode : 1; /* [3] */ ++ unsigned int source_mode : 3; /* [6..4] */ ++ unsigned int tpred_en : 1; /* [7] */ ++ unsigned int reserved_0 : 24; /* [31..8] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_osd_glb_info; ++ ++/* define the union reg_gfx_osd_frame_size */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int frame_width : 13; /* [12..0] */ ++ unsigned int reserved_0 : 3; /* [15..13] */ ++ unsigned int frame_height : 13; /* [28..16] */ ++ unsigned int reserved_1 : 3; /* [31..29] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_osd_frame_size; ++ ++/* define the union reg_gfx_osd_dbg_reg */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 30; /* [29..0] */ ++ unsigned int dcmp_err0 : 1; /* [30] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_osd_dbg_reg; ++ ++/* define the union reg_gfx_osd_dbg_reg1 */ ++typedef union { ++ /* define the struct bits */ ++ struct { ++ unsigned int reserved_0 : 30; /* [29..0] */ ++ unsigned int dcmp_err1 : 1; /* [30] */ ++ unsigned int reserved_1 : 1; /* [31] */ ++ } bits; ++ ++ /* define an unsigned member */ ++ unsigned int u32; ++} reg_gfx_osd_dbg_reg1; ++ ++// ============================================================================== ++/* define the global struct */ ++typedef struct { ++ volatile reg_voctrl voctrl; /* 0x0 */ ++ volatile reg_vointsta vointsta; /* 0x4 */ ++ volatile reg_vomskintsta vomskintsta; /* 0x8 */ ++ volatile reg_vointmsk vointmsk; /* 0xc */ ++ volatile reg_vodebug vodebug; /* 0x10 */ ++ volatile reg_vointsta1 vointsta1; /* 0x14 */ ++ volatile reg_vomskintsta1 vomskintsta1; /* 0x18 */ ++ volatile reg_vointmsk1 vointmsk1; /* 0x1c */ ++ volatile unsigned int vdpversion1; /* 0x20 */ ++ volatile unsigned int vdpversion2; /* 0x24 */ ++ volatile reg_volowpower_ctrl volowpower_ctrl; /* 0x28 */ ++ volatile reg_voufsta voufsta; /* 0x2c */ ++ volatile reg_voufclr voufclr; /* 0x30 */ ++ volatile reg_vointproc_tim vointproc_tim; /* 0x34 */ ++ volatile unsigned int vofpgatest; /* 0x38 */ ++ volatile unsigned int reserved_0[3]; /* 0x3c~0x44 3 regs */ ++ volatile reg_volowpower_ctrl1 volowpower_ctrl1; /* 0x48 */ ++ volatile reg_vofpgadef vofpgadef; /* 0x4c */ ++ volatile reg_volowpower_ctrl2 volowpower_ctrl2; /* 0x50 */ ++ volatile reg_volowpower_ctrl3 volowpower_ctrl3; /* 0x54 */ ++ volatile unsigned int reserved_1[43]; /* 0x58~0x100 43 regs */ ++ volatile reg_vomux_dac vomux_dac; /* 0x104 */ ++ volatile reg_vomux_testsync vomux_testsync; /* 0x108 */ ++ volatile reg_vomux_testdata vomux_testdata; /* 0x10c */ ++ volatile unsigned int reserved_2[4]; /* 0x110~0x11c 4 regs */ ++ volatile reg_vo_dac_ctrl vo_dac_ctrl; /* 0x120 */ ++ volatile reg_vo_dac_otp vo_dac_otp; /* 0x124 */ ++ volatile unsigned int reserved_3[2]; /* 0x128~0x12c 2 regs */ ++ volatile reg_vo_dac0_ctrl vo_dac0_ctrl; /* 0x130 */ ++ volatile reg_vo_dac1_ctrl vo_dac1_ctrl; /* 0x134 */ ++ volatile reg_vo_dac2_ctrl vo_dac2_ctrl; /* 0x138 */ ++ volatile reg_vo_dac3_ctrl vo_dac3_ctrl; /* 0x13c */ ++ volatile reg_vo_dac_stat0 vo_dac_stat0; /* 0x140 */ ++ volatile unsigned int reserved_4[111]; /* 0x144~0x2fc 111 regs */ ++ volatile reg_cbm_bkg1 cbm_bkg1; /* 0x300 */ ++ volatile unsigned int reserved_5; /* 0x304 */ ++ volatile reg_cbm_mix1 cbm_mix1; /* 0x308 */ ++ volatile unsigned int reserved_6[14]; /* 0x30c~0x340 14 regs */ ++ volatile reg_wbc_bmp_thd wbc_bmp_thd; /* 0x344 */ ++ volatile unsigned int reserved_7[2]; /* 0x348~0x34c 2 regs */ ++ volatile unsigned int cbm1_lay0_debug; /* 0x350 */ ++ volatile unsigned int cbm1_lay1_debug; /* 0x354 */ ++ volatile unsigned int cbm1_lay2_debug; /* 0x358 */ ++ volatile unsigned int cbm1_lay3_debug; /* 0x35c */ ++ volatile unsigned int cbm1_lay4_debug; /* 0x360 */ ++ volatile unsigned int cbm1_lay0_last_debug; /* 0x364 */ ++ volatile unsigned int cbm1_lay1_last_debug; /* 0x368 */ ++ volatile unsigned int cbm1_lay2_last_debug; /* 0x36c */ ++ volatile unsigned int cbm1_lay3_last_debug; /* 0x370 */ ++ volatile unsigned int cbm1_lay4_last_debug; /* 0x374 */ ++ volatile unsigned int reserved_8[2]; /* 0x378~0x37c 2 regs */ ++ volatile reg_cbm_bkg2 cbm_bkg2; /* 0x380 */ ++ volatile unsigned int reserved_9; /* 0x384 */ ++ volatile reg_cbm_mix2 cbm_mix2; /* 0x388 */ ++ volatile unsigned int reserved_10[14]; /* 0x38c~0x3c0 14 regs */ ++ volatile reg_hc_bmp_thd hc_bmp_thd; /* 0x3c4 */ ++ volatile unsigned int reserved_11[2]; /* 0x3c8~0x3cc 2 regs */ ++ volatile unsigned int cbm2_lay0_debug; /* 0x3d0 */ ++ volatile unsigned int cbm2_lay1_debug; /* 0x3d4 */ ++ volatile unsigned int cbm2_lay2_debug; /* 0x3d8 */ ++ volatile unsigned int cbm2_lay3_debug; /* 0x3dc */ ++ volatile unsigned int cbm2_lay4_debug; /* 0x3e0 */ ++ volatile unsigned int cbm2_lay0_last_debug; /* 0x3e4 */ ++ volatile unsigned int cbm2_lay1_last_debug; /* 0x3e8 */ ++ volatile unsigned int cbm2_lay2_last_debug; /* 0x3ec */ ++ volatile unsigned int cbm2_lay3_last_debug; /* 0x3f0 */ ++ volatile unsigned int cbm2_lay4_last_debug; /* 0x3f4 */ ++ volatile unsigned int reserved_12[2]; /* 0x3f8~0x3fc 2 regs */ ++ volatile reg_cbm_bkg3 cbm_bkg3; /* 0x400 */ ++ volatile unsigned int reserved_13; /* 0x404 */ ++ volatile reg_cbm_mix3 cbm_mix3; /* 0x408 */ ++ volatile unsigned int reserved_14[17]; /* 0x40c~0x44c 17 regs */ ++ volatile unsigned int cbm3_lay0_debug; /* 0x450 */ ++ volatile unsigned int cbm3_lay1_debug; /* 0x454 */ ++ volatile unsigned int cbm3_lay2_debug; /* 0x458 */ ++ volatile unsigned int cbm3_lay3_debug; /* 0x45c */ ++ volatile unsigned int cbm3_lay4_debug; /* 0x460 */ ++ volatile unsigned int cbm3_lay0_last_debug; /* 0x464 */ ++ volatile unsigned int cbm3_lay1_last_debug; /* 0x468 */ ++ volatile unsigned int cbm3_lay2_last_debug; /* 0x46c */ ++ volatile unsigned int cbm3_lay3_last_debug; /* 0x470 */ ++ volatile unsigned int cbm3_lay4_last_debug; /* 0x474 */ ++ volatile unsigned int reserved_15[98]; /* 0x478~0x5fc 98 regs */ ++ volatile reg_mixv0_bkg mixv0_bkg; /* 0x600 */ ++ volatile unsigned int reserved_16; /* 0x604 */ ++ volatile reg_mixv0_mix mixv0_mix; /* 0x608 */ ++ volatile unsigned int reserved_17[189]; /* 0x60c~0x8fc 189 regs */ ++ volatile reg_mixg0_bkg mixg0_bkg; /* 0x900 */ ++ volatile reg_mixg0_bkalpha mixg0_bkalpha; /* 0x904 */ ++ volatile reg_mixg0_mix mixg0_mix; /* 0x908 */ ++ volatile unsigned int reserved_18[189]; /* 0x90c~0xbfc 189 regs */ ++ volatile reg_link_ctrl link_ctrl; /* 0xc00 */ ++ volatile unsigned int reserved_19[63]; /* 0xc04~0xcfc 63 regs */ ++ volatile reg_vpss_ctrl vpss_ctrl; /* 0xd00 */ ++ volatile reg_vpss_miscellaneous vpss_miscellaneous; /* 0xd04 */ ++ volatile reg_vpss_ftconfig vpss_ftconfig; /* 0xd08 */ ++ volatile unsigned int reserved_20[5]; /* 0xd0c~0xd1c 5 regs */ ++ volatile unsigned int vpss_version; /* 0xd20 */ ++ volatile unsigned int vpss_debug0; /* 0xd24 */ ++ volatile unsigned int vpss_debug1; /* 0xd28 */ ++ volatile unsigned int vpss_debug2; /* 0xd2c */ ++ volatile unsigned int vpss_debug3; /* 0xd30 */ ++ volatile unsigned int vpss_debug4; /* 0xd34 */ ++ volatile unsigned int vpss_debug5; /* 0xd38 */ ++ volatile unsigned int vpss_debug6; /* 0xd3c */ ++ volatile unsigned int reserved_21[48]; /* 0xd40~0xdfc 48 regs */ ++ volatile unsigned int para_haddr_vhd_chn00; /* 0xe00 */ ++ volatile unsigned int para_addr_vhd_chn00; /* 0xe04 */ ++ volatile unsigned int para_haddr_vhd_chn01; /* 0xe08 */ ++ volatile unsigned int para_addr_vhd_chn01; /* 0xe0c */ ++ volatile unsigned int para_haddr_vhd_chn02; /* 0xe10 */ ++ volatile unsigned int para_addr_vhd_chn02; /* 0xe14 */ ++ volatile unsigned int para_haddr_vhd_chn03; /* 0xe18 */ ++ volatile unsigned int para_addr_vhd_chn03; /* 0xe1c */ ++ volatile unsigned int para_haddr_vhd_chn04; /* 0xe20 */ ++ volatile unsigned int para_addr_vhd_chn04; /* 0xe24 */ ++ volatile unsigned int para_haddr_vhd_chn05; /* 0xe28 */ ++ volatile unsigned int para_addr_vhd_chn05; /* 0xe2c */ ++ volatile unsigned int para_haddr_vhd_chn06; /* 0xe30 */ ++ volatile unsigned int para_addr_vhd_chn06; /* 0xe34 */ ++ volatile unsigned int para_haddr_vhd_chn07; /* 0xe38 */ ++ volatile unsigned int para_addr_vhd_chn07; /* 0xe3c */ ++ volatile unsigned int para_haddr_vhd_chn08; /* 0xe40 */ ++ volatile unsigned int para_addr_vhd_chn08; /* 0xe44 */ ++ volatile unsigned int para_haddr_vhd_chn09; /* 0xe48 */ ++ volatile unsigned int para_addr_vhd_chn09; /* 0xe4c */ ++ volatile unsigned int para_haddr_vhd_chn10; /* 0xe50 */ ++ volatile unsigned int para_addr_vhd_chn10; /* 0xe54 */ ++ volatile unsigned int para_haddr_vhd_chn11; /* 0xe58 */ ++ volatile unsigned int para_addr_vhd_chn11; /* 0xe5c */ ++ volatile unsigned int para_haddr_vhd_chn12; /* 0xe60 */ ++ volatile unsigned int para_addr_vhd_chn12; /* 0xe64 */ ++ volatile unsigned int para_haddr_vhd_chn13; /* 0xe68 */ ++ volatile unsigned int para_addr_vhd_chn13; /* 0xe6c */ ++ volatile unsigned int para_haddr_vhd_chn14; /* 0xe70 */ ++ volatile unsigned int para_addr_vhd_chn14; /* 0xe74 */ ++ volatile unsigned int para_haddr_vhd_chn15; /* 0xe78 */ ++ volatile unsigned int para_addr_vhd_chn15; /* 0xe7c */ ++ volatile unsigned int para_haddr_vhd_chn16; /* 0xe80 */ ++ volatile unsigned int para_addr_vhd_chn16; /* 0xe84 */ ++ volatile unsigned int para_haddr_vhd_chn17; /* 0xe88 */ ++ volatile unsigned int para_addr_vhd_chn17; /* 0xe8c */ ++ volatile unsigned int para_haddr_vhd_chn18; /* 0xe90 */ ++ volatile unsigned int para_addr_vhd_chn18; /* 0xe94 */ ++ volatile unsigned int para_haddr_vhd_chn19; /* 0xe98 */ ++ volatile unsigned int para_addr_vhd_chn19; /* 0xe9c */ ++ volatile unsigned int para_haddr_vhd_chn20; /* 0xea0 */ ++ volatile unsigned int para_addr_vhd_chn20; /* 0xea4 */ ++ volatile unsigned int para_haddr_vhd_chn21; /* 0xea8 */ ++ volatile unsigned int para_addr_vhd_chn21; /* 0xeac */ ++ volatile unsigned int para_haddr_vhd_chn22; /* 0xeb0 */ ++ volatile unsigned int para_addr_vhd_chn22; /* 0xeb4 */ ++ volatile unsigned int para_haddr_vhd_chn23; /* 0xeb8 */ ++ volatile unsigned int para_addr_vhd_chn23; /* 0xebc */ ++ volatile unsigned int para_haddr_vhd_chn24; /* 0xec0 */ ++ volatile unsigned int para_addr_vhd_chn24; /* 0xec4 */ ++ volatile unsigned int para_haddr_vhd_chn25; /* 0xec8 */ ++ volatile unsigned int para_addr_vhd_chn25; /* 0xecc */ ++ volatile unsigned int para_haddr_vhd_chn26; /* 0xed0 */ ++ volatile unsigned int para_addr_vhd_chn26; /* 0xed4 */ ++ volatile unsigned int para_haddr_vhd_chn27; /* 0xed8 */ ++ volatile unsigned int para_addr_vhd_chn27; /* 0xedc */ ++ volatile unsigned int para_haddr_vhd_chn28; /* 0xee0 */ ++ volatile unsigned int para_addr_vhd_chn28; /* 0xee4 */ ++ volatile unsigned int para_haddr_vhd_chn29; /* 0xee8 */ ++ volatile unsigned int para_addr_vhd_chn29; /* 0xeec */ ++ volatile unsigned int para_haddr_vhd_chn30; /* 0xef0 */ ++ volatile unsigned int para_addr_vhd_chn30; /* 0xef4 */ ++ volatile unsigned int para_haddr_vhd_chn31; /* 0xef8 */ ++ volatile unsigned int para_addr_vhd_chn31; /* 0xefc */ ++ volatile reg_para_up_vhd para_up_vhd; /* 0xf00 */ ++ volatile unsigned int para_haddr_vsd_chn00; /* 0xf04 */ ++ volatile unsigned int para_addr_vsd_chn00; /* 0xf08 */ ++ volatile unsigned int para_haddr_vsd_chn01; /* 0xf0c */ ++ volatile unsigned int para_addr_vsd_chn01; /* 0xf10 */ ++ volatile unsigned int para_haddr_vsd_chn02; /* 0xf14 */ ++ volatile unsigned int para_addr_vsd_chn02; /* 0xf18 */ ++ volatile unsigned int para_haddr_vsd_chn03; /* 0xf1c */ ++ volatile unsigned int para_addr_vsd_chn03; /* 0xf20 */ ++ volatile unsigned int para_haddr_vsd_chn04; /* 0xf24 */ ++ volatile unsigned int para_addr_vsd_chn04; /* 0xf28 */ ++ volatile unsigned int para_haddr_vsd_chn05; /* 0xf2c */ ++ volatile unsigned int para_addr_vsd_chn05; /* 0xf30 */ ++ volatile unsigned int para_haddr_vsd_chn06; /* 0xf34 */ ++ volatile unsigned int para_addr_vsd_chn06; /* 0xf38 */ ++ volatile unsigned int para_haddr_vsd_chn07; /* 0xf3c */ ++ volatile unsigned int para_addr_vsd_chn07; /* 0xf40 */ ++ volatile reg_para_up_vsd para_up_vsd; /* 0xf44 */ ++ volatile reg_para_conflict_clr para_conflict_clr; /* 0xf48 */ ++ volatile reg_para_conflict_sta para_conflict_sta; /* 0xf4c */ ++ volatile unsigned int reserved_22[44]; /* 0xf50~0xffc 44 regs */ ++ volatile reg_v0_ctrl v0_ctrl; /* 0x1000 */ ++ volatile reg_v0_upd v0_upd; /* 0x1004 */ ++ volatile reg_v0_0reso_read v0_0reso_read; /* 0x1008 */ ++ volatile unsigned int reserved_23; /* 0x100c */ ++ volatile reg_v0_ireso v0_ireso; /* 0x1010 */ ++ volatile unsigned int reserved_24[27]; /* 0x1014~0x107c 27 regs */ ++ volatile reg_v0_dfpos v0_dfpos; /* 0x1080 */ ++ volatile reg_v0_dlpos v0_dlpos; /* 0x1084 */ ++ volatile reg_v0_vfpos v0_vfpos; /* 0x1088 */ ++ volatile reg_v0_vlpos v0_vlpos; /* 0x108c */ ++ volatile reg_v0_bk v0_bk; /* 0x1090 */ ++ volatile reg_v0_alpha v0_alpha; /* 0x1094 */ ++ volatile reg_v0_mute_bk v0_mute_bk; /* 0x1098 */ ++ volatile unsigned int reserved_25; /* 0x109c */ ++ volatile reg_v0_rimwidth v0_rimwidth; /* 0x10a0 */ ++ volatile reg_v0_rimcol0 v0_rimcol0; /* 0x10a4 */ ++ volatile reg_v0_rimcol1 v0_rimcol1; /* 0x10a8 */ ++ volatile unsigned int reserved_26[85]; /* 0x10ac~0x11fc 85 regs */ ++ volatile reg_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; /* 0x1200 */ ++ volatile reg_v0_ot_pp_csc_coef00 v0_ot_pp_csc_coef00; /* 0x1204 */ ++ volatile reg_v0_ot_pp_csc_coef01 v0_ot_pp_csc_coef01; /* 0x1208 */ ++ volatile reg_v0_ot_pp_csc_coef02 v0_ot_pp_csc_coef02; /* 0x120c */ ++ volatile reg_v0_ot_pp_csc_coef10 v0_ot_pp_csc_coef10; /* 0x1210 */ ++ volatile reg_v0_ot_pp_csc_coef11 v0_ot_pp_csc_coef11; /* 0x1214 */ ++ volatile reg_v0_ot_pp_csc_coef12 v0_ot_pp_csc_coef12; /* 0x1218 */ ++ volatile reg_v0_ot_pp_csc_coef20 v0_ot_pp_csc_coef20; /* 0x121c */ ++ volatile reg_v0_ot_pp_csc_coef21 v0_ot_pp_csc_coef21; /* 0x1220 */ ++ volatile reg_v0_ot_pp_csc_coef22 v0_ot_pp_csc_coef22; /* 0x1224 */ ++ volatile reg_v0_ot_pp_csc_scale v0_ot_pp_csc_scale; /* 0x1228 */ ++ volatile reg_v0_ot_pp_csc_idc0 v0_ot_pp_csc_idc0; /* 0x122c */ ++ volatile reg_v0_ot_pp_csc_idc1 v0_ot_pp_csc_idc1; /* 0x1230 */ ++ volatile reg_v0_ot_pp_csc_idc2 v0_ot_pp_csc_idc2; /* 0x1234 */ ++ volatile reg_v0_ot_pp_csc_odc0 v0_ot_pp_csc_odc0; /* 0x1238 */ ++ volatile reg_v0_ot_pp_csc_odc1 v0_ot_pp_csc_odc1; /* 0x123c */ ++ volatile reg_v0_ot_pp_csc_odc2 v0_ot_pp_csc_odc2; /* 0x1240 */ ++ volatile reg_v0_ot_pp_csc_min_y v0_ot_pp_csc_min_y; /* 0x1244 */ ++ volatile reg_v0_ot_pp_csc_min_c v0_ot_pp_csc_min_c; /* 0x1248 */ ++ volatile reg_v0_ot_pp_csc_max_y v0_ot_pp_csc_max_y; /* 0x124c */ ++ volatile reg_v0_ot_pp_csc_max_c v0_ot_pp_csc_max_c; /* 0x1250 */ ++ volatile reg_v0_ot_pp_csc2_coef00 v0_ot_pp_csc2_coef00; /* 0x1254 */ ++ volatile reg_v0_ot_pp_csc2_coef01 v0_ot_pp_csc2_coef01; /* 0x1258 */ ++ volatile reg_v0_ot_pp_csc2_coef02 v0_ot_pp_csc2_coef02; /* 0x125c */ ++ volatile reg_v0_ot_pp_csc2_coef10 v0_ot_pp_csc2_coef10; /* 0x1260 */ ++ volatile reg_v0_ot_pp_csc2_coef11 v0_ot_pp_csc2_coef11; /* 0x1264 */ ++ volatile reg_v0_ot_pp_csc2_coef12 v0_ot_pp_csc2_coef12; /* 0x1268 */ ++ volatile reg_v0_ot_pp_csc2_coef20 v0_ot_pp_csc2_coef20; /* 0x126c */ ++ volatile reg_v0_ot_pp_csc2_coef21 v0_ot_pp_csc2_coef21; /* 0x1270 */ ++ volatile reg_v0_ot_pp_csc2_coef22 v0_ot_pp_csc2_coef22; /* 0x1274 */ ++ volatile reg_v0_ot_pp_csc2_scale v0_ot_pp_csc2_scale; /* 0x1278 */ ++ volatile reg_v0_ot_pp_csc2_idc0 v0_ot_pp_csc2_idc0; /* 0x127c */ ++ volatile reg_v0_ot_pp_csc2_idc1 v0_ot_pp_csc2_idc1; /* 0x1280 */ ++ volatile reg_v0_ot_pp_csc2_idc2 v0_ot_pp_csc2_idc2; /* 0x1284 */ ++ volatile reg_v0_ot_pp_csc2_odc0 v0_ot_pp_csc2_odc0; /* 0x1288 */ ++ volatile reg_v0_ot_pp_csc2_odc1 v0_ot_pp_csc2_odc1; /* 0x128c */ ++ volatile reg_v0_ot_pp_csc2_odc2 v0_ot_pp_csc2_odc2; /* 0x1290 */ ++ volatile reg_v0_ot_pp_csc2_min_y v0_ot_pp_csc2_min_y; /* 0x1294 */ ++ volatile reg_v0_ot_pp_csc2_min_c v0_ot_pp_csc2_min_c; /* 0x1298 */ ++ volatile reg_v0_ot_pp_csc2_max_y v0_ot_pp_csc2_max_y; /* 0x129c */ ++ volatile reg_v0_ot_pp_csc2_max_c v0_ot_pp_csc2_max_c; /* 0x12a0 */ ++ volatile unsigned int reserved_27[19]; /* 0x12a4~0x12ec 19 regs */ ++ volatile reg_v0_ot_pp_csc_ink_ctrl v0_ot_pp_csc_ink_ctrl; /* 0x12f0 */ ++ volatile reg_v0_ot_pp_csc_ink_pos v0_ot_pp_csc_ink_pos; /* 0x12f4 */ ++ volatile unsigned int v0_ot_pp_csc_ink_data; /* 0x12f8 */ ++ volatile unsigned int v0_ot_pp_csc_ink_data2; /* 0x12fc */ ++ volatile unsigned int reserved_28[64]; /* 0x1300~0x13fc 64 regs */ ++ volatile reg_v0_cvfir_vinfo v0_cvfir_vinfo; /* 0x1400 */ ++ volatile reg_v0_cvfir_vsp v0_cvfir_vsp; /* 0x1404 */ ++ volatile reg_v0_cvfir_voffset v0_cvfir_voffset; /* 0x1408 */ ++ volatile reg_v0_cvfir_vboffset v0_cvfir_vboffset; /* 0x140c */ ++ volatile unsigned int reserved_29[8]; /* 0x1410~0x142c 8 regs */ ++ volatile reg_v0_cvfir_vcoef0 v0_cvfir_vcoef0; /* 0x1430 */ ++ volatile reg_v0_cvfir_vcoef1 v0_cvfir_vcoef1; /* 0x1434 */ ++ volatile reg_v0_cvfir_vcoef2 v0_cvfir_vcoef2; /* 0x1438 */ ++ volatile unsigned int reserved_30[49]; /* 0x143c~0x14fc 49 regs */ ++ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; /* 0x1500 */ ++ volatile reg_v0_hfircoef01 v0_hfircoef01; /* 0x1504 */ ++ volatile reg_v0_hfircoef23 v0_hfircoef23; /* 0x1508 */ ++ volatile reg_v0_hfircoef45 v0_hfircoef45; /* 0x150c */ ++ volatile reg_v0_hfircoef67 v0_hfircoef67; /* 0x1510 */ ++ volatile unsigned int reserved_31[699]; /* 0x1514~0x1ffc 699 regs */ ++ volatile reg_v1_ctrl v1_ctrl; /* 0x2000 */ ++ volatile reg_v1_upd v1_upd; /* 0x2004 */ ++ volatile reg_v1_0reso_read v1_0reso_read; /* 0x2008 */ ++ volatile unsigned int reserved_32; /* 0x200c */ ++ volatile reg_v1_ireso v1_ireso; /* 0x2010 */ ++ volatile unsigned int reserved_33[27]; /* 0x2014~0x207c 27 regs */ ++ volatile reg_v1_dfpos v1_dfpos; /* 0x2080 */ ++ volatile reg_v1_dlpos v1_dlpos; /* 0x2084 */ ++ volatile reg_v1_vfpos v1_vfpos; /* 0x2088 */ ++ volatile reg_v1_vlpos v1_vlpos; /* 0x208c */ ++ volatile reg_v1_bk v1_bk; /* 0x2090 */ ++ volatile reg_v1_alpha v1_alpha; /* 0x2094 */ ++ volatile reg_v1_mute_bk v1_mute_bk; /* 0x2098 */ ++ volatile unsigned int reserved_34; /* 0x209c */ ++ volatile reg_v1_rimwidth v1_rimwidth; /* 0x20a0 */ ++ volatile reg_v1_rimcol0 v1_rimcol0; /* 0x20a4 */ ++ volatile reg_v1_rimcol1 v1_rimcol1; /* 0x20a8 */ ++ volatile unsigned int reserved_35[85]; /* 0x20ac~0x21fc 85 regs */ ++ volatile reg_v1_ot_pp_csc_ctrl v1_ot_pp_csc_ctrl; /* 0x2200 */ ++ volatile reg_v1_ot_pp_csc_coef00 v1_ot_pp_csc_coef00; /* 0x2204 */ ++ volatile reg_v1_ot_pp_csc_coef01 v1_ot_pp_csc_coef01; /* 0x2208 */ ++ volatile reg_v1_ot_pp_csc_coef02 v1_ot_pp_csc_coef02; /* 0x220c */ ++ volatile reg_v1_ot_pp_csc_coef10 v1_ot_pp_csc_coef10; /* 0x2210 */ ++ volatile reg_v1_ot_pp_csc_coef11 v1_ot_pp_csc_coef11; /* 0x2214 */ ++ volatile reg_v1_ot_pp_csc_coef12 v1_ot_pp_csc_coef12; /* 0x2218 */ ++ volatile reg_v1_ot_pp_csc_coef20 v1_ot_pp_csc_coef20; /* 0x221c */ ++ volatile reg_v1_ot_pp_csc_coef21 v1_ot_pp_csc_coef21; /* 0x2220 */ ++ volatile reg_v1_ot_pp_csc_coef22 v1_ot_pp_csc_coef22; /* 0x2224 */ ++ volatile reg_v1_ot_pp_csc_scale v1_ot_pp_csc_scale; /* 0x2228 */ ++ volatile reg_v1_ot_pp_csc_idc0 v1_ot_pp_csc_idc0; /* 0x222c */ ++ volatile reg_v1_ot_pp_csc_idc1 v1_ot_pp_csc_idc1; /* 0x2230 */ ++ volatile reg_v1_ot_pp_csc_idc2 v1_ot_pp_csc_idc2; /* 0x2234 */ ++ volatile reg_v1_ot_pp_csc_odc0 v1_ot_pp_csc_odc0; /* 0x2238 */ ++ volatile reg_v1_ot_pp_csc_odc1 v1_ot_pp_csc_odc1; /* 0x223c */ ++ volatile reg_v1_ot_pp_csc_odc2 v1_ot_pp_csc_odc2; /* 0x2240 */ ++ volatile reg_v1_ot_pp_csc_min_y v1_ot_pp_csc_min_y; /* 0x2244 */ ++ volatile reg_v1_ot_pp_csc_min_c v1_ot_pp_csc_min_c; /* 0x2248 */ ++ volatile reg_v1_ot_pp_csc_max_y v1_ot_pp_csc_max_y; /* 0x224c */ ++ volatile reg_v1_ot_pp_csc_max_c v1_ot_pp_csc_max_c; /* 0x2250 */ ++ volatile reg_v1_ot_pp_csc2_coef00 v1_ot_pp_csc2_coef00; /* 0x2254 */ ++ volatile reg_v1_ot_pp_csc2_coef01 v1_ot_pp_csc2_coef01; /* 0x2258 */ ++ volatile reg_v1_ot_pp_csc2_coef02 v1_ot_pp_csc2_coef02; /* 0x225c */ ++ volatile reg_v1_ot_pp_csc2_coef10 v1_ot_pp_csc2_coef10; /* 0x2260 */ ++ volatile reg_v1_ot_pp_csc2_coef11 v1_ot_pp_csc2_coef11; /* 0x2264 */ ++ volatile reg_v1_ot_pp_csc2_coef12 v1_ot_pp_csc2_coef12; /* 0x2268 */ ++ volatile reg_v1_ot_pp_csc2_coef20 v1_ot_pp_csc2_coef20; /* 0x226c */ ++ volatile reg_v1_ot_pp_csc2_coef21 v1_ot_pp_csc2_coef21; /* 0x2270 */ ++ volatile reg_v1_ot_pp_csc2_coef22 v1_ot_pp_csc2_coef22; /* 0x2274 */ ++ volatile reg_v1_ot_pp_csc2_scale v1_ot_pp_csc2_scale; /* 0x2278 */ ++ volatile reg_v1_ot_pp_csc2_idc0 v1_ot_pp_csc2_idc0; /* 0x227c */ ++ volatile reg_v1_ot_pp_csc2_idc1 v1_ot_pp_csc2_idc1; /* 0x2280 */ ++ volatile reg_v1_ot_pp_csc2_idc2 v1_ot_pp_csc2_idc2; /* 0x2284 */ ++ volatile reg_v1_ot_pp_csc2_odc0 v1_ot_pp_csc2_odc0; /* 0x2288 */ ++ volatile reg_v1_ot_pp_csc2_odc1 v1_ot_pp_csc2_odc1; /* 0x228c */ ++ volatile reg_v1_ot_pp_csc2_odc2 v1_ot_pp_csc2_odc2; /* 0x2290 */ ++ volatile reg_v1_ot_pp_csc2_min_y v1_ot_pp_csc2_min_y; /* 0x2294 */ ++ volatile reg_v1_ot_pp_csc2_min_c v1_ot_pp_csc2_min_c; /* 0x2298 */ ++ volatile reg_v1_ot_pp_csc2_max_y v1_ot_pp_csc2_max_y; /* 0x229c */ ++ volatile reg_v1_ot_pp_csc2_max_c v1_ot_pp_csc2_max_c; /* 0x22a0 */ ++ volatile unsigned int reserved_36[19]; /* 0x22a4~0x22ec 19 regs */ ++ volatile reg_v1_ot_pp_csc_ink_ctrl v1_ot_pp_csc_ink_ctrl; /* 0x22f0 */ ++ volatile reg_v1_ot_pp_csc_ink_pos v1_ot_pp_csc_ink_pos; /* 0x22f4 */ ++ volatile unsigned int v1_ot_pp_csc_ink_data; /* 0x22f8 */ ++ volatile unsigned int v1_ot_pp_csc_ink_data2; /* 0x22fc */ ++ volatile unsigned int reserved_37[64]; /* 0x2300~0x23fc 64 regs */ ++ volatile reg_v1_cvfir_vinfo v1_cvfir_vinfo; /* 0x2400 */ ++ volatile reg_v1_cvfir_vsp v1_cvfir_vsp; /* 0x2404 */ ++ volatile reg_v1_cvfir_voffset v1_cvfir_voffset; /* 0x2408 */ ++ volatile reg_v1_cvfir_vboffset v1_cvfir_vboffset; /* 0x240c */ ++ volatile unsigned int reserved_38[8]; /* 0x2410~0x242c 8 regs */ ++ volatile reg_v1_cvfir_vcoef0 v1_cvfir_vcoef0; /* 0x2430 */ ++ volatile reg_v1_cvfir_vcoef1 v1_cvfir_vcoef1; /* 0x2434 */ ++ volatile reg_v1_cvfir_vcoef2 v1_cvfir_vcoef2; /* 0x2438 */ ++ volatile unsigned int reserved_39[49]; /* 0x243c~0x24fc 49 regs */ ++ volatile reg_v1_hfir_ctrl v1_hfir_ctrl; /* 0x2500 */ ++ volatile reg_v1_hfircoef01 v1_hfircoef01; /* 0x2504 */ ++ volatile reg_v1_hfircoef23 v1_hfircoef23; /* 0x2508 */ ++ volatile reg_v1_hfircoef45 v1_hfircoef45; /* 0x250c */ ++ volatile reg_v1_hfircoef67 v1_hfircoef67; /* 0x2510 */ ++ volatile unsigned int reserved_40[699]; /* 0x2514~0x2ffc 699 regs */ ++ volatile reg_v2_ctrl v2_ctrl; /* 0x3000 */ ++ volatile reg_v2_upd v2_upd; /* 0x3004 */ ++ volatile reg_v2_0reso_read v2_0reso_read; /* 0x3008 */ ++ volatile unsigned int reserved_41; /* 0x300c */ ++ volatile reg_v2_ireso v2_ireso; /* 0x3010 */ ++ volatile unsigned int reserved_42[27]; /* 0x3014~0x307c 27 regs */ ++ volatile reg_v2_dfpos v2_dfpos; /* 0x3080 */ ++ volatile reg_v2_dlpos v2_dlpos; /* 0x3084 */ ++ volatile reg_v2_vfpos v2_vfpos; /* 0x3088 */ ++ volatile reg_v2_vlpos v2_vlpos; /* 0x308c */ ++ volatile reg_v2_bk v2_bk; /* 0x3090 */ ++ volatile reg_v2_alpha v2_alpha; /* 0x3094 */ ++ volatile reg_v2_mute_bk v2_mute_bk; /* 0x3098 */ ++ volatile unsigned int reserved_43[89]; /* 0x309c~0x31fc 89 regs */ ++ volatile reg_v2_ot_pp_csc_ctrl v2_ot_pp_csc_ctrl; /* 0x3200 */ ++ volatile reg_v2_ot_pp_csc_coef00 v2_ot_pp_csc_coef00; /* 0x3204 */ ++ volatile reg_v2_ot_pp_csc_coef01 v2_ot_pp_csc_coef01; /* 0x3208 */ ++ volatile reg_v2_ot_pp_csc_coef02 v2_ot_pp_csc_coef02; /* 0x320c */ ++ volatile reg_v2_ot_pp_csc_coef10 v2_ot_pp_csc_coef10; /* 0x3210 */ ++ volatile reg_v2_ot_pp_csc_coef11 v2_ot_pp_csc_coef11; /* 0x3214 */ ++ volatile reg_v2_ot_pp_csc_coef12 v2_ot_pp_csc_coef12; /* 0x3218 */ ++ volatile reg_v2_ot_pp_csc_coef20 v2_ot_pp_csc_coef20; /* 0x321c */ ++ volatile reg_v2_ot_pp_csc_coef21 v2_ot_pp_csc_coef21; /* 0x3220 */ ++ volatile reg_v2_ot_pp_csc_coef22 v2_ot_pp_csc_coef22; /* 0x3224 */ ++ volatile reg_v2_ot_pp_csc_scale v2_ot_pp_csc_scale; /* 0x3228 */ ++ volatile reg_v2_ot_pp_csc_idc0 v2_ot_pp_csc_idc0; /* 0x322c */ ++ volatile reg_v2_ot_pp_csc_idc1 v2_ot_pp_csc_idc1; /* 0x3230 */ ++ volatile reg_v2_ot_pp_csc_idc2 v2_ot_pp_csc_idc2; /* 0x3234 */ ++ volatile reg_v2_ot_pp_csc_odc0 v2_ot_pp_csc_odc0; /* 0x3238 */ ++ volatile reg_v2_ot_pp_csc_odc1 v2_ot_pp_csc_odc1; /* 0x323c */ ++ volatile reg_v2_ot_pp_csc_odc2 v2_ot_pp_csc_odc2; /* 0x3240 */ ++ volatile reg_v2_ot_pp_csc_min_y v2_ot_pp_csc_min_y; /* 0x3244 */ ++ volatile reg_v2_ot_pp_csc_min_c v2_ot_pp_csc_min_c; /* 0x3248 */ ++ volatile reg_v2_ot_pp_csc_max_y v2_ot_pp_csc_max_y; /* 0x324c */ ++ volatile reg_v2_ot_pp_csc_max_c v2_ot_pp_csc_max_c; /* 0x3250 */ ++ volatile reg_v2_ot_pp_csc2_coef00 v2_ot_pp_csc2_coef00; /* 0x3254 */ ++ volatile reg_v2_ot_pp_csc2_coef01 v2_ot_pp_csc2_coef01; /* 0x3258 */ ++ volatile reg_v2_ot_pp_csc2_coef02 v2_ot_pp_csc2_coef02; /* 0x325c */ ++ volatile reg_v2_ot_pp_csc2_coef10 v2_ot_pp_csc2_coef10; /* 0x3260 */ ++ volatile reg_v2_ot_pp_csc2_coef11 v2_ot_pp_csc2_coef11; /* 0x3264 */ ++ volatile reg_v2_ot_pp_csc2_coef12 v2_ot_pp_csc2_coef12; /* 0x3268 */ ++ volatile reg_v2_ot_pp_csc2_coef20 v2_ot_pp_csc2_coef20; /* 0x326c */ ++ volatile reg_v2_ot_pp_csc2_coef21 v2_ot_pp_csc2_coef21; /* 0x3270 */ ++ volatile reg_v2_ot_pp_csc2_coef22 v2_ot_pp_csc2_coef22; /* 0x3274 */ ++ volatile reg_v2_ot_pp_csc2_scale v2_ot_pp_csc2_scale; /* 0x3278 */ ++ volatile reg_v2_ot_pp_csc2_idc0 v2_ot_pp_csc2_idc0; /* 0x327c */ ++ volatile reg_v2_ot_pp_csc2_idc1 v2_ot_pp_csc2_idc1; /* 0x3280 */ ++ volatile reg_v2_ot_pp_csc2_idc2 v2_ot_pp_csc2_idc2; /* 0x3284 */ ++ volatile reg_v2_ot_pp_csc2_odc0 v2_ot_pp_csc2_odc0; /* 0x3288 */ ++ volatile reg_v2_ot_pp_csc2_odc1 v2_ot_pp_csc2_odc1; /* 0x328c */ ++ volatile reg_v2_ot_pp_csc2_odc2 v2_ot_pp_csc2_odc2; /* 0x3290 */ ++ volatile reg_v2_ot_pp_csc2_min_y v2_ot_pp_csc2_min_y; /* 0x3294 */ ++ volatile reg_v2_ot_pp_csc2_min_c v2_ot_pp_csc2_min_c; /* 0x3298 */ ++ volatile reg_v2_ot_pp_csc2_max_y v2_ot_pp_csc2_max_y; /* 0x329c */ ++ volatile reg_v2_ot_pp_csc2_max_c v2_ot_pp_csc2_max_c; /* 0x32a0 */ ++ volatile unsigned int reserved_44[19]; /* 0x32a4~0x32ec 19 regs */ ++ volatile reg_v2_ot_pp_csc_ink_ctrl v2_ot_pp_csc_ink_ctrl; /* 0x32f0 */ ++ volatile reg_v2_ot_pp_csc_ink_pos v2_ot_pp_csc_ink_pos; /* 0x32f4 */ ++ volatile unsigned int v2_ot_pp_csc_ink_data; /* 0x32f8 */ ++ volatile unsigned int v2_ot_pp_csc_ink_data2; /* 0x32fc */ ++ volatile unsigned int reserved_45[64]; /* 0x3300~0x33fc 64 regs */ ++ volatile reg_v2_cvfir_vinfo v2_cvfir_vinfo; /* 0x3400 */ ++ volatile reg_v2_cvfir_vsp v2_cvfir_vsp; /* 0x3404 */ ++ volatile reg_v2_cvfir_voffset v2_cvfir_voffset; /* 0x3408 */ ++ volatile reg_v2_cvfir_vboffset v2_cvfir_vboffset; /* 0x340c */ ++ volatile unsigned int reserved_46[8]; /* 0x3410~0x342c 8 regs */ ++ volatile reg_v2_cvfir_vcoef0 v2_cvfir_vcoef0; /* 0x3430 */ ++ volatile reg_v2_cvfir_vcoef1 v2_cvfir_vcoef1; /* 0x3434 */ ++ volatile reg_v2_cvfir_vcoef2 v2_cvfir_vcoef2; /* 0x3438 */ ++ volatile unsigned int reserved_47[49]; /* 0x343c~0x34fc 49 regs */ ++ volatile reg_v2_hfir_ctrl v2_hfir_ctrl; /* 0x3500 */ ++ volatile reg_v2_hfircoef01 v2_hfircoef01; /* 0x3504 */ ++ volatile reg_v2_hfircoef23 v2_hfircoef23; /* 0x3508 */ ++ volatile reg_v2_hfircoef45 v2_hfircoef45; /* 0x350c */ ++ volatile reg_v2_hfircoef67 v2_hfircoef67; /* 0x3510 */ ++ volatile unsigned int reserved_48[699]; /* 0x3514~0x3ffc 699 regs */ ++ volatile reg_v3_ctrl v3_ctrl; /* 0x4000 */ ++ volatile reg_v3_upd v3_upd; /* 0x4004 */ ++ volatile reg_v3_0reso_read v3_0reso_read; /* 0x4008 */ ++ volatile unsigned int reserved_49; /* 0x400c */ ++ volatile reg_v3_ireso v3_ireso; /* 0x4010 */ ++ volatile unsigned int reserved_50[27]; /* 0x4014~0x407c 27 regs */ ++ volatile reg_v3_dfpos v3_dfpos; /* 0x4080 */ ++ volatile reg_v3_dlpos v3_dlpos; /* 0x4084 */ ++ volatile reg_v3_vfpos v3_vfpos; /* 0x4088 */ ++ volatile reg_v3_vlpos v3_vlpos; /* 0x408c */ ++ volatile reg_v3_bk v3_bk; /* 0x4090 */ ++ volatile reg_v3_alpha v3_alpha; /* 0x4094 */ ++ volatile reg_v3_mute_bk v3_mute_bk; /* 0x4098 */ ++ volatile unsigned int reserved_51; /* 0x409c */ ++ volatile reg_v3_rimwidth v3_rimwidth; /* 0x40a0 */ ++ volatile reg_v3_rimcol0 v3_rimcol0; /* 0x40a4 */ ++ volatile reg_v3_rimcol1 v3_rimcol1; /* 0x40a8 */ ++ volatile unsigned int reserved_52[85]; /* 0x40ac~0x41fc 85 regs */ ++ volatile reg_v3_ot_pp_csc_ctrl v3_ot_pp_csc_ctrl; /* 0x4200 */ ++ volatile reg_v3_ot_pp_csc_coef00 v3_ot_pp_csc_coef00; /* 0x4204 */ ++ volatile reg_v3_ot_pp_csc_coef01 v3_ot_pp_csc_coef01; /* 0x4208 */ ++ volatile reg_v3_ot_pp_csc_coef02 v3_ot_pp_csc_coef02; /* 0x420c */ ++ volatile reg_v3_ot_pp_csc_coef10 v3_ot_pp_csc_coef10; /* 0x4210 */ ++ volatile reg_v3_ot_pp_csc_coef11 v3_ot_pp_csc_coef11; /* 0x4214 */ ++ volatile reg_v3_ot_pp_csc_coef12 v3_ot_pp_csc_coef12; /* 0x4218 */ ++ volatile reg_v3_ot_pp_csc_coef20 v3_ot_pp_csc_coef20; /* 0x421c */ ++ volatile reg_v3_ot_pp_csc_coef21 v3_ot_pp_csc_coef21; /* 0x4220 */ ++ volatile reg_v3_ot_pp_csc_coef22 v3_ot_pp_csc_coef22; /* 0x4224 */ ++ volatile reg_v3_ot_pp_csc_scale v3_ot_pp_csc_scale; /* 0x4228 */ ++ volatile reg_v3_ot_pp_csc_idc0 v3_ot_pp_csc_idc0; /* 0x422c */ ++ volatile reg_v3_ot_pp_csc_idc1 v3_ot_pp_csc_idc1; /* 0x4230 */ ++ volatile reg_v3_ot_pp_csc_idc2 v3_ot_pp_csc_idc2; /* 0x4234 */ ++ volatile reg_v3_ot_pp_csc_odc0 v3_ot_pp_csc_odc0; /* 0x4238 */ ++ volatile reg_v3_ot_pp_csc_odc1 v3_ot_pp_csc_odc1; /* 0x423c */ ++ volatile reg_v3_ot_pp_csc_odc2 v3_ot_pp_csc_odc2; /* 0x4240 */ ++ volatile reg_v3_ot_pp_csc_min_y v3_ot_pp_csc_min_y; /* 0x4244 */ ++ volatile reg_v3_ot_pp_csc_min_c v3_ot_pp_csc_min_c; /* 0x4248 */ ++ volatile reg_v3_ot_pp_csc_max_y v3_ot_pp_csc_max_y; /* 0x424c */ ++ volatile reg_v3_ot_pp_csc_max_c v3_ot_pp_csc_max_c; /* 0x4250 */ ++ volatile reg_v3_ot_pp_csc2_coef00 v3_ot_pp_csc2_coef00; /* 0x4254 */ ++ volatile reg_v3_ot_pp_csc2_coef01 v3_ot_pp_csc2_coef01; /* 0x4258 */ ++ volatile reg_v3_ot_pp_csc2_coef02 v3_ot_pp_csc2_coef02; /* 0x425c */ ++ volatile reg_v3_ot_pp_csc2_coef10 v3_ot_pp_csc2_coef10; /* 0x4260 */ ++ volatile reg_v3_ot_pp_csc2_coef11 v3_ot_pp_csc2_coef11; /* 0x4264 */ ++ volatile reg_v3_ot_pp_csc2_coef12 v3_ot_pp_csc2_coef12; /* 0x4268 */ ++ volatile reg_v3_ot_pp_csc2_coef20 v3_ot_pp_csc2_coef20; /* 0x426c */ ++ volatile reg_v3_ot_pp_csc2_coef21 v3_ot_pp_csc2_coef21; /* 0x4270 */ ++ volatile reg_v3_ot_pp_csc2_coef22 v3_ot_pp_csc2_coef22; /* 0x4274 */ ++ volatile reg_v3_ot_pp_csc2_scale v3_ot_pp_csc2_scale; /* 0x4278 */ ++ volatile reg_v3_ot_pp_csc2_idc0 v3_ot_pp_csc2_idc0; /* 0x427c */ ++ volatile reg_v3_ot_pp_csc2_idc1 v3_ot_pp_csc2_idc1; /* 0x4280 */ ++ volatile reg_v3_ot_pp_csc2_idc2 v3_ot_pp_csc2_idc2; /* 0x4284 */ ++ volatile reg_v3_ot_pp_csc2_odc0 v3_ot_pp_csc2_odc0; /* 0x4288 */ ++ volatile reg_v3_ot_pp_csc2_odc1 v3_ot_pp_csc2_odc1; /* 0x428c */ ++ volatile reg_v3_ot_pp_csc2_odc2 v3_ot_pp_csc2_odc2; /* 0x4290 */ ++ volatile reg_v3_ot_pp_csc2_min_y v3_ot_pp_csc2_min_y; /* 0x4294 */ ++ volatile reg_v3_ot_pp_csc2_min_c v3_ot_pp_csc2_min_c; /* 0x4298 */ ++ volatile reg_v3_ot_pp_csc2_max_y v3_ot_pp_csc2_max_y; /* 0x429c */ ++ volatile reg_v3_ot_pp_csc2_max_c v3_ot_pp_csc2_max_c; /* 0x42a0 */ ++ volatile unsigned int reserved_53[19]; /* 0x42a4~0x42ec 19 regs */ ++ volatile reg_v3_ot_pp_csc_ink_ctrl v3_ot_pp_csc_ink_ctrl; /* 0x42f0 */ ++ volatile reg_v3_ot_pp_csc_ink_pos v3_ot_pp_csc_ink_pos; /* 0x42f4 */ ++ volatile unsigned int v3_ot_pp_csc_ink_data; /* 0x42f8 */ ++ volatile unsigned int v3_ot_pp_csc_ink_data2; /* 0x42fc */ ++ volatile unsigned int reserved_54[64]; /* 0x4300~0x43fc 64 regs */ ++ volatile reg_v3_cvfir_vinfo v3_cvfir_vinfo; /* 0x4400 */ ++ volatile reg_v3_cvfir_vsp v3_cvfir_vsp; /* 0x4404 */ ++ volatile reg_v3_cvfir_voffset v3_cvfir_voffset; /* 0x4408 */ ++ volatile reg_v3_cvfir_vboffset v3_cvfir_vboffset; /* 0x440c */ ++ volatile unsigned int reserved_55[8]; /* 0x4410~0x442c 8 regs */ ++ volatile reg_v3_cvfir_vcoef0 v3_cvfir_vcoef0; /* 0x4430 */ ++ volatile reg_v3_cvfir_vcoef1 v3_cvfir_vcoef1; /* 0x4434 */ ++ volatile reg_v3_cvfir_vcoef2 v3_cvfir_vcoef2; /* 0x4438 */ ++ volatile unsigned int reserved_56[49]; /* 0x443c~0x44fc 49 regs */ ++ volatile reg_v3_hfir_ctrl v3_hfir_ctrl; /* 0x4500 */ ++ volatile reg_v3_hfircoef01 v3_hfircoef01; /* 0x4504 */ ++ volatile reg_v3_hfircoef23 v3_hfircoef23; /* 0x4508 */ ++ volatile reg_v3_hfircoef45 v3_hfircoef45; /* 0x450c */ ++ volatile reg_v3_hfircoef67 v3_hfircoef67; /* 0x4510 */ ++ volatile unsigned int reserved_57[1211]; /* 0x4514~0x57fc 1211 regs */ ++ volatile unsigned int vp0_ctrl; /* 0x5800 */ ++ volatile reg_vp0_upd vp0_upd; /* 0x5804 */ ++ volatile reg_vp0_ireso vp0_ireso; /* 0x5808 */ ++ volatile unsigned int reserved_58[29]; /* 0x580c~0x587c 29 regs */ ++ volatile reg_vp0_lbox_ctrl vp0_lbox_ctrl; /* 0x5880 */ ++ volatile reg_vp0_galpha vp0_galpha; /* 0x5884 */ ++ volatile reg_vp0_dfpos vp0_dfpos; /* 0x5888 */ ++ volatile reg_vp0_dlpos vp0_dlpos; /* 0x588c */ ++ volatile reg_vp0_vfpos vp0_vfpos; /* 0x5890 */ ++ volatile reg_vp0_vlpos vp0_vlpos; /* 0x5894 */ ++ volatile reg_vp0_bk vp0_bk; /* 0x5898 */ ++ volatile reg_vp0_alpha vp0_alpha; /* 0x589c */ ++ volatile reg_vp0_mute_bk vp0_mute_bk; /* 0x58a0 */ ++ volatile unsigned int reserved_59[1495]; /* 0x58a4~0x6ffc 1495 regs */ ++ volatile reg_g0_ctrl g0_ctrl; /* 0x7000 */ ++ volatile reg_g0_upd g0_upd; /* 0x7004 */ ++ volatile unsigned int g0_galpha_sum; /* 0x7008 */ ++ volatile reg_g0_0reso_read g0_0reso_read; /* 0x700c */ ++ volatile reg_g0_ireso g0_ireso; /* 0x7010 */ ++ volatile unsigned int reserved_60[27]; /* 0x7014~0x707c 27 regs */ ++ volatile reg_g0_dfpos g0_dfpos; /* 0x7080 */ ++ volatile reg_g0_dlpos g0_dlpos; /* 0x7084 */ ++ volatile reg_g0_vfpos g0_vfpos; /* 0x7088 */ ++ volatile reg_g0_vlpos g0_vlpos; /* 0x708c */ ++ volatile reg_g0_bk g0_bk; /* 0x7090 */ ++ volatile reg_g0_alpha g0_alpha; /* 0x7094 */ ++ volatile reg_g0_mute_bk g0_mute_bk; /* 0x7098 */ ++ volatile reg_g0_lbox_ctrl g0_lbox_ctrl; /* 0x709c */ ++ volatile unsigned int reserved_61[24]; /* 0x70a0~0x70fc 24 regs */ ++ volatile reg_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; /* 0x7100 */ ++ volatile reg_g0_ot_pp_csc_coef00 g0_ot_pp_csc_coef00; /* 0x7104 */ ++ volatile reg_g0_ot_pp_csc_coef01 g0_ot_pp_csc_coef01; /* 0x7108 */ ++ volatile reg_g0_ot_pp_csc_coef02 g0_ot_pp_csc_coef02; /* 0x710c */ ++ volatile reg_g0_ot_pp_csc_coef10 g0_ot_pp_csc_coef10; /* 0x7110 */ ++ volatile reg_g0_ot_pp_csc_coef11 g0_ot_pp_csc_coef11; /* 0x7114 */ ++ volatile reg_g0_ot_pp_csc_coef12 g0_ot_pp_csc_coef12; /* 0x7118 */ ++ volatile reg_g0_ot_pp_csc_coef20 g0_ot_pp_csc_coef20; /* 0x711c */ ++ volatile reg_g0_ot_pp_csc_coef21 g0_ot_pp_csc_coef21; /* 0x7120 */ ++ volatile reg_g0_ot_pp_csc_coef22 g0_ot_pp_csc_coef22; /* 0x7124 */ ++ volatile reg_g0_ot_pp_csc_scale g0_ot_pp_csc_scale; /* 0x7128 */ ++ volatile reg_g0_ot_pp_csc_idc0 g0_ot_pp_csc_idc0; /* 0x712c */ ++ volatile reg_g0_ot_pp_csc_idc1 g0_ot_pp_csc_idc1; /* 0x7130 */ ++ volatile reg_g0_ot_pp_csc_idc2 g0_ot_pp_csc_idc2; /* 0x7134 */ ++ volatile reg_g0_ot_pp_csc_odc0 g0_ot_pp_csc_odc0; /* 0x7138 */ ++ volatile reg_g0_ot_pp_csc_odc1 g0_ot_pp_csc_odc1; /* 0x713c */ ++ volatile reg_g0_ot_pp_csc_odc2 g0_ot_pp_csc_odc2; /* 0x7140 */ ++ volatile reg_g0_ot_pp_csc_min_y g0_ot_pp_csc_min_y; /* 0x7144 */ ++ volatile reg_g0_ot_pp_csc_min_c g0_ot_pp_csc_min_c; /* 0x7148 */ ++ volatile reg_g0_ot_pp_csc_max_y g0_ot_pp_csc_max_y; /* 0x714c */ ++ volatile reg_g0_ot_pp_csc_max_c g0_ot_pp_csc_max_c; /* 0x7150 */ ++ volatile reg_g0_ot_pp_csc2_coef00 g0_ot_pp_csc2_coef00; /* 0x7154 */ ++ volatile reg_g0_ot_pp_csc2_coef01 g0_ot_pp_csc2_coef01; /* 0x7158 */ ++ volatile reg_g0_ot_pp_csc2_coef02 g0_ot_pp_csc2_coef02; /* 0x715c */ ++ volatile reg_g0_ot_pp_csc2_coef10 g0_ot_pp_csc2_coef10; /* 0x7160 */ ++ volatile reg_g0_ot_pp_csc2_coef11 g0_ot_pp_csc2_coef11; /* 0x7164 */ ++ volatile reg_g0_ot_pp_csc2_coef12 g0_ot_pp_csc2_coef12; /* 0x7168 */ ++ volatile reg_g0_ot_pp_csc2_coef20 g0_ot_pp_csc2_coef20; /* 0x716c */ ++ volatile reg_g0_ot_pp_csc2_coef21 g0_ot_pp_csc2_coef21; /* 0x7170 */ ++ volatile reg_g0_ot_pp_csc2_coef22 g0_ot_pp_csc2_coef22; /* 0x7174 */ ++ volatile reg_g0_ot_pp_csc2_scale g0_ot_pp_csc2_scale; /* 0x7178 */ ++ volatile reg_g0_ot_pp_csc2_idc0 g0_ot_pp_csc2_idc0; /* 0x717c */ ++ volatile reg_g0_ot_pp_csc2_idc1 g0_ot_pp_csc2_idc1; /* 0x7180 */ ++ volatile reg_g0_ot_pp_csc2_idc2 g0_ot_pp_csc2_idc2; /* 0x7184 */ ++ volatile reg_g0_ot_pp_csc2_odc0 g0_ot_pp_csc2_odc0; /* 0x7188 */ ++ volatile reg_g0_ot_pp_csc2_odc1 g0_ot_pp_csc2_odc1; /* 0x718c */ ++ volatile reg_g0_ot_pp_csc2_odc2 g0_ot_pp_csc2_odc2; /* 0x7190 */ ++ volatile reg_g0_ot_pp_csc2_min_y g0_ot_pp_csc2_min_y; /* 0x7194 */ ++ volatile reg_g0_ot_pp_csc2_min_c g0_ot_pp_csc2_min_c; /* 0x7198 */ ++ volatile reg_g0_ot_pp_csc2_max_y g0_ot_pp_csc2_max_y; /* 0x719c */ ++ volatile reg_g0_ot_pp_csc2_max_c g0_ot_pp_csc2_max_c; /* 0x71a0 */ ++ volatile unsigned int reserved_62[19]; /* 0x71a4~0x71ec 19 regs */ ++ volatile reg_g0_ot_pp_csc_ink_ctrl g0_ot_pp_csc_ink_ctrl; /* 0x71f0 */ ++ volatile reg_g0_ot_pp_csc_ink_pos g0_ot_pp_csc_ink_pos; /* 0x71f4 */ ++ volatile unsigned int g0_ot_pp_csc_ink_data; /* 0x71f8 */ ++ volatile unsigned int g0_ot_pp_csc_ink_data2; /* 0x71fc */ ++ volatile reg_osb_mute_bk osb_mute_bk; /* 0x7200 */ ++ volatile reg_osb_bk_alpha osb_bk_alpha; /* 0x7204 */ ++ volatile reg_osb_coef_rd_en osb_coef_rd_en; /* 0x7208 */ ++ volatile unsigned int osb_coef_rd_addr; /* 0x720c */ ++ volatile unsigned int reserved_63[60]; /* 0x7210~0x72fc 60 regs */ ++ volatile reg_g0_zme_hinfo g0_zme_hinfo; /* 0x7300 */ ++ volatile reg_g0_zme_hsp g0_zme_hsp; /* 0x7304 */ ++ volatile reg_g0_zme_hloffset g0_zme_hloffset; /* 0x7308 */ ++ volatile reg_g0_zme_hcoffset g0_zme_hcoffset; /* 0x730c */ ++ volatile unsigned int reserved_64[5]; /* 0x7310~0x7320 5 regs */ ++ volatile reg_g0_zme_coef_ren g0_zme_coef_ren; /* 0x7324 */ ++ volatile reg_g0_zme_coef_rdata g0_zme_coef_rdata; /* 0x7328 */ ++ volatile unsigned int reserved_65[21]; /* 0x732c~0x737c 21 regs */ ++ volatile reg_g0_zme_vinfo g0_zme_vinfo; /* 0x7380 */ ++ volatile reg_g0_zme_vsp g0_zme_vsp; /* 0x7384 */ ++ volatile reg_g0_zme_voffset g0_zme_voffset; /* 0x7388 */ ++ volatile unsigned int reserved_66[285]; /* 0x738c~0x77fc 285 regs */ ++ volatile reg_g1_ctrl g1_ctrl; /* 0x7800 */ ++ volatile reg_g1_upd g1_upd; /* 0x7804 */ ++ volatile unsigned int g1_galpha_sum; /* 0x7808 */ ++ volatile reg_g1_0reso_read g1_0reso_read; /* 0x780c */ ++ volatile reg_g1_ireso g1_ireso; /* 0x7810 */ ++ volatile unsigned int reserved_67[27]; /* 0x7814~0x787c 27 regs */ ++ volatile reg_g1_dfpos g1_dfpos; /* 0x7880 */ ++ volatile reg_g1_dlpos g1_dlpos; /* 0x7884 */ ++ volatile reg_g1_vfpos g1_vfpos; /* 0x7888 */ ++ volatile reg_g1_vlpos g1_vlpos; /* 0x788c */ ++ volatile reg_g1_bk g1_bk; /* 0x7890 */ ++ volatile reg_g1_alpha g1_alpha; /* 0x7894 */ ++ volatile reg_g1_mute_bk g1_mute_bk; /* 0x7898 */ ++ volatile reg_g1_lbox_ctrl g1_lbox_ctrl; /* 0x789c */ ++ volatile unsigned int reserved_68[24]; /* 0x78a0~0x78fc 24 regs */ ++ volatile reg_g1_ot_pp_csc_ctrl g1_ot_pp_csc_ctrl; /* 0x7900 */ ++ volatile reg_g1_ot_pp_csc_coef00 g1_ot_pp_csc_coef00; /* 0x7904 */ ++ volatile reg_g1_ot_pp_csc_coef01 g1_ot_pp_csc_coef01; /* 0x7908 */ ++ volatile reg_g1_ot_pp_csc_coef02 g1_ot_pp_csc_coef02; /* 0x790c */ ++ volatile reg_g1_ot_pp_csc_coef10 g1_ot_pp_csc_coef10; /* 0x7910 */ ++ volatile reg_g1_ot_pp_csc_coef11 g1_ot_pp_csc_coef11; /* 0x7914 */ ++ volatile reg_g1_ot_pp_csc_coef12 g1_ot_pp_csc_coef12; /* 0x7918 */ ++ volatile reg_g1_ot_pp_csc_coef20 g1_ot_pp_csc_coef20; /* 0x791c */ ++ volatile reg_g1_ot_pp_csc_coef21 g1_ot_pp_csc_coef21; /* 0x7920 */ ++ volatile reg_g1_ot_pp_csc_coef22 g1_ot_pp_csc_coef22; /* 0x7924 */ ++ volatile reg_g1_ot_pp_csc_scale g1_ot_pp_csc_scale; /* 0x7928 */ ++ volatile reg_g1_ot_pp_csc_idc0 g1_ot_pp_csc_idc0; /* 0x792c */ ++ volatile reg_g1_ot_pp_csc_idc1 g1_ot_pp_csc_idc1; /* 0x7930 */ ++ volatile reg_g1_ot_pp_csc_idc2 g1_ot_pp_csc_idc2; /* 0x7934 */ ++ volatile reg_g1_ot_pp_csc_odc0 g1_ot_pp_csc_odc0; /* 0x7938 */ ++ volatile reg_g1_ot_pp_csc_odc1 g1_ot_pp_csc_odc1; /* 0x793c */ ++ volatile reg_g1_ot_pp_csc_odc2 g1_ot_pp_csc_odc2; /* 0x7940 */ ++ volatile reg_g1_ot_pp_csc_min_y g1_ot_pp_csc_min_y; /* 0x7944 */ ++ volatile reg_g1_ot_pp_csc_min_c g1_ot_pp_csc_min_c; /* 0x7948 */ ++ volatile reg_g1_ot_pp_csc_max_y g1_ot_pp_csc_max_y; /* 0x794c */ ++ volatile reg_g1_ot_pp_csc_max_c g1_ot_pp_csc_max_c; /* 0x7950 */ ++ volatile reg_g1_ot_pp_csc2_coef00 g1_ot_pp_csc2_coef00; /* 0x7954 */ ++ volatile reg_g1_ot_pp_csc2_coef01 g1_ot_pp_csc2_coef01; /* 0x7958 */ ++ volatile reg_g1_ot_pp_csc2_coef02 g1_ot_pp_csc2_coef02; /* 0x795c */ ++ volatile reg_g1_ot_pp_csc2_coef10 g1_ot_pp_csc2_coef10; /* 0x7960 */ ++ volatile reg_g1_ot_pp_csc2_coef11 g1_ot_pp_csc2_coef11; /* 0x7964 */ ++ volatile reg_g1_ot_pp_csc2_coef12 g1_ot_pp_csc2_coef12; /* 0x7968 */ ++ volatile reg_g1_ot_pp_csc2_coef20 g1_ot_pp_csc2_coef20; /* 0x796c */ ++ volatile reg_g1_ot_pp_csc2_coef21 g1_ot_pp_csc2_coef21; /* 0x7970 */ ++ volatile reg_g1_ot_pp_csc2_coef22 g1_ot_pp_csc2_coef22; /* 0x7974 */ ++ volatile reg_g1_ot_pp_csc2_scale g1_ot_pp_csc2_scale; /* 0x7978 */ ++ volatile reg_g1_ot_pp_csc2_idc0 g1_ot_pp_csc2_idc0; /* 0x797c */ ++ volatile reg_g1_ot_pp_csc2_idc1 g1_ot_pp_csc2_idc1; /* 0x7980 */ ++ volatile reg_g1_ot_pp_csc2_idc2 g1_ot_pp_csc2_idc2; /* 0x7984 */ ++ volatile reg_g1_ot_pp_csc2_odc0 g1_ot_pp_csc2_odc0; /* 0x7988 */ ++ volatile reg_g1_ot_pp_csc2_odc1 g1_ot_pp_csc2_odc1; /* 0x798c */ ++ volatile reg_g1_ot_pp_csc2_odc2 g1_ot_pp_csc2_odc2; /* 0x7990 */ ++ volatile reg_g1_ot_pp_csc2_min_y g1_ot_pp_csc2_min_y; /* 0x7994 */ ++ volatile reg_g1_ot_pp_csc2_min_c g1_ot_pp_csc2_min_c; /* 0x7998 */ ++ volatile reg_g1_ot_pp_csc2_max_y g1_ot_pp_csc2_max_y; /* 0x799c */ ++ volatile reg_g1_ot_pp_csc2_max_c g1_ot_pp_csc2_max_c; /* 0x79a0 */ ++ volatile unsigned int reserved_69[19]; /* 0x79a4~0x79ec 19 regs */ ++ volatile reg_g1_ot_pp_csc_ink_ctrl g1_ot_pp_csc_ink_ctrl; /* 0x79f0 */ ++ volatile reg_g1_ot_pp_csc_ink_pos g1_ot_pp_csc_ink_pos; /* 0x79f4 */ ++ volatile unsigned int g1_ot_pp_csc_ink_data; /* 0x79f8 */ ++ volatile unsigned int g1_ot_pp_csc_ink_data2; /* 0x79fc */ ++ volatile reg_g1_osb_mute_bk g1_osb_mute_bk; /* 0x7a00 */ ++ volatile reg_g1_osb_bk_alpha g1_osb_bk_alpha; /* 0x7a04 */ ++ volatile reg_g1_osb_coef_rd_en g1_osb_coef_rd_en; /* 0x7a08 */ ++ volatile unsigned int g1_osb_coef_rd_addr; /* 0x7a0c */ ++ volatile unsigned int reserved_70[60]; /* 0x7a10~0x7afc 60 regs */ ++ volatile reg_g1_zme_hinfo g1_zme_hinfo; /* 0x7b00 */ ++ volatile reg_g1_zme_hsp g1_zme_hsp; /* 0x7b04 */ ++ volatile reg_g1_zme_hloffset g1_zme_hloffset; /* 0x7b08 */ ++ volatile reg_g1_zme_hcoffset g1_zme_hcoffset; /* 0x7b0c */ ++ volatile unsigned int reserved_71[5]; /* 0x7b10~0x7b20 5 regs */ ++ volatile reg_g1_zme_coef_ren g1_zme_coef_ren; /* 0x7b24 */ ++ volatile reg_g1_zme_coef_rdata g1_zme_coef_rdata; /* 0x7b28 */ ++ volatile unsigned int reserved_72[21]; /* 0x7b2c~0x7b7c 21 regs */ ++ volatile reg_g1_zme_vinfo g1_zme_vinfo; /* 0x7b80 */ ++ volatile reg_g1_zme_vsp g1_zme_vsp; /* 0x7b84 */ ++ volatile reg_g1_zme_voffset g1_zme_voffset; /* 0x7b88 */ ++ volatile unsigned int reserved_73[285]; /* 0x7b8c~0x7ffc 285 regs */ ++ volatile reg_g2_ctrl g2_ctrl; /* 0x8000 */ ++ volatile reg_g2_upd g2_upd; /* 0x8004 */ ++ volatile unsigned int g2_galpha_sum; /* 0x8008 */ ++ volatile reg_g2_0reso_read g2_0reso_read; /* 0x800c */ ++ volatile reg_g2_ireso g2_ireso; /* 0x8010 */ ++ volatile unsigned int reserved_74[27]; /* 0x8014~0x807c 27 regs */ ++ volatile reg_g2_dfpos g2_dfpos; /* 0x8080 */ ++ volatile reg_g2_dlpos g2_dlpos; /* 0x8084 */ ++ volatile reg_g2_vfpos g2_vfpos; /* 0x8088 */ ++ volatile reg_g2_vlpos g2_vlpos; /* 0x808c */ ++ volatile reg_g2_bk g2_bk; /* 0x8090 */ ++ volatile reg_g2_alpha g2_alpha; /* 0x8094 */ ++ volatile reg_g2_mute_bk g2_mute_bk; /* 0x8098 */ ++ volatile reg_g2_lbox_ctrl g2_lbox_ctrl; /* 0x809c */ ++ volatile unsigned int reserved_75[24]; /* 0x80a0~0x80fc 24 regs */ ++ volatile reg_g2_ot_pp_csc_ctrl g2_ot_pp_csc_ctrl; /* 0x8100 */ ++ volatile reg_g2_ot_pp_csc_coef00 g2_ot_pp_csc_coef00; /* 0x8104 */ ++ volatile reg_g2_ot_pp_csc_coef01 g2_ot_pp_csc_coef01; /* 0x8108 */ ++ volatile reg_g2_ot_pp_csc_coef02 g2_ot_pp_csc_coef02; /* 0x810c */ ++ volatile reg_g2_ot_pp_csc_coef10 g2_ot_pp_csc_coef10; /* 0x8110 */ ++ volatile reg_g2_ot_pp_csc_coef11 g2_ot_pp_csc_coef11; /* 0x8114 */ ++ volatile reg_g2_ot_pp_csc_coef12 g2_ot_pp_csc_coef12; /* 0x8118 */ ++ volatile reg_g2_ot_pp_csc_coef20 g2_ot_pp_csc_coef20; /* 0x811c */ ++ volatile reg_g2_ot_pp_csc_coef21 g2_ot_pp_csc_coef21; /* 0x8120 */ ++ volatile reg_g2_ot_pp_csc_coef22 g2_ot_pp_csc_coef22; /* 0x8124 */ ++ volatile reg_g2_ot_pp_csc_scale g2_ot_pp_csc_scale; /* 0x8128 */ ++ volatile reg_g2_ot_pp_csc_idc0 g2_ot_pp_csc_idc0; /* 0x812c */ ++ volatile reg_g2_ot_pp_csc_idc1 g2_ot_pp_csc_idc1; /* 0x8130 */ ++ volatile reg_g2_ot_pp_csc_idc2 g2_ot_pp_csc_idc2; /* 0x8134 */ ++ volatile reg_g2_ot_pp_csc_odc0 g2_ot_pp_csc_odc0; /* 0x8138 */ ++ volatile reg_g2_ot_pp_csc_odc1 g2_ot_pp_csc_odc1; /* 0x813c */ ++ volatile reg_g2_ot_pp_csc_odc2 g2_ot_pp_csc_odc2; /* 0x8140 */ ++ volatile reg_g2_ot_pp_csc_min_y g2_ot_pp_csc_min_y; /* 0x8144 */ ++ volatile reg_g2_ot_pp_csc_min_c g2_ot_pp_csc_min_c; /* 0x8148 */ ++ volatile reg_g2_ot_pp_csc_max_y g2_ot_pp_csc_max_y; /* 0x814c */ ++ volatile reg_g2_ot_pp_csc_max_c g2_ot_pp_csc_max_c; /* 0x8150 */ ++ volatile reg_g2_ot_pp_csc2_coef00 g2_ot_pp_csc2_coef00; /* 0x8154 */ ++ volatile reg_g2_ot_pp_csc2_coef01 g2_ot_pp_csc2_coef01; /* 0x8158 */ ++ volatile reg_g2_ot_pp_csc2_coef02 g2_ot_pp_csc2_coef02; /* 0x815c */ ++ volatile reg_g2_ot_pp_csc2_coef10 g2_ot_pp_csc2_coef10; /* 0x8160 */ ++ volatile reg_g2_ot_pp_csc2_coef11 g2_ot_pp_csc2_coef11; /* 0x8164 */ ++ volatile reg_g2_ot_pp_csc2_coef12 g2_ot_pp_csc2_coef12; /* 0x8168 */ ++ volatile reg_g2_ot_pp_csc2_coef20 g2_ot_pp_csc2_coef20; /* 0x816c */ ++ volatile reg_g2_ot_pp_csc2_coef21 g2_ot_pp_csc2_coef21; /* 0x8170 */ ++ volatile reg_g2_ot_pp_csc2_coef22 g2_ot_pp_csc2_coef22; /* 0x8174 */ ++ volatile reg_g2_ot_pp_csc2_scale g2_ot_pp_csc2_scale; /* 0x8178 */ ++ volatile reg_g2_ot_pp_csc2_idc0 g2_ot_pp_csc2_idc0; /* 0x817c */ ++ volatile reg_g2_ot_pp_csc2_idc1 g2_ot_pp_csc2_idc1; /* 0x8180 */ ++ volatile reg_g2_ot_pp_csc2_idc2 g2_ot_pp_csc2_idc2; /* 0x8184 */ ++ volatile reg_g2_ot_pp_csc2_odc0 g2_ot_pp_csc2_odc0; /* 0x8188 */ ++ volatile reg_g2_ot_pp_csc2_odc1 g2_ot_pp_csc2_odc1; /* 0x818c */ ++ volatile reg_g2_ot_pp_csc2_odc2 g2_ot_pp_csc2_odc2; /* 0x8190 */ ++ volatile reg_g2_ot_pp_csc2_min_y g2_ot_pp_csc2_min_y; /* 0x8194 */ ++ volatile reg_g2_ot_pp_csc2_min_c g2_ot_pp_csc2_min_c; /* 0x8198 */ ++ volatile reg_g2_ot_pp_csc2_max_y g2_ot_pp_csc2_max_y; /* 0x819c */ ++ volatile reg_g2_ot_pp_csc2_max_c g2_ot_pp_csc2_max_c; /* 0x81a0 */ ++ volatile unsigned int reserved_76[19]; /* 0x81a4~0x81ec 19 regs */ ++ volatile reg_g2_ot_pp_csc_ink_ctrl g2_ot_pp_csc_ink_ctrl; /* 0x81f0 */ ++ volatile reg_g2_ot_pp_csc_ink_pos g2_ot_pp_csc_ink_pos; /* 0x81f4 */ ++ volatile unsigned int g2_ot_pp_csc_ink_data; /* 0x81f8 */ ++ volatile unsigned int g2_ot_pp_csc_ink_data2; /* 0x81fc */ ++ volatile unsigned int reserved_77[384]; /* 0x8200~0x87fc 384 regs */ ++ volatile reg_g3_ctrl g3_ctrl; /* 0x8800 */ ++ volatile reg_g3_upd g3_upd; /* 0x8804 */ ++ volatile unsigned int g3_galpha_sum; /* 0x8808 */ ++ volatile reg_g3_0reso_read g3_0reso_read; /* 0x880c */ ++ volatile reg_g3_ireso g3_ireso; /* 0x8810 */ ++ volatile unsigned int reserved_78[27]; /* 0x8814~0x887c 27 regs */ ++ volatile reg_g3_dfpos g3_dfpos; /* 0x8880 */ ++ volatile reg_g3_dlpos g3_dlpos; /* 0x8884 */ ++ volatile reg_g3_vfpos g3_vfpos; /* 0x8888 */ ++ volatile reg_g3_vlpos g3_vlpos; /* 0x888c */ ++ volatile reg_g3_bk g3_bk; /* 0x8890 */ ++ volatile reg_g3_alpha g3_alpha; /* 0x8894 */ ++ volatile reg_g3_mute_bk g3_mute_bk; /* 0x8898 */ ++ volatile reg_g3_lbox_ctrl g3_lbox_ctrl; /* 0x889c */ ++ volatile unsigned int reserved_79[24]; /* 0x88a0~0x88fc 24 regs */ ++ volatile reg_g3_ot_pp_csc_ctrl g3_ot_pp_csc_ctrl; /* 0x8900 */ ++ volatile reg_g3_ot_pp_csc_coef00 g3_ot_pp_csc_coef00; /* 0x8904 */ ++ volatile reg_g3_ot_pp_csc_coef01 g3_ot_pp_csc_coef01; /* 0x8908 */ ++ volatile reg_g3_ot_pp_csc_coef02 g3_ot_pp_csc_coef02; /* 0x890c */ ++ volatile reg_g3_ot_pp_csc_coef10 g3_ot_pp_csc_coef10; /* 0x8910 */ ++ volatile reg_g3_ot_pp_csc_coef11 g3_ot_pp_csc_coef11; /* 0x8914 */ ++ volatile reg_g3_ot_pp_csc_coef12 g3_ot_pp_csc_coef12; /* 0x8918 */ ++ volatile reg_g3_ot_pp_csc_coef20 g3_ot_pp_csc_coef20; /* 0x891c */ ++ volatile reg_g3_ot_pp_csc_coef21 g3_ot_pp_csc_coef21; /* 0x8920 */ ++ volatile reg_g3_ot_pp_csc_coef22 g3_ot_pp_csc_coef22; /* 0x8924 */ ++ volatile reg_g3_ot_pp_csc_scale g3_ot_pp_csc_scale; /* 0x8928 */ ++ volatile reg_g3_ot_pp_csc_idc0 g3_ot_pp_csc_idc0; /* 0x892c */ ++ volatile reg_g3_ot_pp_csc_idc1 g3_ot_pp_csc_idc1; /* 0x8930 */ ++ volatile reg_g3_ot_pp_csc_idc2 g3_ot_pp_csc_idc2; /* 0x8934 */ ++ volatile reg_g3_ot_pp_csc_odc0 g3_ot_pp_csc_odc0; /* 0x8938 */ ++ volatile reg_g3_ot_pp_csc_odc1 g3_ot_pp_csc_odc1; /* 0x893c */ ++ volatile reg_g3_ot_pp_csc_odc2 g3_ot_pp_csc_odc2; /* 0x8940 */ ++ volatile reg_g3_ot_pp_csc_min_y g3_ot_pp_csc_min_y; /* 0x8944 */ ++ volatile reg_g3_ot_pp_csc_min_c g3_ot_pp_csc_min_c; /* 0x8948 */ ++ volatile reg_g3_ot_pp_csc_max_y g3_ot_pp_csc_max_y; /* 0x894c */ ++ volatile reg_g3_ot_pp_csc_max_c g3_ot_pp_csc_max_c; /* 0x8950 */ ++ volatile reg_g3_ot_pp_csc2_coef00 g3_ot_pp_csc2_coef00; /* 0x8954 */ ++ volatile reg_g3_ot_pp_csc2_coef01 g3_ot_pp_csc2_coef01; /* 0x8958 */ ++ volatile reg_g3_ot_pp_csc2_coef02 g3_ot_pp_csc2_coef02; /* 0x895c */ ++ volatile reg_g3_ot_pp_csc2_coef10 g3_ot_pp_csc2_coef10; /* 0x8960 */ ++ volatile reg_g3_ot_pp_csc2_coef11 g3_ot_pp_csc2_coef11; /* 0x8964 */ ++ volatile reg_g3_ot_pp_csc2_coef12 g3_ot_pp_csc2_coef12; /* 0x8968 */ ++ volatile reg_g3_ot_pp_csc2_coef20 g3_ot_pp_csc2_coef20; /* 0x896c */ ++ volatile reg_g3_ot_pp_csc2_coef21 g3_ot_pp_csc2_coef21; /* 0x8970 */ ++ volatile reg_g3_ot_pp_csc2_coef22 g3_ot_pp_csc2_coef22; /* 0x8974 */ ++ volatile reg_g3_ot_pp_csc2_scale g3_ot_pp_csc2_scale; /* 0x8978 */ ++ volatile reg_g3_ot_pp_csc2_idc0 g3_ot_pp_csc2_idc0; /* 0x897c */ ++ volatile reg_g3_ot_pp_csc2_idc1 g3_ot_pp_csc2_idc1; /* 0x8980 */ ++ volatile reg_g3_ot_pp_csc2_idc2 g3_ot_pp_csc2_idc2; /* 0x8984 */ ++ volatile reg_g3_ot_pp_csc2_odc0 g3_ot_pp_csc2_odc0; /* 0x8988 */ ++ volatile reg_g3_ot_pp_csc2_odc1 g3_ot_pp_csc2_odc1; /* 0x898c */ ++ volatile reg_g3_ot_pp_csc2_odc2 g3_ot_pp_csc2_odc2; /* 0x8990 */ ++ volatile reg_g3_ot_pp_csc2_min_y g3_ot_pp_csc2_min_y; /* 0x8994 */ ++ volatile reg_g3_ot_pp_csc2_min_c g3_ot_pp_csc2_min_c; /* 0x8998 */ ++ volatile reg_g3_ot_pp_csc2_max_y g3_ot_pp_csc2_max_y; /* 0x899c */ ++ volatile reg_g3_ot_pp_csc2_max_c g3_ot_pp_csc2_max_c; /* 0x89a0 */ ++ volatile unsigned int reserved_80[19]; /* 0x89a4~0x89ec 19 regs */ ++ volatile reg_g3_ot_pp_csc_ink_ctrl g3_ot_pp_csc_ink_ctrl; /* 0x89f0 */ ++ volatile reg_g3_ot_pp_csc_ink_pos g3_ot_pp_csc_ink_pos; /* 0x89f4 */ ++ volatile unsigned int g3_ot_pp_csc_ink_data; /* 0x89f8 */ ++ volatile unsigned int g3_ot_pp_csc_ink_data2; /* 0x89fc */ ++ volatile reg_g3_osb_mute_bk g3_osb_mute_bk; /* 0x8a00 */ ++ volatile reg_g3_osb_bk_alpha g3_osb_bk_alpha; /* 0x8a04 */ ++ volatile reg_g3_osb_coef_rd_en g3_osb_coef_rd_en; /* 0x8a08 */ ++ volatile unsigned int g3_osb_coef_rd_addr; /* 0x8a0c */ ++ volatile unsigned int reserved_81[380]; /* 0x8a10~0x8ffc 380 regs */ ++ volatile reg_g4_ctrl g4_ctrl; /* 0x9000 */ ++ volatile reg_g4_upd g4_upd; /* 0x9004 */ ++ volatile unsigned int g4_galpha_sum; /* 0x9008 */ ++ volatile reg_g4_0reso_read g4_0reso_read; /* 0x900c */ ++ volatile reg_g4_ireso g4_ireso; /* 0x9010 */ ++ volatile unsigned int reserved_82[27]; /* 0x9014~0x907c 27 regs */ ++ volatile reg_g4_dfpos g4_dfpos; /* 0x9080 */ ++ volatile reg_g4_dlpos g4_dlpos; /* 0x9084 */ ++ volatile reg_g4_vfpos g4_vfpos; /* 0x9088 */ ++ volatile reg_g4_vlpos g4_vlpos; /* 0x908c */ ++ volatile reg_g4_bk g4_bk; /* 0x9090 */ ++ volatile reg_g4_alpha g4_alpha; /* 0x9094 */ ++ volatile reg_g4_mute_bk g4_mute_bk; /* 0x9098 */ ++ volatile reg_g4_lbox_ctrl g4_lbox_ctrl; /* 0x909c */ ++ volatile unsigned int reserved_83[24]; /* 0x90a0~0x90fc 24 regs */ ++ volatile reg_g4_ot_pp_csc_ctrl g4_ot_pp_csc_ctrl; /* 0x9100 */ ++ volatile reg_g4_ot_pp_csc_coef00 g4_ot_pp_csc_coef00; /* 0x9104 */ ++ volatile reg_g4_ot_pp_csc_coef01 g4_ot_pp_csc_coef01; /* 0x9108 */ ++ volatile reg_g4_ot_pp_csc_coef02 g4_ot_pp_csc_coef02; /* 0x910c */ ++ volatile reg_g4_ot_pp_csc_coef10 g4_ot_pp_csc_coef10; /* 0x9110 */ ++ volatile reg_g4_ot_pp_csc_coef11 g4_ot_pp_csc_coef11; /* 0x9114 */ ++ volatile reg_g4_ot_pp_csc_coef12 g4_ot_pp_csc_coef12; /* 0x9118 */ ++ volatile reg_g4_ot_pp_csc_coef20 g4_ot_pp_csc_coef20; /* 0x911c */ ++ volatile reg_g4_ot_pp_csc_coef21 g4_ot_pp_csc_coef21; /* 0x9120 */ ++ volatile reg_g4_ot_pp_csc_coef22 g4_ot_pp_csc_coef22; /* 0x9124 */ ++ volatile reg_g4_ot_pp_csc_scale g4_ot_pp_csc_scale; /* 0x9128 */ ++ volatile reg_g4_ot_pp_csc_idc0 g4_ot_pp_csc_idc0; /* 0x912c */ ++ volatile reg_g4_ot_pp_csc_idc1 g4_ot_pp_csc_idc1; /* 0x9130 */ ++ volatile reg_g4_ot_pp_csc_idc2 g4_ot_pp_csc_idc2; /* 0x9134 */ ++ volatile reg_g4_ot_pp_csc_odc0 g4_ot_pp_csc_odc0; /* 0x9138 */ ++ volatile reg_g4_ot_pp_csc_odc1 g4_ot_pp_csc_odc1; /* 0x913c */ ++ volatile reg_g4_ot_pp_csc_odc2 g4_ot_pp_csc_odc2; /* 0x9140 */ ++ volatile reg_g4_ot_pp_csc_min_y g4_ot_pp_csc_min_y; /* 0x9144 */ ++ volatile reg_g4_ot_pp_csc_min_c g4_ot_pp_csc_min_c; /* 0x9148 */ ++ volatile reg_g4_ot_pp_csc_max_y g4_ot_pp_csc_max_y; /* 0x914c */ ++ volatile reg_g4_ot_pp_csc_max_c g4_ot_pp_csc_max_c; /* 0x9150 */ ++ volatile reg_g4_ot_pp_csc2_coef00 g4_ot_pp_csc2_coef00; /* 0x9154 */ ++ volatile reg_g4_ot_pp_csc2_coef01 g4_ot_pp_csc2_coef01; /* 0x9158 */ ++ volatile reg_g4_ot_pp_csc2_coef02 g4_ot_pp_csc2_coef02; /* 0x915c */ ++ volatile reg_g4_ot_pp_csc2_coef10 g4_ot_pp_csc2_coef10; /* 0x9160 */ ++ volatile reg_g4_ot_pp_csc2_coef11 g4_ot_pp_csc2_coef11; /* 0x9164 */ ++ volatile reg_g4_ot_pp_csc2_coef12 g4_ot_pp_csc2_coef12; /* 0x9168 */ ++ volatile reg_g4_ot_pp_csc2_coef20 g4_ot_pp_csc2_coef20; /* 0x916c */ ++ volatile reg_g4_ot_pp_csc2_coef21 g4_ot_pp_csc2_coef21; /* 0x9170 */ ++ volatile reg_g4_ot_pp_csc2_coef22 g4_ot_pp_csc2_coef22; /* 0x9174 */ ++ volatile reg_g4_ot_pp_csc2_scale g4_ot_pp_csc2_scale; /* 0x9178 */ ++ volatile reg_g4_ot_pp_csc2_idc0 g4_ot_pp_csc2_idc0; /* 0x917c */ ++ volatile reg_g4_ot_pp_csc2_idc1 g4_ot_pp_csc2_idc1; /* 0x9180 */ ++ volatile reg_g4_ot_pp_csc2_idc2 g4_ot_pp_csc2_idc2; /* 0x9184 */ ++ volatile reg_g4_ot_pp_csc2_odc0 g4_ot_pp_csc2_odc0; /* 0x9188 */ ++ volatile reg_g4_ot_pp_csc2_odc1 g4_ot_pp_csc2_odc1; /* 0x918c */ ++ volatile reg_g4_ot_pp_csc2_odc2 g4_ot_pp_csc2_odc2; /* 0x9190 */ ++ volatile reg_g4_ot_pp_csc2_min_y g4_ot_pp_csc2_min_y; /* 0x9194 */ ++ volatile reg_g4_ot_pp_csc2_min_c g4_ot_pp_csc2_min_c; /* 0x9198 */ ++ volatile reg_g4_ot_pp_csc2_max_y g4_ot_pp_csc2_max_y; /* 0x919c */ ++ volatile reg_g4_ot_pp_csc2_max_c g4_ot_pp_csc2_max_c; /* 0x91a0 */ ++ volatile unsigned int reserved_84[19]; /* 0x91a4~0x91ec 19 regs */ ++ volatile reg_g4_ot_pp_csc_ink_ctrl g4_ot_pp_csc_ink_ctrl; /* 0x91f0 */ ++ volatile reg_g4_ot_pp_csc_ink_pos g4_ot_pp_csc_ink_pos; /* 0x91f4 */ ++ volatile unsigned int g4_ot_pp_csc_ink_data; /* 0x91f8 */ ++ volatile unsigned int g4_ot_pp_csc_ink_data2; /* 0x91fc */ ++ volatile reg_g4_osb_mute_bk g4_osb_mute_bk; /* 0x9200 */ ++ volatile reg_g4_osb_bk_alpha g4_osb_bk_alpha; /* 0x9204 */ ++ volatile reg_g4_osb_coef_rd_en g4_osb_coef_rd_en; /* 0x9208 */ ++ volatile unsigned int g4_osb_coef_rd_addr; /* 0x920c */ ++ volatile unsigned int reserved_85[380]; /* 0x9210~0x97fc 380 regs */ ++ volatile unsigned int gp0_ctrl; /* 0x9800 */ ++ volatile reg_gp0_upd gp0_upd; /* 0x9804 */ ++ volatile reg_gp0_ireso gp0_ireso; /* 0x9808 */ ++ volatile unsigned int reserved_86[29]; /* 0x980c~0x987c 29 regs */ ++ volatile reg_gp0_lbox_ctrl gp0_lbox_ctrl; /* 0x9880 */ ++ volatile reg_gp0_galpha gp0_galpha; /* 0x9884 */ ++ volatile unsigned int gp0_galpha_sum; /* 0x9888 */ ++ volatile reg_gp0_dfpos gp0_dfpos; /* 0x988c */ ++ volatile reg_gp0_dlpos gp0_dlpos; /* 0x9890 */ ++ volatile reg_gp0_vfpos gp0_vfpos; /* 0x9894 */ ++ volatile reg_gp0_vlpos gp0_vlpos; /* 0x9898 */ ++ volatile reg_gp0_bk gp0_bk; /* 0x989c */ ++ volatile reg_gp0_alpha gp0_alpha; /* 0x98a0 */ ++ volatile reg_gp0_mute_bk gp0_mute_bk; /* 0x98a4 */ ++ volatile unsigned int reserved_87[22]; /* 0x98a8~0x98fc 22 regs */ ++ volatile reg_gp0_csc_idc gp0_csc_idc; /* 0x9900 */ ++ volatile reg_gp0_csc_odc gp0_csc_odc; /* 0x9904 */ ++ volatile reg_gp0_csc_iodc gp0_csc_iodc; /* 0x9908 */ ++ volatile reg_gp0_csc_p0 gp0_csc_p0; /* 0x990c */ ++ volatile reg_gp0_csc_p1 gp0_csc_p1; /* 0x9910 */ ++ volatile reg_gp0_csc_p2 gp0_csc_p2; /* 0x9914 */ ++ volatile reg_gp0_csc_p3 gp0_csc_p3; /* 0x9918 */ ++ volatile reg_gp0_csc_p4 gp0_csc_p4; /* 0x991c */ ++ volatile unsigned int reserved_88[1464]; /* 0x9920~0xaffc 1464 regs */ ++ volatile reg_wbc_g0_ctrl wbc_g0_ctrl; /* 0xb000 */ ++ volatile reg_wbc_g0_upd wbc_g0_upd; /* 0xb004 */ ++ volatile reg_wbc_g0_cmp wbc_g0_cmp; /* 0xb008 */ ++ volatile unsigned int reserved_89; /* 0xb00c */ ++ volatile unsigned int wbc_g0_ar_addr; /* 0xb010 */ ++ volatile unsigned int wbc_g0_gb_addr; /* 0xb014 */ ++ volatile reg_wbc_g0_stride wbc_g0_stride; /* 0xb018 */ ++ volatile unsigned int wbc_g0_offset; /* 0xb01c */ ++ volatile reg_wbc_g0_oreso wbc_g0_oreso; /* 0xb020 */ ++ volatile reg_wbc_g0_fcrop wbc_g0_fcrop; /* 0xb024 */ ++ volatile reg_wbc_g0_lcrop wbc_g0_lcrop; /* 0xb028 */ ++ volatile unsigned int reserved_90[501]; /* 0xb02c~0xb7fc 501 regs */ ++ volatile reg_wbc_gp0_ctrl wbc_gp0_ctrl; /* 0xb800 */ ++ volatile reg_wbc_gp0_upd wbc_gp0_upd; /* 0xb804 */ ++ volatile unsigned int reserved_91[2]; /* 0xb808~0xb80c 2 regs */ ++ volatile unsigned int wbc_gp0_yaddr; /* 0xb810 */ ++ volatile unsigned int wbc_gp0_caddr; /* 0xb814 */ ++ volatile reg_wbc_gp0_stride wbc_gp0_stride; /* 0xb818 */ ++ volatile unsigned int reserved_92; /* 0xb81c */ ++ volatile reg_wbc_gp0_oreso wbc_gp0_oreso; /* 0xb820 */ ++ volatile reg_wbc_gp0_fcrop wbc_gp0_fcrop; /* 0xb824 */ ++ volatile reg_wbc_gp0_lcrop wbc_gp0_lcrop; /* 0xb828 */ ++ volatile unsigned int reserved_93[53]; /* 0xb82c~0xb8fc 53 regs */ ++ volatile reg_wbc_gp0_dither_ctrl wbc_gp0_dither_ctrl; /* 0xb900 */ ++ volatile reg_wbc_gp0_dither_coef0 wbc_gp0_dither_coef0; /* 0xb904 */ ++ volatile reg_wbc_gp0_dither_coef1 wbc_gp0_dither_coef1; /* 0xb908 */ ++ volatile unsigned int reserved_94[17]; /* 0xb90c~0xb94c 17 regs */ ++ volatile reg_wbc_gp0_hpzme wbc_gp0_hpzme; /* 0xb950 */ ++ volatile unsigned int reserved_95[43]; /* 0xb954~0xb9fc 43 regs */ ++ volatile reg_wbc_me_ctrl wbc_me_ctrl; /* 0xba00 */ ++ volatile reg_wbc_me_upd wbc_me_upd; /* 0xba04 */ ++ volatile reg_wbc_me_wlen_sel wbc_me_wlen_sel; /* 0xba08 */ ++ volatile unsigned int reserved_96; /* 0xba0c */ ++ volatile unsigned int wbc_me_yaddr; /* 0xba10 */ ++ volatile unsigned int wbc_me_caddr; /* 0xba14 */ ++ volatile reg_wbc_me_stride wbc_me_stride; /* 0xba18 */ ++ volatile unsigned int reserved_97; /* 0xba1c */ ++ volatile reg_wbc_me_oreso wbc_me_oreso; /* 0xba20 */ ++ volatile unsigned int reserved_98[2]; /* 0xba24~0xba28 2 regs */ ++ volatile reg_wbc_me_smmu_bypass wbc_me_smmu_bypass; /* 0xba2c */ ++ volatile unsigned int reserved_99[4]; /* 0xba30~0xba3c 4 regs */ ++ volatile reg_wbc_me_paraup wbc_me_paraup; /* 0xba40 */ ++ volatile unsigned int reserved_100[3]; /* 0xba44~0xba4c 3 regs */ ++ volatile unsigned int wbc_me_hlcoefad; /* 0xba50 */ ++ volatile unsigned int wbc_me_hccoefad; /* 0xba54 */ ++ volatile unsigned int wbc_me_vlcoefad; /* 0xba58 */ ++ volatile unsigned int wbc_me_vccoefad; /* 0xba5c */ ++ volatile unsigned int reserved_101[36]; /* 0xba60~0xbaec 36 regs */ ++ volatile unsigned int wbc_me_checksum_y; /* 0xbaf0 */ ++ volatile unsigned int wbc_me_checksum_c; /* 0xbaf4 */ ++ volatile unsigned int reserved_102[2]; /* 0xbaf8~0xbafc 2 regs */ ++ volatile reg_wbc_me_dither_ctrl wbc_me_dither_ctrl; /* 0xbb00 */ ++ volatile reg_wbc_me_dither_coef0 wbc_me_dither_coef0; /* 0xbb04 */ ++ volatile reg_wbc_me_dither_coef1 wbc_me_dither_coef1; /* 0xbb08 */ ++ volatile unsigned int reserved_103[109]; /* 0xbb0c~0xbcbc 109 regs */ ++ volatile reg_wbc_me_zme_hsp wbc_me_zme_hsp; /* 0xbcc0 */ ++ volatile reg_wbc_me_zme_hloffset wbc_me_zme_hloffset; /* 0xbcc4 */ ++ volatile reg_wbc_me_zme_hcoffset wbc_me_zme_hcoffset; /* 0xbcc8 */ ++ volatile unsigned int reserved_104[3]; /* 0xbccc~0xbcd4 3 regs */ ++ volatile reg_wbc_me_zme_vsp wbc_me_zme_vsp; /* 0xbcd8 */ ++ volatile reg_wbc_me_zme_vsr wbc_me_zme_vsr; /* 0xbcdc */ ++ volatile reg_wbc_me_zme_voffset wbc_me_zme_voffset; /* 0xbce0 */ ++ volatile reg_wbc_me_zme_vboffset wbc_me_zme_vboffset; /* 0xbce4 */ ++ volatile unsigned int reserved_105[6]; /* 0xbce8~0xbcfc 6 regs */ ++ volatile reg_wbc_fi_ctrl wbc_fi_ctrl; /* 0xbd00 */ ++ volatile reg_wbc_fi_upd wbc_fi_upd; /* 0xbd04 */ ++ volatile reg_wbc_fi_wlen_sel wbc_fi_wlen_sel; /* 0xbd08 */ ++ volatile unsigned int reserved_106; /* 0xbd0c */ ++ volatile unsigned int wbc_fi_yaddr; /* 0xbd10 */ ++ volatile unsigned int wbc_fi_caddr; /* 0xbd14 */ ++ volatile reg_wbc_fi_stride wbc_fi_stride; /* 0xbd18 */ ++ volatile unsigned int reserved_107; /* 0xbd1c */ ++ volatile reg_wbc_fi_oreso wbc_fi_oreso; /* 0xbd20 */ ++ volatile unsigned int reserved_108[2]; /* 0xbd24~0xbd28 2 regs */ ++ volatile reg_wbc_fi_smmu_bypass wbc_fi_smmu_bypass; /* 0xbd2c */ ++ volatile unsigned int reserved_109[5]; /* 0xbd30~0xbd40 5 regs */ ++ volatile reg_wbc_fi_frame_size wbc_fi_frame_size; /* 0xbd44 */ ++ volatile unsigned int wbc_fi_y_raddr; /* 0xbd48 */ ++ volatile unsigned int wbc_fi_c_raddr; /* 0xbd4c */ ++ volatile unsigned int reserved_110[40]; /* 0xbd50~0xbdec 40 regs */ ++ volatile unsigned int wbc_fi_checksum_y; /* 0xbdf0 */ ++ volatile unsigned int wbc_fi_checksum_c; /* 0xbdf4 */ ++ volatile unsigned int reserved_111[6]; /* 0xbdf8~0xbe0c 6 regs */ ++ volatile reg_wbc_fi_hcds wbc_fi_hcds; /* 0xbe10 */ ++ volatile reg_wbc_fi_hcds_coef0 wbc_fi_hcds_coef0; /* 0xbe14 */ ++ volatile reg_wbc_fi_hcds_coef1 wbc_fi_hcds_coef1; /* 0xbe18 */ ++ volatile unsigned int reserved_112; /* 0xbe1c */ ++ volatile reg_wbc_fi_cmp_mb wbc_fi_cmp_mb; /* 0xbe20 */ ++ volatile reg_wbc_fi_cmp_max_min wbc_fi_cmp_max_min; /* 0xbe24 */ ++ volatile reg_wbc_fi_cmp_adj_thr wbc_fi_cmp_adj_thr; /* 0xbe28 */ ++ volatile reg_wbc_fi_cmp_big_grad wbc_fi_cmp_big_grad; /* 0xbe2c */ ++ volatile reg_wbc_fi_cmp_blk wbc_fi_cmp_blk; /* 0xbe30 */ ++ volatile reg_wbc_fi_cmp_graphic_judge wbc_fi_cmp_graphic_judge; /* 0xbe34 */ ++ volatile reg_wbc_fi_cmp_rc wbc_fi_cmp_rc; /* 0xbe38 */ ++ volatile reg_wbc_fi_cmp_frame_size wbc_fi_cmp_frame_size; /* 0xbe3c */ ++ volatile unsigned int reserved_113[48]; /* 0xbe40~0xbefc 48 regs */ ++ volatile reg_wbc_cmp_glb_info wbc_cmp_glb_info; /* 0xbf00 */ ++ volatile reg_wbc_cmp_framesize wbc_cmp_framesize; /* 0xbf04 */ ++ volatile reg_wbc_cmp_rc_cfg0 wbc_cmp_rc_cfg0; /* 0xbf08 */ ++ volatile reg_wbc_cmp_rc_cfg2 wbc_cmp_rc_cfg2; /* 0xbf0c */ ++ volatile reg_wbc_cmp_rc_cfg3 wbc_cmp_rc_cfg3; /* 0xbf10 */ ++ volatile reg_wbc_cmp_rc_cfg4 wbc_cmp_rc_cfg4; /* 0xbf14 */ ++ volatile reg_wbc_cmp_rc_cfg5 wbc_cmp_rc_cfg5; /* 0xbf18 */ ++ volatile reg_wbc_cmp_rc_cfg6 wbc_cmp_rc_cfg6; /* 0xbf1c */ ++ volatile reg_wbc_cmp_rc_cfg7 wbc_cmp_rc_cfg7; /* 0xbf20 */ ++ volatile reg_wbc_cmp_rc_cfg8 wbc_cmp_rc_cfg8; /* 0xbf24 */ ++ volatile reg_wbc_cmp_rc_cfg10 wbc_cmp_rc_cfg10; /* 0xbf28 */ ++ volatile reg_wbc_cmp_outsize0 wbc_cmp_outsize0; /* 0xbf2c */ ++ volatile unsigned int wbc_cmp_dbg_reg0; /* 0xbf30 */ ++ volatile reg_wbc_cmp_max_row wbc_cmp_max_row; /* 0xbf34 */ ++ volatile reg_wbc_bmp_ctrl wbc_bmp_ctrl; /* 0xbf38 */ ++ volatile reg_wbc_bmp_upd wbc_bmp_upd; /* 0xbf3c */ ++ volatile unsigned int wbc_bmp_yaddr; /* 0xbf40 */ ++ volatile unsigned int reserved_114[23]; /* 0xbf44~0xbf9c 23 regs */ ++ volatile reg_wbc_bmp_oreso wbc_bmp_oreso; /* 0xbfa0 */ ++ volatile reg_wbc_bmp_sum wbc_bmp_sum; /* 0xbfa4 */ ++ volatile unsigned int reserved_115[18]; /* 0xbfa8~0xbfec 18 regs */ ++ volatile unsigned int wbc_bmp_checksum_y; /* 0xbff0 */ ++ volatile unsigned int wbc_bmp_checksum_c; /* 0xbff4 */ ++ volatile unsigned int reserved_116[2]; /* 0xbff8~0xbffc 2 regs */ ++ volatile reg_wbc_dhd0_ctrl wbc_dhd0_ctrl; /* 0xc000 */ ++ volatile reg_wbc_dhd0_upd wbc_dhd0_upd; /* 0xc004 */ ++ volatile reg_wbc_dhd0_oreso wbc_dhd0_oreso; /* 0xc008 */ ++ volatile unsigned int reserved_117[29]; /* 0xc00c~0xc07c 29 regs */ ++ volatile reg_wd_hpzme_ctrl wd_hpzme_ctrl; /* 0xc080 */ ++ volatile reg_wd_hpzmecoef01 wd_hpzmecoef01; /* 0xc084 */ ++ volatile reg_wd_hpzmecoef23 wd_hpzmecoef23; /* 0xc088 */ ++ volatile reg_wd_hpzmecoef45 wd_hpzmecoef45; /* 0xc08c */ ++ volatile reg_wd_hpzmecoef67 wd_hpzmecoef67; /* 0xc090 */ ++ volatile unsigned int reserved_118[91]; /* 0xc094~0xc1fc 91 regs */ ++ volatile reg_wd_hcds_ctrl wd_hcds_ctrl; /* 0xc200 */ ++ volatile reg_wd_hcdscoef01 wd_hcdscoef01; /* 0xc204 */ ++ volatile reg_wd_hcdscoef23 wd_hcdscoef23; /* 0xc208 */ ++ volatile reg_wd_hcdscoef45 wd_hcdscoef45; /* 0xc20c */ ++ volatile reg_wd_hcdscoef67 wd_hcdscoef67; /* 0xc210 */ ++ volatile unsigned int reserved_119[27]; /* 0xc214~0xc27c 27 regs */ ++ volatile reg_dither_ctrl dither_ctrl; /* 0xc280 */ ++ volatile reg_dither_sed_y0 dither_sed_y0; /* 0xc284 */ ++ volatile reg_dither_sed_u0 dither_sed_u0; /* 0xc288 */ ++ volatile reg_dither_sed_v0 dither_sed_v0; /* 0xc28c */ ++ volatile reg_dither_sed_w0 dither_sed_w0; /* 0xc290 */ ++ volatile reg_dither_sed_y1 dither_sed_y1; /* 0xc294 */ ++ volatile reg_dither_sed_u1 dither_sed_u1; /* 0xc298 */ ++ volatile reg_dither_sed_v1 dither_sed_v1; /* 0xc29c */ ++ volatile reg_dither_sed_w1 dither_sed_w1; /* 0xc2a0 */ ++ volatile reg_dither_sed_y2 dither_sed_y2; /* 0xc2a4 */ ++ volatile reg_dither_sed_u2 dither_sed_u2; /* 0xc2a8 */ ++ volatile reg_dither_sed_v2 dither_sed_v2; /* 0xc2ac */ ++ volatile reg_dither_sed_w2 dither_sed_w2; /* 0xc2b0 */ ++ volatile reg_dither_sed_y3 dither_sed_y3; /* 0xc2b4 */ ++ volatile reg_dither_sed_u3 dither_sed_u3; /* 0xc2b8 */ ++ volatile reg_dither_sed_v3 dither_sed_v3; /* 0xc2bc */ ++ volatile reg_dither_sed_w3 dither_sed_w3; /* 0xc2c0 */ ++ volatile reg_dither_thr dither_thr; /* 0xc2c4 */ ++ volatile unsigned int reserved_120[14]; /* 0xc2c8~0xc2fc 14 regs */ ++ volatile reg_wd_zme_hinfo wd_zme_hinfo; /* 0xc300 */ ++ volatile reg_wd_zme_hsp wd_zme_hsp; /* 0xc304 */ ++ volatile reg_wd_zme_hloffset wd_zme_hloffset; /* 0xc308 */ ++ volatile reg_wd_zme_hcoffset wd_zme_hcoffset; /* 0xc30c */ ++ volatile unsigned int reserved_121[5]; /* 0xc310~0xc320 5 regs */ ++ volatile reg_wd_zme_hcoef_ren wd_zme_hcoef_ren; /* 0xc324 */ ++ volatile reg_wd_zme_hcoef_rdata wd_zme_hcoef_rdata; /* 0xc328 */ ++ volatile reg_wd_zme_hdraw wd_zme_hdraw; /* 0xc32c */ ++ volatile reg_wd_zme_hratio wd_zme_hratio; /* 0xc330 */ ++ volatile unsigned int reserved_122[51]; /* 0xc334~0xc3fc 51 regs */ ++ volatile reg_wd_zme_vinfo wd_zme_vinfo; /* 0xc400 */ ++ volatile reg_wd_zme_vsp wd_zme_vsp; /* 0xc404 */ ++ volatile reg_wd_zme_voffset wd_zme_voffset; /* 0xc408 */ ++ volatile reg_wd_zme_vboffset wd_zme_vboffset; /* 0xc40c */ ++ volatile unsigned int reserved_123[5]; /* 0xc410~0xc420 5 regs */ ++ volatile reg_wd_zme_vcoef_ren wd_zme_vcoef_ren; /* 0xc424 */ ++ volatile reg_wd_zme_vcoef_rdata wd_zme_vcoef_rdata; /* 0xc428 */ ++ volatile reg_wd_zme_vdraw wd_zme_vdraw; /* 0xc42c */ ++ volatile reg_wd_zme_vratio wd_zme_vratio; /* 0xc430 */ ++ volatile unsigned int reserved_124[755]; /* 0xc434~0xcffc 755 regs */ ++ volatile reg_dhd0_ctrl dhd0_ctrl; /* 0xd000 */ ++ volatile reg_dhd0_vsync1 dhd0_vsync1; /* 0xd004 */ ++ volatile reg_dhd0_vsync2 dhd0_vsync2; /* 0xd008 */ ++ volatile reg_dhd0_hsync1 dhd0_hsync1; /* 0xd00c */ ++ volatile reg_dhd0_hsync2 dhd0_hsync2; /* 0xd010 */ ++ volatile reg_dhd0_vplus1 dhd0_vplus1; /* 0xd014 */ ++ volatile reg_dhd0_vplus2 dhd0_vplus2; /* 0xd018 */ ++ volatile reg_dhd0_pwr dhd0_pwr; /* 0xd01c */ ++ volatile reg_dhd0_vtthd3 dhd0_vtthd3; /* 0xd020 */ ++ volatile reg_dhd0_vtthd dhd0_vtthd; /* 0xd024 */ ++ volatile reg_dhd0_parathd dhd0_parathd; /* 0xd028 */ ++ volatile reg_dhd0_precharge_thd dhd0_precharge_thd; /* 0xd02c */ ++ volatile reg_dhd0_start_pos dhd0_start_pos; /* 0xd030 */ ++ volatile reg_dhd0_start_pos1 dhd0_start_pos1; /* 0xd034 */ ++ volatile reg_dhd0_paraup dhd0_paraup; /* 0xd038 */ ++ volatile reg_dhd0_sync_inv dhd0_sync_inv; /* 0xd03c */ ++ volatile reg_dhd0_clk_dv_ctrl dhd0_clk_dv_ctrl; /* 0xd040 */ ++ volatile reg_dhd0_rgb_fix_ctrl dhd0_rgb_fix_ctrl; /* 0xd044 */ ++ volatile reg_dhd0_lockcfg dhd0_lockcfg; /* 0xd048 */ ++ volatile unsigned int dhd0_cap_frm_cnt; /* 0xd04c */ ++ volatile unsigned int dhd0_vdp_frm_cnt; /* 0xd050 */ ++ volatile unsigned int dhd0_vsync_cap_vdp_cnt; /* 0xd054 */ ++ volatile unsigned int dhd0_intf_chksum_y; /* 0xd058 */ ++ volatile unsigned int dhd0_intf_chksum_u; /* 0xd05c */ ++ volatile unsigned int dhd0_intf_chksum_v; /* 0xd060 */ ++ volatile unsigned int dhd0_intf1_chksum_y; /* 0xd064 */ ++ volatile unsigned int dhd0_intf1_chksum_u; /* 0xd068 */ ++ volatile unsigned int dhd0_intf1_chksum_v; /* 0xd06c */ ++ volatile reg_dhd0_intf_chksum_high1 dhd0_intf_chksum_high1; /* 0xd070 */ ++ volatile reg_dhd0_intf_chksum_high2 dhd0_intf_chksum_high2; /* 0xd074 */ ++ volatile unsigned int reserved_125[3]; /* 0xd078~0xd080 3 regs */ ++ volatile unsigned int dhd0_afifo_pre_thd; /* 0xd084 */ ++ volatile reg_dhd0_state dhd0_state; /* 0xd088 */ ++ volatile reg_dhd0_uf_state dhd0_uf_state; /* 0xd08c */ ++ volatile reg_vo_mux vo_mux; /* 0xd090 */ ++ volatile reg_vo_mux_sync vo_mux_sync; /* 0xd094 */ ++ volatile reg_vo_mux_data vo_mux_data; /* 0xd098 */ ++ volatile unsigned int reserved_126; /* 0xd09c */ ++ volatile reg_dhd0_vsync_te_state dhd0_vsync_te_state; /* 0xd0a0 */ ++ volatile reg_dhd0_vsync_te_state1 dhd0_vsync_te_state1; /* 0xd0a4 */ ++ volatile unsigned int reserved_127[6]; /* 0xd0a8~0xd0bc 6 regs */ ++ volatile reg_dhd0_ccdoimgmod dhd0_ccdoimgmod; /* 0xd0c0 */ ++ volatile reg_dhd0_ccdoposmskh dhd0_ccdoposmskh; /* 0xd0c4 */ ++ volatile reg_dhd0_ccdoposmskl dhd0_ccdoposmskl; /* 0xd0c8 */ ++ volatile unsigned int reserved_128; /* 0xd0cc */ ++ volatile reg_dhd0_dacdet1 dhd0_dacdet1; /* 0xd0d0 */ ++ volatile reg_dhd0_dacdet2 dhd0_dacdet2; /* 0xd0d4 */ ++ volatile unsigned int reserved_129[2]; /* 0xd0d8~0xd0dc 2 regs */ ++ volatile reg_dhd0_ccd_info1 dhd0_ccd_info1; /* 0xd0e0 */ ++ volatile reg_dhd0_ccd_info2 dhd0_ccd_info2; /* 0xd0e4 */ ++ volatile reg_dhd0_ccd_info3 dhd0_ccd_info3; /* 0xd0e8 */ ++ volatile unsigned int reserved_130[5]; /* 0xd0ec~0xd0fc 5 regs */ ++ volatile reg_intf_hdmi_ctrl intf_hdmi_ctrl; /* 0xd100 */ ++ volatile reg_intf_hdmi_upd intf_hdmi_upd; /* 0xd104 */ ++ volatile reg_intf_hdmi_sync_inv intf_hdmi_sync_inv; /* 0xd108 */ ++ volatile unsigned int reserved_131; /* 0xd10c */ ++ volatile unsigned int hdmi_intf_chksum_y; /* 0xd110 */ ++ volatile unsigned int hdmi_intf_chksum_u; /* 0xd114 */ ++ volatile unsigned int hdmi_intf_chksum_v; /* 0xd118 */ ++ volatile reg_hdmi_intf_chksum_high hdmi_intf_chksum_high; /* 0xd11c */ ++ volatile unsigned int hdmi_intf1_chksum_y; /* 0xd120 */ ++ volatile unsigned int hdmi_intf1_chksum_u; /* 0xd124 */ ++ volatile unsigned int hdmi_intf1_chksum_v; /* 0xd128 */ ++ volatile reg_hdmi_intf1_chksum_high hdmi_intf1_chksum_high; /* 0xd12c */ ++ volatile unsigned int reserved_132[8]; /* 0xd130~0xd14c 8 regs */ ++ volatile reg_hdmi_hfir_coef0 hdmi_hfir_coef0; /* 0xd150 */ ++ volatile reg_hdmi_hfir_coef1 hdmi_hfir_coef1; /* 0xd154 */ ++ volatile reg_hdmi_hfir_coef2 hdmi_hfir_coef2; /* 0xd158 */ ++ volatile reg_hdmi_hfir_coef3 hdmi_hfir_coef3; /* 0xd15c */ ++ volatile reg_hdmi_csc_idc hdmi_csc_idc; /* 0xd160 */ ++ volatile reg_hdmi_csc_odc hdmi_csc_odc; /* 0xd164 */ ++ volatile reg_hdmi_csc_iodc hdmi_csc_iodc; /* 0xd168 */ ++ volatile reg_hdmi_csc_p0 hdmi_csc_p0; /* 0xd16c */ ++ volatile reg_hdmi_csc_p1 hdmi_csc_p1; /* 0xd170 */ ++ volatile reg_hdmi_csc_p2 hdmi_csc_p2; /* 0xd174 */ ++ volatile reg_hdmi_csc_p3 hdmi_csc_p3; /* 0xd178 */ ++ volatile reg_hdmi_csc_p4 hdmi_csc_p4; /* 0xd17c */ ++ volatile reg_intf_mipi_del_ctrl intf_mipi_del_ctrl; /* 0xd180 */ ++ volatile reg_intf_mipi_del_upd intf_mipi_del_upd; /* 0xd184 */ ++ volatile reg_intf_mipi_del_sync_inv intf_mipi_del_sync_inv; /* 0xd188 */ ++ volatile unsigned int reserved_133; /* 0xd18c */ ++ volatile unsigned int mipi_del_intf_chksum_y; /* 0xd190 */ ++ volatile unsigned int mipi_del_intf_chksum_u; /* 0xd194 */ ++ volatile unsigned int mipi_del_intf_chksum_v; /* 0xd198 */ ++ volatile reg_mipi_del_intf_chksum_high mipi_del_intf_chksum_high; /* 0xd19c */ ++ volatile unsigned int mipi_del_intf1_chksum_y; /* 0xd1a0 */ ++ volatile unsigned int mipi_del_intf1_chksum_u; /* 0xd1a4 */ ++ volatile unsigned int mipi_del_intf1_chksum_v; /* 0xd1a8 */ ++ volatile reg_mipi_del_intf1_chksum_high mipi_del_intf1_chksum_high; /* 0xd1ac */ ++ volatile unsigned int reserved_134[8]; /* 0xd1b0~0xd1cc 8 regs */ ++ volatile reg_mipi_del_hfir_coef0 mipi_del_hfir_coef0; /* 0xd1d0 */ ++ volatile reg_mipi_del_hfir_coef1 mipi_del_hfir_coef1; /* 0xd1d4 */ ++ volatile reg_mipi_del_hfir_coef2 mipi_del_hfir_coef2; /* 0xd1d8 */ ++ volatile reg_mipi_del_hfir_coef3 mipi_del_hfir_coef3; /* 0xd1dc */ ++ volatile reg_mipi_del_csc_idc mipi_del_csc_idc; /* 0xd1e0 */ ++ volatile reg_mipi_del_csc_odc mipi_del_csc_odc; /* 0xd1e4 */ ++ volatile reg_mipi_del_csc_iodc mipi_del_csc_iodc; /* 0xd1e8 */ ++ volatile reg_mipi_del_csc_p0 mipi_del_csc_p0; /* 0xd1ec */ ++ volatile reg_mipi_del_csc_p1 mipi_del_csc_p1; /* 0xd1f0 */ ++ volatile reg_mipi_del_csc_p2 mipi_del_csc_p2; /* 0xd1f4 */ ++ volatile reg_mipi_del_csc_p3 mipi_del_csc_p3; /* 0xd1f8 */ ++ volatile reg_mipi_del_csc_p4 mipi_del_csc_p4; /* 0xd1fc */ ++ volatile reg_intf_bt_ctrl intf_bt_ctrl; /* 0xd200 */ ++ volatile reg_intf_bt_upd intf_bt_upd; /* 0xd204 */ ++ volatile reg_intf_bt_sync_inv intf_bt_sync_inv; /* 0xd208 */ ++ volatile unsigned int reserved_135; /* 0xd20c */ ++ volatile reg_bt_clip0_l bt_clip0_l; /* 0xd210 */ ++ volatile reg_bt_clip0_h bt_clip0_h; /* 0xd214 */ ++ volatile unsigned int reserved_136[26]; /* 0xd218~0xd27c 26 regs */ ++ volatile reg_bt_dither_ctrl bt_dither_ctrl; /* 0xd280 */ ++ volatile reg_bt_dither_sed_y0 bt_dither_sed_y0; /* 0xd284 */ ++ volatile reg_bt_dither_sed_u0 bt_dither_sed_u0; /* 0xd288 */ ++ volatile reg_bt_dither_sed_v0 bt_dither_sed_v0; /* 0xd28c */ ++ volatile reg_bt_dither_sed_w0 bt_dither_sed_w0; /* 0xd290 */ ++ volatile reg_bt_dither_sed_y1 bt_dither_sed_y1; /* 0xd294 */ ++ volatile reg_bt_dither_sed_u1 bt_dither_sed_u1; /* 0xd298 */ ++ volatile reg_bt_dither_sed_v1 bt_dither_sed_v1; /* 0xd29c */ ++ volatile reg_bt_dither_sed_w1 bt_dither_sed_w1; /* 0xd2a0 */ ++ volatile reg_bt_dither_sed_y2 bt_dither_sed_y2; /* 0xd2a4 */ ++ volatile reg_bt_dither_sed_u2 bt_dither_sed_u2; /* 0xd2a8 */ ++ volatile reg_bt_dither_sed_v2 bt_dither_sed_v2; /* 0xd2ac */ ++ volatile reg_bt_dither_sed_w2 bt_dither_sed_w2; /* 0xd2b0 */ ++ volatile reg_bt_dither_sed_y3 bt_dither_sed_y3; /* 0xd2b4 */ ++ volatile reg_bt_dither_sed_u3 bt_dither_sed_u3; /* 0xd2b8 */ ++ volatile reg_bt_dither_sed_v3 bt_dither_sed_v3; /* 0xd2bc */ ++ volatile reg_bt_dither_sed_w3 bt_dither_sed_w3; /* 0xd2c0 */ ++ volatile reg_bt_dither_thr bt_dither_thr; /* 0xd2c4 */ ++ volatile unsigned int reserved_137[10]; /* 0xd2c8~0xd2ec 10 regs */ ++ volatile unsigned int bt_intf_chksum_y; /* 0xd2f0 */ ++ volatile unsigned int bt_intf_chksum_u; /* 0xd2f4 */ ++ volatile unsigned int bt_intf_chksum_v; /* 0xd2f8 */ ++ volatile unsigned int reserved_138; /* 0xd2fc */ ++ volatile reg_intf_lcd_ctrl intf_lcd_ctrl; /* 0xd300 */ ++ volatile reg_intf_lcd_upd intf_lcd_upd; /* 0xd304 */ ++ volatile reg_intf_lcd_sync_inv intf_lcd_sync_inv; /* 0xd308 */ ++ volatile unsigned int reserved_139[5]; /* 0xd30c~0xd31c 5 regs */ ++ volatile reg_lcd_csc_idc lcd_csc_idc; /* 0xd320 */ ++ volatile reg_lcd_csc_odc lcd_csc_odc; /* 0xd324 */ ++ volatile reg_lcd_csc_iodc lcd_csc_iodc; /* 0xd328 */ ++ volatile reg_lcd_csc_p0 lcd_csc_p0; /* 0xd32c */ ++ volatile reg_lcd_csc_p1 lcd_csc_p1; /* 0xd330 */ ++ volatile reg_lcd_csc_p2 lcd_csc_p2; /* 0xd334 */ ++ volatile reg_lcd_csc_p3 lcd_csc_p3; /* 0xd338 */ ++ volatile reg_lcd_csc_p4 lcd_csc_p4; /* 0xd33c */ ++ volatile unsigned int reserved_140[16]; /* 0xd340~0xd37c 16 regs */ ++ volatile reg_lcd_dither_ctrl lcd_dither_ctrl; /* 0xd380 */ ++ volatile reg_lcd_dither_sed_y0 lcd_dither_sed_y0; /* 0xd384 */ ++ volatile reg_lcd_dither_sed_u0 lcd_dither_sed_u0; /* 0xd388 */ ++ volatile reg_lcd_dither_sed_v0 lcd_dither_sed_v0; /* 0xd38c */ ++ volatile reg_lcd_dither_sed_w0 lcd_dither_sed_w0; /* 0xd390 */ ++ volatile reg_lcd_dither_sed_y1 lcd_dither_sed_y1; /* 0xd394 */ ++ volatile reg_lcd_dither_sed_u1 lcd_dither_sed_u1; /* 0xd398 */ ++ volatile reg_lcd_dither_sed_v1 lcd_dither_sed_v1; /* 0xd39c */ ++ volatile reg_lcd_dither_sed_w1 lcd_dither_sed_w1; /* 0xd3a0 */ ++ volatile reg_lcd_dither_sed_y2 lcd_dither_sed_y2; /* 0xd3a4 */ ++ volatile reg_lcd_dither_sed_u2 lcd_dither_sed_u2; /* 0xd3a8 */ ++ volatile reg_lcd_dither_sed_v2 lcd_dither_sed_v2; /* 0xd3ac */ ++ volatile reg_lcd_dither_sed_w2 lcd_dither_sed_w2; /* 0xd3b0 */ ++ volatile reg_lcd_dither_sed_y3 lcd_dither_sed_y3; /* 0xd3b4 */ ++ volatile reg_lcd_dither_sed_u3 lcd_dither_sed_u3; /* 0xd3b8 */ ++ volatile reg_lcd_dither_sed_v3 lcd_dither_sed_v3; /* 0xd3bc */ ++ volatile reg_lcd_dither_sed_w3 lcd_dither_sed_w3; /* 0xd3c0 */ ++ volatile reg_lcd_dither_thr lcd_dither_thr; /* 0xd3c4 */ ++ volatile unsigned int reserved_141[10]; /* 0xd3c8~0xd3ec 10 regs */ ++ volatile unsigned int lcd_intf_chksum_y; /* 0xd3f0 */ ++ volatile unsigned int lcd_intf_chksum_u; /* 0xd3f4 */ ++ volatile unsigned int lcd_intf_chksum_v; /* 0xd3f8 */ ++ volatile unsigned int reserved_142; /* 0xd3fc */ ++ volatile reg_intf_hdmi1_ctrl intf_hdmi1_ctrl; /* 0xd400 */ ++ volatile reg_intf_hdmi1_upd intf_hdmi1_upd; /* 0xd404 */ ++ volatile reg_intf_hdmi1_sync_inv intf_hdmi1_sync_inv; /* 0xd408 */ ++ volatile unsigned int reserved_143; /* 0xd40c */ ++ volatile unsigned int hdmi1_intf_chksum_y; /* 0xd410 */ ++ volatile unsigned int hdmi1_intf_chksum_u; /* 0xd414 */ ++ volatile unsigned int hdmi1_intf_chksum_v; /* 0xd418 */ ++ volatile reg_hdmi1_intf_chksum_high hdmi1_intf_chksum_high; /* 0xd41c */ ++ volatile unsigned int hdmi1_intf1_chksum_y; /* 0xd420 */ ++ volatile unsigned int hdmi1_intf1_chksum_u; /* 0xd424 */ ++ volatile unsigned int hdmi1_intf1_chksum_v; /* 0xd428 */ ++ volatile reg_hdmi1_intf1_chksum_high hdmi1_intf1_chksum_high; /* 0xd42c */ ++ volatile unsigned int reserved_144[8]; /* 0xd430~0xd44c 8 regs */ ++ volatile reg_hdmi1_hfir_coef0 hdmi1_hfir_coef0; /* 0xd450 */ ++ volatile reg_hdmi1_hfir_coef1 hdmi1_hfir_coef1; /* 0xd454 */ ++ volatile reg_hdmi1_hfir_coef2 hdmi1_hfir_coef2; /* 0xd458 */ ++ volatile reg_hdmi1_hfir_coef3 hdmi1_hfir_coef3; /* 0xd45c */ ++ volatile unsigned int reserved_145[40]; /* 0xd460~0xd4fc 40 regs */ ++ volatile reg_intf_vga_ctrl intf_vga_ctrl; /* 0xd500 */ ++ volatile reg_intf_vga_upd intf_vga_upd; /* 0xd504 */ ++ volatile reg_intf_vga_sync_inv intf_vga_sync_inv; /* 0xd508 */ ++ volatile unsigned int reserved_146[5]; /* 0xd50c~0xd51c 5 regs */ ++ volatile reg_vga_csc_idc vga_csc_idc; /* 0xd520 */ ++ volatile reg_vga_csc_odc vga_csc_odc; /* 0xd524 */ ++ volatile reg_vga_csc_iodc vga_csc_iodc; /* 0xd528 */ ++ volatile reg_vga_csc_p0 vga_csc_p0; /* 0xd52c */ ++ volatile reg_vga_csc_p1 vga_csc_p1; /* 0xd530 */ ++ volatile reg_vga_csc_p2 vga_csc_p2; /* 0xd534 */ ++ volatile reg_vga_csc_p3 vga_csc_p3; /* 0xd538 */ ++ volatile reg_vga_csc_p4 vga_csc_p4; /* 0xd53c */ ++ volatile reg_vga_hspcfg0 vga_hspcfg0; /* 0xd540 */ ++ volatile reg_vga_hspcfg1 vga_hspcfg1; /* 0xd544 */ ++ volatile unsigned int reserved_147[3]; /* 0xd548~0xd550 3 regs */ ++ volatile reg_vga_hspcfg5 vga_hspcfg5; /* 0xd554 */ ++ volatile reg_vga_hspcfg6 vga_hspcfg6; /* 0xd558 */ ++ volatile reg_vga_hspcfg7 vga_hspcfg7; /* 0xd55c */ ++ volatile reg_vga_hspcfg8 vga_hspcfg8; /* 0xd560 */ ++ volatile unsigned int reserved_148[3]; /* 0xd564~0xd56c 3 regs */ ++ volatile reg_vga_hspcfg12 vga_hspcfg12; /* 0xd570 */ ++ volatile reg_vga_hspcfg13 vga_hspcfg13; /* 0xd574 */ ++ volatile reg_vga_hspcfg14 vga_hspcfg14; /* 0xd578 */ ++ volatile reg_vga_hspcfg15 vga_hspcfg15; /* 0xd57c */ ++ volatile unsigned int reserved_149[28]; /* 0xd580~0xd5ec 28 regs */ ++ volatile unsigned int vga_intf_chksum_y; /* 0xd5f0 */ ++ volatile unsigned int vga_intf_chksum_u; /* 0xd5f4 */ ++ volatile unsigned int vga_intf_chksum_v; /* 0xd5f8 */ ++ volatile unsigned int reserved_150; /* 0xd5fc */ ++ volatile reg_intf_date_ctrl intf_date_ctrl; /* 0xd600 */ ++ volatile reg_intf_date_upd intf_date_upd; /* 0xd604 */ ++ volatile reg_intf_date_sync_inv intf_date_sync_inv; /* 0xd608 */ ++ volatile unsigned int reserved_151; /* 0xd60c */ ++ volatile reg_date_clip0_l date_clip0_l; /* 0xd610 */ ++ volatile reg_date_clip0_h date_clip0_h; /* 0xd614 */ ++ volatile unsigned int reserved_152[58]; /* 0xd618~0xd6fc 58 regs */ ++ volatile reg_intf0_dither_ctrl intf0_dither_ctrl; /* 0xd700 */ ++ volatile reg_intf0_dither_sed_y0 intf0_dither_sed_y0; /* 0xd704 */ ++ volatile reg_intf0_dither_sed_u0 intf0_dither_sed_u0; /* 0xd708 */ ++ volatile reg_intf0_dither_sed_v0 intf0_dither_sed_v0; /* 0xd70c */ ++ volatile reg_intf0_dither_sed_w0 intf0_dither_sed_w0; /* 0xd710 */ ++ volatile reg_intf0_dither_sed_y1 intf0_dither_sed_y1; /* 0xd714 */ ++ volatile reg_intf0_dither_sed_u1 intf0_dither_sed_u1; /* 0xd718 */ ++ volatile reg_intf0_dither_sed_v1 intf0_dither_sed_v1; /* 0xd71c */ ++ volatile reg_intf0_dither_sed_w1 intf0_dither_sed_w1; /* 0xd720 */ ++ volatile reg_intf0_dither_sed_y2 intf0_dither_sed_y2; /* 0xd724 */ ++ volatile reg_intf0_dither_sed_u2 intf0_dither_sed_u2; /* 0xd728 */ ++ volatile reg_intf0_dither_sed_v2 intf0_dither_sed_v2; /* 0xd72c */ ++ volatile reg_intf0_dither_sed_w2 intf0_dither_sed_w2; /* 0xd730 */ ++ volatile reg_intf0_dither_sed_y3 intf0_dither_sed_y3; /* 0xd734 */ ++ volatile reg_intf0_dither_sed_u3 intf0_dither_sed_u3; /* 0xd738 */ ++ volatile reg_intf0_dither_sed_v3 intf0_dither_sed_v3; /* 0xd73c */ ++ volatile reg_intf0_dither_sed_w3 intf0_dither_sed_w3; /* 0xd740 */ ++ volatile reg_intf0_dither_thr intf0_dither_thr; /* 0xd744 */ ++ volatile unsigned int reserved_153[14]; /* 0xd748~0xd77c 14 regs */ ++ volatile reg_intf_mipi_ctrl intf_mipi_ctrl; /* 0xd780 */ ++ volatile reg_intf_mipi_upd intf_mipi_upd; /* 0xd784 */ ++ volatile reg_intf_mipi_sync_inv intf_mipi_sync_inv; /* 0xd788 */ ++ volatile unsigned int reserved_154; /* 0xd78c */ ++ volatile unsigned int mipi_intf_chksum_y; /* 0xd790 */ ++ volatile unsigned int mipi_intf_chksum_u; /* 0xd794 */ ++ volatile unsigned int mipi_intf_chksum_v; /* 0xd798 */ ++ volatile reg_mipi_intf_chksum_high mipi_intf_chksum_high; /* 0xd79c */ ++ volatile unsigned int mipi_intf1_chksum_y; /* 0xd7a0 */ ++ volatile unsigned int mipi_intf1_chksum_u; /* 0xd7a4 */ ++ volatile unsigned int mipi_intf1_chksum_v; /* 0xd7a8 */ ++ volatile reg_mipi_intf1_chksum_high mipi_intf1_chksum_high; /* 0xd7ac */ ++ volatile unsigned int reserved_155[8]; /* 0xd7b0~0xd7cc 8 regs */ ++ volatile reg_mipi_hfir_coef0 mipi_hfir_coef0; /* 0xd7d0 */ ++ volatile reg_mipi_hfir_coef1 mipi_hfir_coef1; /* 0xd7d4 */ ++ volatile reg_mipi_hfir_coef2 mipi_hfir_coef2; /* 0xd7d8 */ ++ volatile reg_mipi_hfir_coef3 mipi_hfir_coef3; /* 0xd7dc */ ++ volatile reg_mipi_csc_idc mipi_csc_idc; /* 0xd7e0 */ ++ volatile reg_mipi_csc_odc mipi_csc_odc; /* 0xd7e4 */ ++ volatile reg_mipi_csc_iodc mipi_csc_iodc; /* 0xd7e8 */ ++ volatile reg_mipi_csc_p0 mipi_csc_p0; /* 0xd7ec */ ++ volatile reg_mipi_csc_p1 mipi_csc_p1; /* 0xd7f0 */ ++ volatile reg_mipi_csc_p2 mipi_csc_p2; /* 0xd7f4 */ ++ volatile reg_mipi_csc_p3 mipi_csc_p3; /* 0xd7f8 */ ++ volatile reg_mipi_csc_p4 mipi_csc_p4; /* 0xd7fc */ ++ volatile reg_mipi_dither_ctrl mipi_dither_ctrl; /* 0xd800 */ ++ volatile reg_mipi_dither_sed_y0 mipi_dither_sed_y0; /* 0xd804 */ ++ volatile reg_mipi_dither_sed_u0 mipi_dither_sed_u0; /* 0xd808 */ ++ volatile reg_mipi_dither_sed_v0 mipi_dither_sed_v0; /* 0xd80c */ ++ volatile reg_mipi_dither_sed_w0 mipi_dither_sed_w0; /* 0xd810 */ ++ volatile reg_mipi_dither_sed_y1 mipi_dither_sed_y1; /* 0xd814 */ ++ volatile reg_mipi_dither_sed_u1 mipi_dither_sed_u1; /* 0xd818 */ ++ volatile reg_mipi_dither_sed_v1 mipi_dither_sed_v1; /* 0xd81c */ ++ volatile reg_mipi_dither_sed_w1 mipi_dither_sed_w1; /* 0xd820 */ ++ volatile reg_mipi_dither_sed_y2 mipi_dither_sed_y2; /* 0xd824 */ ++ volatile reg_mipi_dither_sed_u2 mipi_dither_sed_u2; /* 0xd828 */ ++ volatile reg_mipi_dither_sed_v2 mipi_dither_sed_v2; /* 0xd82c */ ++ volatile reg_mipi_dither_sed_w2 mipi_dither_sed_w2; /* 0xd830 */ ++ volatile reg_mipi_dither_sed_y3 mipi_dither_sed_y3; /* 0xd834 */ ++ volatile reg_mipi_dither_sed_u3 mipi_dither_sed_u3; /* 0xd838 */ ++ volatile reg_mipi_dither_sed_v3 mipi_dither_sed_v3; /* 0xd83c */ ++ volatile reg_mipi_dither_sed_w3 mipi_dither_sed_w3; /* 0xd840 */ ++ volatile reg_mipi_dither_thr mipi_dither_thr; /* 0xd844 */ ++ volatile unsigned int reserved_156[494]; /* 0xd848~0xdffc 494 regs */ ++ volatile reg_dhd1_ctrl dhd1_ctrl; /* 0xe000 */ ++ volatile reg_dhd1_vsync1 dhd1_vsync1; /* 0xe004 */ ++ volatile reg_dhd1_vsync2 dhd1_vsync2; /* 0xe008 */ ++ volatile reg_dhd1_hsync1 dhd1_hsync1; /* 0xe00c */ ++ volatile reg_dhd1_hsync2 dhd1_hsync2; /* 0xe010 */ ++ volatile reg_dhd1_vplus1 dhd1_vplus1; /* 0xe014 */ ++ volatile reg_dhd1_vplus2 dhd1_vplus2; /* 0xe018 */ ++ volatile reg_dhd1_pwr dhd1_pwr; /* 0xe01c */ ++ volatile reg_dhd1_vtthd3 dhd1_vtthd3; /* 0xe020 */ ++ volatile reg_dhd1_vtthd dhd1_vtthd; /* 0xe024 */ ++ volatile reg_dhd1_parathd dhd1_parathd; /* 0xe028 */ ++ volatile reg_dhd1_precharge_thd dhd1_precharge_thd; /* 0xe02c */ ++ volatile reg_dhd1_start_pos dhd1_start_pos; /* 0xe030 */ ++ volatile reg_dhd1_start_pos1 dhd1_start_pos1; /* 0xe034 */ ++ volatile reg_dhd1_paraup dhd1_paraup; /* 0xe038 */ ++ volatile reg_dhd1_sync_inv dhd1_sync_inv; /* 0xe03c */ ++ volatile reg_dhd1_clk_dv_ctrl dhd1_clk_dv_ctrl; /* 0xe040 */ ++ volatile reg_dhd1_rgb_fix_ctrl dhd1_rgb_fix_ctrl; /* 0xe044 */ ++ volatile reg_dhd1_lockcfg dhd1_lockcfg; /* 0xe048 */ ++ volatile unsigned int dhd1_cap_frm_cnt; /* 0xe04c */ ++ volatile unsigned int dhd1_vdp_frm_cnt; /* 0xe050 */ ++ volatile unsigned int dhd1_vsync_cap_vdp_cnt; /* 0xe054 */ ++ volatile unsigned int dhd1_intf_chksum_y; /* 0xe058 */ ++ volatile unsigned int dhd1_intf_chksum_u; /* 0xe05c */ ++ volatile unsigned int dhd1_intf_chksum_v; /* 0xe060 */ ++ volatile unsigned int dhd1_intf1_chksum_y; /* 0xe064 */ ++ volatile unsigned int dhd1_intf1_chksum_u; /* 0xe068 */ ++ volatile unsigned int dhd1_intf1_chksum_v; /* 0xe06c */ ++ volatile reg_dhd1_intf_chksum_high1 dhd1_intf_chksum_high1; /* 0xe070 */ ++ volatile reg_dhd1_intf_chksum_high2 dhd1_intf_chksum_high2; /* 0xe074 */ ++ volatile unsigned int reserved_157[3]; /* 0xe078~0xe080 3 regs */ ++ volatile unsigned int dhd1_afifo_pre_thd; /* 0xe084 */ ++ volatile reg_dhd1_state dhd1_state; /* 0xe088 */ ++ volatile reg_dhd1_uf_state dhd1_uf_state; /* 0xe08c */ ++ volatile unsigned int reserved_158[4]; /* 0xe090~0xe09c 4 regs */ ++ volatile reg_dhd1_vsync_te_state dhd1_vsync_te_state; /* 0xe0a0 */ ++ volatile reg_dhd1_vsync_te_state1 dhd1_vsync_te_state1; /* 0xe0a4 */ ++ volatile unsigned int reserved_159[406]; /* 0xe0a8~0xe6fc 406 regs */ ++ volatile reg_intf1_dither_ctrl intf1_dither_ctrl; /* 0xe700 */ ++ volatile reg_intf1_dither_sed_y0 intf1_dither_sed_y0; /* 0xe704 */ ++ volatile reg_intf1_dither_sed_u0 intf1_dither_sed_u0; /* 0xe708 */ ++ volatile reg_intf1_dither_sed_v0 intf1_dither_sed_v0; /* 0xe70c */ ++ volatile reg_intf1_dither_sed_w0 intf1_dither_sed_w0; /* 0xe710 */ ++ volatile reg_intf1_dither_sed_y1 intf1_dither_sed_y1; /* 0xe714 */ ++ volatile reg_intf1_dither_sed_u1 intf1_dither_sed_u1; /* 0xe718 */ ++ volatile reg_intf1_dither_sed_v1 intf1_dither_sed_v1; /* 0xe71c */ ++ volatile reg_intf1_dither_sed_w1 intf1_dither_sed_w1; /* 0xe720 */ ++ volatile reg_intf1_dither_sed_y2 intf1_dither_sed_y2; /* 0xe724 */ ++ volatile reg_intf1_dither_sed_u2 intf1_dither_sed_u2; /* 0xe728 */ ++ volatile reg_intf1_dither_sed_v2 intf1_dither_sed_v2; /* 0xe72c */ ++ volatile reg_intf1_dither_sed_w2 intf1_dither_sed_w2; /* 0xe730 */ ++ volatile reg_intf1_dither_sed_y3 intf1_dither_sed_y3; /* 0xe734 */ ++ volatile reg_intf1_dither_sed_u3 intf1_dither_sed_u3; /* 0xe738 */ ++ volatile reg_intf1_dither_sed_v3 intf1_dither_sed_v3; /* 0xe73c */ ++ volatile reg_intf1_dither_sed_w3 intf1_dither_sed_w3; /* 0xe740 */ ++ volatile reg_intf1_dither_thr intf1_dither_thr; /* 0xe744 */ ++ volatile unsigned int reserved_160[558]; /* 0xe748~0xeffc 558 regs */ ++ volatile reg_dhd2_ctrl dhd2_ctrl; /* 0xf000 */ ++ volatile reg_dhd2_vsync1 dhd2_vsync1; /* 0xf004 */ ++ volatile reg_dhd2_vsync2 dhd2_vsync2; /* 0xf008 */ ++ volatile reg_dhd2_hsync1 dhd2_hsync1; /* 0xf00c */ ++ volatile reg_dhd2_hsync2 dhd2_hsync2; /* 0xf010 */ ++ volatile reg_dhd2_vplus1 dhd2_vplus1; /* 0xf014 */ ++ volatile reg_dhd2_vplus2 dhd2_vplus2; /* 0xf018 */ ++ volatile reg_dhd2_pwr dhd2_pwr; /* 0xf01c */ ++ volatile reg_dhd2_vtthd3 dhd2_vtthd3; /* 0xf020 */ ++ volatile reg_dhd2_vtthd dhd2_vtthd; /* 0xf024 */ ++ volatile reg_dhd2_parathd dhd2_parathd; /* 0xf028 */ ++ volatile reg_dhd2_precharge_thd dhd2_precharge_thd; /* 0xf02c */ ++ volatile reg_dhd2_start_pos dhd2_start_pos; /* 0xf030 */ ++ volatile reg_dhd2_start_pos1 dhd2_start_pos1; /* 0xf034 */ ++ volatile reg_dhd2_paraup dhd2_paraup; /* 0xf038 */ ++ volatile reg_dhd2_sync_inv dhd2_sync_inv; /* 0xf03c */ ++ volatile reg_dhd2_clk_dv_ctrl dhd2_clk_dv_ctrl; /* 0xf040 */ ++ volatile reg_dhd2_rgb_fix_ctrl dhd2_rgb_fix_ctrl; /* 0xf044 */ ++ volatile reg_dhd2_lockcfg dhd2_lockcfg; /* 0xf048 */ ++ volatile unsigned int dhd2_cap_frm_cnt; /* 0xf04c */ ++ volatile unsigned int dhd2_vdp_frm_cnt; /* 0xf050 */ ++ volatile unsigned int dhd2_vsync_cap_vdp_cnt; /* 0xf054 */ ++ volatile unsigned int dhd2_intf_chksum_y; /* 0xf058 */ ++ volatile unsigned int dhd2_intf_chksum_u; /* 0xf05c */ ++ volatile unsigned int dhd2_intf_chksum_v; /* 0xf060 */ ++ volatile unsigned int dhd2_intf1_chksum_y; /* 0xf064 */ ++ volatile unsigned int dhd2_intf1_chksum_u; /* 0xf068 */ ++ volatile unsigned int dhd2_intf1_chksum_v; /* 0xf06c */ ++ volatile reg_dhd2_intf_chksum_high1 dhd2_intf_chksum_high1; /* 0xf070 */ ++ volatile reg_dhd2_intf_chksum_high2 dhd2_intf_chksum_high2; /* 0xf074 */ ++ volatile unsigned int reserved_161[3]; /* 0xf078~0xf080 3 regs */ ++ volatile unsigned int dhd2_afifo_pre_thd; /* 0xf084 */ ++ volatile reg_dhd2_state dhd2_state; /* 0xf088 */ ++ volatile reg_dhd2_uf_state dhd2_uf_state; /* 0xf08c */ ++ volatile unsigned int reserved_162[4]; /* 0xf090~0xf09c 4 regs */ ++ volatile reg_dhd2_vsync_te_state dhd2_vsync_te_state; /* 0xf0a0 */ ++ volatile reg_dhd2_vsync_te_state1 dhd2_vsync_te_state1; /* 0xf0a4 */ ++ volatile unsigned int reserved_163[406]; /* 0xf0a8~0xf6fc 406 regs */ ++ volatile reg_intf2_dither_ctrl intf2_dither_ctrl; /* 0xf700 */ ++ volatile reg_intf2_dither_sed_y0 intf2_dither_sed_y0; /* 0xf704 */ ++ volatile reg_intf2_dither_sed_u0 intf2_dither_sed_u0; /* 0xf708 */ ++ volatile reg_intf2_dither_sed_v0 intf2_dither_sed_v0; /* 0xf70c */ ++ volatile reg_intf2_dither_sed_w0 intf2_dither_sed_w0; /* 0xf710 */ ++ volatile reg_intf2_dither_sed_y1 intf2_dither_sed_y1; /* 0xf714 */ ++ volatile reg_intf2_dither_sed_u1 intf2_dither_sed_u1; /* 0xf718 */ ++ volatile reg_intf2_dither_sed_v1 intf2_dither_sed_v1; /* 0xf71c */ ++ volatile reg_intf2_dither_sed_w1 intf2_dither_sed_w1; /* 0xf720 */ ++ volatile reg_intf2_dither_sed_y2 intf2_dither_sed_y2; /* 0xf724 */ ++ volatile reg_intf2_dither_sed_u2 intf2_dither_sed_u2; /* 0xf728 */ ++ volatile reg_intf2_dither_sed_v2 intf2_dither_sed_v2; /* 0xf72c */ ++ volatile reg_intf2_dither_sed_w2 intf2_dither_sed_w2; /* 0xf730 */ ++ volatile reg_intf2_dither_sed_y3 intf2_dither_sed_y3; /* 0xf734 */ ++ volatile reg_intf2_dither_sed_u3 intf2_dither_sed_u3; /* 0xf738 */ ++ volatile reg_intf2_dither_sed_v3 intf2_dither_sed_v3; /* 0xf73c */ ++ volatile reg_intf2_dither_sed_w3 intf2_dither_sed_w3; /* 0xf740 */ ++ volatile reg_intf2_dither_thr intf2_dither_thr; /* 0xf744 */ ++ volatile unsigned int reserved_164[46]; /* 0xf748~0xf7fc 46 regs */ ++ volatile reg_date_coeff0 date_coeff0; /* 0xf800 */ ++ volatile reg_date_coeff1 date_coeff1; /* 0xf804 */ ++ volatile unsigned int date_coeff2; /* 0xf808 */ ++ volatile reg_date_coeff3 date_coeff3; /* 0xf80c */ ++ volatile reg_date_coeff4 date_coeff4; /* 0xf810 */ ++ volatile reg_date_coeff5 date_coeff5; /* 0xf814 */ ++ volatile reg_date_coeff6 date_coeff6; /* 0xf818 */ ++ volatile reg_date_coeff7 date_coeff7; /* 0xf81c */ ++ volatile unsigned int date_coeff8; /* 0xf820 */ ++ volatile unsigned int date_coeff9; /* 0xf824 */ ++ volatile reg_date_coeff10 date_coeff10; /* 0xf828 */ ++ volatile reg_date_coeff11 date_coeff11; /* 0xf82c */ ++ volatile reg_date_coeff12 date_coeff12; /* 0xf830 */ ++ volatile reg_date_coeff13 date_coeff13; /* 0xf834 */ ++ volatile reg_date_coeff14 date_coeff14; /* 0xf838 */ ++ volatile reg_date_coeff15 date_coeff15; /* 0xf83c */ ++ volatile reg_date_coeff16 date_coeff16; /* 0xf840 */ ++ volatile unsigned int date_coeff17; /* 0xf844 */ ++ volatile unsigned int date_coeff18; /* 0xf848 */ ++ volatile reg_date_coeff19 date_coeff19; /* 0xf84c */ ++ volatile reg_date_coeff20 date_coeff20; /* 0xf850 */ ++ volatile reg_date_coeff21 date_coeff21; /* 0xf854 */ ++ volatile reg_date_coeff22 date_coeff22; /* 0xf858 */ ++ volatile reg_date_coeff23 date_coeff23; /* 0xf85c */ ++ volatile unsigned int date_coeff24; /* 0xf860 */ ++ volatile reg_date_coeff25 date_coeff25; /* 0xf864 */ ++ volatile reg_date_coeff26 date_coeff26; /* 0xf868 */ ++ volatile reg_date_coeff27 date_coeff27; /* 0xf86c */ ++ volatile reg_date_coeff28 date_coeff28; /* 0xf870 */ ++ volatile reg_date_coeff29 date_coeff29; /* 0xf874 */ ++ volatile reg_date_coeff30 date_coeff30; /* 0xf878 */ ++ volatile unsigned int reserved_165; /* 0xf87c */ ++ volatile reg_date_isrmask date_isrmask; /* 0xf880 */ ++ volatile reg_date_isrstate date_isrstate; /* 0xf884 */ ++ volatile reg_date_isr date_isr; /* 0xf888 */ ++ volatile unsigned int reserved_166; /* 0xf88c */ ++ volatile unsigned int date_version; /* 0xf890 */ ++ volatile reg_date_coeff37 date_coeff37; /* 0xf894 */ ++ volatile reg_date_coeff38 date_coeff38; /* 0xf898 */ ++ volatile reg_date_coeff39 date_coeff39; /* 0xf89c */ ++ volatile reg_date_coeff40 date_coeff40; /* 0xf8a0 */ ++ volatile reg_date_coeff41 date_coeff41; /* 0xf8a4 */ ++ volatile reg_date_coeff42 date_coeff42; /* 0xf8a8 */ ++ volatile unsigned int reserved_167[5]; /* 0xf8ac~0xf8bc 5 regs */ ++ volatile reg_date_dacdet1 date_dacdet1; /* 0xf8c0 */ ++ volatile reg_date_dacdet2 date_dacdet2; /* 0xf8c4 */ ++ volatile reg_date_coeff50 date_coeff50; /* 0xf8c8 */ ++ volatile reg_date_coeff51 date_coeff51; /* 0xf8cc */ ++ volatile reg_date_coeff52 date_coeff52; /* 0xf8d0 */ ++ volatile reg_date_coeff53 date_coeff53; /* 0xf8d4 */ ++ volatile reg_date_coeff54 date_coeff54; /* 0xf8d8 */ ++ volatile reg_date_coeff55 date_coeff55; /* 0xf8dc */ ++ volatile unsigned int reserved_168_1; /* 0xf8e0 */ ++ volatile reg_date_coeff57 date_coeff57; /* 0xf8e4 */ ++ volatile unsigned int reserved_168_2[454]; /* 0xf8e8~0xfffc 454 regs */ ++ volatile reg_mac_outstanding mac_outstanding; /* 0x10000 */ ++ volatile reg_mac_ctrl mac_ctrl; /* 0x10004 */ ++ volatile unsigned int reserved_169[2]; /* 0x10008~0x1000c 2 regs */ ++ volatile reg_mac_rchn_prio mac_rchn_prio; /* 0x10010 */ ++ volatile unsigned int reserved_170; /* 0x10014 */ ++ volatile reg_mac_wchn_prio mac_wchn_prio; /* 0x10018 */ ++ volatile unsigned int reserved_171; /* 0x1001c */ ++ volatile reg_mac_rchn_sel0 mac_rchn_sel0; /* 0x10020 */ ++ volatile unsigned int mac_rchn_sel1; /* 0x10024 */ ++ volatile unsigned int reserved_172[2]; /* 0x10028~0x1002c 2 regs */ ++ volatile reg_mac_wchn_sel0 mac_wchn_sel0; /* 0x10030 */ ++ volatile unsigned int reserved_173[3]; /* 0x10034~0x1003c 3 regs */ ++ volatile reg_mac_bus_err_clr mac_bus_err_clr; /* 0x10040 */ ++ volatile reg_mac_bus_err mac_bus_err; /* 0x10044 */ ++ volatile unsigned int reserved_174[2]; /* 0x10048~0x1004c 2 regs */ ++ volatile unsigned int mac_src0_status0; /* 0x10050 */ ++ volatile unsigned int mac_src0_status1; /* 0x10054 */ ++ volatile unsigned int mac_src1_status0; /* 0x10058 */ ++ volatile unsigned int mac_src1_status1; /* 0x1005c */ ++ volatile unsigned int mac_src2_status0; /* 0x10060 */ ++ volatile unsigned int mac_src2_status1; /* 0x10064 */ ++ volatile unsigned int reserved_175[2]; /* 0x10068~0x1006c 2 regs */ ++ volatile reg_mac_debug_ctrl mac_debug_ctrl; /* 0x10070 */ ++ volatile reg_mac_debug_clr mac_debug_clr; /* 0x10074 */ ++ volatile unsigned int reserved_176[2]; /* 0x10078~0x1007c 2 regs */ ++ volatile unsigned int mac0_debug_info; /* 0x10080 */ ++ volatile unsigned int reserved_177[3]; /* 0x10084~0x1008c 3 regs */ ++ volatile unsigned int mac0_rd_info; /* 0x10090 */ ++ volatile unsigned int mac0_wr_info; /* 0x10094 */ ++ volatile unsigned int mac1_rd_info; /* 0x10098 */ ++ volatile unsigned int mac1_wr_info; /* 0x1009c */ ++ volatile unsigned int mac2_rd_info; /* 0x100a0 */ ++ volatile unsigned int mac2_wr_info; /* 0x100a4 */ ++ volatile unsigned int reserved_178[2]; /* 0x100a8~0x100ac 2 regs */ ++ volatile unsigned int mac0_det_latency0; /* 0x100b0 */ ++ volatile unsigned int mac0_det_latency1; /* 0x100b4 */ ++ volatile unsigned int mac0_det_latency2; /* 0x100b8 */ ++ volatile unsigned int mac0_det_latency3; /* 0x100bc */ ++ volatile unsigned int mac0_det_latency4; /* 0x100c0 */ ++ volatile unsigned int mac0_det_latency5; /* 0x100c4 */ ++ volatile unsigned int mac1_det_latency0; /* 0x100c8 */ ++ volatile unsigned int mac1_det_latency1; /* 0x100cc */ ++ volatile unsigned int mac1_det_latency2; /* 0x100d0 */ ++ volatile unsigned int mac1_det_latency3; /* 0x100d4 */ ++ volatile unsigned int mac1_det_latency4; /* 0x100d8 */ ++ volatile unsigned int mac1_det_latency5; /* 0x100dc */ ++ volatile unsigned int reserved_179[8]; /* 0x100e0~0x100fc 8 regs */ ++ volatile reg_mac_axi_press0_ctrl0 mac_axi_press0_ctrl0; /* 0x10100 */ ++ volatile reg_mac_axi_press0_ctrl1 mac_axi_press0_ctrl1; /* 0x10104 */ ++ volatile reg_mac_axi_press0_ctrl2 mac_axi_press0_ctrl2; /* 0x10108 */ ++ volatile reg_mac_axi_press0_ctrl3 mac_axi_press0_ctrl3; /* 0x1010c */ ++ volatile reg_mac_axi_press0_ctrl4 mac_axi_press0_ctrl4; /* 0x10110 */ ++ volatile unsigned int reserved_180[3]; /* 0x10114~0x1011c 3 regs */ ++ volatile reg_mac_axi_press0_ctrl5 mac_axi_press0_ctrl5; /* 0x10120 */ ++ volatile unsigned int reserved_181[23]; /* 0x10124~0x1017c 23 regs */ ++ volatile reg_mac_axi_press1_ctrl0 mac_axi_press1_ctrl0; /* 0x10180 */ ++ volatile reg_mac_axi_press1_ctrl1 mac_axi_press1_ctrl1; /* 0x10184 */ ++ volatile reg_mac_axi_press1_ctrl2 mac_axi_press1_ctrl2; /* 0x10188 */ ++ volatile reg_mac_axi_press1_ctrl3 mac_axi_press1_ctrl3; /* 0x1018c */ ++ volatile reg_mac_axi_press1_ctrl4 mac_axi_press1_ctrl4; /* 0x10190 */ ++ volatile unsigned int reserved_182[3]; /* 0x10194~0x1019c 3 regs */ ++ volatile reg_mac_axi_press1_ctrl5 mac_axi_press1_ctrl5; /* 0x101a0 */ ++ volatile unsigned int reserved_183[23]; /* 0x101a4~0x101fc 23 regs */ ++ volatile reg_vid_read_ctrl vid_read_ctrl; /* 0x10200 */ ++ volatile reg_vid_mac_ctrl vid_mac_ctrl; /* 0x10204 */ ++ volatile unsigned int reserved_184[2]; /* 0x10208~0x1020c 2 regs */ ++ volatile reg_vid_out_ctrl vid_out_ctrl; /* 0x10210 */ ++ volatile reg_vid_mute_alpha vid_mute_alpha; /* 0x10214 */ ++ volatile unsigned int reserved_185; /* 0x10218 */ ++ volatile reg_vid_mute_bk vid_mute_bk; /* 0x1021c */ ++ volatile unsigned int reserved_186[8]; /* 0x10220~0x1023c 8 regs */ ++ volatile reg_vid_src_info vid_src_info; /* 0x10240 */ ++ volatile reg_vid_src_reso vid_src_reso; /* 0x10244 */ ++ volatile reg_vid_src_crop vid_src_crop; /* 0x10248 */ ++ volatile reg_vid_in_reso vid_in_reso; /* 0x1024c */ ++ volatile unsigned int vid_addr_h; /* 0x10250 */ ++ volatile unsigned int vid_addr_l; /* 0x10254 */ ++ volatile unsigned int vid_caddr_h; /* 0x10258 */ ++ volatile unsigned int vid_caddr_l; /* 0x1025c */ ++ volatile unsigned int vid_naddr_h; /* 0x10260 */ ++ volatile unsigned int vid_naddr_l; /* 0x10264 */ ++ volatile unsigned int vid_ncaddr_h; /* 0x10268 */ ++ volatile unsigned int vid_ncaddr_l; /* 0x1026c */ ++ volatile reg_vid_stride vid_stride; /* 0x10270 */ ++ volatile reg_vid_2bit_stride vid_2bit_stride; /* 0x10274 */ ++ volatile reg_vid_head_stride vid_head_stride; /* 0x10278 */ ++ volatile unsigned int reserved_187; /* 0x1027c */ ++ volatile reg_vid_smmu_bypass vid_smmu_bypass; /* 0x10280 */ ++ volatile unsigned int reserved_188[3]; /* 0x10284~0x1028c 3 regs */ ++ volatile unsigned int vid_head_addr_h; /* 0x10290 */ ++ volatile unsigned int vid_head_addr_l; /* 0x10294 */ ++ volatile unsigned int vid_head_caddr_h; /* 0x10298 */ ++ volatile unsigned int vid_head_caddr_l; /* 0x1029c */ ++ volatile reg_vid_testpat_cfg vid_testpat_cfg; /* 0x102a0 */ ++ volatile reg_vid_testpat_seed vid_testpat_seed; /* 0x102a4 */ ++ volatile unsigned int vid_testpat_chksum_y; /* 0x102a8 */ ++ volatile unsigned int vid_testpat_chksum_c; /* 0x102ac */ ++ volatile unsigned int vid_work_addr_y; /* 0x102b0 */ ++ volatile unsigned int reserved_189[3]; /* 0x102b4~0x102bc 3 regs */ ++ volatile reg_vid_tunl_ctrl vid_tunl_ctrl; /* 0x102c0 */ ++ volatile reg_vid_tunl_crop vid_tunl_crop; /* 0x102c4 */ ++ volatile unsigned int reserved_190[2]; /* 0x102c8~0x102cc 2 regs */ ++ volatile unsigned int vid_tunl_addr_h; /* 0x102d0 */ ++ volatile unsigned int vid_tunl_addr_l; /* 0x102d4 */ ++ volatile unsigned int reserved_191[2]; /* 0x102d8~0x102dc 2 regs */ ++ volatile reg_vid_tunl_errsta vid_tunl_errsta; /* 0x102e0 */ ++ volatile reg_vid_tunl_debug vid_tunl_debug; /* 0x102e4 */ ++ volatile unsigned int reserved_192[6]; /* 0x102e8~0x102fc 6 regs */ ++ volatile unsigned int vid_l_cur_flow; /* 0x10300 */ ++ volatile unsigned int vid_l_cur_sreq_time; /* 0x10304 */ ++ volatile unsigned int vid_c_cur_flow; /* 0x10308 */ ++ volatile unsigned int vid_c_cur_sreq_time; /* 0x1030c */ ++ volatile unsigned int vid_l_last_flow; /* 0x10310 */ ++ volatile unsigned int vid_l_last_sreq_time; /* 0x10314 */ ++ volatile unsigned int vid_c_last_flow; /* 0x10318 */ ++ volatile unsigned int vid_c_last_sreq_time; /* 0x1031c */ ++ volatile unsigned int vid_l_busy_time; /* 0x10320 */ ++ volatile unsigned int vid_l_neednordy_time; /* 0x10324 */ ++ volatile unsigned int vid_l2_neednordy_time; /* 0x10328 */ ++ volatile unsigned int vid_c_busy_time; /* 0x1032c */ ++ volatile unsigned int vid_c_neednordy_time; /* 0x10330 */ ++ volatile unsigned int vid_c2_neednordy_time; /* 0x10334 */ ++ volatile unsigned int reserved_193[2]; /* 0x10338~0x1033c 2 regs */ ++ volatile reg_vid_dcmp_ctrl vid_dcmp_ctrl; /* 0x10340 */ ++ volatile unsigned int vid_dcmp_l_fsize; /* 0x10344 */ ++ volatile unsigned int reserved_194[14]; /* 0x10348~0x1037c 14 regs */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_glb_info vdp_v3r2_lineseg_dcmp_glb_info; /* 0x10380 */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_frame_size vdp_v3r2_lineseg_dcmp_frame_size; /* 0x10384 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0; /* 0x10388 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1; /* 0x1038c */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; /* 0x10390 */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_error_sta vdp_v3r2_lineseg_dcmp_error_sta; /* 0x10394 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra; /* 0x10398 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg; /* 0x1039c */ ++ volatile unsigned int reserved_195[8]; /* 0x103a0~0x103bc 8 regs */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_glb_info_c vdp_v3r2_lineseg_dcmp_glb_info_c; /* 0x103c0 */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_frame_size_c vdp_v3r2_lineseg_dcmp_frame_size_c; /* 0x103c4 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0_c; /* 0x103c8 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1_c; /* 0x103cc */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; /* 0x103d0 */ ++ volatile reg_vdp_v3r2_lineseg_dcmp_error_sta_c vdp_v3r2_lineseg_dcmp_error_sta_c; /* 0x103d4 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra_c; /* 0x103d8 */ ++ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg_c; /* 0x103dc */ ++ volatile unsigned int reserved_196[648]; /* 0x103e0~0x10dfc 648 regs */ ++ volatile reg_gfx_read_ctrl gfx_read_ctrl; /* 0x10e00 */ ++ volatile reg_gfx_mac_ctrl gfx_mac_ctrl; /* 0x10e04 */ ++ volatile reg_gfx_out_ctrl gfx_out_ctrl; /* 0x10e08 */ ++ volatile unsigned int reserved_197; /* 0x10e0c */ ++ volatile reg_gfx_mute_alpha gfx_mute_alpha; /* 0x10e10 */ ++ volatile reg_gfx_mute_bk gfx_mute_bk; /* 0x10e14 2 regs */ ++ volatile unsigned int reserved_198[2]; /* 0x10e18~0x10e1c */ ++ volatile reg_gfx_smmu_bypass gfx_smmu_bypass; /* 0x10e20 */ ++ volatile unsigned int reserved_199; /* 0x10e24 */ ++ volatile reg_gfx_1555_alpha gfx_1555_alpha; /* 0x10e28 */ ++ volatile unsigned int reserved_200[5]; /* 0x10e2c~0x10e3c 5 regs */ ++ volatile reg_gfx_src_info gfx_src_info; /* 0x10e40 */ ++ volatile reg_gfx_src_reso gfx_src_reso; /* 0x10e44 */ ++ volatile reg_gfx_src_crop gfx_src_crop; /* 0x10e48 */ ++ volatile reg_gfx_ireso gfx_ireso; /* 0x10e4c */ ++ volatile unsigned int gfx_addr_h; /* 0x10e50 */ ++ volatile unsigned int gfx_addr_l; /* 0x10e54 */ ++ volatile unsigned int gfx_naddr_h; /* 0x10e58 */ ++ volatile unsigned int gfx_naddr_l; /* 0x10e5c */ ++ volatile reg_gfx_stride gfx_stride; /* 0x10e60 */ ++ volatile unsigned int reserved_201[3]; /* 0x10e64~0x10e6c 3 regs */ ++ volatile unsigned int gfx_dcmp_addr_h; /* 0x10e70 */ ++ volatile unsigned int gfx_dcmp_addr_l; /* 0x10e74 */ ++ volatile unsigned int gfx_dcmp_naddr_h; /* 0x10e78 */ ++ volatile unsigned int gfx_dcmp_naddr_l; /* 0x10e7c */ ++ volatile unsigned int reserved_202[28]; /* 0x10e80~0x10eec 28 regs */ ++ volatile unsigned int gfx_work_addr; /* 0x10ef0 */ ++ volatile unsigned int reserved_203[3]; /* 0x10ef4~0x10efc 3 regs */ ++ volatile reg_gfx_ckey_max gfx_ckey_max; /* 0x10f00 */ ++ volatile reg_gfx_ckey_min gfx_ckey_min; /* 0x10f04 */ ++ volatile reg_gfx_ckey_mask gfx_ckey_mask; /* 0x10f08 */ ++ volatile unsigned int reserved_204; /* 0x10f0c */ ++ volatile reg_gfx_testpat_cfg gfx_testpat_cfg; /* 0x10f10 */ ++ volatile reg_gfx_testpat_seed gfx_testpat_seed; /* 0x10f14 */ ++ volatile unsigned int reserved_205[2]; /* 0x10f18~0x10f1c 2 regs */ ++ volatile unsigned int gfx_dcmp_framesize0; /* 0x10f20 */ ++ volatile unsigned int gfx_dcmp_framesize1; /* 0x10f24 */ ++ volatile unsigned int reserved_206[2]; /* 0x10f28~0x10f2c 2 regs */ ++ volatile unsigned int gfx_cur_flow; /* 0x10f30 */ ++ volatile unsigned int gfx_cur_sreq_time; /* 0x10f34 */ ++ volatile unsigned int gfx_last_flow; /* 0x10f38 */ ++ volatile unsigned int gfx_last_sreq_time; /* 0x10f3c */ ++ volatile unsigned int gfx_busy_time; /* 0x10f40 */ ++ volatile unsigned int gfx_ar_neednordy_time; /* 0x10f44 */ ++ volatile unsigned int gfx_gb_neednordy_time; /* 0x10f48 */ ++ volatile unsigned int reserved_207; /* 0x10f4c */ ++ volatile reg_gfx_ld_ctrl gfx_ld_ctrl; /* 0x10f50 */ ++ volatile unsigned int gfx_tde_safe_dis; /* 0x10f54 */ ++ volatile reg_gfx_ld_smute_ctrl gfx_ld_smute_ctrl; /* 0x10f58 */ ++ volatile reg_gfx_ld_err_sta gfx_ld_err_sta; /* 0x10f5c */ ++ volatile unsigned int gfx_ld_debug0; /* 0x10f60 */ ++ volatile unsigned int gfx_ld_debug1; /* 0x10f64 */ ++ volatile unsigned int gfx_ld_debug2; /* 0x10f68 */ ++ volatile unsigned int gfx_ld_debug3; /* 0x10f6c */ ++ volatile unsigned int gfx_ld_debug4; /* 0x10f70 */ ++ volatile unsigned int gfx_ld_debug5; /* 0x10f74 */ ++ volatile unsigned int reserved_208[2]; /* 0x10f78~0x10f7c 2 regs */ ++ volatile reg_vdp_v3r2_line_osd_dcmp_glb_info vdp_v3r2_line_osd_dcmp_glb_info; /* 0x10f80 */ ++ volatile reg_vdp_v3r2_line_osd_dcmp_frame_size vdp_v3r2_line_osd_dcmp_frame_size; /* 0x10f84 */ ++ volatile reg_vdp_v3r2_line_osd_dcmp_error_sta vdp_v3r2_line_osd_dcmp_error_sta; /* 0x10f88 */ ++ volatile unsigned int reserved_209[541]; /* 0x10f8c~0x117fc 541 regs */ ++ volatile reg_wbc_ctrl wbc_ctrl; /* 0x11800 */ ++ volatile reg_wbc_mac_ctrl wbc_mac_ctrl; /* 0x11804 */ ++ volatile unsigned int reserved_210[3]; /* 0x11808~0x11810 3 regs */ ++ volatile reg_wbc_smmu_bypass wbc_smmu_bypass; /* 0x11814 */ ++ volatile unsigned int reserved_211[2]; /* 0x11818~0x1181c 2 regs */ ++ volatile reg_wbc_lowdlyctrl wbc_lowdlyctrl; /* 0x11820 */ ++ volatile unsigned int wbc_tunladdr_h; /* 0x11824 */ ++ volatile unsigned int wbc_tunladdr_l; /* 0x11828 */ ++ volatile reg_wbc_lowdlysta wbc_lowdlysta; /* 0x1182c */ ++ volatile unsigned int reserved_212[8]; /* 0x11830~0x1184c 8 regs */ ++ volatile unsigned int wbc_yaddr_h; /* 0x11850 */ ++ volatile unsigned int wbc_yaddr_l; /* 0x11854 */ ++ volatile unsigned int wbc_caddr_h; /* 0x11858 */ ++ volatile unsigned int wbc_caddr_l; /* 0x1185c */ ++ volatile reg_wbc_ystride wbc_ystride; /* 0x11860 */ ++ volatile reg_wbc_cstride wbc_cstride; /* 0x11864 */ ++ volatile unsigned int reserved_213[2]; /* 0x11868~0x1186c 2 regs */ ++ volatile unsigned int wbc_ynaddr_h; /* 0x11870 */ ++ volatile unsigned int wbc_ynaddr_l; /* 0x11874 */ ++ volatile unsigned int wbc_cnaddr_h; /* 0x11878 */ ++ volatile unsigned int wbc_cnaddr_l; /* 0x1187c */ ++ volatile reg_wbc_ynstride wbc_ynstride; /* 0x11880 */ ++ volatile reg_wbc_cnstride wbc_cnstride; /* 0x11884 */ ++ volatile unsigned int reserved_214[10]; /* 0x11888~0x118ac 10 regs */ ++ volatile reg_wbc_sta wbc_sta; /* 0x118b0 */ ++ volatile reg_wbc_line_num wbc_line_num; /* 0x118b4 */ ++ volatile reg_wbc_cap_reso wbc_cap_reso; /* 0x118b8 */ ++ volatile unsigned int wbc_cap_info; /* 0x118bc */ ++ volatile unsigned int reserved_215[16]; /* 0x118c0~0x118fc 16 regs */ ++ volatile reg_vdp_v3r2_lineseg_cmp_glb_info vdp_v3r2_lineseg_cmp_glb_info; /* 0x11900 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_frame_size vdp_v3r2_lineseg_cmp_frame_size; /* 0x11904 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg0 vdp_v3r2_lineseg_cmp_rc_cfg0; /* 0x11908 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg1 vdp_v3r2_lineseg_cmp_rc_cfg1; /* 0x1190c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2; /* 0x11910 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3; /* 0x11914 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4; /* 0x11918 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5; /* 0x1191c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6; /* 0x11920 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7; /* 0x11924 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8; /* 0x11928 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9; /* 0x1192c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10; /* 0x11930 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11; /* 0x11934 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg12 vdp_v3r2_lineseg_cmp_rc_cfg12; /* 0x11938 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg13 vdp_v3r2_lineseg_cmp_rc_cfg13; /* 0x1193c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14; /* 0x11940 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15; /* 0x11944 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0; /* 0x11948 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1; /* 0x1194c */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg16 vdp_v3r2_lineseg_cmp_rc_cfg16; /* 0x11950 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg; /* 0x11954 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_glb_st vdp_v3r2_lineseg_cmp_glb_st; /* 0x11958 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg; /* 0x1195c */ ++ volatile unsigned int reserved_216[8]; /* 0x11960~0x1197c 8 regs */ ++ volatile reg_vdp_v3r2_lineseg_cmp_glb_info_c vdp_v3r2_lineseg_cmp_glb_info_c; /* 0x11980 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_frame_size_c vdp_v3r2_lineseg_cmp_frame_size_c; /* 0x11984 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg0_c vdp_v3r2_lineseg_cmp_rc_cfg0_c; /* 0x11988 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg1_c vdp_v3r2_lineseg_cmp_rc_cfg1_c; /* 0x1198c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2_c; /* 0x11990 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3_c; /* 0x11994 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4_c; /* 0x11998 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5_c; /* 0x1199c */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6_c; /* 0x119a0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7_c; /* 0x119a4 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8_c; /* 0x119a8 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9_c; /* 0x119ac */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10_c; /* 0x119b0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11_c; /* 0x119b4 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg12_c vdp_v3r2_lineseg_cmp_rc_cfg12_c; /* 0x119b8 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg13_c vdp_v3r2_lineseg_cmp_rc_cfg13_c; /* 0x119bc */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14_c; /* 0x119c0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15_c; /* 0x119c4 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0_c; /* 0x119c8 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1_c; /* 0x119cc */ ++ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg16_c vdp_v3r2_lineseg_cmp_rc_cfg16_c; /* 0x119d0 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg_c; /* 0x119d4 */ ++ volatile reg_vdp_v3r2_lineseg_cmp_glb_st_c vdp_v3r2_lineseg_cmp_glb_st_c; /* 0x119d8 */ ++ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg_c; /* 0x119dc */ ++ volatile unsigned int reserved_217[264]; /* 0x119e0~0x11dfc 264 regs */ ++ volatile reg_wbc_cmp_ctrl wbc_cmp_ctrl; /* 0x11e00 */ ++ volatile reg_wbc_cmp_upd wbc_cmp_upd; /* 0x11e04 */ ++ volatile reg_wbc_cmp_height wbc_cmp_height; /* 0x11e08 */ ++ volatile reg_wbc_cmp_oreso wbc_cmp_oreso; /* 0x11e0c */ ++ volatile unsigned int wbc_cmp_yaddr; /* 0x11e10 */ ++ volatile unsigned int wbc_cmp_yaddr1; /* 0x11e14 */ ++ volatile unsigned int wbc_cmp_caddr; /* 0x11e18 */ ++ volatile unsigned int wbc_cmp_caddr1; /* 0x11e1c */ ++ volatile unsigned int wbc_cmp_addr0_t0; /* 0x11e20 */ ++ volatile unsigned int wbc_cmp_addr1_t0; /* 0x11e24 */ ++ volatile unsigned int wbc_cmp_addr0_t1; /* 0x11e28 */ ++ volatile unsigned int wbc_cmp_addr1_t1; /* 0x11e2c */ ++ volatile unsigned int wbc_cmp_l_fsize; /* 0x11e30 */ ++ volatile unsigned int wbc_cmp_c_fsize; /* 0x11e34 */ ++ volatile unsigned int wbc_cmp_t0_fsize; /* 0x11e38 */ ++ volatile unsigned int wbc_cmp_t1_fsize; /* 0x11e3c */ ++ volatile unsigned int wbc_sety_fsize; /* 0x11e40 */ ++ volatile unsigned int wbc_setc_fsize; /* 0x11e44 */ ++ volatile unsigned int wbc_sett0_fsize; /* 0x11e48 */ ++ volatile unsigned int wbc_sett1_fsize; /* 0x11e4c */ ++ volatile reg_wbc_od_state wbc_od_state; /* 0x11e50 */ ++ volatile unsigned int reserved_218[43]; /* 0x11e54~0x11efc 43 regs */ ++ volatile reg_od_pic_osd_glb_info od_pic_osd_glb_info; /* 0x11f00 */ ++ volatile reg_od_pic_osd_frame_size od_pic_osd_frame_size; /* 0x11f04 */ ++ volatile reg_od_pic_osd_rc_cfg0 od_pic_osd_rc_cfg0; /* 0x11f08 */ ++ volatile reg_od_pic_osd_rc_cfg1 od_pic_osd_rc_cfg1; /* 0x11f0c */ ++ volatile reg_od_pic_osd_rc_cfg2 od_pic_osd_rc_cfg2; /* 0x11f10 */ ++ volatile reg_od_pic_osd_rc_cfg3 od_pic_osd_rc_cfg3; /* 0x11f14 */ ++ volatile reg_od_pic_osd_rc_cfg4 od_pic_osd_rc_cfg4; /* 0x11f18 */ ++ volatile reg_od_pic_osd_rc_cfg5 od_pic_osd_rc_cfg5; /* 0x11f1c */ ++ volatile reg_od_pic_osd_rc_cfg6 od_pic_osd_rc_cfg6; /* 0x11f20 */ ++ volatile reg_od_pic_osd_rc_cfg7 od_pic_osd_rc_cfg7; /* 0x11f24 */ ++ volatile reg_od_pic_osd_rc_cfg8 od_pic_osd_rc_cfg8; /* 0x11f28 */ ++ volatile reg_od_pic_osd_rc_cfg9 od_pic_osd_rc_cfg9; /* 0x11f2c */ ++ volatile reg_od_pic_osd_rc_cfg10 od_pic_osd_rc_cfg10; /* 0x11f30 */ ++ volatile reg_od_pic_osd_rc_cfg11 od_pic_osd_rc_cfg11; /* 0x11f34 */ ++ volatile reg_od_pic_osd_rc_cfg12 od_pic_osd_rc_cfg12; /* 0x11f38 */ ++ volatile reg_od_pic_osd_rc_cfg13 od_pic_osd_rc_cfg13; /* 0x11f3c */ ++ volatile reg_od_pic_osd_rc_cfg14 od_pic_osd_rc_cfg14; /* 0x11f40 */ ++ volatile reg_od_pic_osd_rc_cfg15 od_pic_osd_rc_cfg15; /* 0x11f44 */ ++ volatile reg_od_pic_osd_rc_cfg16 od_pic_osd_rc_cfg16; /* 0x11f48 */ ++ volatile reg_od_pic_osd_rc_cfg17 od_pic_osd_rc_cfg17; /* 0x11f4c */ ++ volatile reg_od_pic_osd_rc_cfg18 od_pic_osd_rc_cfg18; /* 0x11f50 */ ++ volatile reg_od_pic_osd_rc_cfg19 od_pic_osd_rc_cfg19; /* 0x11f54 */ ++ volatile unsigned int reserved_219[2]; /* 0x11f58~0x11f5c 2 regs */ ++ volatile reg_od_pic_osd_stat_thr od_pic_osd_stat_thr; /* 0x11f60 */ ++ volatile reg_od_pic_osd_pcmp od_pic_osd_pcmp; /* 0x11f64 */ ++ volatile unsigned int reserved_220[6]; /* 0x11f68~0x11f7c 6 regs */ ++ volatile reg_od_pic_osd_bs_size od_pic_osd_bs_size; /* 0x11f80 */ ++ volatile reg_od_pic_osd_worst_row od_pic_osd_worst_row; /* 0x11f84 */ ++ volatile reg_od_pic_osd_best_row od_pic_osd_best_row; /* 0x11f88 */ ++ volatile reg_od_pic_osd_stat_info od_pic_osd_stat_info; /* 0x11f8c */ ++ volatile unsigned int od_pic_osd_debug0; /* 0x11f90 */ ++ volatile unsigned int od_pic_osd_debug1; /* 0x11f94 */ ++ volatile unsigned int reserved_221[26]; /* 0x11f98~0x11ffc 26 regs */ ++ volatile reg_v0_mrg_ctrl v0_mrg_ctrl; /* 0x12000 */ ++ volatile reg_v0_mrg_disp_pos v0_mrg_disp_pos; /* 0x12004 */ ++ volatile reg_v0_mrg_disp_reso v0_mrg_disp_reso; /* 0x12008 */ ++ volatile reg_v0_mrg_src_reso v0_mrg_src_reso; /* 0x1200c */ ++ volatile reg_v0_mrg_src_offset v0_mrg_src_offset; /* 0x12010 */ ++ volatile unsigned int v0_mrg_y_addr; /* 0x12014 */ ++ volatile unsigned int v0_mrg_c_addr; /* 0x12018 */ ++ volatile reg_v0_mrg_stride v0_mrg_stride; /* 0x1201c */ ++ volatile unsigned int v0_mrg_yh_addr; /* 0x12020 */ ++ volatile unsigned int v0_mrg_ch_addr; /* 0x12024 */ ++ volatile reg_v0_mrg_hstride v0_mrg_hstride; /* 0x12028 */ ++ volatile unsigned int reserved_222[5]; /* 0x1202c~0x1203c 5 regs */ ++ volatile reg_v0_mrg_read_ctrl v0_mrg_read_ctrl; /* 0x12040 */ ++ volatile reg_v0_mrg_read_en v0_mrg_read_en; /* 0x12044 */ ++ volatile unsigned int reserved_223[750]; /* 0x12048~0x12bfc 750 regs */ ++ volatile reg_v1_mrg_ctrl v1_mrg_ctrl; /* 0x12c00 */ ++ volatile reg_v1_mrg_disp_pos v1_mrg_disp_pos; /* 0x12c04 */ ++ volatile reg_v1_mrg_disp_reso v1_mrg_disp_reso; /* 0x12c08 */ ++ volatile reg_v1_mrg_src_reso v1_mrg_src_reso; /* 0x12c0c */ ++ volatile reg_v1_mrg_src_offset v1_mrg_src_offset; /* 0x12c10 */ ++ volatile unsigned int v1_mrg_y_addr; /* 0x12c14 */ ++ volatile unsigned int v1_mrg_c_addr; /* 0x12c18 */ ++ volatile reg_v1_mrg_stride v1_mrg_stride; /* 0x12c1c */ ++ volatile unsigned int v1_mrg_yh_addr; /* 0x12c20 */ ++ volatile unsigned int v1_mrg_ch_addr; /* 0x12c24 */ ++ volatile reg_v1_mrg_hstride v1_mrg_hstride; /* 0x12c28 */ ++ volatile unsigned int reserved_224[5]; /* 0x12c2c~0x12c3c 5 regs */ ++ volatile reg_v1_mrg_read_ctrl v1_mrg_read_ctrl; /* 0x12c40 */ ++ volatile reg_v1_mrg_read_en v1_mrg_read_en; /* 0x12c44 */ ++ volatile unsigned int reserved_225[1262]; /* 0x12c48~0x13ffc 1262 regs */ ++ volatile reg_g1_osb_ctrl1_box_0 g1_osb_ctrl1_box_0; /* 0x14000 */ ++ volatile reg_g1_osb_ctrl2_box_0 g1_osb_ctrl2_box_0; /* 0x14004 */ ++ volatile reg_g1_osb_ctrl3_box_0 g1_osb_ctrl3_box_0; /* 0x14008 */ ++ volatile unsigned int reserved_226[509]; /* 0x1400c~0x147fc 509 regs */ ++ volatile reg_g3_osb_ctrl1_box_0 g3_osb_ctrl1_box_0; /* 0x14800 */ ++ volatile reg_g3_osb_ctrl2_box_0 g3_osb_ctrl2_box_0; /* 0x14804 */ ++ volatile reg_g3_osb_ctrl3_box_0 g3_osb_ctrl3_box_0; /* 0x14808 */ ++ volatile unsigned int reserved_227[509]; /* 0x1480c~0x14ffc 509 regs */ ++ volatile reg_g4_osb_ctrl1_box_0 g4_osb_ctrl1_box_0; /* 0x15000 */ ++ volatile reg_g4_osb_ctrl2_box_0 g4_osb_ctrl2_box_0; /* 0x15004 */ ++ volatile reg_g4_osb_ctrl3_box_0 g4_osb_ctrl3_box_0; /* 0x15008 */ ++ volatile unsigned int reserved_228[1021]; /* 0x1500c~0x15ffc 1021 regs */ ++ volatile reg_v1_csc_idc v1_csc_idc; /* 0x16000 */ ++ volatile reg_v1_csc_odc v1_csc_odc; /* 0x16004 */ ++ volatile reg_v1_csc_iodc v1_csc_iodc; /* 0x16008 */ ++ volatile reg_v1_csc_p0 v1_csc_p0; /* 0x1600c */ ++ volatile reg_v1_csc_p1 v1_csc_p1; /* 0x16010 */ ++ volatile reg_v1_csc_p2 v1_csc_p2; /* 0x16014 */ ++ volatile reg_v1_csc_p3 v1_csc_p3; /* 0x16018 */ ++ volatile reg_v1_csc_p4 v1_csc_p4; /* 0x1601c */ ++ volatile reg_v1_csc1_idc v1_csc1_idc; /* 0x16020 */ ++ volatile reg_v1_csc1_odc v1_csc1_odc; /* 0x16024 */ ++ volatile reg_v1_csc1_iodc v1_csc1_iodc; /* 0x16028 */ ++ volatile reg_v1_csc1_p0 v1_csc1_p0; /* 0x1602c */ ++ volatile reg_v1_csc1_p1 v1_csc1_p1; /* 0x16030 */ ++ volatile reg_v1_csc1_p2 v1_csc1_p2; /* 0x16034 */ ++ volatile reg_v1_csc1_p3 v1_csc1_p3; /* 0x16038 */ ++ volatile reg_v1_csc1_p4 v1_csc1_p4; /* 0x1603c */ ++ volatile unsigned int reserved_229[48]; /* 0x16040~0x160fc 48 regs */ ++ volatile reg_v2_csc_idc v2_csc_idc; /* 0x16100 */ ++ volatile reg_v2_csc_odc v2_csc_odc; /* 0x16104 */ ++ volatile reg_v2_csc_iodc v2_csc_iodc; /* 0x16108 */ ++ volatile reg_v2_csc_p0 v2_csc_p0; /* 0x1610c */ ++ volatile reg_v2_csc_p1 v2_csc_p1; /* 0x16110 */ ++ volatile reg_v2_csc_p2 v2_csc_p2; /* 0x16114 */ ++ volatile reg_v2_csc_p3 v2_csc_p3; /* 0x16118 */ ++ volatile reg_v2_csc_p4 v2_csc_p4; /* 0x1611c */ ++ volatile reg_v2_csc1_idc v2_csc1_idc; /* 0x16120 */ ++ volatile reg_v2_csc1_odc v2_csc1_odc; /* 0x16124 */ ++ volatile reg_v2_csc1_iodc v2_csc1_iodc; /* 0x16128 */ ++ volatile reg_v2_csc1_p0 v2_csc1_p0; /* 0x1612c */ ++ volatile reg_v2_csc1_p1 v2_csc1_p1; /* 0x16130 */ ++ volatile reg_v2_csc1_p2 v2_csc1_p2; /* 0x16134 */ ++ volatile reg_v2_csc1_p3 v2_csc1_p3; /* 0x16138 */ ++ volatile reg_v2_csc1_p4 v2_csc1_p4; /* 0x1613c */ ++ volatile unsigned int reserved_230[48]; /* 0x16140~0x161fc 48 regs */ ++ volatile reg_g1_csc_idc g1_csc_idc; /* 0x16200 */ ++ volatile reg_g1_csc_odc g1_csc_odc; /* 0x16204 */ ++ volatile reg_g1_csc_iodc g1_csc_iodc; /* 0x16208 */ ++ volatile reg_g1_csc_p0 g1_csc_p0; /* 0x1620c */ ++ volatile reg_g1_csc_p1 g1_csc_p1; /* 0x16210 */ ++ volatile reg_g1_csc_p2 g1_csc_p2; /* 0x16214 */ ++ volatile reg_g1_csc_p3 g1_csc_p3; /* 0x16218 */ ++ volatile reg_g1_csc_p4 g1_csc_p4; /* 0x1621c */ ++ volatile reg_g1_csc1_idc g1_csc1_idc; /* 0x16220 */ ++ volatile reg_g1_csc1_odc g1_csc1_odc; /* 0x16224 */ ++ volatile reg_g1_csc1_iodc g1_csc1_iodc; /* 0x16228 */ ++ volatile reg_g1_csc1_p0 g1_csc1_p0; /* 0x1622c */ ++ volatile reg_g1_csc1_p1 g1_csc1_p1; /* 0x16230 */ ++ volatile reg_g1_csc1_p2 g1_csc1_p2; /* 0x16234 */ ++ volatile reg_g1_csc1_p3 g1_csc1_p3; /* 0x16238 */ ++ volatile reg_g1_csc1_p4 g1_csc1_p4; /* 0x1623c */ ++ volatile unsigned int reserved_231[48]; /* 0x16240~0x162fc 48 regs */ ++ volatile reg_g3_csc_idc g3_csc_idc; /* 0x16300 */ ++ volatile reg_g3_csc_odc g3_csc_odc; /* 0x16304 */ ++ volatile reg_g3_csc_iodc g3_csc_iodc; /* 0x16308 */ ++ volatile reg_g3_csc_p0 g3_csc_p0; /* 0x1630c */ ++ volatile reg_g3_csc_p1 g3_csc_p1; /* 0x16310 */ ++ volatile reg_g3_csc_p2 g3_csc_p2; /* 0x16314 */ ++ volatile reg_g3_csc_p3 g3_csc_p3; /* 0x16318 */ ++ volatile reg_g3_csc_p4 g3_csc_p4; /* 0x1631c */ ++ volatile reg_g3_csc1_idc g3_csc1_idc; /* 0x16320 */ ++ volatile reg_g3_csc1_odc g3_csc1_odc; /* 0x16324 */ ++ volatile reg_g3_csc1_iodc g3_csc1_iodc; /* 0x16328 */ ++ volatile reg_g3_csc1_p0 g3_csc1_p0; /* 0x1632c */ ++ volatile reg_g3_csc1_p1 g3_csc1_p1; /* 0x16330 */ ++ volatile reg_g3_csc1_p2 g3_csc1_p2; /* 0x16334 */ ++ volatile reg_g3_csc1_p3 g3_csc1_p3; /* 0x16338 */ ++ volatile reg_g3_csc1_p4 g3_csc1_p4; /* 0x1633c */ ++ volatile unsigned int reserved_232[176]; /* 0x16340~0x165fc 176 regs */ ++ volatile reg_v0_zme_hinfo v0_zme_hinfo; /* 0x16600 */ ++ volatile reg_v0_zme_hsp v0_zme_hsp; /* 0x16604 */ ++ volatile reg_v0_zme_hloffset v0_zme_hloffset; /* 0x16608 */ ++ volatile reg_v0_zme_hcoffset v0_zme_hcoffset; /* 0x1660c */ ++ volatile reg_v0_zme_hzone0delta v0_zme_hzone0delta; /* 0x16610 */ ++ volatile reg_v0_zme_hzone2delta v0_zme_hzone2delta; /* 0x16614 */ ++ volatile reg_v0_zme_hzoneend v0_zme_hzoneend; /* 0x16618 */ ++ volatile reg_v0_zme_hl_shootctrl v0_zme_hl_shootctrl; /* 0x1661c */ ++ volatile reg_v0_zme_hc_shootctrl v0_zme_hc_shootctrl; /* 0x16620 */ ++ volatile reg_v0_zme_hcoef_ren v0_zme_hcoef_ren; /* 0x16624 */ ++ volatile reg_v0_zme_hcoef_rdata v0_zme_hcoef_rdata; /* 0x16628 */ ++ volatile unsigned int reserved_233[53]; /* 0x1662c~0x166fc 53 regs */ ++ volatile reg_v0_zme_vinfo v0_zme_vinfo; /* 0x16700 */ ++ volatile reg_v0_zme_vsp v0_zme_vsp; /* 0x16704 */ ++ volatile reg_v0_zme_voffset v0_zme_voffset; /* 0x16708 */ ++ volatile reg_v0_zme_vboffset v0_zme_vboffset; /* 0x1670c */ ++ volatile unsigned int reserved_234[3]; /* 0x16710~0x16718 3 regs */ ++ volatile reg_v0_zme_vl_shootctrl v0_zme_vl_shootctrl; /* 0x1671c */ ++ volatile reg_v0_zme_vc_shootctrl v0_zme_vc_shootctrl; /* 0x16720 */ ++ volatile reg_v0_zme_vcoef_ren v0_zme_vcoef_ren; /* 0x16724 */ ++ volatile reg_v0_zme_vcoef_rdata v0_zme_vcoef_rdata; /* 0x16728 */ ++ volatile unsigned int reserved_235[533]; /* 0x1672c~0x16f7c 533 regs */ ++ volatile reg_gfx_osd_glb_info gfx_osd_glb_info; /* 0x16f80 */ ++ volatile reg_gfx_osd_frame_size gfx_osd_frame_size; /* 0x16f84 */ ++ volatile unsigned int reserved_236[2]; /* 0x16f88~0x16f8c 2 regs */ ++ volatile reg_gfx_osd_dbg_reg gfx_osd_dbg_reg; /* 0x16f90 */ ++ volatile reg_gfx_osd_dbg_reg1 gfx_osd_dbg_reg1; /* 0x16f94 */ ++} reg_vdp_regs; ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#endif /* HAL_VO_REG_H */ +diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_video.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_video.h +new file mode 100755 +index 000000000..98e167283 +--- /dev/null ++++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_video.h +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see ++ * . ++ */ ++ ++#ifndef HAL_VO_VIDEO_H ++#define HAL_VO_VIDEO_H ++ ++#include "hal_vo_video_comm.h" ++#include "ot_inner_video.h" ++ ++#ifdef __cplusplus ++#if __cplusplus ++extern "C" { ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#if vo_desc("UBOOT_VO") ++td_void hal_cbm_set_cbm_attr(hal_disp_layer layer, ot_vo_dev dev); ++td_void hal_cbm_set_cbm_bkg(hal_cbmmix mixer, const hal_disp_bkcolor *bkg); ++td_void hal_cbm_set_cbm_mixer_prio(ot_vo_layer layer, td_u8 prio, td_u8 mixer_id); ++#endif /* #if vo_desc("UBOOT_VO") */ ++ ++#if vo_desc("KERNEL_VO") ++td_void hal_write_mrg_reg(td_u32 *address, td_u32 value); ++td_u32 hal_read_mrg_reg(const td_u32 *address); ++td_u32 hal_layer_get_layer_max_area_num(hal_disp_layer layer); ++td_void hal_para_set_para_addr_vhd_chn08(td_phys_addr_t para_addr_vhd_chn08); ++#endif /* #if vo_desc("KERNEL_VO") */ ++ ++#ifdef __cplusplus ++#if __cplusplus ++} ++#endif ++#endif /* end of #ifdef __cplusplus */ ++ ++#endif /* end of HAL_VO_VIDEO_H */ diff --git a/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-support.patch b/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-support.patch index 9ae502f4..d90cc9d4 100644 --- a/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-support.patch +++ b/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/0004-kernel-drm-support.patch @@ -45,60742 +45,3 @@ index 4919595..80f4dcf 100644 svp_npu: svp_npu@0x15000000 { compatible = "vendor,svp_npu"; reg = <0x15000000 0x10000>; -diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig -index cc5a244..6c34add 100644 ---- a/drivers/gpu/drm/hisilicon/Kconfig -+++ b/drivers/gpu/drm/hisilicon/Kconfig -@@ -5,3 +5,4 @@ - - source "drivers/gpu/drm/hisilicon/hibmc/Kconfig" - source "drivers/gpu/drm/hisilicon/kirin/Kconfig" -+source "drivers/gpu/drm/hisilicon/smart_vision/Kconfig" -diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile -index 69dec60..26b3a4d 100644 ---- a/drivers/gpu/drm/hisilicon/Makefile -+++ b/drivers/gpu/drm/hisilicon/Makefile -@@ -5,3 +5,4 @@ - - obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc/ - obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/ -+obj-$(CONFIG_DRM_HISI_SMART_VISION) += smart_vision/ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/Kconfig b/drivers/gpu/drm/hisilicon/smart_vision/Kconfig -new file mode 100755 -index 0000000..2b466ee ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/Kconfig -@@ -0,0 +1,12 @@ -+config DRM_HISI_SMART_VISION -+ tristate "DRM support for SMART VISION Graphics" -+ depends on DRM && OF -+ select DRM_KMS_HELPER -+ select DRM_DISPLAY_HELPER -+ select DRM_DISPLAY_DP_HELPER -+ select DRM_DISPLAY_HDCP_HELPER -+ select DRM_DISPLAY_HDMI_HELPER -+ select DRM_GEM_DMA_HELPER -+ help -+ Choose this option if you have a Unisoc chipset. -+ If M is selected the module will be called smart_drm. -\ No newline at end of file -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/Makefile b/drivers/gpu/drm/hisilicon/smart_vision/Makefile -new file mode 100755 -index 0000000..b9f501b ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/Makefile -@@ -0,0 +1,26 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ccflags-y := -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100 -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include -+ccflags-y += -I$(srctree)/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100 -+ -+ -+ -+smart_drm-y := \ -+ smart_drm_drv.o \ -+ hi3403v100/hdmi_product_define.o \ -+ hi3403v100/regs/hdmi_reg_crg.o \ -+ ctrl/v100/regs/hdmi_reg_aon.o \ -+ ctrl/v100/regs/hdmi_reg_audio_path.o \ -+ ctrl/v100/regs/hdmi_reg_ctrl.o \ -+ ctrl/v100/regs/hdmi_reg_tx.o \ -+ ctrl/v100/regs/hdmi_reg_video_path.o \ -+ phy/v200/regs/hdmi_reg_dphy.o \ -+ smart_vo.o \ -+ smart_hdmi.o -+ -+obj-$(CONFIG_DRM_HISI_SMART_VISION) += smart_drm.o -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100/ot_defines.h b/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100/ot_defines.h -new file mode 100755 -index 0000000..01a0b46 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/base/arch/hi3403v100/include/hi3403v100/ot_defines.h -@@ -0,0 +1,42 @@ -+ -+/* For VO */ -+#define OT_VO_MAX_PHYS_DEV_NUM 2 /* max physical dev num */ -+#define OT_VO_MAX_VIRT_DEV_NUM 32 /* max virtual dev num */ -+#define OT_VO_MAX_CAS_DEV_NUM 0 /* max cascade dev num */ -+/* max dev num */ -+#define OT_VO_MAX_DEV_NUM (OT_VO_MAX_PHYS_DEV_NUM + OT_VO_MAX_VIRT_DEV_NUM + OT_VO_MAX_CAS_DEV_NUM) -+ -+#define OT_VO_VIRT_DEV_0 2 /* virtual device 0 */ -+#define OT_VO_VIRT_DEV_1 3 /* virtual device 1 */ -+#define OT_VO_VIRT_DEV_2 4 /* virtual device 2 */ -+#define OT_VO_VIRT_DEV_3 5 /* virtual device 3 */ -+ -+#define OT_VO_MAX_PHYS_VIDEO_LAYER_NUM 3 /* max physical video layer num */ -+#define OT_VO_MAX_GFX_LAYER_NUM 3 /* max graphic layer num */ -+/* max physical layer num */ -+#define OT_VO_MAX_PHYS_LAYER_NUM (OT_VO_MAX_PHYS_VIDEO_LAYER_NUM + OT_VO_MAX_GFX_LAYER_NUM) -+/* max layer num */ -+#define OT_VO_MAX_LAYER_NUM (OT_VO_MAX_PHYS_LAYER_NUM + OT_VO_MAX_VIRT_DEV_NUM + OT_VO_MAX_CAS_DEV_NUM) -+#define OT_VO_MAX_LAYER_IN_DEV 2 /* max video layer num of each dev */ -+ -+#define OT_VO_LAYER_V0 0 /* video layer 0 */ -+#define OT_VO_LAYER_V1 1 /* video layer 1 */ -+#define OT_VO_LAYER_V2 2 /* video layer 2 */ -+#define OT_VO_LAYER_G0 3 /* graphics layer 0 */ -+#define OT_VO_LAYER_G1 4 /* graphics layer 1 */ -+#define OT_VO_LAYER_G3 5 /* graphics layer 3 */ -+#define ot_vo_get_virt_layer(vo_virt_dev) ((vo_virt_dev) + 4) /* get virtual layer of virtual dev */ -+ -+#define OT_VO_MAX_PRIORITY 3 /* max layer priority */ -+#define OT_VO_MIN_TOLERATE 1 /* min play toleration 1ms */ -+#define OT_VO_MAX_TOLERATE 100000 /* max play toleration 100s */ -+ -+#define OT_VO_MAX_CHN_NUM 64 /* max chn num */ -+#define OT_VO_MIN_CHN_WIDTH 32 /* channel minimal width */ -+#define OT_VO_MIN_CHN_HEIGHT 32 /* channel minimal height */ -+#define OT_VO_MAX_ZOOM_RATIO 1000 /* max zoom ratio, 1000 means 100% scale */ -+#define OT_VO_MAX_NODE_NUM 16 /* max node num */ -+ -+#define OT_VO_MAX_WBC_NUM 0 /* max wbc num */ -+#define OT_VO_MAX_IMG_WIDTH 16384 /* vo max img width */ -+#define OT_VO_MAX_IMG_HEIGHT 8192 /* vo max img height */ -\ No newline at end of file -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.c -new file mode 100755 -index 0000000..bf90d97 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.c -@@ -0,0 +1,192 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#include "hdmi_reg_aon.h" -+#include "hdmi_product_define.h" -+ -+volatile tx_aon_regs *g_tx_aon_regs = NULL; -+ -+int hdmi_reg_aon_regs_init(const char *addr) -+{ -+ g_tx_aon_regs = (volatile tx_aon_regs *)(addr + (HDMI_TX_BASE_ADDR_AON)); -+ return 0; -+} -+ -+int hdmi_reg_aon_regs_deinit(void) -+{ -+ if (g_tx_aon_regs != NULL) { -+ g_tx_aon_regs = NULL; -+ } -+ return 0; -+} -+ -+void hdmi_reg_aon_intr_mask0_set(unsigned char aon_intr_mask0) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_intr_mask mask; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_mask.u32); -+ mask.u32 = hdmi_tx_reg_read(reg_addr); -+ mask.bits.aon_intr_mask0 = aon_intr_mask0; -+ hdmi_tx_reg_write(reg_addr, mask.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aon_intr_stat1_set(unsigned char aon_intr_stat1) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_intr_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); -+ state.u32 = 0; -+ state.bits.aon_intr_stat1 = aon_intr_stat1; -+ hdmi_tx_reg_write(reg_addr, state.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aon_intr_stat0_set(unsigned char aon_intr_stat0) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_intr_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); -+ state.u32 = 0; -+ state.bits.aon_intr_stat0 = aon_intr_stat0; -+ hdmi_tx_reg_write(reg_addr, state.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dcc_man_en_set(unsigned char dcc_man_en) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_mst_ctrl ctrl; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.dcc_man_en = dcc_man_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ddc_sda_oen_set(unsigned char ddc_sda_oen) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_man_ctrl ctrl; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.ddc_sda_oen = ddc_sda_oen; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ddc_scl_oen_set(unsigned char ddc_scl_oen) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_man_ctrl ctrl; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.ddc_scl_oen = ddc_scl_oen; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_ddc_i2c_no_ack_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_mst_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->mst_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.ddc_i2c_no_ack; -+} -+ -+unsigned char hdmi_reg_ddc_i2c_bus_low_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_mst_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->mst_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.ddc_i2c_bus_low; -+} -+ -+unsigned char hdmi_reg_hpd_polarity_ctl_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ hotplug_st_cfg cfg; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->hpd_cfg.u32); -+ cfg.u32 = hdmi_tx_reg_read(reg_addr); -+ return cfg.bits.hpd_polarity_ctl; -+} -+ -+unsigned char hdmi_reg_phy_rx_sense_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.phy_rx_sense; -+} -+ -+unsigned char hdmi_reg_hotplug_state_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.hotplug_state; -+} -+ -+unsigned char hdmi_reg_aon_intr_stat1_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_intr_state state; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.aon_intr_stat1; -+} -+ -+unsigned char hdmi_reg_aon_intr_stat0_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_aon_intr_state state; -+ if (!g_tx_aon_regs) { -+ return 0; -+ } -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->aon_irq_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.aon_intr_stat0; -+} -+ -+unsigned char hdmi_reg_ddc_sda_st_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_man_ctrl ctrl; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.ddc_sda_st; -+} -+ -+unsigned char hdmi_reg_ddc_scl_st_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_man_ctrl ctrl; -+ reg_addr = (unsigned int *)&(g_tx_aon_regs->ddc_sw_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.ddc_scl_st; -+} -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.h -new file mode 100755 -index 0000000..44af4e0 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_aon.h -@@ -0,0 +1,259 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef HDMI_REG_AON_H -+#define HDMI_REG_AON_H -+ -+ -+typedef union { -+ struct { -+ unsigned int tx_hw_day : 8; /* [7:0] */ -+ unsigned int tx_hw_month : 8; /* [15:8] */ -+ unsigned int tx_hw_year : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} tx_hw_info; -+ -+typedef union { -+ struct { -+ unsigned int tx_reg_version : 8; /* [7:0] */ -+ unsigned int tx_drv_version : 8; /* [15:8] */ -+ unsigned int tx_rtl_version : 8; /* [23:16] */ -+ unsigned int rsv_0 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} tx_hw_version; -+ -+typedef union { -+ struct { -+ unsigned int rsv_1 : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} tx_hw_feature; -+ -+typedef union { -+ struct { -+ unsigned int tx_aon_soft_arst_req : 1; /* [0] */ -+ unsigned int rsv_2 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} tx_aon_rst_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int hpd_fillter_en : 1; /* [0] */ -+ unsigned int hpd_override_en : 1; /* [1] */ -+ unsigned int hpd_polarity_ctl : 1; /* [2] */ -+ unsigned int hpd_soft_value : 1; /* [3] */ -+ unsigned int osc_div_cnt : 12; /* [15:4] */ -+ unsigned int rsv_3 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} hotplug_st_cfg; -+ -+typedef union { -+ struct { -+ unsigned int hpd_high_reshold : 16; /* [15:0] */ -+ unsigned int hpd_low_reshold : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} hotplug_fillter_cfg; -+ -+typedef union { -+ struct { -+ unsigned int hotplug_state : 1; /* [0] */ -+ unsigned int phy_rx_sense : 1; /* [1] */ -+ unsigned int rsv_4 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} tx_aon_state; -+ -+typedef union { -+ struct { -+ unsigned int aon_intr_mask0 : 1; /* [0] */ -+ unsigned int aon_intr_mask1 : 1; /* [1] */ -+ unsigned int rsv_5 : 1; /* [2] */ -+ unsigned int rsv_6 : 1; /* [3] */ -+ unsigned int aon_intr_mask4 : 1; /* [4] */ -+ unsigned int aon_intr_mask5 : 1; /* [5] */ -+ unsigned int aon_intr_mask6 : 1; /* [6] */ -+ unsigned int aon_intr_mask7 : 1; /* [7] */ -+ unsigned int aon_intr_mask8 : 1; /* [8] */ -+ unsigned int aon_intr_mask9 : 1; /* [9] */ -+ unsigned int aon_intr_mask10 : 1; /* [10] */ -+ unsigned int aon_intr_mask11 : 1; /* [11] */ -+ unsigned int aon_intr_mask12 : 1; /* [12] */ -+ unsigned int aon_intr_mask13 : 1; /* [13] */ -+ unsigned int rsv_7 : 18; /* [31:14] */ -+ } bits; -+ unsigned int u32; -+} tx_aon_intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int aon_intr_stat0 : 1; /* [0] */ -+ unsigned int aon_intr_stat1 : 1; /* [1] */ -+ unsigned int rsv_8 : 1; /* [2] */ -+ unsigned int rsv_9 : 1; /* [3] */ -+ unsigned int aon_intr_stat4 : 1; /* [4] */ -+ unsigned int aon_intr_stat5 : 1; /* [5] */ -+ unsigned int aon_intr_stat6 : 1; /* [6] */ -+ unsigned int aon_intr_stat7 : 1; /* [7] */ -+ unsigned int aon_intr_stat8 : 1; /* [8] */ -+ unsigned int aon_intr_stat9 : 1; /* [9] */ -+ unsigned int aon_intr_stat10 : 1; /* [10] */ -+ unsigned int aon_intr_stat11 : 1; /* [11] */ -+ unsigned int aon_intr_stat12 : 1; /* [12] */ -+ unsigned int aon_intr_stat13 : 1; /* [13] */ -+ unsigned int rsv_10 : 18; /* [31:14] */ -+ } bits; -+ unsigned int u32; -+} tx_aon_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int ddc_aon_access : 1; /* [0] */ -+ unsigned int dcc_man_en : 1; /* [1] */ -+ unsigned int rsv_11 : 2; /* [3:2] */ -+ unsigned int ddc_speed_cnt : 9; /* [12:4] */ -+ unsigned int rsv_12 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int ddc_fifo_data_out : 8; /* [7:0] */ -+ unsigned int rsv_13 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} ddc_fifo_rdata; -+ -+typedef union { -+ struct { -+ unsigned int ddc_fifo_data_in : 8; /* [7:0] */ -+ unsigned int rsv_14 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} ddc_fifo_wdata; -+ -+typedef union { -+ struct { -+ unsigned int ddc_fifo_data_cnt : 5; /* [4:0] */ -+ unsigned int rsv_15 : 3; /* [7:5] */ -+ unsigned int ddc_data_out_cnt : 10; /* [17:8] */ -+ unsigned int rsv_16 : 14; /* [31:18] */ -+ } bits; -+ unsigned int u32; -+} ddc_data_cnt; -+ -+typedef union { -+ struct { -+ unsigned int ddc_slave_addr : 8; /* [7:0] */ -+ unsigned int ddc_slave_offset : 8; /* [15:8] */ -+ unsigned int ddc_slave_seg : 8; /* [23:16] */ -+ unsigned int rsv_17 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} ddc_slave_cfg; -+ -+typedef union { -+ struct { -+ unsigned int ddc_i2c_no_ack : 1; /* [0] */ -+ unsigned int ddc_i2c_bus_low : 1; /* [1] */ -+ unsigned int ddc_i2c_in_prog : 1; /* [2] */ -+ unsigned int ddc_fifo_wr_in_use : 1; /* [3] */ -+ unsigned int ddc_fifo_rd_in_use : 1; /* [4] */ -+ unsigned int ddc_fifo_empty : 1; /* [5] */ -+ unsigned int ddc_fifo_half_full : 1; /* [6] */ -+ unsigned int ddc_fifo_full : 1; /* [7] */ -+ unsigned int rsv_18 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_state; -+ -+typedef union { -+ struct { -+ unsigned int ddc_mst_cmd : 4; /* [3:0] */ -+ unsigned int rsv_19 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_cmd; -+ -+typedef union { -+ struct { -+ unsigned int ddc_scl_st : 1; /* [0] */ -+ unsigned int ddc_sda_st : 1; /* [1] */ -+ unsigned int ddc_scl_oen : 1; /* [2] */ -+ unsigned int ddc_sda_oen : 1; /* [3] */ -+ unsigned int rsv_20 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} ddc_man_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int ddc_clr_bus_low : 1; /* [0] */ -+ unsigned int ddc_clr_no_ack : 1; /* [1] */ -+ unsigned int rsv_21 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} ddc_state_clr; -+ -+typedef struct { -+ volatile tx_hw_info hw_info; /* 4000 */ -+ volatile tx_hw_version tx_hw_vers; /* 4004 */ -+ volatile tx_hw_feature hw_feature; /* 4008 */ -+ unsigned int reserved_0[4]; /* 400C-4018 */ -+ volatile tx_aon_rst_ctrl aon_rst; /* 401C */ -+ volatile hotplug_st_cfg hpd_cfg; /* 4020 */ -+ volatile hotplug_fillter_cfg hpd_filt_cfg; /* 4024 */ -+ volatile tx_aon_state aon_state; /* 4028 */ -+ unsigned int reserved_2[1]; /* 402C */ -+ volatile tx_aon_intr_mask aon_irq_mask; /* 4030 */ -+ volatile tx_aon_intr_state aon_irq_state; /* 4034 */ -+ unsigned int reserved_3[2]; /* 4038-403C */ -+ volatile ddc_mst_ctrl ddc_ctrl; /* 4040 */ -+ volatile ddc_fifo_rdata ddc_rdata; /* 4044 */ -+ volatile ddc_fifo_wdata ddc_wdata; /* 4048 */ -+ volatile ddc_data_cnt data_count; /* 404C */ -+ volatile ddc_slave_cfg slave_cfg; /* 4050 */ -+ volatile ddc_mst_state mst_state; /* 4054 */ -+ volatile ddc_mst_cmd mst_cmd; /* 4058 */ -+ volatile ddc_man_ctrl ddc_sw_ctrl; /* 405C */ -+ volatile ddc_state_clr state_clr; /* 4060 */ -+} tx_aon_regs; -+ -+int hdmi_reg_aon_regs_init(const char *addr); -+int hdmi_reg_aon_regs_deinit(void); -+void hdmi_reg_aon_intr_mask0_set(unsigned char aon_intr_mask0); -+void hdmi_reg_aon_intr_stat0_set(unsigned char aon_intr_stat0); -+void hdmi_reg_aon_intr_stat1_set(unsigned char aon_intr_stat1); -+void hdmi_reg_dcc_man_en_set(unsigned char dcc_man_en); -+void hdmi_reg_ddc_scl_oen_set(unsigned char ddc_scl_oen); -+void hdmi_reg_ddc_sda_oen_set(unsigned char ddc_sda_oen); -+unsigned char hdmi_reg_ddc_i2c_bus_low_get(void); -+unsigned char hdmi_reg_ddc_i2c_no_ack_get(void); -+unsigned char hdmi_reg_hpd_polarity_ctl_get(void); -+unsigned char hdmi_reg_hotplug_state_get(void); -+unsigned char hdmi_reg_phy_rx_sense_get(void); -+unsigned char hdmi_reg_aon_intr_stat0_get(void); -+unsigned char hdmi_reg_aon_intr_stat1_get(void); -+unsigned char hdmi_reg_ddc_scl_st_get(void); -+unsigned char hdmi_reg_ddc_sda_st_get(void); -+#endif /* HDMI_REG_AON_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.c -new file mode 100755 -index 0000000..2d21797 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.c -@@ -0,0 +1,462 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#include "hdmi_reg_audio_path.h" -+#include "hdmi_product_define.h" -+ -+volatile hdmi_reg_audio_path *g_audio_path_regs = NULL; -+ -+int hdmi_reg_audio_path_regs_init(const char *addr) -+{ -+ g_audio_path_regs = (volatile hdmi_reg_audio_path *)(addr + (HDMI_TX_BASE_ADDR_AUDIO)); -+ return 0; -+} -+ -+int hdmi_reg_audio_path_regs_deinit(void) -+{ -+ if (g_audio_path_regs != NULL) { -+ g_audio_path_regs = NULL; -+ } -+ return 0; -+} -+ -+void hdmi_reg_aud_spdif_en_set(unsigned char aud_spdif_en) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.aud_spdif_en = aud_spdif_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aud_i2s_en_set(unsigned char aud_i2s_en) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.aud_i2s_en = aud_i2s_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aud_layout_set(unsigned char aud_layout) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.aud_layout = aud_layout; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aud_in_en_set(unsigned char aud_in_en) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.aud_in_en = aud_in_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_ch_swap_set(unsigned char i2s_ch_swap) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_ch_swap = i2s_ch_swap; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_length_set(unsigned char i2s_length) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_length = i2s_length; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_vbit_set(unsigned char i2s_vbit) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_vbit = i2s_vbit; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_data_dir_set(unsigned char i2s_data_dir) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_data_dir = i2s_data_dir; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_justify_set(unsigned char i2s_justify) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_justify = i2s_justify; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_ws_polarity_set(unsigned char i2s_ws_polarity) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_ws_polarity = i2s_ws_polarity; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_1st_shift_set(unsigned char i2s_1st_shift) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_1st_shift = i2s_1st_shift; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_i2s_hbra_on_set(unsigned char i2s_hbra_on) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_i2s_ctrl.bits.i2s_hbra_on = i2s_hbra_on; -+ hdmi_tx_reg_write(reg_addr, aud_i2s_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_chst_byte3_clock_accuracy_set(unsigned char chst_byte3_clock_accuracy) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg0 aud_chst_cfg0; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); -+ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_chst_cfg0.bits.chst_byte3_clock_accuracy = chst_byte3_clock_accuracy; -+ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); -+ -+ return; -+} -+ -+void hdmi_reg_chst_byte3_fs_set(unsigned char chst_byte3_fs) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg0 aud_chst_cfg0; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); -+ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_chst_cfg0.bits.chst_byte3_fs = chst_byte3_fs; -+ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); -+ -+ return; -+} -+ -+void hdmi_reg_chst_byte0_bset(unsigned char chst_byte0_b) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg0 aud_chst_cfg0; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); -+ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_chst_cfg0.bits.chst_byte0_b = chst_byte0_b; -+ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); -+ -+ return; -+} -+ -+void hdmi_reg_chst_byte0_aset(unsigned char chst_byte0_a) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg0 aud_chst_cfg0; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); -+ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_chst_cfg0.bits.chst_byte0_a = chst_byte0_a; -+ hdmi_tx_reg_write(reg_addr, aud_chst_cfg0.u32); -+ -+ return; -+} -+ -+void hdmi_reg_chst_byte4_org_fs_set(unsigned char chst_byte4_org_fs) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg1 aud_chst_cfg1; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); -+ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_chst_cfg1.bits.chst_byte4_org_fs = chst_byte4_org_fs; -+ hdmi_tx_reg_write(reg_addr, aud_chst_cfg1.u32); -+ -+ return; -+} -+ -+void hdmi_reg_chst_byte4_length_set(unsigned char chst_byte4_length) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg1 aud_chst_cfg1; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); -+ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_chst_cfg1.bits.chst_byte4_length = chst_byte4_length; -+ hdmi_tx_reg_write(reg_addr, aud_chst_cfg1.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aud_fifo_hbr_mask_set(unsigned char aud_fifo_hbr_mask) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_fifo_ctrl aud_fifo_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->fifo_ctl.u32); -+ aud_fifo_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_fifo_ctrl.bits.aud_fifo_hbr_mask = aud_fifo_hbr_mask; -+ hdmi_tx_reg_write(reg_addr, aud_fifo_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aud_fifo_test_set(unsigned char aud_fifo_test) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_fifo_ctrl aud_fifo_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->fifo_ctl.u32); -+ aud_fifo_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_fifo_ctrl.bits.aud_fifo_test = aud_fifo_test; -+ hdmi_tx_reg_write(reg_addr, aud_fifo_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_acr_cts_hw_sw_sel_set(unsigned char acr_cts_hw_sw_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_acr_ctrl aud_acr_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_ctl.u32); -+ aud_acr_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ aud_acr_ctrl.bits.acr_cts_hw_sw_sel = acr_cts_hw_sw_sel; -+ hdmi_tx_reg_write(reg_addr, aud_acr_ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_acr_n_val_sw_set(unsigned int acr_n_value) -+{ -+ unsigned int *reg_addr = NULL; -+ acr_n_val_sw acr_n_val; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_sw_n.u32); -+ acr_n_val.u32 = hdmi_tx_reg_read(reg_addr); -+ acr_n_val.bits.acr_n_val_sw = acr_n_value; -+ hdmi_tx_reg_write(reg_addr, acr_n_val.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_aud_spdif_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.aud_spdif_en; -+} -+ -+unsigned char hdmi_reg_aud_i2s_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.aud_i2s_en; -+} -+ -+unsigned char hdmi_reg_aud_layout_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.aud_layout; -+} -+ -+unsigned char hdmi_reg_aud_mute_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.aud_mute_en; -+} -+ -+unsigned char hdmi_reg_aud_in_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->audio_ctl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.aud_in_en; -+} -+ -+unsigned char hdmi_reg_i2s_hbra_on_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_i2s_ctrl aud_i2s_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->i2s_ctl.u32); -+ aud_i2s_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return aud_i2s_ctrl.bits.i2s_hbra_on; -+} -+ -+unsigned char hdmi_reg_chst_byte3_fs_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg0 aud_chst_cfg0; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg0.u32); -+ aud_chst_cfg0.u32 = hdmi_tx_reg_read(reg_addr); -+ return aud_chst_cfg0.bits.chst_byte3_fs; -+} -+ -+unsigned char hdmi_reg_chst_byte4_org_fs_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg1 aud_chst_cfg1; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); -+ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); -+ return aud_chst_cfg1.bits.chst_byte4_org_fs; -+} -+ -+unsigned char hdmi_reg_chst_byte4_length_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_chst_cfg1 aud_chst_cfg1; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->chst_cfg1.u32); -+ aud_chst_cfg1.u32 = hdmi_tx_reg_read(reg_addr); -+ return aud_chst_cfg1.bits.chst_byte4_length; -+} -+ -+unsigned char hdmi_reg_aud_length_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_audio_state state; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->aud_state.u32); -+ state.u32 = hdmi_tx_reg_read(reg_addr); -+ return state.bits.aud_length; -+} -+ -+unsigned char hdmi_reg_acr_cts_hw_sw_sel_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ audio_acr_ctrl aud_acr_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_ctl.u32); -+ aud_acr_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return aud_acr_ctrl.bits.acr_cts_hw_sw_sel; -+} -+ -+unsigned int hdmi_reg_acr_n_val_sw_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ acr_n_val_sw acr_n_val; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_sw_n.u32); -+ acr_n_val.u32 = hdmi_tx_reg_read(reg_addr); -+ return acr_n_val.bits.acr_n_val_sw; -+} -+ -+unsigned int hdmi_reg_acr_cts_val_sw_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ acr_cts_val_sw acr_cts_val; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_sw_cts.u32); -+ acr_cts_val.u32 = hdmi_tx_reg_read(reg_addr); -+ return acr_cts_val.bits.acr_cts_val_sw; -+} -+ -+unsigned int hdmi_reg_acr_cts_val_hw_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ acr_cts_val_hw acr_cts_val; -+ -+ reg_addr = (unsigned int *)&(g_audio_path_regs->acr_hw_cts.u32); -+ acr_cts_val.u32 = hdmi_tx_reg_read(reg_addr); -+ return acr_cts_val.bits.acr_cts_val_hw; -+} -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.h -new file mode 100755 -index 0000000..97a0463 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.h -@@ -0,0 +1,226 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef HDMI_REG_AUDIO_PATH_H -+#define HDMI_REG_AUDIO_PATH_H -+ -+ -+typedef union { -+ struct { -+ unsigned int aud_in_en : 1; /* [0] */ -+ unsigned int aud_mute_en : 1; /* [1] */ -+ unsigned int aud_layout : 1; /* [2] */ -+ unsigned int rsv_0 : 1; /* [3] */ -+ unsigned int aud_i2s_en : 4; /* [7:4] */ -+ unsigned int aud_spdif_en : 1; /* [8] */ -+ unsigned int aud_src_en : 1; /* [9] */ -+ unsigned int aud_src_ctrl : 1; /* [10] */ -+ unsigned int rsv_1 : 1; /* [11] */ -+ unsigned int aud_fifo0_map : 2; /* [13:12] */ -+ unsigned int aud_fifo1_map : 2; /* [15:14] */ -+ unsigned int aud_fifo2_map : 2; /* [17:16] */ -+ unsigned int aud_fifo3_map : 2; /* [19:18] */ -+ unsigned int rsv_2 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} tx_audio_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int i2s_hbra_on : 1; /* [0] */ -+ unsigned int i2s_1st_shift : 1; /* [1] */ -+ unsigned int i2s_ws_polarity : 1; /* [2] */ -+ unsigned int i2s_justify : 1; /* [3] */ -+ unsigned int i2s_data_dir : 1; /* [4] */ -+ unsigned int i2s_vbit : 1; /* [5] */ -+ unsigned int rsv_3 : 2; /* [7:6] */ -+ unsigned int i2s_length : 4; /* [11:8] */ -+ unsigned int i2s_ch_swap : 4; /* [15:12] */ -+ unsigned int rsv_4 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} audio_i2s_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int spdif_1ui_lock : 1; /* [0] */ -+ unsigned int spdif_2ui_lock : 1; /* [1] */ -+ unsigned int i2s_cbit_order : 1; /* [2] */ -+ unsigned int spdif_fs_ovr_en : 1; /* [3] */ -+ unsigned int spdif_err_thresh : 6; /* [9:4] */ -+ unsigned int spdif_size_sw : 2; /* [11:10] */ -+ unsigned int spdif_1ui_max : 8; /* [19:12] */ -+ unsigned int spdif_2ui_max : 8; /* [27:20] */ -+ unsigned int rsv_5 : 4; /* [31:28] */ -+ } bits; -+ unsigned int u32; -+} audio_spdif_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int chst_byte0_a : 1; /* [0] */ -+ unsigned int chst_byte0_b : 1; /* [1] */ -+ unsigned int chst_byte0_other : 6; /* [7:2] */ -+ unsigned int chst_byte1 : 8; /* [15:8] */ -+ unsigned int chst_byte2 : 8; /* [23:16] */ -+ unsigned int chst_byte3_fs : 4; /* [27:24] */ -+ unsigned int chst_byte3_clock_accuracy : 4; /* [31:28] */ -+ } bits; -+ unsigned int u32; -+} audio_chst_cfg0; -+ -+typedef union { -+ struct { -+ unsigned int chst_byte4_length : 4; /* [3:0] */ -+ unsigned int chst_byte4_org_fs : 4; /* [7:4] */ -+ unsigned int chst_byte5_6 : 16; /* [23:8] */ -+ unsigned int rsv_6 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} audio_chst_cfg1; -+ -+typedef union { -+ struct { -+ unsigned int aud_inavailable : 1; /* [0] */ -+ unsigned int aud_spdif_new_fs : 1; /* [1] */ -+ unsigned int rsv_7 : 2; /* [3:2] */ -+ unsigned int aud_length : 4; /* [7:4] */ -+ unsigned int aud_spdif_fs : 6; /* [13:8] */ -+ unsigned int rsv_8 : 2; /* [15:14] */ -+ unsigned int spdif_max_1ui_st : 8; /* [23:16] */ -+ unsigned int spdif_max_2ui_st : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} tx_audio_state; -+ -+typedef union { -+ struct { -+ unsigned int aud_fifo_test : 5; /* [4:0] */ -+ unsigned int rsv_9 : 3; /* [7:5] */ -+ unsigned int aud_fifo_hbr_mask : 4; /* [11:8] */ -+ unsigned int rsv_10 : 4; /* [15:12] */ -+ unsigned int aud_fifo_ptr_diff : 6; /* [21:16] */ -+ unsigned int rsv_11 : 10; /* [31:22] */ -+ } bits; -+ unsigned int u32; -+} audio_fifo_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int acr_cts_req_en : 1; /* [0] */ -+ unsigned int acr_cts_hw_sw_sel : 1; /* [1] */ -+ unsigned int acr_cts_gen_sel : 1; /* [2] */ -+ unsigned int acr_cts_flt_en : 1; /* [3] */ -+ unsigned int acr_use_sw_cts : 1; /* [4] */ -+ unsigned int acr_cts_ave_en : 1; /* [5] */ -+ unsigned int rsv_12 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} audio_acr_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int acr_fm_val_sw : 3; /* [2:0] */ -+ unsigned int acr_ave_max : 5; /* [7:3] */ -+ unsigned int acr_cts_thre : 8; /* [15:8] */ -+ unsigned int acr_cts_chg_thre : 8; /* [23:16] */ -+ unsigned int rsv_13 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} audio_acr_cfg; -+ -+typedef union { -+ struct { -+ unsigned int acr_n_val_sw : 20; /* [19:0] */ -+ unsigned int rsv_14 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} acr_n_val_sw; -+ -+typedef union { -+ struct { -+ unsigned int acr_cts_val_sw : 20; /* [19:0] */ -+ unsigned int rsv_15 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} acr_cts_val_sw; -+ -+typedef union { -+ struct { -+ unsigned int acr_cts_val_hw : 20; /* [19:0] */ -+ unsigned int rsv_16 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} acr_cts_val_hw; -+ -+typedef struct { -+ volatile tx_audio_ctrl audio_ctl; /* 1000 */ -+ volatile audio_i2s_ctrl i2s_ctl; /* 1004 */ -+ volatile audio_spdif_ctrl spdif_ctl; /* 1008 */ -+ volatile audio_chst_cfg0 chst_cfg0; /* 100C */ -+ volatile audio_chst_cfg1 chst_cfg1; /* 1010 */ -+ volatile tx_audio_state aud_state; /* 1014 */ -+ volatile audio_fifo_ctrl fifo_ctl; /* 1018 */ -+ unsigned int reserved_0[9]; -+ volatile audio_acr_ctrl acr_ctl; /* 1040 */ -+ volatile audio_acr_cfg acr_cfg; /* 1044 */ -+ volatile acr_n_val_sw acr_sw_n; /* 1048 */ -+ volatile acr_cts_val_sw acr_sw_cts; /* 104C */ -+ volatile acr_cts_val_hw acr_hw_cts; /* 1050 */ -+} hdmi_reg_audio_path; -+ -+int hdmi_reg_audio_path_regs_init(const char *addr); -+int hdmi_reg_audio_path_regs_deinit(void); -+void hdmi_reg_aud_in_en_set(unsigned char aud_in_en); -+void hdmi_reg_aud_layout_set(unsigned char aud_layout); -+void hdmi_reg_aud_i2s_en_set(unsigned char aud_i2s_en); -+void hdmi_reg_aud_spdif_en_set(unsigned char aud_spdif_en); -+void hdmi_reg_i2s_hbra_on_set(unsigned char i2s_hbra_on); -+void hdmi_reg_i2s_1st_shift_set(unsigned char i2s_1st_shift); -+void hdmi_reg_i2s_ws_polarity_set(unsigned char i2s_ws_polarity); -+void hdmi_reg_i2s_justify_set(unsigned char i2s_justify); -+void hdmi_reg_i2s_data_dir_set(unsigned char i2s_data_dir); -+void hdmi_reg_i2s_vbit_set(unsigned char i2s_vbit); -+void hdmi_reg_i2s_length_set(unsigned char i2s_length); -+void hdmi_reg_i2s_ch_swap_set(unsigned char i2s_ch_swap); -+void hdmi_reg_chst_byte0_aset(unsigned char chst_byte0_a); -+void hdmi_reg_chst_byte0_bset(unsigned char chst_byte0_b); -+void hdmi_reg_chst_byte3_fs_set(unsigned char chst_byte3_fs); -+void hdmi_reg_chst_byte3_clock_accuracy_set(unsigned char chst_byte3_clock_accuracy); -+void hdmi_reg_chst_byte4_length_set(unsigned char chst_byte4_length); -+void hdmi_reg_chst_byte4_org_fs_set(unsigned char chst_byte4_org_fs); -+void hdmi_reg_aud_fifo_test_set(unsigned char aud_fifo_test); -+void hdmi_reg_aud_fifo_hbr_mask_set(unsigned char aud_fifo_hbr_mask); -+void hdmi_reg_acr_cts_hw_sw_sel_set(unsigned char acr_cts_hw_sw_sel); -+void hdmi_reg_acr_n_val_sw_set(unsigned int acr_n_value); -+unsigned char hdmi_reg_aud_in_en_get(void); -+unsigned char hdmi_reg_aud_mute_en_get(void); -+unsigned char hdmi_reg_aud_layout_get(void); -+unsigned char hdmi_reg_aud_i2s_en_get(void); -+unsigned char hdmi_reg_aud_spdif_en_get(void); -+unsigned char hdmi_reg_i2s_hbra_on_get(void); -+unsigned char hdmi_reg_chst_byte3_fs_get(void); -+unsigned char hdmi_reg_chst_byte4_length_get(void); -+unsigned char hdmi_reg_chst_byte4_org_fs_get(void); -+unsigned char hdmi_reg_aud_length_get(void); -+unsigned char hdmi_reg_acr_cts_hw_sw_sel_get(void); -+unsigned int hdmi_reg_acr_n_val_sw_get(void); -+unsigned int hdmi_reg_acr_cts_val_sw_get(void); -+unsigned int hdmi_reg_acr_cts_val_hw_get(void); -+ -+#endif /* HDMI_REG_AUDIO_PATH_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.c -new file mode 100755 -index 0000000..92741d1 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.c -@@ -0,0 +1,213 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#include "hdmi_reg_ctrl.h" -+#include "hdmi_product_define.h" -+ -+volatile hdmi_reg_tx_ctrl *g_tx_ctrl_regs = NULL; -+ -+int hdmi_reg_tx_ctrl_regs_init(const char *addr) -+{ -+ g_tx_ctrl_regs = (volatile hdmi_reg_tx_ctrl *)(addr + HDMI_TX_BASE_ADDR_CTRL); -+ return 0; -+} -+ -+int hdmi_reg_tx_ctrl_regs_deinit(void) -+{ -+ if (g_tx_ctrl_regs != NULL) { -+ g_tx_ctrl_regs = NULL; -+ } -+ return 0; -+} -+ -+void hdmi_reg_tx_afifo_srst_req_set(unsigned char tx_afifo_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pwd_rst_ctrl tx_pwd_rst; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); -+ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); -+ tx_pwd_rst.bits.tx_afifo_srst_req = tx_afifo_srst_req; -+ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); -+ -+ return; -+} -+ -+void hdmi_reg_tx_acr_srst_req_set(unsigned char tx_acr_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pwd_rst_ctrl tx_pwd_rst; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); -+ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); -+ tx_pwd_rst.bits.tx_acr_srst_req = tx_acr_srst_req; -+ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); -+ -+ return; -+} -+ -+void hdmi_reg_tx_aud_srst_req_set(unsigned char tx_aud_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pwd_rst_ctrl tx_pwd_rst; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); -+ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); -+ tx_pwd_rst.bits.tx_aud_srst_req = tx_aud_srst_req; -+ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); -+ -+ return; -+} -+ -+void hdmi_reg_tx_hdmi_srst_req_set(unsigned char tx_hdmi_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pwd_rst_ctrl tx_pwd_rst; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); -+ tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); -+ tx_pwd_rst.bits.tx_hdmi_srst_req = tx_hdmi_srst_req; -+ hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pwd_fifo_data_in_set(unsigned char pwd_fifo_data_in) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_fifo_wdata fifo_wdata; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->wdata.u32); -+ fifo_wdata.u32 = hdmi_tx_reg_read(reg_addr); -+ fifo_wdata.bits.pwd_fifo_data_in = pwd_fifo_data_in; -+ hdmi_tx_reg_write(reg_addr, fifo_wdata.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pwd_data_out_cnt_set(unsigned short pwd_data_out_cnt) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_data_cnt data_cnt; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->data_cnt.u32); -+ data_cnt.u32 = hdmi_tx_reg_read(reg_addr); -+ data_cnt.bits.pwd_data_out_cnt = pwd_data_out_cnt; -+ hdmi_tx_reg_write(reg_addr, data_cnt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pwd_slave_seg_set(unsigned char pwd_slave_seg) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_slave_cfg cfg; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->slave_cfg.u32); -+ cfg.u32 = hdmi_tx_reg_read(reg_addr); -+ cfg.bits.pwd_slave_seg = pwd_slave_seg; -+ hdmi_tx_reg_write(reg_addr, cfg.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pwd_slave_offset_set(unsigned char pwd_slave_offset) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_slave_cfg cfg; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->slave_cfg.u32); -+ cfg.u32 = hdmi_tx_reg_read(reg_addr); -+ cfg.bits.pwd_slave_offset = pwd_slave_offset; -+ hdmi_tx_reg_write(reg_addr, cfg.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pwd_slave_addr_set(unsigned char pwd_slave_addr) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_slave_cfg cfg; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->slave_cfg.u32); -+ cfg.u32 = hdmi_tx_reg_read(reg_addr); -+ cfg.bits.pwd_slave_addr = pwd_slave_addr; -+ hdmi_tx_reg_write(reg_addr, cfg.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pwd_mst_cmd_set(unsigned char mst_cmd) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_mst_cmd cmd; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->mst_cmd.u32); -+ cmd.u32 = hdmi_tx_reg_read(reg_addr); -+ cmd.bits.pwd_mst_cmd = mst_cmd; -+ hdmi_tx_reg_write(reg_addr, cmd.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cpu_ddc_req_set(unsigned char cpu_ddc_req) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_mst_arb_reql arb_req; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->ddc_arb_req.u32); -+ arb_req.u32 = hdmi_tx_reg_read(reg_addr); -+ arb_req.bits.cpu_ddc_req = cpu_ddc_req; -+ hdmi_tx_reg_write(reg_addr, arb_req.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_rdata_pwd_fifo_data_out_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_fifo_rdata fifo_rdata; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->rdata.u32); -+ fifo_rdata.u32 = hdmi_tx_reg_read(reg_addr); -+ return fifo_rdata.bits.pwd_fifo_data_out; -+} -+ -+unsigned char hdmi_reg_pwd_fifo_data_out_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_data_cnt data_cnt; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->data_cnt.u32); -+ data_cnt.u32 = hdmi_tx_reg_read(reg_addr); -+ return data_cnt.bits.pwd_fifo_data_cnt; -+} -+ -+unsigned char hdmi_reg_pwd_fifo_empty_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_mst_state mst_state; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->mst_state.u32); -+ mst_state.u32 = hdmi_tx_reg_read(reg_addr); -+ return mst_state.bits.pwd_fifo_empty; -+} -+ -+unsigned char hdmi_reg_pwd_i2c_in_prog_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ pwd_mst_state mst_state; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->mst_state.u32); -+ mst_state.u32 = hdmi_tx_reg_read(reg_addr); -+ return mst_state.bits.pwd_i2c_in_prog; -+} -+ -+unsigned char hdmi_reg_cpu_ddc_req_ack_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ ddc_mst_arb_ack arb_ack; -+ reg_addr = (unsigned int *)&(g_tx_ctrl_regs->ddc_arb_ack.u32); -+ arb_ack.u32 = hdmi_tx_reg_read(reg_addr); -+ return arb_ack.bits.cpu_ddc_req_ack; -+} -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.h -new file mode 100755 -index 0000000..024e5a2 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.h -@@ -0,0 +1,394 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef HDMI_REG_CTRL_H -+#define HDMI_REG_CTRL_H -+ -+ -+typedef union { -+ struct { -+ unsigned int tx_pwd_srst_req : 1; /* [0] */ -+ unsigned int tx_sys_srst_req : 1; /* [1] */ -+ unsigned int tx_vid_srst_req : 1; /* [2] */ -+ unsigned int tx_hdmi_srst_req : 1; /* [3] */ -+ unsigned int tx_hdcp1x_srst_req : 1; /* [4] */ -+ unsigned int tx_phy_srst_req : 1; /* [5] */ -+ unsigned int tx_aud_srst_req : 1; /* [6] */ -+ unsigned int tx_acr_srst_req : 1; /* [7] */ -+ unsigned int tx_afifo_srst_req : 1; /* [8] */ -+ unsigned int tx_hdcp2x_srst_req : 1; /* [9] */ -+ unsigned int tx_mcu_srst_req : 1; /* [10] */ -+ unsigned int rsv_0 : 21; /* [31:11] */ -+ } bits; -+ unsigned int u32; -+} tx_pwd_rst_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int scdc_ddcm_abort : 1; /* [0] */ -+ unsigned int scdc_access_en : 1; /* [1] */ -+ unsigned int scdc_auto_reply : 1; /* [2] */ -+ unsigned int scdc_auto_poll : 1; /* [3] */ -+ unsigned int scdc_auto_reply_stop : 1; /* [4] */ -+ unsigned int scdc_poll_sel : 1; /* [5] */ -+ unsigned int scdc_hdcp_det_en : 1; /* [6] */ -+ unsigned int scdc_stall_req : 1; /* [7] */ -+ unsigned int rsv_1 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} scdc_fsm_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int scdc_poll_timer : 22; /* [21:0] */ -+ unsigned int rsv_2 : 10; /* [31:22] */ -+ } bits; -+ unsigned int u32; -+} scdc_poll_timerl; -+ -+typedef union { -+ struct { -+ unsigned int scdc_fsm_state : 4; /* [3:0] */ -+ unsigned int scdc_rreq_state : 4; /* [7:4] */ -+ unsigned int scdc_active : 1; /* [8] */ -+ unsigned int scdc_in_prog : 1; /* [9] */ -+ unsigned int scdc_rreq_in_prog : 1; /* [10] */ -+ unsigned int rsv_3 : 21; /* [31:11] */ -+ } bits; -+ unsigned int u32; -+} scdc_fsm_state; -+ -+typedef union { -+ struct { -+ unsigned int scdc_flag_byte0 : 8; /* [7:0] */ -+ unsigned int scdc_flag_byte1 : 8; /* [15:8] */ -+ unsigned int rsv_4 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} scdc_flag_byte; -+ -+typedef union { -+ struct { -+ unsigned int pwd_fifo_data_out : 8; /* [7:0] */ -+ unsigned int rsv_5 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} pwd_fifo_rdata; -+ -+typedef union { -+ struct { -+ unsigned int pwd_fifo_data_in : 8; /* [7:0] */ -+ unsigned int rsv_6 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} pwd_fifo_wdata; -+ -+typedef union { -+ struct { -+ unsigned int pwd_fifo_data_cnt : 5; /* [4:0] */ -+ unsigned int rsv_7 : 3; /* [7:5] */ -+ unsigned int pwd_data_out_cnt : 10; /* [17:8] */ -+ unsigned int rsv_8 : 14; /* [31:18] */ -+ } bits; -+ unsigned int u32; -+} pwd_data_cnt; -+ -+typedef union { -+ struct { -+ unsigned int pwd_slave_addr : 8; /* [7:0] */ -+ unsigned int pwd_slave_offset : 8; /* [15:8] */ -+ unsigned int pwd_slave_seg : 8; /* [23:16] */ -+ unsigned int rsv_9 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} pwd_slave_cfg; -+ -+typedef union { -+ struct { -+ unsigned int pwd_i2c_no_ack : 1; /* [0] */ -+ unsigned int pwd_i2c_bus_low : 1; /* [1] */ -+ unsigned int pwd_i2c_in_prog : 1; /* [2] */ -+ unsigned int pwd_fifo_wr_in_use : 1; /* [3] */ -+ unsigned int pwd_fifo_rd_in_use : 1; /* [4] */ -+ unsigned int pwd_fifo_empty : 1; /* [5] */ -+ unsigned int pwd_fifo_half_full : 1; /* [6] */ -+ unsigned int pwd_fifo_full : 1; /* [7] */ -+ unsigned int rsv_10 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} pwd_mst_state; -+ -+typedef union { -+ struct { -+ unsigned int pwd_mst_cmd : 4; /* [3:0] */ -+ unsigned int rsv_11 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} pwd_mst_cmd; -+ -+typedef union { -+ struct { -+ unsigned int pwd_clr_bus_low : 1; /* [0] */ -+ unsigned int pwd_clr_no_ack : 1; /* [1] */ -+ unsigned int rsv_12 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} pwd_mst_clr; -+ -+typedef union { -+ struct { -+ unsigned int cpu_ddc_force_req : 1; /* [0] */ -+ unsigned int reg_auto_abort_en : 1; /* [1] */ -+ unsigned int rsv_13 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_arb_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int cpu_ddc_req : 1; /* [0] */ -+ unsigned int rsv_14 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_arb_reql; -+ -+typedef union { -+ struct { -+ unsigned int cpu_ddc_req_ack : 1; /* [0] */ -+ unsigned int rsv_15 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_arb_ack; -+ -+typedef union { -+ struct { -+ unsigned int ddc_arb_state : 9; /* [8:0] */ -+ unsigned int rsv_16 : 23; /* [31:9] */ -+ } bits; -+ unsigned int u32; -+} ddc_mst_arb_state; -+ -+typedef union { -+ struct { -+ unsigned int tx_pwd_intr_state : 1; /* [0] */ -+ unsigned int rsv_17 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} tx_pwd_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int tx_sys_intr_state : 1; /* [0] */ -+ unsigned int vidpath_intr_state : 1; /* [1] */ -+ unsigned int audpath_intr_state : 1; /* [2] */ -+ unsigned int txhdmi_intr_state : 1; /* [3] */ -+ unsigned int txhdcp_intr_state : 1; /* [4] */ -+ unsigned int hdcp2x_intr_state : 1; /* [5] */ -+ unsigned int rsv_18 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} pwd_sub_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int tx_sys_intr_mask : 1; /* [0] */ -+ unsigned int vidpath_intr_mask : 1; /* [1] */ -+ unsigned int audpath_intr_mask : 1; /* [2] */ -+ unsigned int txhdmi_intr_mask : 1; /* [3] */ -+ unsigned int txhdcp_intr_mask : 1; /* [4] */ -+ unsigned int hdcp2x_intr_mask : 1; /* [5] */ -+ unsigned int rsv_19 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} pwd_sub_intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int tx_sys_intr_state0 : 1; /* [0] */ -+ unsigned int tx_sys_intr_state1 : 1; /* [1] */ -+ unsigned int tx_sys_intr_state2 : 1; /* [2] */ -+ unsigned int tx_sys_intr_state3 : 1; /* [3] */ -+ unsigned int tx_sys_intr_state4 : 1; /* [4] */ -+ unsigned int tx_sys_intr_state5 : 1; /* [5] */ -+ unsigned int rsv_20 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} txsys_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int tx_sys_intr_mask0 : 1; /* [0] */ -+ unsigned int tx_sys_intr_mask1 : 1; /* [1] */ -+ unsigned int tx_sys_intr_mask2 : 1; /* [2] */ -+ unsigned int tx_sys_intr_mask3 : 1; /* [3] */ -+ unsigned int tx_sys_intr_mask4 : 1; /* [4] */ -+ unsigned int tx_sys_intr_mask5 : 1; /* [5] */ -+ unsigned int rsv_21 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} txsys_intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int vidpath_intr_state0 : 1; /* [0] */ -+ unsigned int vidpath_intr_state1 : 1; /* [1] */ -+ unsigned int vidpath_intr_state2 : 1; /* [2] */ -+ unsigned int vidpath_intr_state3 : 1; /* [3] */ -+ unsigned int vidpath_intr_state4 : 1; /* [4] */ -+ unsigned int vidpath_intr_state5 : 1; /* [5] */ -+ unsigned int vidpath_intr_state6 : 1; /* [6] */ -+ unsigned int rsv_22 : 25; /* [31:7] */ -+ } bits; -+ unsigned int u32; -+} video_path_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int vidpath_intr_mask0 : 1; /* [0] */ -+ unsigned int vidpath_intr_mask1 : 1; /* [1] */ -+ unsigned int vidpath_intr_mask2 : 1; /* [2] */ -+ unsigned int vidpath_intr_mask3 : 1; /* [3] */ -+ unsigned int vidpath_intr_mask4 : 1; /* [4] */ -+ unsigned int vidpath_intr_mask5 : 1; /* [5] */ -+ unsigned int vidpath_intr_mask6 : 1; /* [6] */ -+ unsigned int rsv_23 : 25; /* [31:7] */ -+ } bits; -+ unsigned int u32; -+} video_path_intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int audpath_intr_state0 : 1; /* [0] */ -+ unsigned int audpath_intr_state1 : 1; /* [1] */ -+ unsigned int audpath_intr_state2 : 1; /* [2] */ -+ unsigned int audpath_intr_state3 : 1; /* [3] */ -+ unsigned int audpath_intr_state4 : 1; /* [4] */ -+ unsigned int audpath_intr_state5 : 1; /* [5] */ -+ unsigned int audpath_intr_state6 : 1; /* [6] */ -+ unsigned int audpath_intr_state7 : 1; /* [7] */ -+ unsigned int audpath_intr_state8 : 1; /* [8] */ -+ unsigned int rsv_24 : 23; /* [31:9] */ -+ } bits; -+ unsigned int u32; -+} audio_path_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int audpath_intr_mask0 : 1; /* [0] */ -+ unsigned int audpath_intr_mask1 : 1; /* [1] */ -+ unsigned int audpath_intr_mask2 : 1; /* [2] */ -+ unsigned int audpath_intr_mask3 : 1; /* [3] */ -+ unsigned int audpath_intr_mask4 : 1; /* [4] */ -+ unsigned int audpath_intr_mask5 : 1; /* [5] */ -+ unsigned int audpath_intr_mask6 : 1; /* [6] */ -+ unsigned int audpath_intr_mask7 : 1; /* [7] */ -+ unsigned int audpath_intr_mask8 : 1; /* [8] */ -+ unsigned int rsv_25 : 23; /* [31:9] */ -+ } bits; -+ unsigned int u32; -+} audio_path_intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int txhdmi_intr_state0 : 1; /* [0] */ -+ unsigned int rsv_26 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} txhdmi_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int txhdmi_intr_mask0 : 1; /* [0] */ -+ unsigned int rsv_27 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} txhdmi_intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int hdcp_intr_state0 : 1; /* [0] */ -+ unsigned int hdcp_intr_state1 : 1; /* [1] */ -+ unsigned int rsv_28 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} hdcp_intr_state; -+ -+typedef union { -+ struct { -+ unsigned int hdcp_intr_mask0 : 1; /* [0] */ -+ unsigned int hdcp_intr_mask1 : 1; /* [1] */ -+ unsigned int rsv_29 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} hdcp_intr_mask; -+ -+typedef struct { -+ unsigned int reserved_0[4]; /* 0-C */ -+ volatile tx_pwd_rst_ctrl pwd_rst_ctrl; /* 10 */ -+ volatile scdc_fsm_ctrl fsm_ctrl; /* 14 */ -+ volatile scdc_poll_timerl poll_timer; /* 18 */ -+ volatile scdc_fsm_state fsm_state; /* 1C */ -+ volatile scdc_flag_byte flag; /* 20 */ -+ unsigned int reserved_1[5]; /* 0-c */ -+ volatile pwd_fifo_rdata rdata; /* 38 */ -+ volatile pwd_fifo_wdata wdata; /* 3C */ -+ volatile pwd_data_cnt data_cnt; /* 40 */ -+ volatile pwd_slave_cfg slave_cfg; /* 44 */ -+ volatile pwd_mst_state mst_state; /* 48 */ -+ volatile pwd_mst_cmd mst_cmd; /* 4C */ -+ volatile pwd_mst_clr mst_clr; /* 50 */ -+ unsigned int reserved_2[4]; /* 54-60 */ -+ volatile ddc_mst_arb_ctrl ddc_arb_ctrl; /* 64 */ -+ volatile ddc_mst_arb_reql ddc_arb_req; /* 68 */ -+ volatile ddc_mst_arb_ack ddc_arb_ack; /* 6C */ -+ volatile ddc_mst_arb_state ddc_arb_state; /* 70 */ -+ unsigned int reserved_3[35]; /* 74-FC */ -+ volatile tx_pwd_intr_state pwd_irq_state; /* 100 */ -+ volatile pwd_sub_intr_state sub_irq_state; /* 104 */ -+ volatile pwd_sub_intr_mask sub_irq_mask; /* 108 */ -+ volatile txsys_intr_state sys_irq_state; /* 10C */ -+ volatile txsys_intr_mask sys_irq_mask; /* 110 */ -+ volatile video_path_intr_state video_irq_state; /* 114 */ -+ volatile video_path_intr_mask video_irq_mask; /* 118 */ -+ volatile audio_path_intr_state audio_irq_state; /* 11C */ -+ volatile audio_path_intr_mask audio_irq_mask; /* 120 */ -+ volatile txhdmi_intr_state hdmi_irq_state; /* 124 */ -+ volatile txhdmi_intr_mask hdmi_irq_mask; /* 128 */ -+ volatile hdcp_intr_state hdcp_irq_state; /* 12C */ -+ volatile hdcp_intr_mask hdcp_irq_mask; /* 130 */ -+} hdmi_reg_tx_ctrl; -+ -+int hdmi_reg_tx_ctrl_regs_init(const char *addr); -+int hdmi_reg_tx_ctrl_regs_deinit(void); -+void hdmi_reg_tx_afifo_srst_req_set(unsigned char tx_afifo_srst_req); -+void hdmi_reg_tx_acr_srst_req_set(unsigned char tx_acr_srst_req); -+void hdmi_reg_tx_aud_srst_req_set(unsigned char tx_aud_srst_req); -+void hdmi_reg_tx_hdmi_srst_req_set(unsigned char tx_hdmi_srst_req); -+void hdmi_reg_pwd_fifo_data_in_set(unsigned char pwd_fifo_data_in); -+void hdmi_reg_pwd_data_out_cnt_set(unsigned short pwd_data_out_cnt); -+void hdmi_reg_pwd_slave_addr_set(unsigned char pwd_slave_addr); -+void hdmi_reg_pwd_slave_offset_set(unsigned char pwd_slave_offset); -+void hdmi_reg_pwd_slave_seg_set(unsigned char pwd_slave_seg); -+void hdmi_reg_pwd_mst_cmd_set(unsigned char pwd_mst_cmd); -+void hdmi_reg_cpu_ddc_req_set(unsigned char cpu_ddc_req); -+unsigned char hdmi_reg_rdata_pwd_fifo_data_out_get(void); -+unsigned char hdmi_reg_pwd_fifo_data_out_get(void); -+unsigned char hdmi_reg_pwd_i2c_in_prog_get(void); -+unsigned char hdmi_reg_pwd_fifo_empty_get(void); -+unsigned char hdmi_reg_cpu_ddc_req_ack_get(void); -+#endif /* HDMI_REG_CTRL_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.c -new file mode 100755 -index 0000000..61b8603 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.c -@@ -0,0 +1,1352 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#include "hdmi_reg_tx.h" -+#include "hdmi_product_define.h" -+ -+volatile tx_hdmi_reg_regs_type *g_tx_hdmi_regs = NULL; -+ -+int hdmi_reg_tx_hdmi_regs_init(const char *addr) -+{ -+ g_tx_hdmi_regs = (volatile tx_hdmi_reg_regs_type *)(addr + HDMI_TX_BASE_ADDR_HDMITX); -+ return 0; -+} -+ -+int hdmi_reg_tx_hdmi_regs_deinit(void) -+{ -+ if (g_tx_hdmi_regs != NULL) { -+ g_tx_hdmi_regs = NULL; -+ } -+ return 0; -+} -+ -+void hdmi_reg_tmds_pack_mode_set(unsigned char tmds_pack_mode) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pack_fifo_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.tmds_pack_mode = tmds_pack_mode; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt_header_hb_set(unsigned char hb0, unsigned char hb1, unsigned char hb2) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_pkt_header tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_pkt_hb2 = hb2; -+ tmp.bits.avi_pkt_hb1 = hb1; -+ tmp.bits.avi_pkt_hb0 = hb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt0_low_set(unsigned char avi_pkt0_pb0, unsigned char avi_pkt0_pb1, unsigned char avi_pkt0_pb2, unsigned char avi_pkt0_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt0_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt0_pb3 = avi_pkt0_pb3; -+ tmp.bits.avi_sub_pkt0_pb2 = avi_pkt0_pb2; -+ tmp.bits.avi_sub_pkt0_pb1 = avi_pkt0_pb1; -+ tmp.bits.avi_sub_pkt0_pb0 = avi_pkt0_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt0_high_set(unsigned char avi_pkt0_pb4, unsigned char avi_pkt0_pb5, unsigned char avi_pkt0_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt0_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt0_pb6 = avi_pkt0_pb6; -+ tmp.bits.avi_sub_pkt0_pb5 = avi_pkt0_pb5; -+ tmp.bits.avi_sub_pkt0_pb4 = avi_pkt0_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt1_low_set(unsigned char avi_pkt1_pb0, -+ unsigned char avi_pkt1_pb1, unsigned char avi_pkt1_pb2, unsigned char avi_pkt1_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt1_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt1_pb3 = avi_pkt1_pb3; -+ tmp.bits.avi_sub_pkt1_pb2 = avi_pkt1_pb2; -+ tmp.bits.avi_sub_pkt1_pb1 = avi_pkt1_pb1; -+ tmp.bits.avi_sub_pkt1_pb0 = avi_pkt1_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt1_high_set(unsigned char avi_pkt1_pb4, unsigned char avi_pkt1_pb5, unsigned char avi_pkt1_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt1_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt1_pb6 = avi_pkt1_pb6; -+ tmp.bits.avi_sub_pkt1_pb5 = avi_pkt1_pb5; -+ tmp.bits.avi_sub_pkt1_pb4 = avi_pkt1_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt2_low_set(unsigned char avi_pkt2_pb0, -+ unsigned char avi_pkt2_pb1, unsigned char avi_pkt2_pb2, unsigned char avi_pkt2_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt2_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt2_pb3 = avi_pkt2_pb3; -+ tmp.bits.avi_sub_pkt2_pb2 = avi_pkt2_pb2; -+ tmp.bits.avi_sub_pkt2_pb1 = avi_pkt2_pb1; -+ tmp.bits.avi_sub_pkt2_pb0 = avi_pkt2_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt2_high_set(unsigned char avi_pkt2_pb4, unsigned char avi_pkt2_pb5, unsigned char avi_pkt2_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt2_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt2_pb6 = avi_pkt2_pb6; -+ tmp.bits.avi_sub_pkt2_pb5 = avi_pkt2_pb5; -+ tmp.bits.avi_sub_pkt2_pb4 = avi_pkt2_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt3_low_set(unsigned char avi_pkt3_pb0, unsigned char avi_pkt3_pb1, unsigned char avi_pkt3_pb2, -+ unsigned char avi_pkt3_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt3_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt3_pb3 = avi_pkt3_pb3; -+ tmp.bits.avi_sub_pkt3_pb2 = avi_pkt3_pb2; -+ tmp.bits.avi_sub_pkt3_pb1 = avi_pkt3_pb1; -+ tmp.bits.avi_sub_pkt3_pb0 = avi_pkt3_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt3_high_set(unsigned char avi_pkt3_pb4, unsigned char avi_pkt3_pb5, unsigned char avi_pkt3_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt3_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.avi_sub_pkt3_pb6 = avi_pkt3_pb6; -+ tmp.bits.avi_sub_pkt3_pb5 = avi_pkt3_pb5; -+ tmp.bits.avi_sub_pkt3_pb4 = avi_pkt3_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt_header_hb_get(avi_pkt_header *avi_header) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_pkt_header tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_header->bits.avi_pkt_hb2 = tmp.bits.avi_pkt_hb2; -+ avi_header->bits.avi_pkt_hb1 = tmp.bits.avi_pkt_hb1; -+ avi_header->bits.avi_pkt_hb0 = tmp.bits.avi_pkt_hb0; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt0_low_get(avi_sub_pkt0_low *avi_pkt0_low) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt0_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt0_low->bits.avi_sub_pkt0_pb3 = tmp.bits.avi_sub_pkt0_pb3; -+ avi_pkt0_low->bits.avi_sub_pkt0_pb2 = tmp.bits.avi_sub_pkt0_pb2; -+ avi_pkt0_low->bits.avi_sub_pkt0_pb1 = tmp.bits.avi_sub_pkt0_pb1; -+ avi_pkt0_low->bits.avi_sub_pkt0_pb0 = tmp.bits.avi_sub_pkt0_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt0_high_get(avi_sub_pkt0_high *avi_pkt0_high) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt0_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt0_high->bits.avi_sub_pkt0_pb6 = tmp.bits.avi_sub_pkt0_pb6; -+ avi_pkt0_high->bits.avi_sub_pkt0_pb5 = tmp.bits.avi_sub_pkt0_pb5; -+ avi_pkt0_high->bits.avi_sub_pkt0_pb4 = tmp.bits.avi_sub_pkt0_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt1_low_get(avi_sub_pkt1_low *avi_pkt1_low) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt1_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt1_low->bits.avi_sub_pkt1_pb3 = tmp.bits.avi_sub_pkt1_pb3; -+ avi_pkt1_low->bits.avi_sub_pkt1_pb2 = tmp.bits.avi_sub_pkt1_pb2; -+ avi_pkt1_low->bits.avi_sub_pkt1_pb1 = tmp.bits.avi_sub_pkt1_pb1; -+ avi_pkt1_low->bits.avi_sub_pkt1_pb0 = tmp.bits.avi_sub_pkt1_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt1_high_get(avi_sub_pkt1_high *avi_pkt1_h) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt1_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt1_h->bits.avi_sub_pkt1_pb6 = tmp.bits.avi_sub_pkt1_pb6; -+ avi_pkt1_h->bits.avi_sub_pkt1_pb5 = tmp.bits.avi_sub_pkt1_pb5; -+ avi_pkt1_h->bits.avi_sub_pkt1_pb4 = tmp.bits.avi_sub_pkt1_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt2_low_get(avi_sub_pkt2_low *avi_pkt2_l) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt2_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt2_l->bits.avi_sub_pkt2_pb3 = tmp.bits.avi_sub_pkt2_pb3; -+ avi_pkt2_l->bits.avi_sub_pkt2_pb2 = tmp.bits.avi_sub_pkt2_pb2; -+ avi_pkt2_l->bits.avi_sub_pkt2_pb1 = tmp.bits.avi_sub_pkt2_pb1; -+ avi_pkt2_l->bits.avi_sub_pkt2_pb0 = tmp.bits.avi_sub_pkt2_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt2_high_get(avi_sub_pkt2_high *avi_pkt2_h) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt2_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt2_h->bits.avi_sub_pkt2_pb6 = tmp.bits.avi_sub_pkt2_pb6; -+ avi_pkt2_h->bits.avi_sub_pkt2_pb5 = tmp.bits.avi_sub_pkt2_pb5; -+ avi_pkt2_h->bits.avi_sub_pkt2_pb4 = tmp.bits.avi_sub_pkt2_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt3_low_get(avi_sub_pkt3_low *avi_pkt3_low) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt3_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt3_low->bits.avi_sub_pkt3_pb3 = tmp.bits.avi_sub_pkt3_pb3; -+ avi_pkt3_low->bits.avi_sub_pkt3_pb2 = tmp.bits.avi_sub_pkt3_pb2; -+ avi_pkt3_low->bits.avi_sub_pkt3_pb1 = tmp.bits.avi_sub_pkt3_pb1; -+ avi_pkt3_low->bits.avi_sub_pkt3_pb0 = tmp.bits.avi_sub_pkt3_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_avi_pkt3_high_get(avi_sub_pkt3_high *avi_pkt3_high) -+{ -+ unsigned int *reg_addr = NULL; -+ avi_sub_pkt3_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ avi_pkt3_high->bits.avi_sub_pkt3_pb6 = tmp.bits.avi_sub_pkt3_pb6; -+ avi_pkt3_high->bits.avi_sub_pkt3_pb5 = tmp.bits.avi_sub_pkt3_pb5; -+ avi_pkt3_high->bits.avi_sub_pkt3_pb4 = tmp.bits.avi_sub_pkt3_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_pkt_header tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_pkt_hb2 = hb2; -+ tmp.bits.aif_pkt_hb1 = hb1; -+ tmp.bits.aif_pkt_hb0 = hb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt0_low_set(unsigned char audio_pkt0_pb0, -+ unsigned char audio_pkt0_pb1, unsigned char audio_pkt0_pb2, unsigned char audio_pkt0_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt0_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt0_pb3 = audio_pkt0_pb3; -+ tmp.bits.aif_sub_pkt0_pb2 = audio_pkt0_pb2; -+ tmp.bits.aif_sub_pkt0_pb1 = audio_pkt0_pb1; -+ tmp.bits.aif_sub_pkt0_pb0 = audio_pkt0_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt0_high_set(unsigned char audio_pkt0_pb4, -+ unsigned char audio_pkt0_pb5, unsigned char audio_pkt0_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt0_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt0_pb6 = audio_pkt0_pb6; -+ tmp.bits.aif_sub_pkt0_pb5 = audio_pkt0_pb5; -+ tmp.bits.aif_sub_pkt0_pb4 = audio_pkt0_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt1_low_set(unsigned char audio_pkt1_pb0, -+ unsigned char audio_pkt1_pb1, unsigned char audio_pkt1_pb2, unsigned char audio_pkt1_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt1_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt1_pb3 = audio_pkt1_pb3; -+ tmp.bits.aif_sub_pkt1_pb2 = audio_pkt1_pb2; -+ tmp.bits.aif_sub_pkt1_pb1 = audio_pkt1_pb1; -+ tmp.bits.aif_sub_pkt1_pb0 = audio_pkt1_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt1_high_set(unsigned char audio_pkt1_pb4, -+ unsigned char audio_pkt1_pb5, unsigned char audio_pkt1_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt1_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt1_pb6 = audio_pkt1_pb6; -+ tmp.bits.aif_sub_pkt1_pb5 = audio_pkt1_pb5; -+ tmp.bits.aif_sub_pkt1_pb4 = audio_pkt1_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt2_low_set(unsigned char audio_pkt2_pb0, -+ unsigned char audio_pkt2_pb1, unsigned char audio_pkt2_pb2, unsigned char audio_pkt2_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt2_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt2_pb3 = audio_pkt2_pb3; -+ tmp.bits.aif_sub_pkt2_pb2 = audio_pkt2_pb2; -+ tmp.bits.aif_sub_pkt2_pb1 = audio_pkt2_pb1; -+ tmp.bits.aif_sub_pkt2_pb0 = audio_pkt2_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt2_high_set(unsigned char audio_pkt2_pb4, -+ unsigned char audio_pkt2_pb5, unsigned char audio_pkt2_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt2_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt2_pb6 = audio_pkt2_pb6; -+ tmp.bits.aif_sub_pkt2_pb5 = audio_pkt2_pb5; -+ tmp.bits.aif_sub_pkt2_pb4 = audio_pkt2_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt3_low_set(unsigned char audio_pkt3_pb0, -+ unsigned char audio_pkt3_pb1, unsigned char audio_pkt3_pb2, unsigned char audio_pkt3_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt3_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt3_pb3 = audio_pkt3_pb3; -+ tmp.bits.aif_sub_pkt3_pb2 = audio_pkt3_pb2; -+ tmp.bits.aif_sub_pkt3_pb1 = audio_pkt3_pb1; -+ tmp.bits.aif_sub_pkt3_pb0 = audio_pkt3_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_audio_pkt3_high_set(unsigned char audio_pkt3_pb4, -+ unsigned char audio_pkt3_pb5, unsigned char audio_pkt3_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt3_high tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.aif_sub_pkt3_pb6 = audio_pkt3_pb6; -+ tmp.bits.aif_sub_pkt3_pb5 = audio_pkt3_pb5; -+ tmp.bits.aif_sub_pkt3_pb4 = audio_pkt3_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt_header_get(aif_pkt_header *aif_header) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_pkt_header tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_header->bits.aif_pkt_hb2 = tmp.bits.aif_pkt_hb2; -+ aif_header->bits.aif_pkt_hb1 = tmp.bits.aif_pkt_hb1; -+ aif_header->bits.aif_pkt_hb0 = tmp.bits.aif_pkt_hb0; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt0_low_get(aif_sub_pkt0_low *aif_pkt0_low) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt0_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt0_low->bits.aif_sub_pkt0_pb3 = tmp.bits.aif_sub_pkt0_pb3; -+ aif_pkt0_low->bits.aif_sub_pkt0_pb2 = tmp.bits.aif_sub_pkt0_pb2; -+ aif_pkt0_low->bits.aif_sub_pkt0_pb1 = tmp.bits.aif_sub_pkt0_pb1; -+ aif_pkt0_low->bits.aif_sub_pkt0_pb0 = tmp.bits.aif_sub_pkt0_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt0_high_get(aif_sub_pkt0_high *aif_pkt0_high) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt0_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt0_high->bits.aif_sub_pkt0_pb6 = tmp.bits.aif_sub_pkt0_pb6; -+ aif_pkt0_high->bits.aif_sub_pkt0_pb5 = tmp.bits.aif_sub_pkt0_pb5; -+ aif_pkt0_high->bits.aif_sub_pkt0_pb4 = tmp.bits.aif_sub_pkt0_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt1_low_get(aif_sub_pkt1_low *aif_pkt1_low) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt1_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt1_low->bits.aif_sub_pkt1_pb3 = tmp.bits.aif_sub_pkt1_pb3; -+ aif_pkt1_low->bits.aif_sub_pkt1_pb2 = tmp.bits.aif_sub_pkt1_pb2; -+ aif_pkt1_low->bits.aif_sub_pkt1_pb1 = tmp.bits.aif_sub_pkt1_pb1; -+ aif_pkt1_low->bits.aif_sub_pkt1_pb0 = tmp.bits.aif_sub_pkt1_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt1_high_get(aif_sub_pkt1_high *aif_pkt1_high) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt1_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt1_high->bits.aif_sub_pkt1_pb6 = tmp.bits.aif_sub_pkt1_pb6; -+ aif_pkt1_high->bits.aif_sub_pkt1_pb5 = tmp.bits.aif_sub_pkt1_pb5; -+ aif_pkt1_high->bits.aif_sub_pkt1_pb4 = tmp.bits.aif_sub_pkt1_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt2_low_get(aif_sub_pkt2_low *aif_pkt2_low) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt2_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt2_low->bits.aif_sub_pkt2_pb3 = tmp.bits.aif_sub_pkt2_pb3; -+ aif_pkt2_low->bits.aif_sub_pkt2_pb2 = tmp.bits.aif_sub_pkt2_pb2; -+ aif_pkt2_low->bits.aif_sub_pkt2_pb1 = tmp.bits.aif_sub_pkt2_pb1; -+ aif_pkt2_low->bits.aif_sub_pkt2_pb0 = tmp.bits.aif_sub_pkt2_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt2_high_get(aif_sub_pkt2_high *aif_pkt2_high) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt2_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt2_high->bits.aif_sub_pkt2_pb6 = tmp.bits.aif_sub_pkt2_pb6; -+ aif_pkt2_high->bits.aif_sub_pkt2_pb5 = tmp.bits.aif_sub_pkt2_pb5; -+ aif_pkt2_high->bits.aif_sub_pkt2_pb4 = tmp.bits.aif_sub_pkt2_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt3_low_get(aif_sub_pkt3_low *aif_pkt3_low) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt3_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt3_low->bits.aif_sub_pkt3_pb3 = tmp.bits.aif_sub_pkt3_pb3; -+ aif_pkt3_low->bits.aif_sub_pkt3_pb2 = tmp.bits.aif_sub_pkt3_pb2; -+ aif_pkt3_low->bits.aif_sub_pkt3_pb1 = tmp.bits.aif_sub_pkt3_pb1; -+ aif_pkt3_low->bits.aif_sub_pkt3_pb0 = tmp.bits.aif_sub_pkt3_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_aif_pkt3_high_get(aif_sub_pkt3_high *aif_pkt3_high) -+{ -+ unsigned int *reg_addr = NULL; -+ aif_sub_pkt3_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aif_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ aif_pkt3_high->bits.aif_sub_pkt3_pb6 = tmp.bits.aif_sub_pkt3_pb6; -+ aif_pkt3_high->bits.aif_sub_pkt3_pb5 = tmp.bits.aif_sub_pkt3_pb5; -+ aif_pkt3_high->bits.aif_sub_pkt3_pb4 = tmp.bits.aif_sub_pkt3_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt_header_get(gamut_pkt_header *gamut_header) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_pkt_header tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_header->bits.gamut_pkt_hb2 = tmp.bits.gamut_pkt_hb2; -+ gamut_header->bits.gamut_pkt_hb1 = tmp.bits.gamut_pkt_hb1; -+ gamut_header->bits.gamut_pkt_hb0 = tmp.bits.gamut_pkt_hb0; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt0_low_get(gamut_sub_pkt0_low *gamut_pkt0_low) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt0_low tmp; -+ -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt0_low->bits.gamut_sub_pkt0_pb3 = tmp.bits.gamut_sub_pkt0_pb3; -+ gamut_pkt0_low->bits.gamut_sub_pkt0_pb2 = tmp.bits.gamut_sub_pkt0_pb2; -+ gamut_pkt0_low->bits.gamut_sub_pkt0_pb1 = tmp.bits.gamut_sub_pkt0_pb1; -+ gamut_pkt0_low->bits.gamut_sub_pkt0_pb0 = tmp.bits.gamut_sub_pkt0_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt0_high_get(gamut_sub_pkt0_high *gamut_pkt0_high) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt0_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt0_high->bits.gamut_sub_pkt0_pb6 = tmp.bits.gamut_sub_pkt0_pb6; -+ gamut_pkt0_high->bits.gamut_sub_pkt0_pb5 = tmp.bits.gamut_sub_pkt0_pb5; -+ gamut_pkt0_high->bits.gamut_sub_pkt0_pb4 = tmp.bits.gamut_sub_pkt0_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt1_low_get(gamut_sub_pkt1_low *gamut_pkt1_low) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt1_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt1_low->bits.gamut_sub_pkt1_pb3 = tmp.bits.gamut_sub_pkt1_pb3; -+ gamut_pkt1_low->bits.gamut_sub_pkt1_pb2 = tmp.bits.gamut_sub_pkt1_pb2; -+ gamut_pkt1_low->bits.gamut_sub_pkt1_pb1 = tmp.bits.gamut_sub_pkt1_pb1; -+ gamut_pkt1_low->bits.gamut_sub_pkt1_pb0 = tmp.bits.gamut_sub_pkt1_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt1_high_get(gamut_sub_pkt1_high *gamut_pkt1_high) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt1_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt1_high->bits.gamut_sub_pkt1_pb6 = tmp.bits.gamut_sub_pkt1_pb6; -+ gamut_pkt1_high->bits.gamut_sub_pkt1_pb5 = tmp.bits.gamut_sub_pkt1_pb5; -+ gamut_pkt1_high->bits.gamut_sub_pkt1_pb4 = tmp.bits.gamut_sub_pkt1_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt2_low_get(gamut_sub_pkt2_low *gamut_pkt2_low) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt2_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt2_low->bits.gamut_sub_pkt2_pb3 = tmp.bits.gamut_sub_pkt2_pb3; -+ gamut_pkt2_low->bits.gamut_sub_pkt2_pb2 = tmp.bits.gamut_sub_pkt2_pb2; -+ gamut_pkt2_low->bits.gamut_sub_pkt2_pb1 = tmp.bits.gamut_sub_pkt2_pb1; -+ gamut_pkt2_low->bits.gamut_sub_pkt2_pb0 = tmp.bits.gamut_sub_pkt2_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt2_high_get(gamut_sub_pkt2_high *gamut_pkt2_high) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt2_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt2_high->bits.gamut_sub_pkt2_pb6 = tmp.bits.gamut_sub_pkt2_pb6; -+ gamut_pkt2_high->bits.gamut_sub_pkt2_pb5 = tmp.bits.gamut_sub_pkt2_pb5; -+ gamut_pkt2_high->bits.gamut_sub_pkt2_pb4 = tmp.bits.gamut_sub_pkt2_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt3_low_get(gamut_sub_pkt3_low *gamut_pkt3_low) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt3_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt3_low->bits.gamut_sub_pkt3_pb3 = tmp.bits.gamut_sub_pkt3_pb3; -+ gamut_pkt3_low->bits.gamut_sub_pkt3_pb2 = tmp.bits.gamut_sub_pkt3_pb2; -+ gamut_pkt3_low->bits.gamut_sub_pkt3_pb1 = tmp.bits.gamut_sub_pkt3_pb1; -+ gamut_pkt3_low->bits.gamut_sub_pkt3_pb0 = tmp.bits.gamut_sub_pkt3_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_gamut_pkt3_high_get(gamut_sub_pkt3_high *gamut_pkt3_high) -+{ -+ unsigned int *reg_addr = NULL; -+ gamut_sub_pkt3_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ gamut_pkt3_high->bits.gamut_sub_pkt3_pb6 = tmp.bits.gamut_sub_pkt3_pb6; -+ gamut_pkt3_high->bits.gamut_sub_pkt3_pb5 = tmp.bits.gamut_sub_pkt3_pb5; -+ gamut_pkt3_high->bits.gamut_sub_pkt3_pb4 = tmp.bits.gamut_sub_pkt3_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_pkt_header tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_pkt_hb2 = hb2; -+ tmp.bits.vsif_pkt_hb1 = hb1; -+ tmp.bits.vsif_pkt_hb0 = hb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt0_low_set(unsigned char vsif_pkt0_pb0, -+ unsigned char vsif_pkt0_pb1, unsigned char vsif_pkt0_pb2, unsigned char vsif_pkt0_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt0_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt0_pb3 = vsif_pkt0_pb3; -+ tmp.bits.vsif_sub_pkt0_pb2 = vsif_pkt0_pb2; -+ tmp.bits.vsif_sub_pkt0_pb1 = vsif_pkt0_pb1; -+ tmp.bits.vsif_sub_pkt0_pb0 = vsif_pkt0_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt0_high_set(unsigned char vsif_pkt0_pb4, unsigned char vsif_pkt0_pb5, unsigned char vsif_pkt0_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt0_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt0_pb6 = vsif_pkt0_pb6; -+ tmp.bits.vsif_sub_pkt0_pb5 = vsif_pkt0_pb5; -+ tmp.bits.vsif_sub_pkt0_pb4 = vsif_pkt0_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt1_low_set(unsigned char vsif_pkt1_pb0, -+ unsigned char vsif_pkt1_pb1, unsigned char vsif_pkt1_pb2, unsigned char vsif_pkt1_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt1_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt1_pb3 = vsif_pkt1_pb3; -+ tmp.bits.vsif_sub_pkt1_pb2 = vsif_pkt1_pb2; -+ tmp.bits.vsif_sub_pkt1_pb1 = vsif_pkt1_pb1; -+ tmp.bits.vsif_sub_pkt1_pb0 = vsif_pkt1_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt1_high_set(unsigned char vsif_pkt1_pb4, unsigned char vsif_pkt1_pb5, unsigned char vsif_pkt1_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt1_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt1_pb6 = vsif_pkt1_pb6; -+ tmp.bits.vsif_sub_pkt1_pb5 = vsif_pkt1_pb5; -+ tmp.bits.vsif_sub_pkt1_pb4 = vsif_pkt1_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt2_low_set(unsigned char vsif_pkt2_pb0, -+ unsigned char vsif_pkt2_pb1, unsigned char vsif_pkt2_pb2, unsigned char vsif_pkt2_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt2_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt2_pb3 = vsif_pkt2_pb3; -+ tmp.bits.vsif_sub_pkt2_pb2 = vsif_pkt2_pb2; -+ tmp.bits.vsif_sub_pkt2_pb1 = vsif_pkt2_pb1; -+ tmp.bits.vsif_sub_pkt2_pb0 = vsif_pkt2_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt2_high_set(unsigned char vsif_pkt2_pb4, unsigned char vsif_pkt2_pb5, unsigned char vsif_pkt2_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt2_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt2_pb6 = vsif_pkt2_pb6; -+ tmp.bits.vsif_sub_pkt2_pb5 = vsif_pkt2_pb5; -+ tmp.bits.vsif_sub_pkt2_pb4 = vsif_pkt2_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt3_low_set(unsigned char vsif_pkt3_pb0, -+ unsigned char vsif_pkt3_pb1, unsigned char vsif_pkt3_pb2, unsigned char vsif_pkt3_pb3) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt3_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt3_pb3 = vsif_pkt3_pb3; -+ tmp.bits.vsif_sub_pkt3_pb2 = vsif_pkt3_pb2; -+ tmp.bits.vsif_sub_pkt3_pb1 = vsif_pkt3_pb1; -+ tmp.bits.vsif_sub_pkt3_pb0 = vsif_pkt3_pb0; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt3_high_set(unsigned char vsif_pkt3_pb4, unsigned char vsif_pkt3_pb5, unsigned char vsif_pkt3_pb6) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt3_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.vsif_sub_pkt3_pb6 = vsif_pkt3_pb6; -+ tmp.bits.vsif_sub_pkt3_pb5 = vsif_pkt3_pb5; -+ tmp.bits.vsif_sub_pkt3_pb4 = vsif_pkt3_pb4; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_avi_rpt_en_set(unsigned char cea_avi_rpt_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avi_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_avi_rpt_en = cea_avi_rpt_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_avi_en_set(unsigned char cea_avi_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avi_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_avi_en = cea_avi_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt_header_get(vsif_pkt_header *vsif_header) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_pkt_header tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt_head.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_header->bits.vsif_pkt_hb2 = tmp.bits.vsif_pkt_hb2; -+ vsif_header->bits.vsif_pkt_hb1 = tmp.bits.vsif_pkt_hb1; -+ vsif_header->bits.vsif_pkt_hb0 = tmp.bits.vsif_pkt_hb0; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt0_low_get(vsif_sub_pkt0_low *vsif_pkt0_low) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt0_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt0_low->bits.vsif_sub_pkt0_pb3 = tmp.bits.vsif_sub_pkt0_pb3; -+ vsif_pkt0_low->bits.vsif_sub_pkt0_pb2 = tmp.bits.vsif_sub_pkt0_pb2; -+ vsif_pkt0_low->bits.vsif_sub_pkt0_pb1 = tmp.bits.vsif_sub_pkt0_pb1; -+ vsif_pkt0_low->bits.vsif_sub_pkt0_pb0 = tmp.bits.vsif_sub_pkt0_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt0_high_get(vsif_sub_pkt0_high *vsif_pkt0_high) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt0_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt0h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt0_high->bits.vsif_sub_pkt0_pb6 = tmp.bits.vsif_sub_pkt0_pb6; -+ vsif_pkt0_high->bits.vsif_sub_pkt0_pb5 = tmp.bits.vsif_sub_pkt0_pb5; -+ vsif_pkt0_high->bits.vsif_sub_pkt0_pb4 = tmp.bits.vsif_sub_pkt0_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt1_low_get(vsif_sub_pkt1_low *vsif_pkt1_low) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt1_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt1_low->bits.vsif_sub_pkt1_pb3 = tmp.bits.vsif_sub_pkt1_pb3; -+ vsif_pkt1_low->bits.vsif_sub_pkt1_pb2 = tmp.bits.vsif_sub_pkt1_pb2; -+ vsif_pkt1_low->bits.vsif_sub_pkt1_pb1 = tmp.bits.vsif_sub_pkt1_pb1; -+ vsif_pkt1_low->bits.vsif_sub_pkt1_pb0 = tmp.bits.vsif_sub_pkt1_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt1_high_get(vsif_sub_pkt1_high *vsif_pkt1_high) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt1_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt1h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt1_high->bits.vsif_sub_pkt1_pb6 = tmp.bits.vsif_sub_pkt1_pb6; -+ vsif_pkt1_high->bits.vsif_sub_pkt1_pb5 = tmp.bits.vsif_sub_pkt1_pb5; -+ vsif_pkt1_high->bits.vsif_sub_pkt1_pb4 = tmp.bits.vsif_sub_pkt1_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt2_low_get(vsif_sub_pkt2_low *vsif_pkt2_low) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt2_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt2_low->bits.vsif_sub_pkt2_pb3 = tmp.bits.vsif_sub_pkt2_pb3; -+ vsif_pkt2_low->bits.vsif_sub_pkt2_pb2 = tmp.bits.vsif_sub_pkt2_pb2; -+ vsif_pkt2_low->bits.vsif_sub_pkt2_pb1 = tmp.bits.vsif_sub_pkt2_pb1; -+ vsif_pkt2_low->bits.vsif_sub_pkt2_pb0 = tmp.bits.vsif_sub_pkt2_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt2_high_get(vsif_sub_pkt2_high *vsif_pkt2_high) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt2_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt2h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt2_high->bits.vsif_sub_pkt2_pb6 = tmp.bits.vsif_sub_pkt2_pb6; -+ vsif_pkt2_high->bits.vsif_sub_pkt2_pb5 = tmp.bits.vsif_sub_pkt2_pb5; -+ vsif_pkt2_high->bits.vsif_sub_pkt2_pb4 = tmp.bits.vsif_sub_pkt2_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt3_low_get(vsif_sub_pkt3_low *vsif_pkt3_low) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt3_low tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3l.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt3_low->bits.vsif_sub_pkt3_pb3 = tmp.bits.vsif_sub_pkt3_pb3; -+ vsif_pkt3_low->bits.vsif_sub_pkt3_pb2 = tmp.bits.vsif_sub_pkt3_pb2; -+ vsif_pkt3_low->bits.vsif_sub_pkt3_pb1 = tmp.bits.vsif_sub_pkt3_pb1; -+ vsif_pkt3_low->bits.vsif_sub_pkt3_pb0 = tmp.bits.vsif_sub_pkt3_pb0; -+ -+ return; -+} -+ -+void hdmi_reg_vsif_pkt3_high_get(vsif_sub_pkt3_high *vsif_pkt3_high) -+{ -+ unsigned int *reg_addr = NULL; -+ vsif_sub_pkt3_high tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_pkt3h.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ vsif_pkt3_high->bits.vsif_sub_pkt3_pb6 = tmp.bits.vsif_sub_pkt3_pb6; -+ vsif_pkt3_high->bits.vsif_sub_pkt3_pb5 = tmp.bits.vsif_sub_pkt3_pb5; -+ vsif_pkt3_high->bits.vsif_sub_pkt3_pb4 = tmp.bits.vsif_sub_pkt3_pb4; -+ -+ return; -+} -+ -+void hdmi_reg_cea_aud_rpt_en_set(unsigned char cea_aud_rpt_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_aud_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aud_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_aud_rpt_en = cea_aud_rpt_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_aud_en_set(unsigned char cea_aud_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_aud_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aud_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_aud_en = cea_aud_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_cp_rpt_cnt_set(unsigned char cea_cp_rpt_cnt) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_cp_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_cp_rpt_cnt = cea_cp_rpt_cnt; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_cp_rpt_en_set(unsigned char cea_cp_rpt_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_cp_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_cp_rpt_en = cea_cp_rpt_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_cp_en_set(unsigned char cea_cp_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_cp_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_cp_en = cea_cp_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_vsif_rpt_en_set(unsigned char cea_vsif_rpt_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_vsif_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_vsif_rpt_en = cea_vsif_rpt_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cea_vsif_en_set(unsigned char cea_vsif_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_vsif_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cea_vsif_en = cea_vsif_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dc_pkt_en_set(unsigned char dc_pkt_en) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avmixer_config tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.dc_pkt_en = dc_pkt_en; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_hdmi_mode_set(unsigned char hdmi_mode) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avmixer_config tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.hdmi_mode = hdmi_mode; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cp_clr_avmute_set(unsigned char cp_clr_avmute) -+{ -+ unsigned int *reg_addr = NULL; -+ cp_pkt_avmute tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pkt_avmute.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cp_clr_avmute = cp_clr_avmute; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_cp_set_avmute_set(unsigned char cp_set_avmute) -+{ -+ unsigned int *reg_addr = NULL; -+ cp_pkt_avmute tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pkt_avmute.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.cp_set_avmute = cp_set_avmute; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_enc_bypass_set(unsigned char enc_bypass) -+{ -+ unsigned int *reg_addr = NULL; -+ hdmi_enc_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.enc_bypass = enc_bypass; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_enc_scr_on_set(unsigned char enc_scr_on) -+{ -+ unsigned int *reg_addr = NULL; -+ hdmi_enc_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.enc_scr_on = enc_scr_on; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_enc_hdmi2_on_set(unsigned char enc_hdmi2_on) -+{ -+ unsigned int *reg_addr = NULL; -+ hdmi_enc_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ tmp.bits.enc_hdmi2_on = enc_hdmi2_on; -+ hdmi_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_tmds_pack_mode_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pack_fifo_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.tmds_pack_mode; -+} -+ -+unsigned char hdmi_reg_pclk2tclk_stable_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_pack_fifo_st tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pack_fifo_status.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.pclk2tclk_stable; -+} -+ -+unsigned char hdmi_reg_cea_avi_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avi_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avi_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.cea_avi_en; -+} -+ -+unsigned char hdmi_reg_cea_aud_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_aud_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->aud_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.cea_aud_en; -+} -+ -+unsigned char hdmi_reg_cea_cp_rpt_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_cp_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->cp_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.cea_cp_rpt_en; -+} -+ -+unsigned char hdmi_reg_cea_gamut_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_gamut_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->gamut_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.cea_gamut_en; -+} -+ -+unsigned char hdmi_reg_cea_vsif_rpt_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_vsif_cfg tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->vsif_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.cea_vsif_rpt_en; -+} -+ -+unsigned char hdmi_reg_dc_pkt_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avmixer_config tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.dc_pkt_en; -+} -+ -+unsigned char hdmi_reg_hdmi_mode_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cea_avmixer_config tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->avmixer_cfg.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.hdmi_mode; -+} -+ -+unsigned char hdmi_reg_cp_set_avmute_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ cp_pkt_avmute tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->pkt_avmute.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.cp_set_avmute; -+} -+ -+unsigned char hdmi_reg_enc_scr_on_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ hdmi_enc_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.enc_scr_on; -+} -+ -+unsigned char hdmi_reg_enc_hdmi2_on_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ hdmi_enc_ctrl tmp; -+ -+ reg_addr = (unsigned int *)&(g_tx_hdmi_regs->enc_ctrl.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.enc_hdmi2_on; -+} -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.h -new file mode 100755 -index 0000000..0062af9 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.h -@@ -0,0 +1,1482 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef HHDMI_REG_TX_H -+#define HHDMI_REG_TX_H -+ -+ -+typedef union { -+ struct { -+ unsigned int tmds_pack_mode : 2; /* [1:0] */ -+ unsigned int reg_fifo_auto_rst_en : 1; /* [2] */ -+ unsigned int reg_fifo_manu_rst : 1; /* [3] */ -+ unsigned int reg_clock_det_en : 1; /* [4] */ -+ unsigned int reg_ext_tmds_para : 1; /* [5] */ -+ unsigned int rsv_0 : 2; /* [7:6] */ -+ unsigned int reg_fifo_delay_cnt : 8; /* [15:8] */ -+ unsigned int rsv_1 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} tx_pack_fifo_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int pclk2tclk_stable : 1; /* [0] */ -+ unsigned int rsv_2 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} tx_pack_fifo_st; -+ -+typedef union { -+ struct { -+ unsigned int reg_pclk_refer_cnt : 18; /* [17:0] */ -+ unsigned int rsv_3 : 14; /* [31:18] */ -+ } bits; -+ unsigned int u32; -+} pclk_refer_cnt; -+ -+typedef union { -+ struct { -+ unsigned int reg_tcnt_lower_threshold : 18; /* [17:0] */ -+ unsigned int rsv_4 : 14; /* [31:18] */ -+ } bits; -+ unsigned int u32; -+} tclk_lower_threshold; -+ -+typedef union { -+ struct { -+ unsigned int reg_tcnt_upper_threshold : 18; /* [17:0] */ -+ unsigned int rsv_5 : 14; /* [31:18] */ -+ } bits; -+ unsigned int u32; -+} tclk_upper_threshold; -+ -+typedef union { -+ struct { -+ unsigned int avi_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int avi_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int avi_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_6 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int avi_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_7 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int avi_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_8 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int avi_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_9 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int avi_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int avi_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int avi_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int avi_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_10 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} avi_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int aif_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int aif_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int aif_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_11 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int aif_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_12 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int aif_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_13 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int aif_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_14 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int aif_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int aif_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int aif_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int aif_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_15 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} aif_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int spd_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int spd_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int spd_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_16 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int spd_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_17 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int spd_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_18 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int spd_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_19 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int spd_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int spd_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int spd_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int spd_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_20 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} spif_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int mpeg_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int mpeg_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_21 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} speg_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int mpeg_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} speg_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_22 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} speg_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int mpeg_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} speg_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_23 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} mpeg_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int mpeg_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} mpeg_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_24 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} mpeg_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int mpeg_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} mpeg_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int mpeg_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int mpeg_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int mpeg_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_25 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} mpeg_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int gen_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int gen_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int gen_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_26 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int gen_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_27 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int gen_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_28 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int gen_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_29 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int gen_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int gen_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int gen_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int gen_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_30 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int gen2_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int gen2_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int gen2_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_31 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int gen2_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_32 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int gen2_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_33 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int gen2_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_34 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int gen2_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int gen2_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int gen2_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int gen2_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_35 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen2_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int gen3_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int gen3_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int gen3_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_36 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int gen3_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_37 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int gen3_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_38 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int gen3_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_39 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int gen3_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int gen3_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int gen3_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int gen3_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_40 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen3_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int gen4_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int gen4_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int gen4_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_41 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int gen4_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_42 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int gen4_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_43 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int gen4_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_44 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int gen4_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int gen4_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int gen4_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int gen4_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_45 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen4_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int gen5_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int gen5_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int gen5_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_46 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int gen5_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_47 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int gen5_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_48 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int gen5_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_49 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int gen5_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int gen5_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int gen5_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int gen5_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_50 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gen5_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int gamut_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int gamut_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int gamut_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_51 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int gamut_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_52 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int gamut_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_53 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int gamut_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_54 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int gamut_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int gamut_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int gamut_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int gamut_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_55 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} gamut_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int vsif_pkt_hb0 : 8; /* [7:0] */ -+ unsigned int vsif_pkt_hb1 : 8; /* [15:8] */ -+ unsigned int vsif_pkt_hb2 : 8; /* [23:16] */ -+ unsigned int rsv_56 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_pkt_header; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt0_pb0 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt0_pb1 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt0_pb2 : 8; /* [23:16] */ -+ unsigned int vsif_sub_pkt0_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt0_low; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt0_pb4 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt0_pb5 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt0_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_57 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt0_high; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt1_pb0 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt1_pb1 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt1_pb2 : 8; /* [23:16] */ -+ unsigned int vsif_sub_pkt1_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt1_low; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt1_pb4 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt1_pb5 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt1_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_58 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt1_high; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt2_pb0 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt2_pb1 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt2_pb2 : 8; /* [23:16] */ -+ unsigned int vsif_sub_pkt2_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt2_low; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt2_pb4 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt2_pb5 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt2_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_59 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt2_high; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt3_pb0 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt3_pb1 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt3_pb2 : 8; /* [23:16] */ -+ unsigned int vsif_sub_pkt3_pb3 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt3_low; -+ -+typedef union { -+ struct { -+ unsigned int vsif_sub_pkt3_pb4 : 8; /* [7:0] */ -+ unsigned int vsif_sub_pkt3_pb5 : 8; /* [15:8] */ -+ unsigned int vsif_sub_pkt3_pb6 : 8; /* [23:16] */ -+ unsigned int rsv_60 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsif_sub_pkt3_high; -+ -+typedef union { -+ struct { -+ unsigned int cea_avi_en : 1; /* [0] */ -+ unsigned int cea_avi_rpt_en : 1; /* [1] */ -+ unsigned int rsv_61 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_avi_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_spf_en : 1; /* [0] */ -+ unsigned int cea_spf_rpt_en : 1; /* [1] */ -+ unsigned int rsv_62 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_spf_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_aud_en : 1; /* [0] */ -+ unsigned int cea_aud_rpt_en : 1; /* [1] */ -+ unsigned int rsv_63 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_aud_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_mpeg_en : 1; /* [0] */ -+ unsigned int cea_mpeg_rpt_en : 1; /* [1] */ -+ unsigned int rsv_64 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_mpeg_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_gen_en : 1; /* [0] */ -+ unsigned int cea_gen_rpt_en : 1; /* [1] */ -+ unsigned int rsv_65 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_gen_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_cp_en : 1; /* [0] */ -+ unsigned int cea_cp_rpt_en : 1; /* [1] */ -+ unsigned int cea_cp_rpt_cnt : 8; /* [2:7] */ -+ unsigned int rsv_66 : 22; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} cea_cp_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_gen2_en : 1; /* [0] */ -+ unsigned int cea_gen2_rpt_en : 1; /* [1] */ -+ unsigned int rsv_67 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_gen2_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_gen3_en : 1; /* [0] */ -+ unsigned int cea_gen3_rpt_en : 1; /* [1] */ -+ unsigned int rsv_68 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_gen3_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_gen4_en : 1; /* [0] */ -+ unsigned int cea_gen4_rpt_en : 1; /* [1] */ -+ unsigned int rsv_69 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_gen4_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_gen5_en : 1; /* [0] */ -+ unsigned int cea_gen5_rpt_en : 1; /* [1] */ -+ unsigned int rsv_70 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_gen5_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_gamut_en : 1; /* [0] */ -+ unsigned int cea_gamut_rpt_en : 1; /* [1] */ -+ unsigned int rsv_71 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_gamut_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_vsif_en : 1; /* [0] */ -+ unsigned int cea_vsif_rpt_en : 1; /* [1] */ -+ unsigned int rsv_72 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cea_vsif_cfg; -+ -+typedef union { -+ struct { -+ unsigned int cea_avi_state : 1; /* [0] */ -+ unsigned int cea_aud_state : 1; /* [1] */ -+ unsigned int cea_cp_state : 1; /* [2] */ -+ unsigned int cea_gen_state : 1; /* [3] */ -+ unsigned int cea_gen2_state : 1; /* [4] */ -+ unsigned int cea_gen3_state : 1; /* [5] */ -+ unsigned int cea_gen4_state : 1; /* [6] */ -+ unsigned int cea_gen5_state : 1; /* [7] */ -+ unsigned int cea_spd_state : 1; /* [8] */ -+ unsigned int cea_mpeg_state : 1; /* [9] */ -+ unsigned int cea_gamut_state : 1; /* [10] */ -+ unsigned int cea_vsif_state : 1; /* [11] */ -+ unsigned int rsv_73 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} cea_pktf_state; -+ -+typedef union { -+ struct { -+ unsigned int hdmi_mode : 1; /* [0] */ -+ unsigned int dc_pkt_en : 1; /* [1] */ -+ unsigned int null_pkt_en : 1; /* [2] */ -+ unsigned int null_pkt_en_vs_high : 1; /* [3] */ -+ unsigned int intr_encryption : 1; /* [4] */ -+ unsigned int ovr_dc_pkt_en : 1; /* [5] */ -+ unsigned int priotity_ctl : 1; /* [6] */ -+ unsigned int pkt_bypass_mode : 1; /* [7] */ -+ unsigned int avmute_in_phase : 1; /* [8] */ -+ unsigned int hdmi_dvi_sel : 1; /* [9] */ -+ unsigned int eess_mode_en : 1; /* [10] */ -+ unsigned int rsv_74 : 21; /* [31:11] */ -+ } bits; -+ unsigned int u32; -+} cea_avmixer_config; -+ -+typedef union { -+ struct { -+ unsigned int cp_set_avmute : 1; /* [0] */ -+ unsigned int cp_clr_avmute : 1; /* [1] */ -+ unsigned int rsv_75 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} cp_pkt_avmute; -+ -+typedef union { -+ struct { -+ unsigned int video_blank : 24; /* [23:0] */ -+ unsigned int rsv_76 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} video_blank_cfg; -+ -+typedef union { -+ struct { -+ unsigned int reg_tbist_en : 1; /* [0] */ -+ unsigned int reg_tbist_syn_pol : 2; /* [2:1] */ -+ unsigned int reg_tbist_timing_sel : 6; /* [8:3] */ -+ unsigned int reg_tbist_patt_sel : 5; /* [13:9] */ -+ unsigned int rsv_77 : 18; /* [31:14] */ -+ } bits; -+ unsigned int u32; -+} tmds_bist_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int enc_hdmi2_on : 1; /* [0] */ -+ unsigned int enc_scr_on : 1; /* [1] */ -+ unsigned int enc_scr_md : 1; /* [2] */ -+ unsigned int enc_hdmi_val : 1; /* [3] */ -+ unsigned int enc_hdmi_ovr : 1; /* [4] */ -+ unsigned int enc_bypass : 1; /* [5] */ -+ unsigned int enc_ck_div_sel : 2; /* [7:6] */ -+ unsigned int rsv_78 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} hdmi_enc_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int enc_ck_sharp0 : 10; /* [9:0] */ -+ unsigned int enc_ck_sharp1 : 10; /* [19:10] */ -+ unsigned int enc_ck_sharp2 : 10; /* [29:20] */ -+ unsigned int rsv_79 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} enc_ck_sharp; -+ -+typedef struct { -+ volatile tx_pack_fifo_ctrl pack_fifo_ctrl; /* 1800 */ -+ volatile tx_pack_fifo_st pack_fifo_status; /* 1804 */ -+ volatile pclk_refer_cnt pclk_ref_cnt; /* 1808 */ -+ volatile tclk_lower_threshold lower_threshold; /* 180C */ -+ volatile tclk_upper_threshold upper_threshold; /* 1810 */ -+ unsigned int reserved_0[1]; /* 1814 */ -+ volatile avi_pkt_header avi_head; /* 1818 */ -+ volatile avi_sub_pkt0_low avi_pkt0l; /* 181C */ -+ volatile avi_sub_pkt0_high avi_pkt0h; /* 1820 */ -+ volatile avi_sub_pkt1_low avi_pkt1l; /* 1824 */ -+ volatile avi_sub_pkt1_high avi_pkt1h; /* 1828 */ -+ volatile avi_sub_pkt1_low avi_pkt2l; /* 182C */ -+ volatile avi_sub_pkt2_high avi_pkt2h; /* 1830 */ -+ volatile avi_sub_pkt3_low avi_pkt3l; /* 1834 */ -+ volatile avi_sub_pkt3_high avi_pkt3h; /* 1838 */ -+ volatile aif_pkt_header aif_pkt_head; /* 183C */ -+ volatile aif_sub_pkt0_low aif_pkt0l; /* 1840 */ -+ volatile aif_sub_pkt0_high aif_pkt0h; /* 1844 */ -+ volatile aif_sub_pkt1_low aif_pkt1l; /* 1848 */ -+ volatile aif_sub_pkt1_high aif_pkt1h; /* 184C */ -+ volatile aif_sub_pkt2_low aif_pkt2l; /* 1850 */ -+ volatile aif_sub_pkt2_high aif_pkt2h; /* 1854 */ -+ volatile aif_sub_pkt3_low aif_pkt3l; /* 1858 */ -+ volatile aif_sub_pkt3_high aif_pkt3h; /* 185C */ -+ volatile spif_pkt_header spif_pkt_head; /* 1860 */ -+ volatile spif_sub_pkt0_low spif_pkt0l; /* 1864 */ -+ volatile spif_sub_pkt0_high spif_pkt0h; /* 1868 */ -+ volatile spif_sub_pkt1_low spif_pkt1l; /* 186C */ -+ volatile spif_sub_pkt1_high spif_pkt1h; /* 1870 */ -+ volatile spif_sub_pkt2_low spif_pkt2l; /* 1874 */ -+ volatile spif_sub_pkt2_high spif_pkt2h; /* 1878 */ -+ volatile spif_sub_pkt3_low spif_pkt3l; /* 187C */ -+ volatile spif_sub_pkt3_high spif_pkt3h; /* 1880 */ -+ volatile speg_pkt_header mpeg_pkt_head; /* 1884 */ -+ volatile speg_sub_pkt0_low mpeg_pkt0l; /* 1888 */ -+ volatile speg_sub_pkt0_high mpeg_pkt0h; /* 188C */ -+ volatile speg_sub_pkt1_low mpeg_pkt1l; /* 1890 */ -+ volatile mpeg_sub_pkt1_high mpeg_pkt1h; /* 1894 */ -+ volatile mpeg_sub_pkt2_low mpeg_pkt2l; /* 1898 */ -+ volatile mpeg_sub_pkt2_high mpeg_pkt2h; /* 189C */ -+ volatile mpeg_sub_pkt3_low mpeg_pkt3l; /* 18A0 */ -+ volatile mpeg_sub_pkt3_high mpeg_pkt3h; /* 18A4 */ -+ volatile gen_pkt_header gen_pkt_head; /* 18A8 */ -+ volatile gen_sub_pkt0_low gen_pkt0l; /* 18AC */ -+ volatile gen_sub_pkt0_high gen_pkt0h; /* 18B0 */ -+ volatile gen_sub_pkt1_low gen_pkt1l; /* 18B4 */ -+ volatile gen_sub_pkt1_high gen_pkt1h; /* 18B8 */ -+ volatile gen_sub_pkt2_low gen_pkt2l; /* 18BC */ -+ volatile gen_sub_pkt2_high gen_pkt2h; /* 18C0 */ -+ volatile gen_sub_pkt3_low gen_pkt3l; /* 18C4 */ -+ volatile gen_sub_pkt3_high gen_pkt3h; /* 18C8 */ -+ volatile gen2_pkt_header gen2_pkt_head; /* 18CC */ -+ volatile gen2_sub_pkt0_low gen2_pkt0l; /* 18D0 */ -+ volatile gen2_sub_pkt0_high gen2_pkt0h; /* 18D4 */ -+ volatile gen2_sub_pkt1_low gen2_pkt1l; /* 18D8 */ -+ volatile gen2_sub_pkt1_high gen2_pkt1h; /* 18DC */ -+ volatile gen2_sub_pkt2_low gen2_pkt2l; /* 18E0 */ -+ volatile gen2_sub_pkt2_high gen2_pkt2h; /* 18E4 */ -+ volatile gen2_sub_pkt3_low gen2_pkt3l; /* 18E8 */ -+ volatile gen2_sub_pkt3_high gen2_pkt3h; /* 18EC */ -+ volatile gen3_pkt_header gen3_pkt_head; /* 18F0 */ -+ volatile gen3_sub_pkt0_low gen3_pkt0l; /* 18F4 */ -+ volatile gen3_sub_pkt0_high gen3_pkt0h; /* 18F8 */ -+ volatile gen3_sub_pkt1_low gen3_pkt1l; /* 18FC */ -+ volatile gen3_sub_pkt1_high gen3_pkt1h; /* 1900 */ -+ volatile gen3_sub_pkt2_low gen3_pkt2l; /* 1904 */ -+ volatile gen3_sub_pkt2_high gen3_pkt2h; /* 1908 */ -+ volatile gen3_sub_pkt3_low gen3_pkt3l; /* 190C */ -+ volatile gen3_sub_pkt3_high gen3_pkt3h; /* 1910 */ -+ volatile gen4_pkt_header gen4_pkt_head; /* 1914 */ -+ volatile gen4_sub_pkt0_low gen4_pkt0l; /* 1918 */ -+ volatile gen4_sub_pkt0_high gen4_pkt0h; /* 191C */ -+ volatile gen4_sub_pkt1_low gen4_pkt1l; /* 1920 */ -+ volatile gen4_sub_pkt1_high gen4_pkt1h; /* 1924 */ -+ volatile gen4_sub_pkt2_low gen4_pkt2l; /* 1928 */ -+ volatile gen4_sub_pkt2_high gen4_pkt2h; /* 192C */ -+ volatile gen4_sub_pkt3_low gen4_pkt3l; /* 1930 */ -+ volatile gen4_sub_pkt3_high gen4_pkt3h; /* 1934 */ -+ volatile gen5_pkt_header gen5_pkt_head; /* 1938 */ -+ volatile gen5_sub_pkt0_low gen5_pkt0l; /* 193C */ -+ volatile gen5_sub_pkt0_high gen5_pkt0h; /* 1940 */ -+ volatile gen5_sub_pkt1_low gen5_pkt1l; /* 1944 */ -+ volatile gen5_sub_pkt1_high gen5_pkt1h; /* 1948 */ -+ volatile gen5_sub_pkt2_low gen5_pkt2l; /* 194C */ -+ volatile gen5_sub_pkt2_high gen5_pkt2h; /* 1950 */ -+ volatile gen5_sub_pkt3_low gen5_pkt3l; /* 1954 */ -+ volatile gen5_sub_pkt3_high gen5_pkt3h; /* 1958 */ -+ volatile gamut_pkt_header gamut_pkt_head; /* 195C */ -+ volatile gamut_sub_pkt0_low gamut_pkt0l; /* 1960 */ -+ volatile gamut_sub_pkt0_high gamut_pkt0h; /* 1964 */ -+ volatile gamut_sub_pkt1_low gamut_pkt1l; /* 1968 */ -+ volatile gamut_sub_pkt1_high gamut_pkt1h; /* 196C */ -+ volatile gamut_sub_pkt2_low gamut_pkt2l; /* 1970 */ -+ volatile gamut_sub_pkt2_high gamut_pkt2h; /* 1974 */ -+ volatile gamut_sub_pkt3_low gamut_pkt3l; /* 1978 */ -+ volatile gamut_sub_pkt3_high gamut_pkt3h; /* 197C */ -+ volatile vsif_pkt_header vsif_pkt_head; /* 1980 */ -+ volatile vsif_sub_pkt0_low vsif_pkt0l; /* 1984 */ -+ volatile vsif_sub_pkt0_high vsif_pkt0h; /* 1988 */ -+ volatile vsif_sub_pkt1_low vsif_pkt1l; /* 198C */ -+ volatile vsif_sub_pkt1_high vsif_pkt1h; /* 1990 */ -+ volatile vsif_sub_pkt2_low vsif_pkt2l; /* 1994 */ -+ volatile vsif_sub_pkt2_high vsif_pkt2h; /* 1998 */ -+ volatile vsif_sub_pkt3_low vsif_pkt3l; /* 199C */ -+ volatile vsif_sub_pkt3_high vsif_pkt3h; /* 19A0 */ -+ volatile cea_avi_cfg avi_cfg; /* 19A4 */ -+ volatile cea_spf_cfg spf_cfg; /* 19A8 */ -+ volatile cea_aud_cfg aud_cfg; /* 19AC */ -+ volatile cea_mpeg_cfg mpeg_cfg; /* 19B0 */ -+ volatile cea_gen_cfg gen_cfg; /* 19B4 */ -+ volatile cea_cp_cfg cp_cfg; /* 19B8 */ -+ volatile cea_gen2_cfg gen2_cfg; /* 19BC */ -+ volatile cea_gen3_cfg gen3_cfg; /* 19C0 */ -+ volatile cea_gen4_cfg gen4_cfg; /* 19C4 */ -+ volatile cea_gen5_cfg gen5_cfg; /* 19C8 */ -+ volatile cea_gamut_cfg gamut_cfg; /* 19CC */ -+ volatile cea_vsif_cfg vsif_cfg; /* 19D0 */ -+ unsigned int reserved_1[3]; /* 19D4-19DC */ -+ volatile cea_pktf_state pkt_stats; /* 19E0 */ -+ unsigned int reserved_2[9]; /* 19E4-1A04 */ -+ volatile cea_avmixer_config avmixer_cfg; /* 1A08 */ -+ volatile cp_pkt_avmute pkt_avmute; /* 1A0C */ -+ volatile video_blank_cfg vblank_cfg; /* 1A10 */ -+ unsigned int reserved_3[16]; /* 1A14-1A50 */ -+ volatile tmds_bist_ctrl bist_ctrl; /* 1A54 */ -+ unsigned int reserved_4[2]; /* 1A58-1A5C */ -+ volatile hdmi_enc_ctrl enc_ctrl; /* 1A60 */ -+ volatile enc_ck_sharp enc_sharp; /* 1A64 */ -+} tx_hdmi_reg_regs_type; -+ -+int hdmi_reg_tx_hdmi_regs_init(const char *addr); -+int hdmi_reg_tx_hdmi_regs_deinit(void); -+void hdmi_reg_tmds_pack_mode_set(unsigned char tmds_pack_mode); -+void hdmi_reg_avi_pkt_header_hb_set(unsigned char hb0, unsigned char hb1, unsigned char hb2); -+void hdmi_reg_avi_pkt0_low_set(unsigned char avi_pkt0_pb0, unsigned char avi_pkt0_pb1, unsigned char avi_pkt0_pb2, unsigned char avi_pkt0_pb3); -+void hdmi_reg_avi_pkt0_high_set(unsigned char avi_pkt0_pb4, unsigned char avi_pkt0_pb5, unsigned char avi_pkt0_pb6); -+void hdmi_reg_avi_pkt1_low_set(unsigned char avi_pkt1_pb0, unsigned char avi_pkt1_pb1, unsigned char avi_pkt1_pb2, unsigned char avi_pkt1_pb3); -+void hdmi_reg_avi_pkt1_high_set(unsigned char avi_pkt1_pb4, unsigned char avi_pkt1_pb5, unsigned char avi_pkt1_pb6); -+void hdmi_reg_avi_pkt2_low_set(unsigned char avi_pkt2_pb0, unsigned char avi_pkt2_pb1, unsigned char avi_pkt2_pb2, unsigned char avi_pkt2_pb3); -+void hdmi_reg_avi_pkt2_high_set(unsigned char avi_pkt2_pb4, unsigned char avi_pkt2_pb5, unsigned char avi_pkt2_pb6); -+void hdmi_reg_avi_pkt3_low_set(unsigned char avi_pkt3_pb0, unsigned char avi_pkt3_pb1, unsigned char avi_pkt3_pb2, unsigned char avi_pkt3_pb3); -+void hdmi_reg_avi_pkt3_high_set(unsigned char avi_pkt3_pb4, unsigned char avi_pkt3_pb5, unsigned char avi_pkt3_pb6); -+void hdmi_reg_avi_pkt_header_hb_get(avi_pkt_header *pkt_header); -+void hdmi_reg_avi_pkt0_low_get(avi_sub_pkt0_low *sub_pkt0_low); -+void hdmi_reg_avi_pkt0_high_get(avi_sub_pkt0_high *sub_pkt0_high); -+void hdmi_reg_avi_pkt1_low_get(avi_sub_pkt1_low *sub_pkt1_low); -+void hdmi_reg_avi_pkt1_high_get(avi_sub_pkt1_high *sub_pkt1_high); -+void hdmi_reg_avi_pkt2_low_get(avi_sub_pkt2_low *sub_pkt2_low); -+void hdmi_reg_avi_pkt2_high_get(avi_sub_pkt2_high *sub_pkt2_high); -+void hdmi_reg_avi_pkt3_low_get(avi_sub_pkt3_low *sub_pkt3_low); -+void hdmi_reg_avi_pkt3_high_get(avi_sub_pkt3_high *sub_pkt3_high); -+void hdmi_reg_audio_pkt_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2); -+void hdmi_reg_audio_pkt0_low_set(unsigned char avi_pkt0_pb0, unsigned char avi_pkt0_pb1, unsigned char avi_pkt0_pb2, unsigned char avi_pkt0_pb3); -+void hdmi_reg_audio_pkt0_high_set(unsigned char avi_pkt0_pb4, unsigned char avi_pkt0_pb5, unsigned char avi_pkt0_pb6); -+void hdmi_reg_audio_pkt1_low_set(unsigned char avi_pkt1_pb0, unsigned char avi_pkt1_pb1, unsigned char avi_pkt1_pb2, unsigned char avi_pkt1_pb3); -+void hdmi_reg_audio_pkt1_high_set(unsigned char avi_pkt1_pb4, unsigned char avi_pkt1_pb5, unsigned char avi_pkt1_pb6); -+void hdmi_reg_audio_pkt2_low_set(unsigned char avi_pkt2_pb0, unsigned char avi_pkt2_pb1, unsigned char avi_pkt2_pb2, unsigned char avi_pkt2_pb3); -+void hdmi_reg_audio_pkt2_high_set(unsigned char avi_pkt2_pb4, unsigned char avi_pkt2_pb5, unsigned char avi_pkt2_pb6); -+void hdmi_reg_audio_pkt3_low_set(unsigned char avi_pkt3_pb0, unsigned char avi_pkt3_pb1, unsigned char avi_pkt3_pb2, unsigned char avi_pkt3_pb3); -+void hdmi_reg_audio_pkt3_high_set(unsigned char avi_pkt3_pb4, unsigned char avi_pkt3_pb5, unsigned char avi_pkt3_pb6); -+void hdmi_reg_aif_pkt_header_get(aif_pkt_header *pkt_header); -+void hdmi_reg_aif_pkt0_low_get(aif_sub_pkt0_low *sub_pkt0_low); -+void hdmi_reg_aif_pkt0_high_get(aif_sub_pkt0_high *sub_pkt0_high); -+void hdmi_reg_aif_pkt1_low_get(aif_sub_pkt1_low *sub_pkt1_low); -+void hdmi_reg_aif_pkt1_high_get(aif_sub_pkt1_high *sub_pkt1_high); -+void hdmi_reg_aif_pkt2_low_get(aif_sub_pkt2_low *sub_pkt2_low); -+void hdmi_reg_aif_pkt2_high_get(aif_sub_pkt2_high *sub_pkt2_high); -+void hdmi_reg_aif_pkt3_low_get(aif_sub_pkt3_low *sub_pkt3_low); -+void hdmi_reg_aif_pkt3_high_get(aif_sub_pkt3_high *sub_pkt3_high); -+void hdmi_reg_gamut_pkt_header_get(gamut_pkt_header *pkt_header); -+void hdmi_reg_gamut_pkt0_low_get(gamut_sub_pkt0_low *sub_pkt0_low); -+void hdmi_reg_gamut_pkt0_high_get(gamut_sub_pkt0_high *sub_pkt0_high); -+void hdmi_reg_gamut_pkt1_low_get(gamut_sub_pkt1_low *sub_pkt1_low); -+void hdmi_reg_gamut_pkt1_high_get(gamut_sub_pkt1_high *sub_pkt1_high); -+void hdmi_reg_gamut_pkt2_low_get(gamut_sub_pkt2_low *sub_pkt2_low); -+void hdmi_reg_gamut_pkt2_high_get(gamut_sub_pkt2_high *sub_pkt2_high); -+void hdmi_reg_gamut_pkt3_low_get(gamut_sub_pkt3_low *sub_pkt3_low); -+void hdmi_reg_gamut_pkt3_high_get(gamut_sub_pkt3_high *sub_pkt3_high); -+void hdmi_reg_vsif_header_set(unsigned char hb0, unsigned char hb1, unsigned char hb2); -+void hdmi_reg_vsif_pkt0_low_set(unsigned char vsif_pkt0_pb0, unsigned char vsif_pkt0_pb1, unsigned char vsif_pkt0_pb2, unsigned char vsif_pkt0_pb3); -+void hdmi_reg_vsif_pkt0_high_set(unsigned char vsif_pkt0_pb4, unsigned char vsif_pkt0_pb5, unsigned char vsif_pkt0_pb6); -+void hdmi_reg_vsif_pkt1_low_set(unsigned char vsif_pkt1_pb0, unsigned char vsif_pkt1_pb1, unsigned char vsif_pkt1_pb2, unsigned char vsif_pkt1_pb3); -+void hdmi_reg_vsif_pkt1_high_set(unsigned char vsif_pkt1_pb4, unsigned char vsif_pkt1_pb5, unsigned char vsif_pkt1_pb6); -+void hdmi_reg_vsif_pkt2_low_set(unsigned char vsif_pkt2_pb0, unsigned char vsif_pkt2_pb1, unsigned char vsif_pkt2_pb2, unsigned char vsif_pkt2_pb3); -+void hdmi_reg_vsif_pkt2_high_set(unsigned char vsif_pkt2_pb4, unsigned char vsif_pkt2_pb5, unsigned char vsif_pkt2_pb6); -+void hdmi_reg_vsif_pkt3_low_set(unsigned char vsif_pkt3_pb0, unsigned char vsif_pkt3_pb1, unsigned char vsif_pkt3_pb2, unsigned char vsif_pkt3_pb3); -+void hdmi_reg_vsif_pkt3_high_set(unsigned char vsif_pkt3_pb4, unsigned char vsif_pkt3_pb5, unsigned char vsif_pkt3_pb6); -+void hdmi_reg_vsif_pkt_header_get(vsif_pkt_header *pkt_header); -+void hdmi_reg_vsif_pkt0_low_get(vsif_sub_pkt0_low *sub_pkt0_low); -+void hdmi_reg_vsif_pkt0_high_get(vsif_sub_pkt0_high *sub_pkt0_high); -+void hdmi_reg_vsif_pkt1_low_get(vsif_sub_pkt1_low *sub_pkt1_low); -+void hdmi_reg_vsif_pkt1_high_get(vsif_sub_pkt1_high *sub_pkt1_high); -+void hdmi_reg_vsif_pkt2_low_get(vsif_sub_pkt2_low *sub_pkt2_low); -+void hdmi_reg_vsif_pkt2_high_get(vsif_sub_pkt2_high *sub_pkt2_high); -+void hdmi_reg_vsif_pkt3_low_get(vsif_sub_pkt3_low *sub_pkt3_low); -+void hdmi_reg_vsif_pkt3_high_get(vsif_sub_pkt3_high *sub_pkt3_high); -+void hdmi_reg_cea_avi_en_set(unsigned char cea_avi_en); -+void hdmi_reg_cea_avi_rpt_en_set(unsigned char cea_avi_rpt_en); -+void hdmi_reg_cea_aud_en_set(unsigned char cea_aud_en); -+void hdmi_reg_cea_aud_rpt_en_set(unsigned char cea_aud_rpt_en); -+void hdmi_reg_cea_cp_en_set(unsigned char cea_cp_en); -+void hdmi_reg_cea_cp_rpt_cnt_set(unsigned char cea_cp_rpt_cnt); -+void hdmi_reg_cea_cp_rpt_en_set(unsigned char cea_cp_rpt_en); -+void hdmi_reg_cea_vsif_en_set(unsigned char cea_vsif_en); -+void hdmi_reg_cea_vsif_rpt_en_set(unsigned char cea_vsif_rpt_en); -+void hdmi_reg_hdmi_mode_set(unsigned char hdmi_mode); -+void hdmi_reg_dc_pkt_en_set(unsigned char dc_pkt_en); -+void hdmi_reg_cp_set_avmute_set(unsigned char cp_set_avmute); -+void hdmi_reg_cp_clr_avmute_set(unsigned char cp_clr_avmute); -+void hdmi_reg_enc_hdmi2_on_set(unsigned char enc_hdmi2_on); -+void hdmi_reg_enc_scr_on_set(unsigned char enc_scr_on); -+void hdmi_reg_enc_bypass_set(unsigned char enc_bypass); -+unsigned char hdmi_reg_tmds_pack_mode_get(void); -+unsigned char hdmi_reg_pclk2tclk_stable_get(void); -+unsigned char hdmi_reg_cea_avi_en_get(void); -+unsigned char hdmi_reg_cea_aud_en_get(void); -+unsigned char hdmi_reg_cea_cp_rpt_en_get(void); -+unsigned char hdmi_reg_cea_gamut_en_get(void); -+unsigned char hdmi_reg_cea_vsif_rpt_en_get(void); -+unsigned char hdmi_reg_hdmi_mode_get(void); -+unsigned char hdmi_reg_dc_pkt_en_get(void); -+unsigned char hdmi_reg_cp_set_avmute_get(void); -+unsigned char hdmi_reg_enc_hdmi2_on_get(void); -+unsigned char hdmi_reg_enc_scr_on_get(void); -+#endif /* HHDMI_REG_TX_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.c b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.c -new file mode 100755 -index 0000000..9f145ac ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.c -@@ -0,0 +1,593 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#include "hdmi_reg_video_path.h" -+#include "hdmi_product_define.h" -+ -+volatile video_path_reg_regs_type *g_video_path_regs = NULL; -+ -+int hdmi_reg_video_path_regs_init(const char *addr) -+{ -+ -+ g_video_path_regs = (volatile video_path_reg_regs_type *)(addr + HDMI_TX_BASE_ADDR_VIDEO); -+ return 0; -+} -+ -+int hdmi_reg_video_path_regs_deinit(void) -+{ -+ -+ if (g_video_path_regs != NULL) { -+ g_video_path_regs = NULL; -+ } -+ return 0; -+} -+ -+int hdmi_video_path_regs_is_inited(void) -+{ -+ -+ if (g_video_path_regs == NULL) { -+ return -1; -+ } -+ return 0; -+} -+ -+void hdmi_reg_video_blank_en_set(unsigned char reg_video_blank_en) -+{ -+ unsigned int *reg_addr = NULL; -+ video_path_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->vid_path_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_video_blank_en = reg_video_blank_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_video_blank_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_path_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->vid_path_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.reg_video_blank_en; -+} -+ -+void hdmi_reg_solid_pattern_en_set(unsigned char solid_pattern_en) -+{ -+ unsigned int *reg_addr = NULL; -+ pattern_gen_ctrll pattern_gen_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->ptn_gen_ctrl.u32); -+ pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ pattern_gen_ctrl.bits.solid_pattern_en = solid_pattern_en; -+ hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_solid_pattern_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ pattern_gen_ctrll pattern_gen_ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->ptn_gen_ctrl.u32); -+ pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return pattern_gen_ctrl.bits.solid_pattern_en; -+} -+ -+void hdmi_reg_solid_pattern_cr_set(unsigned short solid_pattern_cr) -+{ -+ unsigned int *reg_addr = NULL; -+ solid_pattern_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->solid_ptn_ctrl.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.solid_pattern_cr = solid_pattern_cr; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+void hdmi_reg_solid_pattern_y_set(unsigned short solid_pattern_y) -+{ -+ unsigned int *reg_addr = NULL; -+ solid_pattern_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->solid_ptn_ctrl.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.solid_pattern_y = solid_pattern_y; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+void hdmi_reg_solid_pattern_cb_set(unsigned short solid_pattern_cb) -+{ -+ unsigned int *reg_addr = NULL; -+ solid_pattern_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->solid_ptn_ctrl.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.solid_pattern_cb = solid_pattern_cb; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fdt_status_clear_set(unsigned char fdt_status_clear) -+{ -+ unsigned int *reg_addr = NULL; -+ format_det_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_det_cfg.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.fdt_status_clear = fdt_status_clear; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sync_polarity_force_set(unsigned char sync_polarity_force) -+{ -+ unsigned int *reg_addr = NULL; -+ format_det_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_det_cfg.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.sync_polarity_force = sync_polarity_force; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_vsync_polarity_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_status status; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_status.u32); -+ status.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return status.bits.vsync_polarity; -+} -+ -+unsigned char hdmi_reg_hsync_polarity_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_status status; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_status.u32); -+ status.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return status.bits.hsync_polarity; -+} -+ -+unsigned char hdmi_reg_interlaced_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_status status; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_status.u32); -+ status.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return status.bits.interlaced; -+} -+ -+unsigned short hdmi_reg_hsync_total_cnt_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_hori_res tmp; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_res.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return tmp.bits.hsync_total_cnt; -+} -+ -+unsigned short hdmi_reg_hsync_active_cnt_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_hori_res tmp; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_res.u32); -+ tmp.u32 = hdmi_tx_reg_read(reg_addr); -+ return tmp.bits.hsync_active_cnt; -+} -+ -+unsigned short hdmi_reg_vsync_total_cnt_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_hori_vert_res fdet_vert_res; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_vert_res.u32); -+ fdet_vert_res.u32 = hdmi_tx_reg_read(reg_addr); -+ return fdet_vert_res.bits.vsync_total_cnt; -+} -+ -+unsigned short hdmi_reg_vsync_active_cnt_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ fdet_hori_vert_res fdet_vert_res; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->fmt_dect_hori_vert_res.u32); -+ fdet_vert_res.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return fdet_vert_res.bits.vsync_active_cnt; -+} -+ -+unsigned char hdmi_reg_dwsm_vert_bypass_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_dwsm_vert_byp; -+} -+ -+unsigned char hdmi_reg_dwsm_vert_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_dwsm_vert_en; -+} -+ -+unsigned char hdmi_reg_hori_filter_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ -+ video_dwsm_ctrl ctrl; -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.reg_hori_filter_en; -+} -+ -+unsigned char hdmi_reg_dwsm_hori_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_dwsm_hori_en; -+} -+ -+unsigned char hdmi_reg_pxl_div_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ data_align_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_pxl_div_en; -+} -+ -+unsigned char hdmi_reg_demux_420_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ data_align_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_demux_420_en; -+} -+ -+unsigned char hdmi_reg_inver_sync_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_inver_sync; -+} -+ -+unsigned char hdmi_reg_vmux_cr_sel_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_vmux_cr_sel; -+} -+ -+unsigned char hdmi_reg_vmux_cb_sel_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_vmux_cb_sel; -+} -+ -+unsigned char hdmi_reg_vmux_y_sel_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_vmux_y_sel; -+} -+ -+unsigned char hdmi_reg_dither_mode_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ dither_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return config.bits.dither_mode; -+} -+ -+unsigned char hdmi_reg_dither_rnd_bypass_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ dither_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return config.bits.dither_rnd_byp; -+} -+ -+unsigned char hdmi_reg_csc_en_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ multi_csc_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ -+ return ctrl.bits.reg_csc_en; -+} -+ -+unsigned char hdmi_reg_csc_mode_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ multi_csc_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ return ctrl.bits.reg_csc_mode; -+} -+ -+void hdmi_reg_dither_mode_set(unsigned char dither_mode) -+{ -+ unsigned int *reg_addr = NULL; -+ dither_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.dither_mode = dither_mode; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dither_rnd_bypass_set(unsigned char dither_rnd_byp) -+{ -+ unsigned int *reg_addr = NULL; -+ dither_config config; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dither_cfg.u32); -+ config.u32 = hdmi_tx_reg_read(reg_addr); -+ config.bits.dither_rnd_byp = dither_rnd_byp; -+ hdmi_tx_reg_write(reg_addr, config.u32); -+ -+ return; -+} -+ -+void hdmi_reg_csc_mode_set(unsigned char reg_csc_mode) -+{ -+ unsigned int *reg_addr = NULL; -+ multi_csc_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_csc_mode = reg_csc_mode; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_csc_saturate_en_set(unsigned char reg_csc_saturate_en) -+{ -+ unsigned int *reg_addr = NULL; -+ multi_csc_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_csc_saturate_en = reg_csc_saturate_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_csc_en_set(unsigned char reg_csc_en) -+{ -+ unsigned int *reg_addr = NULL; -+ multi_csc_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->csc_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_csc_en = reg_csc_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dwsm_vert_bypass_set(unsigned char reg_dwsm_vert_byp) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_dwsm_vert_byp = reg_dwsm_vert_byp; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dwsm_vert_en_set(unsigned char reg_dwsm_vert_en) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_dwsm_vert_en = reg_dwsm_vert_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_hori_filter_en_set(unsigned char reg_hori_filter_en) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_hori_filter_en = reg_hori_filter_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dwsm_hori_en_set(unsigned char reg_dwsm_hori_en) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dwsm_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dwsm_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_dwsm_hori_en = reg_dwsm_hori_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pxl_div_en_set(unsigned char reg_pxl_div_en) -+{ -+ unsigned int *reg_addr = NULL; -+ data_align_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_pxl_div_en = reg_pxl_div_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_demux_420_en_set(unsigned char reg_demux_420_en) -+{ -+ unsigned int *reg_addr = NULL; -+ data_align_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->align_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_demux_420_en = reg_demux_420_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_inver_sync_set(unsigned char reg_inver_sync) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_inver_sync = reg_inver_sync; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_syncmask_en_set(unsigned char reg_syncmask_en) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_syncmask_en = reg_syncmask_en; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vmux_cr_sel_set(unsigned char reg_vmux_cr_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_vmux_cr_sel = reg_vmux_cr_sel; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vmux_cb_sel_set(unsigned char reg_vmux_cb_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_vmux_cb_sel = reg_vmux_cb_sel; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -+void hdmi_reg_vmux_y_sel_set(unsigned char reg_vmux_y_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ video_dmux_ctrl ctrl; -+ -+ reg_addr = (unsigned int *)&(g_video_path_regs->dmux_ctrl.u32); -+ ctrl.u32 = hdmi_tx_reg_read(reg_addr); -+ ctrl.bits.reg_vmux_y_sel = reg_vmux_y_sel; -+ hdmi_tx_reg_write(reg_addr, ctrl.u32); -+ -+ return; -+} -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.h b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.h -new file mode 100755 -index 0000000..9aef315 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_video_path.h -@@ -0,0 +1,723 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef HDMI_REG_VIDEO_PATH_H -+#define HDMI_REG_VIDEO_PATH_H -+ -+ -+typedef union { -+ struct { -+ unsigned int reg_timing_gen_en : 1; /* [0] */ -+ unsigned int reg_extmode : 1; /* [1] */ -+ unsigned int reg_timing_sel : 6; /* [7:2] */ -+ unsigned int reg_sync_polarity : 2; /* [9:8] */ -+ unsigned int rsv_0 : 22; /* [31:10] */ -+ } bits; -+ unsigned int u32; -+} timing_gen_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int hsync_total_count : 13; /* [12:0] */ -+ unsigned int hsync_high_to_low_count : 13; /* [25:13] */ -+ unsigned int rsv_1 : 6; /* [31:26] */ -+ } bits; -+ unsigned int u32; -+} hsync_timing_config0; -+ -+typedef union { -+ struct { -+ unsigned int hsync_de_start_count : 13; /* [12:0] */ -+ unsigned int hsync_de_end_count : 13; /* [25:13] */ -+ unsigned int rsv_2 : 6; /* [31:26] */ -+ } bits; -+ unsigned int u32; -+} hsync_timing_config1; -+ -+typedef union { -+ struct { -+ unsigned int hsync_low_to_high_count : 13; /* [12:0] */ -+ unsigned int rsv_3 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} hsync_timing_config2; -+ -+typedef union { -+ struct { -+ unsigned int vsync_total_count : 12; /* [11:0] */ -+ unsigned int vsync_high_to_low_count : 12; /* [23:12] */ -+ unsigned int rsv_4 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsync_timing_config0; -+ -+typedef union { -+ struct { -+ unsigned int vsync_de_start_count : 12; /* [11:0] */ -+ unsigned int vsync_de_end_count : 12; /* [23:12] */ -+ unsigned int rsv_5 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} vsync_timing_config1; -+ -+typedef union { -+ struct { -+ unsigned int vsync_low_to_high_count : 12; /* [11:0] */ -+ unsigned int rsv_6 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} vsync_timing_config2; -+ -+typedef union { -+ struct { -+ unsigned int reg_video_blank_en : 1; /* [0] */ -+ unsigned int rsv_6 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} video_path_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int tpg_enable : 1; /* [0] */ -+ unsigned int video_format : 2; /* [2:1] */ -+ unsigned int solid_pattern_en : 1; /* [3] */ -+ unsigned int colorbar_en : 1; /* [4] */ -+ unsigned int square_pattern_en : 1; /* [5] */ -+ unsigned int mask_pattern_en : 3; /* [8:6] */ -+ unsigned int replace_pattern_en : 3; /* [11:9] */ -+ unsigned int bar_pattern_extmode : 1; /* [12] */ -+ unsigned int cbar_pattern_sel : 2; /* [14:13] */ -+ unsigned int mix_color_en : 1; /* [15] */ -+ unsigned int increase_en : 1; /* [16] */ -+ unsigned int rsv_7 : 15; /* [31:17] */ -+ } bits; -+ unsigned int u32; -+} pattern_gen_ctrll; -+ -+typedef union { -+ struct { -+ unsigned int solid_pattern_cb : 10; /* [9:0] */ -+ unsigned int solid_pattern_y : 10; /* [19:10] */ -+ unsigned int solid_pattern_cr : 10; /* [29:20] */ -+ unsigned int rsv_8 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} solid_pattern_config; -+ -+typedef union { -+ struct { -+ unsigned int mask_pattern_cb : 10; /* [9:0] */ -+ unsigned int mask_pattern_y : 10; /* [19:10] */ -+ unsigned int mask_pattern_cr : 10; /* [29:20] */ -+ unsigned int rsv_9 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} mask_pattern_config; -+ -+typedef union { -+ struct { -+ unsigned int colorbar_width : 12; /* [11:0] */ -+ unsigned int square_height : 12; /* [23:12] */ -+ unsigned int rsv_10 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} bar_ext_config; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a0 : 30; /* [29:0] */ -+ unsigned int rsv_11 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a0; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a1 : 30; /* [29:0] */ -+ unsigned int rsv_12 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a1; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a2 : 30; /* [29:0] */ -+ unsigned int rsv_13 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a2; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a3 : 30; /* [29:0] */ -+ unsigned int rsv_14 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a3; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a4 : 30; /* [29:0] */ -+ unsigned int rsv_15 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a4; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a5 : 30; /* [29:0] */ -+ unsigned int rsv_16 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a5; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a6 : 30; /* [29:0] */ -+ unsigned int rsv_17 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a6; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_a7 : 30; /* [29:0] */ -+ unsigned int rsv_18 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_a7; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b0 : 30; /* [29:0] */ -+ unsigned int rsv_19 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b0; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b1 : 30; /* [29:0] */ -+ unsigned int rsv_20 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b1; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b2 : 30; /* [29:0] */ -+ unsigned int rsv_21 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b2; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b3 : 30; /* [29:0] */ -+ unsigned int rsv_22 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b3; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b4 : 30; /* [29:0] */ -+ unsigned int rsv_23 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b4; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b5 : 30; /* [29:0] */ -+ unsigned int rsv_24 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b5; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b6 : 30; /* [29:0] */ -+ unsigned int rsv_25 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b6; -+ -+typedef union { -+ struct { -+ unsigned int bar_pattern_b7 : 30; /* [29:0] */ -+ unsigned int rsv_26 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} cbar_pattern_b7; -+ -+typedef union { -+ struct { -+ unsigned int sync_polarity_force : 1; /* [0] */ -+ unsigned int hsync_polarity_value : 1; /* [1] */ -+ unsigned int vsync_polarity_value : 1; /* [2] */ -+ unsigned int fdt_status_clear : 1; /* [3] */ -+ unsigned int pixel_cnt_threhold : 4; /* [7:4] */ -+ unsigned int rsv_27 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} format_det_config; -+ -+typedef union { -+ struct { -+ unsigned int interlaced : 1; /* [0] */ -+ unsigned int hsync_polarity : 1; /* [1] */ -+ unsigned int vsync_polarity : 1; /* [2] */ -+ unsigned int rsv_28 : 29; /* [31:3] */ -+ } bits; -+ unsigned int u32; -+} fdet_status; -+ -+typedef union { -+ struct { -+ unsigned int hsync_active_cnt : 13; /* [12:0] */ -+ unsigned int hsync_total_cnt : 13; /* [25:13] */ -+ unsigned int rsv_29 : 6; /* [31:26] */ -+ } bits; -+ unsigned int u32; -+} fdet_hori_res; -+ -+typedef union { -+ struct { -+ unsigned int vsync_active_cnt : 13; /* [12:0] */ -+ unsigned int vsync_total_cnt : 13; /* [25:13] */ -+ unsigned int rsv_30 : 6; /* [31:26] */ -+ } bits; -+ unsigned int u32; -+} fdet_hori_vert_res; -+ -+typedef union { -+ struct { -+ unsigned int dither_rnd_byp : 1; /* [0] */ -+ unsigned int dither_mode : 2; /* [2:1] */ -+ unsigned int dither_rnd_en : 1; /* [3] */ -+ unsigned int dither_spatial_en : 1; /* [4] */ -+ unsigned int dither_spatial_dual : 1; /* [5] */ -+ unsigned int rsv_31 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} dither_config; -+ -+typedef union { -+ struct { -+ unsigned int range_clip_byp : 1; /* [0] */ -+ unsigned int clip_rgb_mode : 1; /* [1] */ -+ unsigned int rsv_32 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} clip_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int clip_y_min : 12; /* [11:0] */ -+ unsigned int clip_y_max : 12; /* [23:12] */ -+ unsigned int rsv_33 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} clip_y_config; -+ -+typedef union { -+ struct { -+ unsigned int clip_c_min : 12; /* [11:0] */ -+ unsigned int clip_c_max : 12; /* [23:12] */ -+ unsigned int rsv_34 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} clip_c_config; -+ -+typedef union { -+ struct { -+ unsigned int auto_trigger_en : 1; /* [0] */ -+ unsigned int soft_trigger_en : 1; /* [1] */ -+ unsigned int show_point_en : 1; /* [2] */ -+ unsigned int rsv_35 : 1; /* [3] */ -+ unsigned int cap_stat_done : 1; /* [4] */ -+ unsigned int cap_stat_busy : 1; /* [5] */ -+ unsigned int cap_stat_error : 1; /* [6] */ -+ unsigned int rsv_36 : 25; /* [31:7] */ -+ } bits; -+ unsigned int u32; -+} pxl_cap_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int cap_pixel_position : 13; /* [12:0] */ -+ unsigned int cap_line_position : 13; /* [25:13] */ -+ unsigned int rsv_37 : 6; /* [31:26] */ -+ } bits; -+ unsigned int u32; -+} pxl_cap_position; -+ -+typedef union { -+ struct { -+ unsigned int capture_y_value : 12; /* [11:0] */ -+ unsigned int rsv_38 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} cap_y_value; -+ -+typedef union { -+ struct { -+ unsigned int capture_cb_value : 12; /* [11:0] */ -+ unsigned int rsv_39 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} cap_cb_value; -+ -+typedef union { -+ struct { -+ unsigned int capture_cr_value : 12; /* [11:0] */ -+ unsigned int rsv_40 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} cap_cr_value; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_en : 1; /* [0] */ -+ unsigned int reg_csc_coef_ext : 1; /* [1] */ -+ unsigned int reg_csc_dither_en : 1; /* [2] */ -+ unsigned int reg_csc_saturate_en : 1; /* [3] */ -+ unsigned int reg_csc_mode : 8; /* [11:4] */ -+ unsigned int rsv_41 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r1c1 : 16; /* [15:0] */ -+ unsigned int rsv_42 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff11; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r1c2 : 16; /* [15:0] */ -+ unsigned int rsv_43 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff12; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r1c3 : 16; /* [15:0] */ -+ unsigned int rsv_44 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff13; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r2c1 : 16; /* [15:0] */ -+ unsigned int rsv_45 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff21; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r2c2 : 16; /* [15:0] */ -+ unsigned int rsv_46 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff22; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r2c3 : 16; /* [15:0] */ -+ unsigned int rsv_47 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff23; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r3c1 : 16; /* [15:0] */ -+ unsigned int rsv_48 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff31; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r3c2 : 16; /* [15:0] */ -+ unsigned int rsv_49 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff32; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_r3c3 : 16; /* [15:0] */ -+ unsigned int rsv_50 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_coeff33; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_inoffset_y : 13; /* [12:0] */ -+ unsigned int rsv_51 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_inoffset_y; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_inoffset_cb : 13; /* [12:0] */ -+ unsigned int rsv_52 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_inoffset_cb; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_inoffset_cr : 13; /* [12:0] */ -+ unsigned int rsv_53 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_inoffset_cr; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_outoffset_y : 13; /* [12:0] */ -+ unsigned int rsv_54 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_outoffset_y; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_outoffset_cb : 13; /* [12:0] */ -+ unsigned int rsv_55 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_outoffset_cb; -+ -+typedef union { -+ struct { -+ unsigned int reg_csc_outoffset_cr : 13; /* [12:0] */ -+ unsigned int rsv_56 : 19; /* [31:13] */ -+ } bits; -+ unsigned int u32; -+} multi_csc_outoffset_cr; -+ -+typedef union { -+ struct { -+ unsigned int reg_dwsm_hori_en : 1; /* [0] */ -+ unsigned int reg_hori_filter_en : 1; /* [1] */ -+ unsigned int reg_dwsm_vert_en : 1; /* [2] */ -+ unsigned int reg_dwsm_vert_byp : 1; /* [3] */ -+ unsigned int reg_vert_cbcr_sel : 1; /* [4] */ -+ unsigned int rsv_57 : 27; /* [31:5] */ -+ } bits; -+ unsigned int u32; -+} video_dwsm_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int reg_demux_420_en : 1; /* [0] */ -+ unsigned int reg_ddr_en : 1; /* [1] */ -+ unsigned int reg_yc_mux_en : 1; /* [2] */ -+ unsigned int reg_blank_replace_en : 1; /* [3] */ -+ unsigned int reg_pixel_rate : 2; /* [5:4] */ -+ unsigned int reg_ddr_polarity : 1; /* [6] */ -+ unsigned int reg_yc_mux_polarity : 1; /* [7] */ -+ unsigned int reg_cbcr_order : 1; /* [8] */ -+ unsigned int reg_demux_cb_or_cr : 1; /* [9] */ -+ unsigned int reg_pxl_div_en : 1; /* [10] */ -+ unsigned int rsv_58 : 21; /* [31:11] */ -+ } bits; -+ unsigned int u32; -+} data_align_ctrl; -+ -+typedef union { -+ struct { -+ unsigned int reg_blank_y : 12; /* [11:0] */ -+ unsigned int rsv_59 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} blank_data_y; -+ -+typedef union { -+ struct { -+ unsigned int reg_blank_cb : 12; /* [11:0] */ -+ unsigned int rsv_60 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} blank_data_cb; -+ -+typedef union { -+ struct { -+ unsigned int reg_blank_cr : 12; /* [11:0] */ -+ unsigned int rsv_61 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} blank_data_cr; -+ -+typedef union { -+ struct { -+ unsigned int reg_vmux_y_sel : 3; /* [2:0] */ -+ unsigned int reg_vmux_cb_sel : 3; /* [5:3] */ -+ unsigned int reg_vmux_cr_sel : 3; /* [8:6] */ -+ unsigned int reg_bitmask_y : 2; /* [10:9] */ -+ unsigned int reg_bitmask_cb : 2; /* [12:11] */ -+ unsigned int reg_bitmask_cr : 2; /* [14:13] */ -+ unsigned int reg_bitrev_en : 3; /* [17:15] */ -+ unsigned int reg_datamask_en : 3; /* [20:18] */ -+ unsigned int reg_syncmask_en : 4; /* [24:21] */ -+ unsigned int reg_inver_sync : 4; /* [28:25] */ -+ unsigned int rsv_62 : 3; /* [31:29] */ -+ } bits; -+ unsigned int u32; -+} video_dmux_ctrl; -+ -+typedef struct { -+ volatile timing_gen_ctrl tim_gen_ctrl; /* 800 */ -+ volatile hsync_timing_config0 hsync_timing_cfg0; /* 804 */ -+ volatile hsync_timing_config1 hsync_timing_cfg1; /* 808 */ -+ volatile hsync_timing_config2 hsync_timing_cfg2; /* 80C */ -+ volatile vsync_timing_config0 vsync_timing_cfg0; /* 810 */ -+ volatile vsync_timing_config1 vsync_timing_cfg1; /* 814 */ -+ volatile vsync_timing_config2 vsync_timing_cfg2; /* 818 */ -+ unsigned int reserved_0[5]; /* 81C-82C */ -+ volatile video_path_ctrl vid_path_ctrl; /* 830 */ -+ unsigned int reserved_1[3]; /* 834-83c */ -+ volatile pattern_gen_ctrll ptn_gen_ctrl; /* 840 */ -+ volatile solid_pattern_config solid_ptn_ctrl; /* 844 */ -+ volatile mask_pattern_config mask_ptn_ctrl; /* 848 */ -+ volatile bar_ext_config bar_ext_cfg; /* 84C */ -+ volatile cbar_pattern_a0 cbar_a0; /* 850 */ -+ volatile cbar_pattern_a1 cbar_a1; /* 854 */ -+ volatile cbar_pattern_a2 cbar_a2; /* 858 */ -+ volatile cbar_pattern_a3 cbar_a3; /* 85C */ -+ volatile cbar_pattern_a4 cbar_a4; /* 860 */ -+ volatile cbar_pattern_a5 cbar_a5; /* 864 */ -+ volatile cbar_pattern_a6 cbar_a6; /* 868 */ -+ volatile cbar_pattern_a7 cbar_a7; /* 86C */ -+ volatile cbar_pattern_b0 cbar_b0; /* 870 */ -+ volatile cbar_pattern_b1 cbar_b1; /* 874 */ -+ volatile cbar_pattern_b2 cbar_b2; /* 878 */ -+ volatile cbar_pattern_b3 cbar_b3; /* 87C */ -+ volatile cbar_pattern_b4 cbar_b4; /* 880 */ -+ volatile cbar_pattern_b5 cbar_b5; /* 884 */ -+ volatile cbar_pattern_b6 cbar_b6; /* 888 */ -+ volatile cbar_pattern_b7 cbar_b7; /* 88C */ -+ unsigned int reserved_2[10]; /* 890-8B4 */ -+ volatile format_det_config fmt_det_cfg; /* 8B8 */ -+ volatile fdet_status fmt_dect_status; /* 8BC */ -+ volatile fdet_hori_res fmt_dect_hori_res; /* 8C0 */ -+ volatile fdet_hori_vert_res fmt_dect_hori_vert_res; /* 8C4 */ -+ unsigned int reserved_3[9]; /* 8C8-8E8 */ -+ volatile dither_config dither_cfg; /* 8EC */ -+ unsigned int reserved_4[2]; /* 8F0-8F4 */ -+ volatile clip_ctrl clip_ctrl; /* 8F8 */ -+ volatile clip_y_config clip_y_cfg; /* 8FC */ -+ volatile clip_c_config clip_c_cfg; /* 900 */ -+ unsigned int reserved_5[2]; /* 904-908 */ -+ volatile pxl_cap_ctrl capture_ctrl; /* 90C */ -+ volatile pxl_cap_position capture_cfg; /* 910 */ -+ volatile cap_y_value pxl_y_capture; /* 914 */ -+ volatile cap_cb_value pxl_cb_capture; /* 918 */ -+ volatile cap_cr_value pxl_cr_capture; /* 91C */ -+ unsigned int reserved_6[5]; /* 920-930 */ -+ volatile multi_csc_ctrl csc_ctrl; /* 934 */ -+ volatile multi_csc_coeff11 csc_coeff11; /* 938 */ -+ volatile multi_csc_coeff12 csc_coeff12; /* 93C */ -+ volatile multi_csc_coeff13 csc_coeff13; /* 940 */ -+ volatile multi_csc_coeff21 csc_coeff21; /* 944 */ -+ volatile multi_csc_coeff22 csc_coeff22; /* 948 */ -+ volatile multi_csc_coeff23 csc_coeff23; /* 94C */ -+ volatile multi_csc_coeff31 csc_coeff31; /* 950 */ -+ volatile multi_csc_coeff32 csc_coeff32; /* 954 */ -+ volatile multi_csc_coeff33 csc_coeff33; /* 958 */ -+ volatile multi_csc_inoffset_y y_in_offset; /* 95C */ -+ volatile multi_csc_inoffset_cb cb_in_offset; /* 960 */ -+ volatile multi_csc_inoffset_cr cr_in_offset; /* 964 */ -+ volatile multi_csc_outoffset_y y_out_offset; /* 968 */ -+ volatile multi_csc_outoffset_cb cb_out_offset; /* 96C */ -+ volatile multi_csc_outoffset_cr cr_out_offset; /* 970 */ -+ unsigned int reserved_7[3]; /* 974-97c */ -+ volatile video_dwsm_ctrl dwsm_ctrl; /* 980 */ -+ unsigned int reserved_8[2]; /* 984-988 */ -+ volatile data_align_ctrl align_ctrl; /* 98C */ -+ volatile blank_data_y blk_data_y; /* 990 */ -+ volatile blank_data_cb blk_data_cb; /* 994 */ -+ volatile blank_data_cr blk_data_cr; /* 998 */ -+ unsigned int reserved_9[3]; /* 99C-9A4 */ -+ volatile video_dmux_ctrl dmux_ctrl; /* 9A8 */ -+} video_path_reg_regs_type; -+ -+int hdmi_reg_video_path_regs_init(const char *addr); -+int hdmi_reg_video_path_regs_deinit(void); -+int hdmi_video_path_regs_is_inited(void); -+void hdmi_reg_video_blank_en_set(unsigned char reg_video_blank_en); -+unsigned char hdmi_reg_video_blank_en_get(void); -+void hdmi_reg_solid_pattern_en_set(unsigned char solid_pattern_en); -+unsigned char hdmi_reg_solid_pattern_en_get(void); -+void hdmi_reg_solid_pattern_cb_set(unsigned short solid_pattern_cb); -+void hdmi_reg_solid_pattern_y_set(unsigned short solid_pattern_y); -+void hdmi_reg_solid_pattern_cr_set(unsigned short solid_pattern_cr); -+void hdmi_reg_sync_polarity_force_set(unsigned char sync_polarity_force); -+void hdmi_reg_fdt_status_clear_set(unsigned char fdt_status_clear); -+unsigned char hdmi_reg_interlaced_get(void); -+unsigned char hdmi_reg_hsync_polarity_get(void); -+unsigned char hdmi_reg_vsync_polarity_get(void); -+unsigned short hdmi_reg_hsync_active_cnt_get(void); -+unsigned short hdmi_reg_hsync_total_cnt_get(void); -+unsigned short hdmi_reg_vsync_active_cnt_get(void); -+unsigned short hdmi_reg_vsync_total_cnt_get(void); -+void hdmi_reg_dither_rnd_bypass_set(unsigned char dither_rnd_byp); -+unsigned char hdmi_reg_dither_rnd_bypass_get(void); -+void hdmi_reg_dither_mode_set(unsigned char dither_mode); -+unsigned char hdmi_reg_dither_mode_get(void); -+void hdmi_reg_csc_en_set(unsigned char reg_csc_en); -+unsigned char hdmi_reg_csc_en_get(void); -+void hdmi_reg_csc_saturate_en_set(unsigned char reg_csc_saturate_en); -+void hdmi_reg_csc_mode_set(unsigned char reg_csc_mode); -+unsigned char hdmi_reg_csc_mode_get(void); -+void hdmi_reg_dwsm_hori_en_set(unsigned char reg_dwsm_hori_en); -+unsigned char hdmi_reg_dwsm_hori_en_get(void); -+void hdmi_reg_hori_filter_en_set(unsigned char reg_hori_filter_en); -+unsigned char hdmi_reg_hori_filter_en_get(void); -+void hdmi_reg_dwsm_vert_en_set(unsigned char reg_dwsm_vert_en); -+unsigned char hdmi_reg_dwsm_vert_en_get(void); -+void hdmi_reg_dwsm_vert_bypass_set(unsigned char reg_dwsm_vert_byp); -+unsigned char hdmi_reg_dwsm_vert_bypass_get(void); -+void hdmi_reg_demux_420_en_set(unsigned char reg_demux_420_en); -+unsigned char hdmi_reg_demux_420_en_get(void); -+void hdmi_reg_pxl_div_en_set(unsigned char reg_pxl_div_en); -+unsigned char hdmi_reg_pxl_div_en_get(void); -+void hdmi_reg_vmux_y_sel_set(unsigned char reg_vmux_y_sel); -+unsigned char hdmi_reg_vmux_y_sel_get(void); -+void hdmi_reg_vmux_cb_sel_set(unsigned char reg_vmux_cb_sel); -+unsigned char hdmi_reg_vmux_cb_sel_get(void); -+void hdmi_reg_vmux_cr_sel_set(unsigned char reg_vmux_cr_sel); -+unsigned char hdmi_reg_vmux_cr_sel_get(void); -+void hdmi_reg_syncmask_en_set(unsigned char reg_syncmask_en); -+void hdmi_reg_inver_sync_set(unsigned char reg_inver_sync); -+unsigned char hdmi_reg_inver_sync_get(void); -+ -+#endif /* HDMI_REG_VIDEO_PATH_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/drv_hdmi_common.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/drv_hdmi_common.h -new file mode 100755 -index 0000000..70ac3db ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/drv_hdmi_common.h -@@ -0,0 +1,1342 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef DRV_HDMI_COMMON_H -+#define DRV_HDMI_COMMON_H -+ -+#include "ot_type.h" -+#include "drv_hdmi_infoframe.h" -+#include "hdmi_ext.h" -+#include "securec.h" -+#include "ot_common_hdmi.h" -+ -+ -+#define HDMI_VER_MAJOR 2 -+#define HDMI_VER_MINOR 0 -+#define HDMI_VER_REVISE 0 -+#define HDMI_VER_DATE 20240402 -+#define HDMI_VER_TIMES 0 -+ -+#define make_ver_bit(x) #x -+#define make_macro2str(exp) make_ver_bit(exp) -+#define MAKE_VERSION \ -+ make_macro2str(HDMI_VER_MAJOR) "." \ -+ make_macro2str(HDMI_VER_MINOR) "." \ -+ make_macro2str(HDMI_VER_REVISE) "." \ -+ make_macro2str(HDMI_VER_DATE) "." \ -+ make_macro2str(HDMI_VER_TIMES) -+ -+#define AEN_TX_FFE_LEN 4 -+#define MAX_FRL_RATE 6 -+#define HDMI_FRL_LANE_MAX_NUM 4 -+#define CEA_VIDEO_CODE_MAX 44 -+#define VESA_VIDEO_CODE_MAX 31 -+#define CEA861_F_VIDEO_CODES_MAX_4K 4 -+#define HDMI_INFO_FRAME_MAX_SIZE 31 -+#define SCDC_TMDS_BIT_CLK_RATIO_10X 10 -+#define SCDC_TMDS_BIT_CLK_RATIO_40X 40 -+#define HDMI_DECIMAL 10 -+#define HDMI_HUNDRED 100 -+#define HDMI_THOUSAND 1000 -+#define FMT_PIX_CLK_13400 13400 -+#define FMT_PIX_CLK_74250 74250 -+#define FMT_PIX_CLK_165000 165000 -+#define FMT_PIX_CLK_190000 190000 -+#define FMT_PIX_CLK_297000 297000 -+#define FMT_PIX_CLK_340000 340000 -+#define ZERO_DRMIF_SEND_TIME 2000 /* unit: ms */ -+#define HDRMODE_CHANGE_TIME 500 /* unit: ms */ -+#define HDMI_EDID_BLOCK_SIZE 128 -+#define HDMI_EDID_TOTAL_BLOCKS 4 -+#define HDMI_EDID_SIZE (HDMI_EDID_BLOCK_SIZE * HDMI_EDID_TOTAL_BLOCKS) -+#define HDMI_REGISTER_SIZE 4 -+#define HDMI_EDID_BLOCK_SIZE 128 -+#define HDMI_EDID_MAX_BLOCK_NUM 4 -+#define HDMI_HW_PARAM_LEN 4 -+#define HDMI_EDID_TOTAL_SIZE ((HDMI_EDID_BLOCK_SIZE) * (HDMI_EDID_MAX_BLOCK_NUM)) -+#define hdmi_array_size(a) ((sizeof(a)) / (sizeof(a[0]))) -+#ifdef HDMI_FPGA_SUPPORT -+#define FPGA_SUPPORT TD_TRUE -+#else -+#define FPGA_SUPPORT TD_FALSE -+#endif -+#define DEBUG_MAX_ARGV_NUM 10 -+#define hdmi_unused(x) (x) = (x) -+ -+#define PRT_RED "\033[31;1m" -+#define PRT_GREEN "\033[32;1m" -+#define PRT_CLEAN "\033[0m" -+ -+#define FRL_CTRL_TYPE_COMPRESS_ALL 0x00 -+#define FRL_CTRL_TYPE_COMPRESS_HW 0x01 -+#define FRL_CTRL_TYPE_COMPRESS_NON 0x03 -+#define HDMI_FRL_COMPRESS_DEBUG_MASK 0x4 -+ -+/* AVI InfoFrame Packet byte offset define */ -+#define AVI_OFFSET_TYPE 0 -+#define AVI_OFFSET_VERSION 1 -+#define AVI_OFFSET_LENGTH 2 -+#define AVI_OFFSET_CHECKSUM 3 -+/* -+ * include : -+ * color space -+ * active information present -+ * bar Info data valid -+ * scan Information -+ */ -+#define AVI_OFFSET_PB1 4 -+/* -+ * include : -+ * colorimetry -+ * picture aspect ratio -+ * active format aspect ratio -+ */ -+#define AVI_OFFSET_PB2 5 -+/* -+ * include : -+ * IT content -+ * extended colorimetry -+ * quantization range -+ * non-uniform picture scaling -+ */ -+#define AVI_OFFSET_PB3 6 -+#define AVI_OFFSET_VIC 7 -+/* -+ * include : -+ * YCC quantization range -+ * content type -+ * pixel repetition factor -+ */ -+#define AVI_OFFSET_PB5 8 -+#define AVI_OFFSET_TOP_BAR_LOWER 9 -+#define AVI_OFFSET_TOP_BAR_UPPER 10 -+#define AVI_OFFSET_BOTTOM_BAR_LOWER 11 -+#define AVI_OFFSET_BOTTOM_BAR_UPPER 12 -+#define AVI_OFFSET_LEFT_BAR_LOWER 13 -+#define AVI_OFFSET_LEFT_BAR_UPPER 14 -+#define AVI_OFFSET_RIGHT_BAR_LOWER 15 -+#define AVI_OFFSET_RIGHT_BAR_UPPER 16 -+#define AVI_OFFSET_PB14 17 -+#define AVI_OFFSET_PB15 18 -+#define AVI_OFFSET_PB16 19 -+#define AVI_OFFSET_PB17 20 -+#define AVI_OFFSET_PB18 21 -+#define AVI_OFFSET_PB19 22 -+#define AVI_OFFSET_PB20 23 -+#define AVI_OFFSET_PB21 24 -+#define AVI_OFFSET_PB22 25 -+#define AVI_OFFSET_PB23 26 -+#define AVI_OFFSET_PB24 27 -+#define AVI_OFFSET_PB25 28 -+#define AVI_OFFSET_PB26 29 -+#define AVI_OFFSET_PB27 30 -+#define AVI_FRAME_COLORIMETRY_MASK 0x3 -+#define AVI_FRAME_PIC_ASPECT_MASK 0x3 -+#define AVI_FRAME_ACTIVE_ASPECT_MASK 0xF -+#define AVI_FRAME_EXT_COLORIMETRY_MASK 0x7 -+#define AVI_FRAME_QUANT_RANGE_MASK 0x3 -+#define AVI_FRAME_YCC_QUANT_RANGE_MASK 0x3 -+#define AVI_FRAME_PIXEL_REPET_MASK 0xF -+ -+/* audio infoFrame packet byte offset define */ -+#define AUDIO_OFFSET_TYPE 0 -+#define AUDIO_OFFSET_VERSION 1 -+#define AUDIO_OFFSET_LENGHT 2 -+#define AUDIO_OFFSET_CHECKSUM 3 -+/* -+ * include : -+ * channel count -+ * coding type -+ */ -+#define AUDIO_OFFSET_PB1 4 -+/* -+ * include : -+ * sample size -+ * sample frequency -+ */ -+#define AUDIO_OFFSET_PB2 5 -+#define AUDIO_OFFSET_FORMAT 6 -+#define AUDIO_OFFSET_CA 7 -+/* -+ * include : -+ * level shift value -+ * downmix inhibit -+ * LFE playback level information -+ */ -+#define AUDIO_OFFSET_PB5 8 -+#define AUDIO_OFFSET_PB6 9 -+#define AUDIO_OFFSET_PB7 10 -+#define AUDIO_OFFSET_PB8 11 -+#define AUDIO_OFFSET_PB9 12 -+#define AUDIO_OFFSET_PB10 13 -+#define AUDIO_OFFSET_PB11 14 -+#define AUDIO_OFFSET_PB12 15 -+#define AUDIO_OFFSET_PB13 16 -+#define AUDIO_OFFSET_PB14 17 -+#define AUDIO_OFFSET_PB15 18 -+#define AUDIO_OFFSET_PB16 19 -+#define AUDIO_OFFSET_PB17 20 -+#define AUDIO_OFFSET_PB18 21 -+#define AUDIO_OFFSET_PB19 22 -+#define AUDIO_OFFSET_PB20 23 -+#define AUDIO_OFFSET_PB21 24 -+#define AUDIO_OFFSET_PB22 25 -+#define AUDIO_OFFSET_PB23 26 -+#define AUDIO_OFFSET_PB24 27 -+#define AUDIO_OFFSET_PB25 28 -+#define AUDIO_OFFSET_PB26 29 -+#define AUDIO_OFFSET_PB27 30 -+#define AUDIO_FRAME_CODE_TYPE_MASK 0xF -+ -+/* gdb infoFrame packet byte offset define */ -+#define GDB_OFFSET_HB0 0 -+#define GDB_OFFSET_HB1 1 -+#define GDB_OFFSET_HB2 2 -+#define GDB_OFFSET_CHECKSUM 3 -+#define GDB_OFFSET_PB1 4 -+#define GDB_OFFSET_PB2 5 -+#define GDB_OFFSET_PB3 6 -+#define GDB_OFFSET_PB4 7 -+#define GDB_OFFSET_PB5 8 -+#define GDB_OFFSET_PB6 9 -+#define GDB_OFFSET_PB7 10 -+#define GDB_OFFSET_PB8 11 -+#define GDB_OFFSET_PB9 12 -+#define GDB_OFFSET_PB10 13 -+#define GDB_OFFSET_PB11 14 -+#define GDB_OFFSET_PB12 15 -+#define GDB_OFFSET_PB13 16 -+#define GDB_OFFSET_PB14 17 -+#define GDB_OFFSET_PB15 18 -+#define GDB_OFFSET_PB16 19 -+#define GDB_OFFSET_PB17 20 -+#define GDB_OFFSET_PB18 21 -+#define GDB_OFFSET_PB19 22 -+#define GDB_OFFSET_PB20 23 -+#define GDB_OFFSET_PB21 24 -+#define GDB_OFFSET_PB22 25 -+#define GDB_OFFSET_PB23 26 -+#define GDB_OFFSET_PB24 27 -+#define GDB_OFFSET_PB25 28 -+#define GDB_OFFSET_PB26 29 -+#define GDB_OFFSET_PB27 30 -+ -+/* vendor infoFrame packet byte offset define */ -+#define VENDOR_OFFSET_TYPE 0 -+#define VENDOR_OFFSET_VERSION 1 -+#define VENDOR_OFFSET_LENGHT 2 -+#define VENDOR_OFFSET_CHECSUM 3 -+#define VENDOR_OFFSET_IEEE_LOWER 4 -+#define VENDOR_OFFSET_IEEE_UPPER 5 -+#define VENDOR_OFFSET_IEEE 6 -+#define VENDOR_OFFSET_VIDEO_FMT 7 -+#define VENDOR_OFFSET_VIC 8 -+#define VENDOR_OFFSET_3D_STRUCT 9 -+#define VENDOR_OFFSET_3D_EXT_DATA 10 -+#define VENDOR_OFFSET_PB7 11 -+#define VENDOR_OFFSET_PB8 12 -+#define VENDOR_OFFSET_PB9 13 -+#define VENDOR_OFFSET_PB10 14 -+#define VENDOR_OFFSET_PB11 15 -+#define VENDOR_OFFSET_PB12 16 -+#define VENDOR_OFFSET_PB13 17 -+#define VENDOR_OFFSET_PB14 18 -+#define VENDOR_OFFSET_PB15 19 -+#define VENDOR_OFFSET_PB16 20 -+#define VENDOR_OFFSET_PB17 21 -+#define VENDOR_OFFSET_PB18 22 -+#define VENDOR_OFFSET_PB19 23 -+#define VENDOR_OFFSET_PB20 24 -+#define VENDOR_OFFSET_PB21 25 -+#define VENDOR_OFFSET_PB22 26 -+#define VENDOR_OFFSET_PB23 27 -+#define VENDOR_OFFSET_PB24 28 -+#define VENDOR_OFFSET_PB25 29 -+#define VENDOR_OFFSET_PB26 30 -+#define VENDOR_FARAME_VIDEO_FMT_MASK 0x7 -+#define VENDOR_3D_STRUCT_MASK 0xF -+ -+#define HDMI_BKSV_LEN 5 -+#define HDMI_AKSV_LEN 5 -+ -+#define hdmi_unlock_if_null_return(p, mutex, ret) \ -+ do { \ -+ if ((p) == TD_NULL) { \ -+ hdmi_err("%s is null pointer!\n", #p); \ -+ hdmi_mutex_unlock((mutex)); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_null_return(p, ret) \ -+ do { \ -+ if ((p) == TD_NULL) { \ -+ hdmi_err("%s is null pointer!\n", #p); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_null_return_void(p) \ -+ do { \ -+ if ((p) == TD_NULL) { \ -+ hdmi_err("%s is null pointer!\n", #p); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_null_warn_return(p, ret) \ -+ do { \ -+ if ((p) == TD_NULL) { \ -+ hdmi_warn("%s is null pointer!\n", #p); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_null_warn_return_void(p) \ -+ do { \ -+ if ((p) == TD_NULL) { \ -+ hdmi_warn("%s is null pointer!\n", #p); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_false_return_void(b) \ -+ do { \ -+ if ((b) != TD_TRUE) { \ -+ hdmi_err("%s is FALSE!\n", #b); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_false_return(tmp, ret) \ -+ do { \ -+ if ((tmp) != TD_TRUE) { \ -+ hdmi_err("%s is FALSE!\n", #tmp); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_false_warn_return(tmp, ret) \ -+ do { \ -+ if ((tmp) != TD_TRUE) { \ -+ hdmi_warn("%s is FALSE!\n", #tmp); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_false_warn_return_void(tmp) \ -+ do { \ -+ if ((tmp) != TD_TRUE) { \ -+ hdmi_warn("%s is FALSE!\n", #tmp); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_check_is_change_return(tmp0, tmp1, ret) \ -+ do { \ -+ if ((tmp0) != (tmp1)) { \ -+ hdmi_info("%s change, old(%u)->new(%u) \n", #tmp0, (td_u32)(tmp0), (td_u32)(tmp1)); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_check_max_return(value, max, ret) \ -+ do { \ -+ if ((value) > (max)) { \ -+ hdmi_warn("value %u exceed max!\n", (td_u32)(value)); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_failure_return(tmp, ret) \ -+ do { \ -+ if ((tmp) != TD_SUCCESS) { \ -+ hdmi_err("%s is failure!\n", #tmp); \ -+ return (ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_failure_return_void(tmp) \ -+ do { \ -+ if ((tmp) != TD_SUCCESS) { \ -+ hdmi_err("%s is failure!\n", #tmp); \ -+ return; \ -+ } \ -+ } while (0) -+#define hdmi_if_failure_warn_return_void(tmp) \ -+ do { \ -+ if ((tmp) != TD_SUCCESS) { \ -+ hdmi_warn("%s is failure!\n", #tmp); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_set_bit(var, bit) \ -+ do { \ -+ (var) |= 1 << (bit); \ -+ } while (0) -+ -+#define hdmi_clr_bit(var, bit) \ -+ do { \ -+ (var) &= ~(1 << (bit)); \ -+ } while (0) -+ -+#ifdef HDMI_FPGA_SUPPORT -+#define hdmi_if_fpga_return(ret) \ -+ do { \ -+ if (FPGA_SUPPORT) { \ -+ hdmi_warn("FPGA CFG!\n"); \ -+ return(ret); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_fpga_return_void() \ -+ do { \ -+ if (FPGA_SUPPORT) { \ -+ hdmi_warn("FPGA CFG!\n"); \ -+ return; \ -+ } \ -+ } while (0) -+#else -+#define hdmi_if_fpga_return(ret) -+#define hdmi_if_fpga_return_void() -+#endif -+ -+#define is_bit_set(var, bit) ({ (var) & (0x1 << (bit)) ? TD_TRUE : TD_FALSE; }) -+ -+#define hal_call_ret(ret, func, param...) \ -+ do { \ -+ if (hdmi_dev != TD_NULL && hdmi_dev->hal != TD_NULL && \ -+ hdmi_dev->hal->func != TD_NULL) { \ -+ ret = hdmi_dev->hal->func(param); \ -+ } else { \ -+ ret = OT_ERR_HDMI_NULL_PTR; \ -+ } \ -+ } while (0) -+ -+#define hal_call_void(func, param...) \ -+ do { \ -+ if (hdmi_dev != TD_NULL && hdmi_dev->hal != TD_NULL && \ -+ hdmi_dev->hal->func != TD_NULL) { \ -+ hdmi_dev->hal->func(param); \ -+ } else { \ -+ hdmi_warn("null pointer! \n"); \ -+ } \ -+ } while (0) -+ -+#define hdmi_if_zero_return_void(x) \ -+ do { \ -+ if ((x) == 0) { \ -+ hdmi_err("%s is zero!\n", #x); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_unequal_eok_return(ret, err_code) \ -+ do { \ -+ if ((ret) != EOK) { \ -+ hdmi_err("secure function error:%d\n", (ret)); \ -+ return (err_code); \ -+ } \ -+ } while (0) -+ -+#define hdmi_unlock_unequal_eok_return(ret, mutex, err_code) \ -+ do { \ -+ if ((ret) != EOK) { \ -+ hdmi_err("secure function error:%d\n", (ret)); \ -+ hdmi_mutex_unlock((mutex)); \ -+ return (err_code); \ -+ } \ -+ } while (0) -+ -+#define hdmi_unequal_eok_return_void(ret) \ -+ do { \ -+ if ((ret) != EOK) { \ -+ hdmi_err("secure function error:%d\n", (ret)); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define hdmi_check_open_return(state) \ -+ do { \ -+ if (!((state) & HDMI_RUN_STATE_OPEN)) { \ -+ hdmi_warn("device not open\n"); \ -+ return OT_ERR_HDMI_DEV_NOT_OPEN; \ -+ } \ -+ } while (0) -+ -+typedef enum { -+ HDMI_DEVICE_ID0, -+ HDMI_DEVICE_ID1, -+ HDMI_DEVICE_ID_BUTT -+} hdmi_device_id; -+ -+#ifdef HDMI_SUPPORT_DUAL_CHANNEL -+#define HDMI_ID_MAX HDMI_DEVICE_ID_BUTT -+#else -+#define HDMI_ID_MAX HDMI_DEVICE_ID1 -+#endif -+ -+typedef enum { -+ HDMI_THREAD_STATE_IDLE, -+ HDMI_THREAD_STATE_RUN, -+ HDMI_THREAD_STATE_STOP -+} hdmi_thread_state; -+ -+typedef enum { -+ HDMI_EVENT_HOTPLUG = 0x10, -+ HDMI_EVENT_HOTUNPLUG, -+ HDMI_EVENT_EDID_FAIL, -+ HDMI_EVENT_RSEN_CONNECT, -+ HDMI_EVENT_RSEN_DISCONNECT, -+ HDMI_EVENT_SCRAMBLE_FAIL, -+ HDMI_EVENT_SCRAMBLE_SUCCESS, -+ HDMI_EVENT_ZERO_DRMIF_TIMEOUT, -+ HDMI_EVENT_SWITCH_TO_HDRMODE_TIMEOUT, -+ HDMI_EVENT_BUTT -+} hdmi_event; -+ -+typedef enum { -+ HDMI_DEBUG_BASE_OSD = 8, -+ HDMI_DEBUG_BASE_DEC = 10, -+ HDMI_DEBUG_BASE_HEX = 16 -+} hdmi_debug_base; -+ -+typedef td_s32 (*hdmi_callback)(td_void *, hdmi_event); -+ -+typedef struct { -+ hdmi_device_id hdmi_id; -+ td_char *argv[DEBUG_MAX_ARGV_NUM]; -+ td_u32 argc; -+ td_u32 remain_len; -+} hdmi_debug_cmd_arg; -+ -+typedef td_s32 (*cmd_func)(const hdmi_debug_cmd_arg *cmd_arg); -+ -+typedef struct { -+ td_char *name; -+ td_char *short_name; -+ cmd_func fn_cmd_func; -+ td_char *comment_help; -+} hdmi_debug_cmd_info; -+ -+typedef struct { -+ td_u32 ddc_reg_cfg; -+ td_u32 approximate_value; -+ td_char *read_value; -+} hdmi_ddc_freq; -+ -+typedef struct { -+ td_bool data_valid; -+ td_s32 len; -+ td_u8 data[HDMI_EDID_TOTAL_SIZE]; -+} hdmi_debug_edid; -+ -+typedef struct { -+ td_void *event_data; -+ hdmi_callback event_callback; -+ td_u32 hdmi_dev_id; -+ td_char *base_addr; -+ td_char *phy_addr; -+} hdmi_hal_init; -+ -+typedef struct { -+ td_u32 cmd; -+ td_s32 (*hdmi_ioctrl_func)(td_void *arg, td_bool user); -+} hdmi_ioctrl_func; -+ -+typedef struct { -+ hdmi_colorimetry colorimetry; -+ hdmi_quant_range quantization; -+ hdmi_pixel_encoding pixel_encoding; -+} hdmi_csc_attr; -+ -+typedef struct { -+ td_u8 edid_valid; -+ td_u32 edid_len; -+ td_u8 edid[HDMI_EDID_SIZE]; -+} hdmi_edid_raw_data; -+ -+typedef enum { -+ HDMI_HDCP_VERSION_NONE, -+ HDMI_HDCP_VERSION_1_4, -+ HDMI_HDCP_VERSION_2_2, -+ HDMI_HDCP_VERSION_BUTT -+} hdmi_hdcp_version; -+ -+typedef struct { -+ td_bool connected; -+ td_bool sink_power_on; -+ td_bool authed; -+ td_u8 bksv[HDMI_BKSV_LEN]; -+ hdmi_hdcp_version hdcp_version; -+} hdmi_status; -+ -+typedef struct { -+ td_u32 i_de_main_clk; -+ td_u32 i_de_main_data; -+ td_u32 i_main_clk; -+ td_u32 i_main_data; -+ td_u32 ft_cap_clk; -+ td_u32 ft_cap_data; -+} hdmi_hw_param; -+ -+typedef struct { -+ hdmi_hw_param hw_param[HDMI_HW_PARAM_LEN]; -+} hdmi_hw_spec; -+ -+typedef struct { -+ hdmi_hw_spec hwspec_user; -+ hdmi_hw_spec hwspec_def; -+ hdmi_hw_param hwparam_cur; -+} hdmi_hwspec; -+ -+typedef enum { -+ HDMI_DEEP_COLOR_24BIT, -+ HDMI_DEEP_COLOR_30BIT, -+ HDMI_DEEP_COLOR_36BIT, -+ HDMI_DEEP_COLOR_48BIT, -+ HDMI_DEEP_COLOR_OFF = 0xff, -+ HDMI_DEEP_COLOR_BUTT -+} hdmi_deep_color; -+ -+typedef enum { -+ HDMI_VIDEO_BITDEPTH_8, -+ HDMI_VIDEO_BITDEPTH_10, -+ HDMI_VIDEO_BITDEPTH_12, -+ HDMI_VIDEO_BITDEPTH_16, -+ HDMI_VIDEO_BITDEPTH_OFF, -+ HDMI_VIDEO_BITDEPTH_BUTT -+} hdmi_video_bit_depth; -+ -+typedef enum { -+ HDMI_HV_SYNC_POL_HPVP, -+ HDMI_HV_SYNC_POL_HPVN, -+ HDMI_HV_SYNC_POL_HNVP, -+ HDMI_HV_SYNC_POL_HNVN, -+ HDMI_HV_SYNC_POL_BUTT -+} hdmi_hvsync_polarity; -+ -+typedef enum { -+ HDMI_PICTURE_NON_UNIFORM_SCALING, -+ HDMI_PICTURE_SCALING_H, -+ HDMI_PICTURE_SCALING_V, -+ HDMI_PICTURE_SCALING_HV -+} hdmi_picture_scaling; -+ -+typedef struct { -+ td_u32 clk_fs; /* VDP setting(in) */ -+ td_u32 tmds_clk; -+ td_u32 hdmi_adapt_pix_clk; /* HDMI adapt setting(out) */ -+ td_u32 pixel_repeat; -+ td_bool v_sync_pol; -+ td_bool h_sync_pol; -+ td_bool de_pol; -+ hdmi_video_timing video_timing; -+ hdmi_3d_mode stereo_mode; -+ hdmi_colorspace in_color_space; -+ hdmi_colormetry colorimetry; -+ hdmi_extended_colormetry extended_colorimetry; -+ hdmi_quantization_range rgb_quantization; -+ hdmi_ycc_quantization_range ycc_quantization; -+ hdmi_picture_aspect picture_aspect; -+ hdmi_active_aspect active_aspect; -+ hdmi_picture_scaling picture_scaling; -+ hdmi_video_bit_depth in_bit_depth; -+ hdmi_disp_format disp_fmt; -+} hdmi_vo_attr; -+ -+typedef enum { -+ HDMI_AUDIO_FORMAT_2CH = 0x2, -+ HDMI_AUDIO_FORMAT_3CH, -+ HDMI_AUDIO_FORMAT_4CH, -+ HDMI_AUDIO_FORMAT_5CH, -+ HDMI_AUDIO_FORMAT_6CH, -+ HDMI_AUDIO_FORMAT_7CH, -+ HDMI_AUDIO_FORMAT_8CH, -+ HDMI_AUDIO_FORMAT_BUTT -+} hdmi_audio_ch; -+ -+typedef enum { -+ HDMI_AUDIO_INTF_I2S, -+ HDMI_AUDIO_INTF_SPDIF, -+ HDMI_AUDIO_INTF_HBRA, -+ HDMI_AUDIO_INTF_BUTT -+} hdmi_audio_interface; -+ -+typedef enum { -+ HDMI_AUDIO_BIT_DEPTH_UNKNOWN, -+ HDMI_AUDIO_BIT_DEPTH_8 = 8, -+ HDMI_AUDIO_BIT_DEPTH_16 = 16, -+ HDMI_AUDIO_BIT_DEPTH_18 = 18, -+ HDMI_AUDIO_BIT_DEPTH_20 = 20, -+ HDMI_AUDIO_BIT_DEPTH_24 = 24, -+ HDMI_AUDIO_BIT_DEPTH_32 = 32, -+ HDMI_AUDIO_BIT_DEPTH_BUTT -+} hdmi_audio_bit_depth; -+ -+typedef enum { -+ HDMI_SAMPLE_RATE_UNKNOWN, -+ HDMI_SAMPLE_RATE_8K = 8000, -+ HDMI_SAMPLE_RATE_11K = 11025, -+ HDMI_SAMPLE_RATE_12K = 12000, -+ HDMI_SAMPLE_RATE_16K = 16000, -+ HDMI_SAMPLE_RATE_22K = 22050, -+ HDMI_SAMPLE_RATE_24K = 24000, -+ HDMI_SAMPLE_RATE_32K = 32000, -+ HDMI_SAMPLE_RATE_44K = 44100, -+ HDMI_SAMPLE_RATE_48K = 48000, -+ HDMI_SAMPLE_RATE_88K = 88200, -+ HDMI_SAMPLE_RATE_96K = 96000, -+ HDMI_SAMPLE_RATE_176K = 176400, -+ HDMI_SAMPLE_RATE_192K = 192000, -+ HDMI_SAMPLE_RATE_768K = 768000, -+ HDMI_SAMPLE_RATE_BUTT -+} hdmi_sample_rate; -+ -+typedef struct { -+ td_bool down_sample; -+ hdmi_sample_rate sample_fs; -+ hdmi_audio_ch channels; -+ hdmi_audio_interface sound_intf; -+ hdmi_audio_bit_depth sample_depth; -+ hdmi_audio_format_code audio_code; -+} hdmi_ao_attr; -+ -+typedef enum { -+ HDMI_TMDS_MODE_NONE, -+ HDMI_TMDS_MODE_DVI, -+ HDMI_TMDS_MODE_HDMI_1_4, -+ HDMI_TMDS_MODE_HDMI_2_0, -+ HDMI_TMDS_MODE_AUTO, -+ HDMI_TMDS_MODE_HDMI_2_1, -+ HDMI_TMDS_MODE_BUTT -+} hdmi_tmds_mode; -+ -+typedef enum { -+ HDMI_HDCP_MODE_AUTO, -+ HDMI_HDCP_MODE_1_4, -+ HDMI_HDCP_MODE_2_2, -+ HDMI_HDCP_MODE_BUTT -+} hdmi_hdcp_mode; -+ -+typedef enum { -+ HDMI_DEFAULT_ACTION_NULL, -+ HDMI_DEFAULT_ACTION_HDMI, -+ HDMI_DEFAULT_ACTION_DVI, -+ HDMI_DEFAULT_ACTION_BUTT -+} hdmi_default_action; -+ -+typedef enum { -+ HDMI_VIDEO_DITHER_12_10, -+ HDMI_VIDEO_DITHER_12_8, -+ HDMI_VIDEO_DITHER_10_8, -+ HDMI_VIDEO_DITHER_DISALBE -+} hdmi_video_dither; -+ -+typedef struct { -+ td_bool enable_hdmi; -+ td_bool enable_video; -+ td_bool enable_audio; -+ hdmi_colorspace out_color_space; -+ hdmi_quantization_range out_csc_quantization; -+ hdmi_deep_color deep_color_mode; -+ td_bool xvycc_mode; -+ td_bool enable_avi_infoframe; -+ td_bool enable_spd_infoframe; -+ td_bool enable_mpeg_infoframe; -+ td_bool enable_aud_infoframe; -+ td_u32 debug_flag; -+ td_bool hdcp_enable; -+ hdmi_default_action hdmi_action; -+ td_bool enable_clr_space_adapt; -+ td_bool enable_deep_clr_adapt; -+ td_bool auth_mode; -+ hdmi_hdcp_mode hdcp_mode; -+} hdmi_app_attr; -+ -+typedef struct { -+ td_bool enable_hdmi; -+ td_bool enable_video; -+ hdmi_disp_format disp_fmt; -+ hdmi_video_timing video_timing; -+ td_u32 pix_clk; -+ hdmi_colorspace in_color_space; -+ hdmi_colorspace out_color_space; -+ hdmi_deep_color deep_color_mode; -+ hdmi_quantization_range out_csc_quantization; -+ td_bool enable_audio; -+ hdmi_sample_rate sample_rate; -+ hdmi_audio_bit_depth bit_depth; -+ td_bool enable_avi_infoframe; -+ td_bool enable_aud_infoframe; -+ hdmi_default_action hdmi_action; -+ td_bool enable_vid_mode_adapt; -+ td_bool enable_deep_clr_adapt; -+ td_bool auth_mode; -+} hdmi_property; -+ -+typedef struct { -+ hdmi_ao_attr ao_attr; -+ hdmi_vo_attr vo_attr; -+ hdmi_app_attr app_attr; -+} hdmi_attr; -+ -+typedef enum { -+ HDMI_TRANSITION_NONE, -+ HDMI_TRANSITION_BOOT_MCE, -+ HDMI_TRANSITION_MCE_APP, -+ HDMI_TRANSITION_BOOT_APP = 0x4 -+} hdmi_transition_state; -+ -+typedef enum { -+ HDMI_RUN_STATE_NONE, -+ HDMI_RUN_STATE_INIT, -+ HDMI_RUN_STATE_OPEN, -+ HDMI_RUN_STATE_START = 0x4, -+ HDMI_RUN_STATE_STOP = 0x8, -+ HDMI_RUN_STATE_CLOSE = 0x10, -+ HDMI_RUN_STATE_DEINIT = 0x20 -+} hdmi_run_state; -+ -+typedef struct { -+ td_u16 length; -+ td_u8 *list; -+ td_u8 *list_start; -+} hdmi_hdcp_ksv_list; -+ -+typedef struct { -+ td_bool tx_hdmi_14; -+ td_bool tx_hdmi_20; -+ td_bool tx_hdmi_21; -+ td_bool tx_hdcp_14; -+ td_bool tx_hdcp_22; -+ td_bool tx_rgb444; -+ td_bool tx_ycbcr444; -+ td_bool tx_ycbcr422; -+ td_bool tx_ycbcr420; -+ td_bool tx_deep_clr10_bit; -+ td_bool tx_deep_clr12_bit; -+ td_bool tx_deep_clr16_bit; -+ td_bool tx_rgb_ycbcr444; -+ td_bool tx_ycbcr444_422; -+ td_bool tx_ycbcr422_420; -+ td_bool tx_ycbcr420_422; -+ td_bool tx_ycbcr422_444; -+ td_bool tx_ycbcr444_rgb; -+ td_bool tx_scdc; -+ td_u32 tx_max_tmds_clk; -+ td_u32 tx_max_frl_rate; -+} hdmi_tx_capability_data; -+ -+typedef enum { -+ HDMI_CONV_STD_BT_709, -+ HDMI_CONV_STD_BT_601, -+ HDMI_CONV_STD_BT_2020_NON_CONST_LUMINOUS, -+ HDMI_CONV_STD_BT_2020_CONST_LUMINOUS, -+ HDMI_CONV_STD_BUTT -+} hdmi_conversion_stb; -+ -+typedef struct { -+ hdmi_video_timing timing; -+ td_u32 pixel_clk; -+ td_u32 tmds_clk; -+ td_bool v_sync_pol; -+ td_bool h_sync_pol; -+ td_bool de_pol; -+ hdmi_conversion_stb conv_std; -+ hdmi_quantization_range quantization; -+ hdmi_colorspace in_color_space; -+ hdmi_colorspace out_color_space; -+ hdmi_deep_color deep_color; -+ hdmi_video_bit_depth in_bit_depth; -+ hdmi_quantization_range out_csc_quantization; -+ td_bool emi_enable; -+} hdmi_video_config; -+ -+typedef struct { -+ td_bool enable_audio; -+ td_bool down_sample; -+ td_u32 tmds_clk; -+ td_u32 pixel_repeat; -+ hdmi_sample_rate sample_fs; -+ hdmi_audio_ch layout; -+ hdmi_audio_interface sound_intf; -+ hdmi_audio_bit_depth sample_depth; -+} hdmi_audio_config; -+ -+typedef enum { -+ HDMI_FRL_MODE_TMDS, -+ HDMI_FRL_MODE_FRL, -+ HDMI_FRL_MODE_BUTT -+} hdmi_frl_mode; -+ -+typedef struct { -+ hdmi_sample_rate sample_rate; -+ hdmi_frl_mode hdmi_mode; -+ td_u8 frl_rate; -+ td_u32 pixel_clk; -+} hdmi_audio_ncts; -+ -+typedef struct { -+ td_bool phy_oe; -+ td_bool phy_power_on; -+ hdmi_video_bit_depth deep_color; -+} hdmi_phy_status; -+ -+typedef struct { -+ td_bool sw_emi_enable; -+ td_bool hw_emi_enable; -+ td_bool debug_enable; -+} hdmi_emi_status; -+ -+typedef struct { -+ td_bool video_mute; -+ td_bool ycbcr2rgb; -+ td_bool rgb2ycbcr; -+ td_bool ycbcr444_422; -+ td_bool ycbcr422_420; -+ td_bool ycbcr420_422; -+ td_bool ycbcr422_444; -+ td_bool in420_ydemux; -+ td_bool out420_ydemux; -+ hdmi_video_dither dither; -+ td_bool v_sync_pol; -+ td_bool h_sync_pol; -+ td_bool sync_pol; -+ td_bool de_pol; -+ td_bool swap_hs_cs; -+ hdmi_colorspace in_color_space; -+ hdmi_colorspace out_color_space; -+ hdmi_video_bit_depth out_bit_depth; -+ hdmi_hvsync_polarity hv_sync_pol; -+ hdmi_quantization_range out_csc_quantization; -+ /* detect timing */ -+ td_bool sync_sw_enable; -+ td_bool vsync_polarity; /* when sync_sw_enable==0,indicates hw;or ,indicates sw */ -+ td_bool hsync_polarity; /* when sync_sw_enable==0,indicates hw;or ,indicates sw */ -+ td_bool progressive; -+ td_u32 hsync_total; -+ td_u32 hactive_cnt; -+ td_u32 vsync_total; -+ td_u32 vactive_cnt; -+} hdmi_video_status; -+ -+typedef struct { -+ td_bool hdcp14_support; -+ td_bool hdcp22_support; -+} hdmi_hdcp_capability; -+ -+typedef struct { -+ td_bool audio_mute; -+ td_bool audio_enable; -+ td_bool down_sample; -+ hdmi_sample_rate sample_fs; -+ hdmi_audio_ch layout; -+ hdmi_audio_interface sound_intf; -+ hdmi_audio_bit_depth sample_depth; -+ td_u32 ref_n; -+ td_u32 reg_n; -+ td_u32 ref_cts; -+ td_u32 reg_cts; -+} hdmi_audio_status; -+ -+typedef struct { -+ td_bool hotplug; -+ td_bool rsen; -+ td_bool avmute; -+ hdmi_tmds_mode tmds_mode; -+} hdmi_common_status; -+ -+typedef struct { -+ td_bool source_scramble_on; -+ td_bool sink_scramble_on; -+ td_u8 tmds_bit_clk_ratio; -+ td_bool sink_read_quest; -+ /* in unit of ms.for [0,200], force to default 200; or, set the value cfg(>200). */ -+ td_u32 scramble_timeout; -+ /* in unit of ms, range[20,200). for [0,20] or >=200, force to default 20; or, set the value cfg[20,200). */ -+ td_u32 scramble_interval; -+} hdmi_scdc_status; -+ -+typedef struct { -+ td_bool avi_enable; -+ td_bool audio_enable; -+ td_bool vsif_enable; -+ td_bool spd_enable; -+ td_bool mpeg_enable; -+ td_bool gbd_enable; -+ td_u8 avi[HDMI_INFO_FRAME_MAX_SIZE]; -+ td_u8 audio[HDMI_INFO_FRAME_MAX_SIZE]; -+ td_u8 vsif[HDMI_INFO_FRAME_MAX_SIZE]; -+ td_u8 spd[HDMI_INFO_FRAME_MAX_SIZE]; -+ td_u8 mpeg[HDMI_INFO_FRAME_MAX_SIZE]; -+ td_u8 gdb[HDMI_INFO_FRAME_MAX_SIZE]; -+} hdmi_infoframe_status; -+ -+typedef struct { -+ td_bool hdcp22_enable; -+ td_bool hdcp14_enable; -+ td_bool repeater_on; -+ td_u8 bksv[HDMI_BKSV_LEN]; -+ td_u8 aksv[HDMI_AKSV_LEN]; -+ td_u8 hdcp_status; -+} hdmi_hdcp_status; -+ -+typedef enum { -+ FRL_WORK_MODE_NONE, -+ FRL_WORK_MODE_3L3G, -+ FRL_WORK_MODE_3L6G, -+ FRL_WORK_MODE_4L6G, -+ FRL_WORK_MODE_4L8G, -+ FRL_WORK_MODE_4L10G, -+ FRL_WORK_MODE_4L12G, -+ FRL_WORK_MODE_BUTT -+} hdmi_work_mode; -+ -+typedef struct { -+ td_bool frl_start; -+ td_bool work_en; -+ hdmi_work_mode work_mode; -+} hdmi_frl_status; -+ -+typedef enum { -+ FRL_TXFFE_MODE_0, -+ FRL_TXFFE_MODE_1, -+ FRL_TXFFE_MODE_2, -+ FRL_TXFFE_MODE_3, -+ FRL_TXFFE_MODE_BUTT -+} hdmi_txfff_mode; -+ -+typedef struct { -+ hdmi_common_status common_status; -+ hdmi_phy_status phy_status; -+ hdmi_video_status video_status; -+ hdmi_audio_status audio_status; -+ hdmi_infoframe_status info_frame_status; -+ hdmi_hdcp_status hdcp_status; -+ hdmi_hwspec phy_hwspec; -+ hdmi_frl_status frl_status; -+} hdmi_hardware_status; -+ -+typedef struct { -+ td_u32 max_tmds_character_rate; -+ td_bool scdc_present; -+ td_bool rr_capable; -+ td_bool lte340_mcsc_scramble; -+ td_bool _3d_osd_disparity; -+ td_bool dual_view; -+ td_bool independent_view; -+ td_bool dc30bit420; -+ td_bool dc36bit420; -+ td_bool dc48bit420; -+ td_bool scdc_enable; -+} hdmi_scdc_config; -+ -+typedef struct { -+ td_u32 mute_delay; /* delay for avmute */ -+ td_u32 fmt_delay; /* delay for setformat */ -+ td_bool force_fmt_delay; /* force setformat delay mode */ -+ td_bool force_mute_delay; /* force avmute delay mode */ -+} hdmi_delay; -+ -+typedef enum { -+ HDMI_VIDEO_UNKNOWN, -+ HDMI_VIDEO_PROGRESSIVE, -+ HDMI_VIDEO_INTERLACE, -+ HDMI_VIDEO_BUTT -+} hdmi_video_format_type; -+ -+typedef struct { -+ hdmi_video_code_vic video_code; -+ td_u32 pixclk; -+ td_u32 rate; -+ td_u32 hactive; -+ td_u32 vactive; -+ td_u32 hblank; -+ td_u32 vblank; -+ td_u32 hfront; -+ td_u32 hsync; -+ td_u32 hback; -+ td_u32 vfront; -+ td_u32 vsync; -+ td_u32 vback; -+ hdmi_picture_aspect aspect_ratio; -+ hdmi_video_timing timing; -+ hdmi_video_format_type pi_type; -+ td_char *fmt_str; -+} hdmi_video_def; -+ -+typedef struct { -+ hdmi_vsif_vic hdmi_vic; -+ hdmi_video_code_vic equivalent_video_code; -+ td_u32 pixclk; -+ td_u32 rate; -+ td_u32 hactive; -+ td_u32 vactive; -+ hdmi_picture_aspect aspect_ratio; -+ hdmi_video_timing timing; -+ hdmi_video_format_type pi_type; -+ td_char *fmt_str; -+} hdmi_video_4k_def; -+ -+typedef struct { -+ td_u32 attach_in_time; -+ td_u32 attach_out_time; -+ td_u32 de_attach_in_time; -+ td_u32 de_attach_out_time; -+ td_u32 preformat_in_time; -+ td_u32 preformat_out_time; -+ td_u32 setformat_in_time; -+ td_u32 setformat_out_time; -+ td_u32 suspend_in_time; -+ td_u32 suspend_out_time; -+ td_u32 resume_in_time; -+ td_u32 resume_out_time; -+ td_u32 event_thread_cycle_time; -+} hdmi_intf_status; -+ -+typedef struct { -+ td_bool black_enable; -+ td_u8 in_color_space; -+ td_u8 in_bit_depth; -+ td_u8 in_quantization; -+} hdmi_black_frame_info; -+ -+typedef struct { -+ td_u32 stop_delay; -+ hdmi_intf_status intf_status; -+} hdmi_debug; -+ -+typedef enum { -+ HDMI_TIMER_ZERO_DRMIF, -+ HDMI_TIMER_SDR_TO_HDR10, -+ HDMI_TIMER_TYPE_BUTT -+} hdmi_timer_type; -+ -+typedef struct { -+ td_bool mute_pkg_en; -+ td_bool mute_set; -+ td_bool mute_clr; -+ td_bool mute_rpt_en; -+ td_u32 rpt_cnt; -+} hdmi_avmute_cfg; -+ -+typedef enum { -+ HDMI_FRL_SCDC_TYPE_SINK_VERSION, -+ HDMI_FRL_SCDC_TYPE_SOURCE_VERSION, -+ HDMI_FRL_SCDC_TYPE_UPDATE_FLAGS, -+ HDMI_FRL_SCDC_TYPE_STATUS_FLAGS, -+ HDMI_FRL_SCDC_TYPE_CONFIG, -+ HDMI_FRL_SCDC_TYPE_TXFFE_REQ, -+ HDMI_FRL_FLAGS_TYPE_BUTT -+} hdmi_frl_scdc_type; -+ -+typedef enum { -+ HDMI_FRL_TRAIN_PATTERN_NONE, -+ HDMI_FRL_TRAIN_PATTERN_LP1, -+ HDMI_FRL_TRAIN_PATTERN_LP2, -+ HDMI_FRL_TRAIN_PATTERN_LP3, -+ HDMI_FRL_TRAIN_PATTERN_LP4, -+ HDMI_FRL_TRAIN_PATTERN_LP5, -+ HDMI_FRL_TRAIN_PATTERN_LP6, -+ HDMI_FRL_TRAIN_PATTERN_LP7, -+ HDMI_FRL_TRAIN_PATTERN_LP8, -+ HDMI_FRL_TRAIN_PATTERN_RESERVED, -+ HDMI_FRL_TRAIN_PATTERN_0E = 0xE, -+ HDMI_FRL_TRAIN_PATTERN_0F = 0xF, -+ HDMI_FRL_TRAIN_PATTERN_BUTT -+} hdmi_frl_train_pattern; -+ -+typedef enum { -+ HDMI_FRL_TRAIN_NONE, -+ HDMI_FRL_TRAIN_FAIL, -+ HDMI_FRL_TRAIN_SUCCESS, -+ HDMI_FRL_TRAIN_BUSY, -+ HDMI_FRL_TRAIN_BUTT -+} hdmi_frl_train_status; -+ -+typedef enum { -+ HDMI_FRL_TRAIN_FAIL_NORMAL, -+ HDMI_FRL_TRAIN_FAIL_FLTTIMEOUT, -+ HDMI_FRL_TRAIN_FAIL_FLTSTEPTIMEOUT, -+ HDMI_FRL_TRAIN_FAIL_RATECHANGE, -+ HDMI_FRL_TRAIN_FAIL_FFECHANGE, -+ HDMI_FRL_TRAIN_FAIL_BUTT -+} hdmi_frl_train_fail_code; -+ -+typedef enum { -+ HDMI_FRL_TRAIN_SEL_SW, -+ HDMI_FRL_TRAIN_SEL_HW, -+ HDMI_FRL_TRAIN_SEL_BUTT -+} hdmi_frl_train_sel; -+ -+typedef enum { -+ FRL_DEBUG_RATE, -+ FRL_DEBUG_SW_TRAIN_SEL, -+ FRL_DEBUG_LTP_PATTERN, -+ FRL_DEBUG_SELECT_CHANNEL, -+ FRL_DEBUG_LTS3_INTERVAL, -+ FRL_DEBUG_LTS3_TIMEOUT, -+ FRL_DEBUG_TRAINING_BREAK, -+ FRL_DEBUG_LM_TABLE_GET, -+ FRL_DEBUG_CTRL_TYPE_CONFIG, -+ FRL_DEBUG_BUTT -+} frl_debug_cmd; -+ -+typedef enum { -+ FRL_SW_TRAIN_DELAY, -+ FRL_SW_TRAIN_TIMER, -+ FRL_SW_TRAIN_BUTT -+} frl_sw_train_mode; -+ -+typedef enum { -+ FRL_CHL_SEL_NORMAL, -+ FRL_CHL_SEL_RX_TMDS, -+ FRL_CHL_SEL_BUTT -+} frl_channel_sel; -+ -+typedef struct { -+ hdmi_frl_train_status frl_train_status; -+ hdmi_frl_train_pattern train_pattern[HDMI_FRL_LANE_MAX_NUM]; -+ hdmi_frl_train_fail_code train_fail_res; -+} hdmi_frl_train; -+ -+typedef enum { -+ HDMI_FRL_MACH_MODE_STEP, -+ HDMI_FRL_MACH_MODE_TIMEOUT, -+ HDMI_FRL_MACH_MODE_BUTT -+} hdmi_frl_mach_mode; -+ -+typedef struct { -+ td_bool frl_no_timeout; -+ td_u8 frl_rate; -+ td_u8 ffe_levels; -+ td_u32 train_timeout; -+ hdmi_frl_mach_mode mach_mode; -+ frl_sw_train_mode sw_train_mode; -+ td_u8 ctl_type_config; -+} hdmi_frl_train_config; -+ -+typedef struct { -+ frl_debug_cmd debug_cmd; -+ td_u8 rate; -+ td_u8 ltp; -+ td_u8 lane_idx; -+ td_u8 training_break; -+ frl_sw_train_mode sw_train_mode; -+ frl_channel_sel channel_sel; -+ td_u32 lts3_interval; -+ td_u32 lts3_timeout; -+ td_u8 crtl_type_config; -+ td_u8 avi_send_by_gen5; -+} frl_debug; -+ -+typedef enum { -+ SCDC_CMD_SET_SOURCE_VER, -+ SCDC_CMD_GET_SOURCE_VER, -+ SCDC_CMD_GET_SINK_VER, -+ SCDC_CMD_SET_FLT_UPDATE, -+ SCDC_CMD_GET_FLT_UPDATE, -+ SCDC_CMD_SET_FLT_UPDATE_TRIM, -+ SCDC_CMD_GET_FLT_UPDATE_TRIM, -+ SCDC_CMD_SET_FRL_START, -+ SCDC_CMD_GET_FRL_START, -+ SCDC_CMD_SET_CONFIG1, -+ SCDC_CMD_GET_CONFIG1, -+ SCDC_CMD_GET_TEST_CONFIG, -+ SCDC_CMD_GET_FLT_READY, -+ SCDC_CMD_GET_LTP_REQ, -+ SCDC_CMD_BUTT -+} scdc_cmd; -+ -+typedef struct { -+ td_u8 frl_rate; -+ td_u8 ffe_levels; -+} scdc_config1; -+ -+typedef struct { -+ td_bool pre_shoot_only; -+ td_bool de_emphasis_only; -+ td_bool no_ffe; -+ td_bool flt_no_timeout; -+ td_bool dsc_frl_max; -+ td_bool frl_max; -+} scdc_test_config; -+ -+typedef struct { -+ td_u8 ln0_ltp; -+ td_u8 ln1_ltp; -+ td_u8 ln2_ltp; -+ td_u8 ln3_ltp; -+} scdc_ltp_req; -+ -+typedef enum { -+ HDMI_PHY_MODE_CFG_TMDS, -+ HDMI_PHY_MODE_CFG_FRL, -+ HDMI_PHY_MODE_CFG_TXFFE -+} hdmi_phy_mode_cfg; -+ -+typedef enum { -+ HDMI_TRACE_LEN_0, /* 1.0 inch */ -+ HDMI_TRACE_LEN_1, /* 1.5 inch */ -+ HDMI_TRACE_LEN_2, /* 2.0 inch */ -+ HDMI_TRACE_LEN_3, /* 2.5 inch */ -+ HDMI_TRACE_LEN_4, /* 3.0 inch */ -+ HDMI_TRACE_LEN_5, /* 3.5 inch */ -+ HDMI_TRACE_LEN_6, /* 4.0 inch */ -+ HDMI_TRACE_LEN_7, /* 4.5 inch */ -+ HDMI_TRACE_LEN_8, /* 5.0 inch */ -+ HDMI_TRACE_DEFAULT, /* default config */ -+ HDMI_TRACE_BUTT -+} hdmi_trace_len; -+ -+typedef struct { -+ td_bool emi_en; -+ hdmi_trace_len trace_len; -+} hdmi_mode_param; -+ -+typedef struct { -+ td_u32 pixel_clk; -+ td_u32 tmds_clk; /* in khz */ -+ td_bool emi_enable; -+ hdmi_deep_color deep_color; /* deep color(color depth) */ -+ hdmi_phy_mode_cfg mode_cfg; /* tmds/frl/tx ffe */ -+ hdmi_trace_len trace_len; -+ hdmi_colorspace color_space; -+ hdmi_work_mode rate; /* lane and rate */ -+ hdmi_txfff_mode aen_tx_ffe[AEN_TX_FFE_LEN]; /* tx ffe */ -+} hdmi_phy_cfg; -+ -+hdmi_video_code_vic drv_hdmi_vic_search(hdmi_video_timing, hdmi_picture_aspect, td_bool); -+ -+td_void hdmi_reg_write(volatile td_u32 *reg_addr, td_u32 value); -+ -+td_u32 hdmi_reg_read(volatile td_u32 *reg_addr); -+ -+td_u32 drv_hdmi_vic_to_index(td_u32 vic); -+ -+hdmi_video_timing drv_hdmi_video_timing_get(hdmi_video_code_vic vic, hdmi_picture_aspect aspect); -+ -+hdmi_video_timing drv_hdmi_vsif_video_timing_get(hdmi_vsif_vic vic); -+ -+hdmi_video_4k_def *drv_hdmi_video_codes_4k_get(td_u32 cnt); -+ -+hdmi_video_def *drv_hdmi_comm_format_param_get(hdmi_video_code_vic vic); -+ -+#endif /* DRV_HDMI_COMMON_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/gfbg_reg.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/gfbg_reg.h -new file mode 100755 -index 0000000..b760b4a ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/gfbg_reg.h -@@ -0,0 +1,18438 @@ -+/* -+ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2019-2019. All rights reserved. -+ * Description: gfbg reg -+ */ -+ -+#ifndef GFBG_REG_H -+#define GFBG_REG_H -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif -+/* Define the union u_voctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 23; /* [22..0] */ -+ unsigned int g3_ck_gt_en : 1; /* [23] */ -+ unsigned int v2_ck_gt_en : 1; /* [24] */ -+ unsigned int wbc_dhd_ck_gt_en : 1; /* [25] */ -+ unsigned int g1_ck_gt_en : 1; /* [26] */ -+ unsigned int g0_ck_gt_en : 1; /* [27] */ -+ unsigned int v1_ck_gt_en : 1; /* [28] */ -+ unsigned int v0_ck_gt_en : 1; /* [29] */ -+ unsigned int chk_sum_en : 1; /* [30] */ -+ unsigned int vo_ck_gt_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_voctrl; -+ -+/* Define the union u_vointsta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_int : 1; /* [0] */ -+ unsigned int dhd0vtthd2_int : 1; /* [1] */ -+ unsigned int dhd0vtthd3_int : 1; /* [2] */ -+ unsigned int dhd0uf_int : 1; /* [3] */ -+ unsigned int dhd1vtthd1_int : 1; /* [4] */ -+ unsigned int dhd1vtthd2_int : 1; /* [5] */ -+ unsigned int dhd1vtthd3_int : 1; /* [6] */ -+ unsigned int dhd1uf_int : 1; /* [7] */ -+ unsigned int dsdvtthd1_int : 1; /* [8] */ -+ unsigned int dsdvtthd2_int : 1; /* [9] */ -+ unsigned int dsdvtthd3_int : 1; /* [10] */ -+ unsigned int dsduf_int : 1; /* [11] */ -+ unsigned int b0_err_int : 1; /* [12] */ -+ unsigned int b1_err_int : 1; /* [13] */ -+ unsigned int b2_err_int : 1; /* [14] */ -+ unsigned int wbc_dhd_over_int : 1; /* [15] */ -+ unsigned int vdac0_int : 1; /* [16] */ -+ unsigned int vdac1_int : 1; /* [17] */ -+ unsigned int vdac2_int : 1; /* [18] */ -+ unsigned int vdac3_int : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vointsta; -+ -+/* Define the union u_vomskintsta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_clr : 1; /* [0] */ -+ unsigned int dhd0vtthd2_clr : 1; /* [1] */ -+ unsigned int dhd0vtthd3_clr : 1; /* [2] */ -+ unsigned int dhd0uf_clr : 1; /* [3] */ -+ unsigned int dhd1vtthd1_clr : 1; /* [4] */ -+ unsigned int dhd1vtthd2_clr : 1; /* [5] */ -+ unsigned int dhd1vtthd3_clr : 1; /* [6] */ -+ unsigned int dhd1uf_clr : 1; /* [7] */ -+ unsigned int dsdvtthd1_clr : 1; /* [8] */ -+ unsigned int dsdvtthd2_clr : 1; /* [9] */ -+ unsigned int dsdvtthd3_clr : 1; /* [10] */ -+ unsigned int dsduf_clr : 1; /* [11] */ -+ unsigned int b0_err_clr : 1; /* [12] */ -+ unsigned int b1_err_clr : 1; /* [13] */ -+ unsigned int b2_err_clr : 1; /* [14] */ -+ unsigned int wbc_dhd_over_clr : 1; /* [15] */ -+ unsigned int vdac0_clr : 1; /* [16] */ -+ unsigned int vdac1_clr : 1; /* [17] */ -+ unsigned int vdac2_clr : 1; /* [18] */ -+ unsigned int vdac3_clr : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vomskintsta; -+ -+/* Define the union u_vointmsk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ -+ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ -+ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ -+ unsigned int dhd0uf_intmask : 1; /* [3] */ -+ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ -+ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ -+ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ -+ unsigned int dhd1uf_intmask : 1; /* [7] */ -+ unsigned int dsdvtthd1_intmask : 1; /* [8] */ -+ unsigned int dsdvtthd2_intmask : 1; /* [9] */ -+ unsigned int dsdvtthd3_intmask : 1; /* [10] */ -+ unsigned int dsduf_intmask : 1; /* [11] */ -+ unsigned int b0_err_intmask : 1; /* [12] */ -+ unsigned int b1_err_intmask : 1; /* [13] */ -+ unsigned int b2_err_intmask : 1; /* [14] */ -+ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ -+ unsigned int vdac0_intmask : 1; /* [16] */ -+ unsigned int vdac1_intmask : 1; /* [17] */ -+ unsigned int vdac2_intmask : 1; /* [18] */ -+ unsigned int vdac3_intmask : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vointmsk; -+ -+/* Define the union u_vodebug */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rm_en_chn : 4; /* [3..0] */ -+ unsigned int dhd0_ff_info : 2; /* [5..4] */ -+ unsigned int dhd1_ff_info : 2; /* [7..6] */ -+ unsigned int dsd0_ff_info : 2; /* [9..8] */ -+ unsigned int bfm_vga_en : 1; /* [10] */ -+ unsigned int bfm_cvbs_en : 1; /* [11] */ -+ unsigned int bfm_lcd_en : 1; /* [12] */ -+ unsigned int bfm_bt1120_en : 1; /* [13] */ -+ unsigned int wbc2_ff_info : 2; /* [15..14] */ -+ unsigned int wbc_mode : 4; /* [19..16] */ -+ unsigned int node_num : 4; /* [23..20] */ -+ unsigned int wbc_cmp_mode : 2; /* [25..24] */ -+ unsigned int bfm_mode : 3; /* [28..26] */ -+ unsigned int bfm_clk_sel : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vodebug; -+ -+/* Define the union u_vointsta1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_int : 1; /* [0] */ -+ unsigned int dhd0vtthd2_int : 1; /* [1] */ -+ unsigned int dhd0vtthd3_int : 1; /* [2] */ -+ unsigned int dhd0uf_int : 1; /* [3] */ -+ unsigned int dhd1vtthd1_int : 1; /* [4] */ -+ unsigned int dhd1vtthd2_int : 1; /* [5] */ -+ unsigned int dhd1vtthd3_int : 1; /* [6] */ -+ unsigned int dhd1uf_int : 1; /* [7] */ -+ unsigned int dsdvtthd1_int : 1; /* [8] */ -+ unsigned int dsdvtthd2_int : 1; /* [9] */ -+ unsigned int dsdvtthd3_int : 1; /* [10] */ -+ unsigned int dsduf_int : 1; /* [11] */ -+ unsigned int b0_err_int : 1; /* [12] */ -+ unsigned int b1_err_int : 1; /* [13] */ -+ unsigned int b2_err_int : 1; /* [14] */ -+ unsigned int wbc_dhd_over_int : 1; /* [15] */ -+ unsigned int vdac0_int : 1; /* [16] */ -+ unsigned int vdac1_int : 1; /* [17] */ -+ unsigned int vdac2_int : 1; /* [18] */ -+ unsigned int vdac3_int : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vointsta1; -+ -+/* Define the union u_vomskintsta1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_clr : 1; /* [0] */ -+ unsigned int dhd0vtthd2_clr : 1; /* [1] */ -+ unsigned int dhd0vtthd3_clr : 1; /* [2] */ -+ unsigned int dhd0uf_clr : 1; /* [3] */ -+ unsigned int dhd1vtthd1_clr : 1; /* [4] */ -+ unsigned int dhd1vtthd2_clr : 1; /* [5] */ -+ unsigned int dhd1vtthd3_clr : 1; /* [6] */ -+ unsigned int dhd1uf_clr : 1; /* [7] */ -+ unsigned int dsdvtthd1_clr : 1; /* [8] */ -+ unsigned int dsdvtthd2_clr : 1; /* [9] */ -+ unsigned int dsdvtthd3_clr : 1; /* [10] */ -+ unsigned int dsduf_clr : 1; /* [11] */ -+ unsigned int b0_err_clr : 1; /* [12] */ -+ unsigned int b1_err_clr : 1; /* [13] */ -+ unsigned int b2_err_clr : 1; /* [14] */ -+ unsigned int wbc_dhd_over_clr : 1; /* [15] */ -+ unsigned int vdac0_clr : 1; /* [16] */ -+ unsigned int vdac1_clr : 1; /* [17] */ -+ unsigned int vdac2_clr : 1; /* [18] */ -+ unsigned int vdac3_clr : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vomskintsta1; -+ -+/* Define the union u_vointmsk1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ -+ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ -+ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ -+ unsigned int dhd0uf_intmask : 1; /* [3] */ -+ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ -+ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ -+ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ -+ unsigned int dhd1uf_intmask : 1; /* [7] */ -+ unsigned int dsdvtthd1_intmask : 1; /* [8] */ -+ unsigned int dsdvtthd2_intmask : 1; /* [9] */ -+ unsigned int dsdvtthd3_intmask : 1; /* [10] */ -+ unsigned int dsduf_intmask : 1; /* [11] */ -+ unsigned int b0_err_intmask : 1; /* [12] */ -+ unsigned int b1_err_intmask : 1; /* [13] */ -+ unsigned int b2_err_intmask : 1; /* [14] */ -+ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ -+ unsigned int vdac0_intmask : 1; /* [16] */ -+ unsigned int vdac1_intmask : 1; /* [17] */ -+ unsigned int vdac2_intmask : 1; /* [18] */ -+ unsigned int vdac3_intmask : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vointmsk1; -+ -+/* Define the union u_volowpower_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rfs_ema : 3; /* [2..0] */ -+ unsigned int rfs_emaw : 2; /* [4..3] */ -+ unsigned int ret1n : 1; /* [5] */ -+ unsigned int rft_emaa : 3; /* [8..6] */ -+ unsigned int rft_emab : 3; /* [11..9] */ -+ unsigned int rfs_colldisn : 1; /* [12] */ -+ unsigned int rft_emasa : 1; /* [13] */ -+ unsigned int rftuhd_ema : 3; /* [16..14] */ -+ unsigned int rftuhd_emaw : 2; /* [18..17] */ -+ unsigned int rftuhd_emas : 1; /* [19] */ -+ unsigned int rftuhd_emap : 1; /* [20] */ -+ unsigned int rftuhd_stov : 1; /* [21] */ -+ unsigned int rftuhd_stovab : 1; /* [22] */ -+ unsigned int rfs_wabl : 1; /* [23] */ -+ unsigned int rfs_wablm : 2; /* [25..24] */ -+ unsigned int ras_ema : 3; /* [28..26] */ -+ unsigned int ras_emaw : 2; /* [30..29] */ -+ unsigned int ras_stov : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_volowpower_ctrl; -+ -+/* Define the union u_voufsta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_uf_sta : 1; /* [0] */ -+ unsigned int v1_uf_sta : 1; /* [1] */ -+ unsigned int reserved_0 : 1; /* [2] */ -+ unsigned int v3_uf_sta : 1; /* [3] */ -+ unsigned int reserved_1 : 4; /* [7..4] */ -+ unsigned int g0_uf_sta : 1; /* [8] */ -+ unsigned int g1_uf_sta : 1; /* [9] */ -+ unsigned int g2_uf_sta : 1; /* [10] */ -+ unsigned int g3_uf_sta : 1; /* [11] */ -+ unsigned int g4_uf_sta : 1; /* [12] */ -+ unsigned int reserved_2 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_voufsta; -+ -+/* Define the union u_voufclr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_uf_clr : 1; /* [0] */ -+ unsigned int v1_uf_clr : 1; /* [1] */ -+ unsigned int reserved_0 : 1; /* [2] */ -+ unsigned int v3_uf_clr : 1; /* [3] */ -+ unsigned int reserved_1 : 4; /* [7..4] */ -+ unsigned int g0_uf_clr : 1; /* [8] */ -+ unsigned int g1_uf_clr : 1; /* [9] */ -+ unsigned int g2_uf_clr : 1; /* [10] */ -+ unsigned int g3_uf_clr : 1; /* [11] */ -+ unsigned int g4_uf_clr : 1; /* [12] */ -+ unsigned int reserved_2 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_voufclr; -+ -+/* Define the union u_vointproc_tim */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vointproc_time : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vointproc_tim; -+ -+/* Define the union u_volowpower_ctrl1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rftf_rct : 2; /* [1..0] */ -+ unsigned int rftf_kp : 3; /* [4..2] */ -+ unsigned int rft_wtsel : 2; /* [6..5] */ -+ unsigned int rft_rtsel : 2; /* [8..7] */ -+ unsigned int rft_mtsel : 2; /* [10..9] */ -+ unsigned int rasshds_wtsel : 2; /* [12..11] */ -+ unsigned int rasshds_rtsel : 2; /* [14..13] */ -+ unsigned int rasshdm_wtsel : 2; /* [16..15] */ -+ unsigned int rasshdm_rtsel : 2; /* [18..17] */ -+ unsigned int rashds_wtsel : 2; /* [20..19] */ -+ unsigned int rashds_rtsel : 2; /* [22..21] */ -+ unsigned int rashdm_wtsel : 2; /* [24..23] */ -+ unsigned int rashdm_rtsel : 2; /* [26..25] */ -+ unsigned int ras_wtsel : 2; /* [28..27] */ -+ unsigned int ras_rtsel : 2; /* [30..29] */ -+ unsigned int ras_emas : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_volowpower_ctrl1; -+ -+/* Define the union u_vofpgadef */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_hdr_v_def : 1; /* [0] */ -+ unsigned int ot_hdr_g_def : 1; /* [1] */ -+ unsigned int ot_hdr_wd_def : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vofpgadef; -+ -+/* Define the union u_volowpower_ctrl2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int s14_rfshd_rm : 4; /* [3..0] */ -+ unsigned int s14_rfshs_rm : 4; /* [7..4] */ -+ unsigned int s14_rasehd_rm : 4; /* [11..8] */ -+ unsigned int s14_rashd_rm : 4; /* [15..12] */ -+ unsigned int s14_rfshd_rme : 1; /* [16] */ -+ unsigned int s14_rfshs_rme : 1; /* [17] */ -+ unsigned int s14_rasehd_rme : 1; /* [18] */ -+ unsigned int s14_rashd_rme : 1; /* [19] */ -+ unsigned int s14_rfthd_rma : 4; /* [23..20] */ -+ unsigned int s14_rfthd_rmb : 4; /* [27..24] */ -+ unsigned int s14_rfthd_rmea : 1; /* [28] */ -+ unsigned int s14_rfthd_rmeb : 1; /* [29] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_volowpower_ctrl2; -+ -+/* Define the union u_volowpower_ctrl3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int s14_rom_rm : 4; /* [3..0] */ -+ unsigned int s14_rom_rme : 1; /* [4] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_volowpower_ctrl3; -+ -+/* Define the union u_vomux_dac */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dac0_sel : 4; /* [3..0] */ -+ unsigned int dac1_sel : 4; /* [7..4] */ -+ unsigned int dac2_sel : 4; /* [11..8] */ -+ unsigned int dac3_sel : 4; /* [15..12] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vomux_dac; -+ -+/* Define the union u_vomux_testsync */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int test_dv : 1; /* [0] */ -+ unsigned int test_hsync : 1; /* [1] */ -+ unsigned int test_vsync : 1; /* [2] */ -+ unsigned int test_field : 1; /* [3] */ -+ unsigned int reserved_0 : 27; /* [30..4] */ -+ unsigned int vo_test_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vomux_testsync; -+ -+/* Define the union u_vomux_testdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int test_data : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vomux_testdata; -+ -+/* Define the union u_vo_dac_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dac_reg_rev : 16; /* [15..0] */ -+ unsigned int enctr : 4; /* [19..16] */ -+ unsigned int enextref : 1; /* [20] */ -+ unsigned int pdchopper : 1; /* [21] */ -+ unsigned int envbg : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac_ctrl; -+ -+/* Define the union u_vo_dac_otp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dac_otp_reg : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac_otp; -+ -+/* Define the union u_vo_dac0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac0_ctrl; -+ -+/* Define the union u_vo_dac1_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac1_ctrl; -+ -+/* Define the union u_vo_dac2_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac2_ctrl; -+ -+/* Define the union u_vo_dac3_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac3_ctrl; -+ -+/* Define the union u_vo_dac_stat0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cableout0 : 1; /* [0] */ -+ unsigned int cableout1 : 1; /* [1] */ -+ unsigned int cableout2 : 1; /* [2] */ -+ unsigned int cableout3 : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_dac_stat0; -+ -+/* Define the union u_cbm_bkg1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cbm_bkgcr1 : 10; /* [9..0] */ -+ unsigned int cbm_bkgcb1 : 10; /* [19..10] */ -+ unsigned int cbm_bkgy1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_cbm_bkg1; -+ -+/* Define the union u_cbm_mix1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int mixer_prio4 : 4; /* [19..16] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_cbm_mix1; -+ -+/* Define the union u_wbc_bmp_thd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_bmp_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_bmp_thd; -+ -+/* Define the union u_cbm_bkg2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cbm_bkgcr2 : 10; /* [9..0] */ -+ unsigned int cbm_bkgcb2 : 10; /* [19..10] */ -+ unsigned int cbm_bkgy2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_cbm_bkg2; -+ -+/* Define the union u_cbm_mix2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int mixer_prio4 : 4; /* [19..16] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_cbm_mix2; -+ -+/* Define the union u_hc_bmp_thd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hc_bmp_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hc_bmp_thd; -+ -+/* Define the union u_cbm_bkg3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cbm_bkgcr3 : 10; /* [9..0] */ -+ unsigned int cbm_bkgcb3 : 10; /* [19..10] */ -+ unsigned int cbm_bkgy3 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_cbm_bkg3; -+ -+/* Define the union u_cbm_mix3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_cbm_mix3; -+ -+/* Define the union u_mixv0_bkg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_bkgcr : 10; /* [9..0] */ -+ unsigned int mixer_bkgcb : 10; /* [19..10] */ -+ unsigned int mixer_bkgy : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mixv0_bkg; -+ -+/* Define the union u_mixv0_mix */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mixv0_mix; -+ -+/* Define the union u_mixg0_bkg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_bkgcr : 10; /* [9..0] */ -+ unsigned int mixer_bkgcb : 10; /* [19..10] */ -+ unsigned int mixer_bkgy : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mixg0_bkg; -+ -+/* Define the union u_mixg0_bkalpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mixg0_bkalpha; -+ -+/* Define the union u_mixg0_mix */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mixg0_mix; -+typedef union { -+ struct { -+ unsigned int v2_link : 2; /* [1..0] */ -+ unsigned int g3_link : 2; /* [3..2] */ -+ unsigned int g2_link : 2; /* borrow 2 bits from reserved for complie */ -+ unsigned int g4_link : 2; /* borrow 2 bits from reserved for complie */ -+ unsigned int reserved : 24; /* [31..8] */ -+ } bits; -+ unsigned int u32; -+} u_link_ctrl; -+ -+/* Define the union u_vpss_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vpss_en : 1; /* [0] */ -+ unsigned int chk_sum_en : 1; /* [1] */ -+ unsigned int dei_en : 1; /* [2] */ -+ unsigned int mcdi_en : 1; /* [3] */ -+ unsigned int nx2_vc1_en : 1; /* [4] */ -+ unsigned int rgme_en : 1; /* [5] */ -+ unsigned int meds_en : 1; /* [6] */ -+ unsigned int hsp_en : 1; /* [7] */ -+ unsigned int snr_en : 1; /* [8] */ -+ unsigned int tnr_en : 1; /* [9] */ -+ unsigned int rfr_en : 1; /* [10] */ -+ unsigned int ifmd_en : 1; /* [11] */ -+ unsigned int igbm_en : 1; /* [12] */ -+ unsigned int cue_en : 1; /* [13] */ -+ unsigned int scd_en : 1; /* [14] */ -+ unsigned int blk_det_en : 1; /* [15] */ -+ unsigned int reserved_0 : 7; /* [22..16] */ -+ unsigned int vpss_node_init : 1; /* [23] */ -+ unsigned int ram_bank : 4; /* [27..24] */ -+ unsigned int dei_debug_en : 1; /* [28] */ -+ unsigned int dei_repeat_mode : 1; /* [29] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vpss_ctrl; -+ -+/* Define the union u_vpss_miscellaneous */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 4; /* [3..0] */ -+ unsigned int reserved_1 : 4; /* [7..4] */ -+ unsigned int reserved_2 : 16; /* [23..8] */ -+ unsigned int ck_gt_en : 1; /* [24] */ -+ unsigned int ck_gt_en_calc : 1; /* [25] */ -+ unsigned int reserved_3 : 2; /* [27..26] */ -+ unsigned int reserved_4 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vpss_miscellaneous; -+ -+/* Define the union u_vpss_ftconfig */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int node_rst_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vpss_ftconfig; -+ -+/* Define the union u_para_up_vhd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_up_vhd_chn00 : 1; /* [0] */ -+ unsigned int para_up_vhd_chn01 : 1; /* [1] */ -+ unsigned int para_up_vhd_chn02 : 1; /* [2] */ -+ unsigned int para_up_vhd_chn03 : 1; /* [3] */ -+ unsigned int para_up_vhd_chn04 : 1; /* [4] */ -+ unsigned int para_up_vhd_chn05 : 1; /* [5] */ -+ unsigned int para_up_vhd_chn06 : 1; /* [6] */ -+ unsigned int para_up_vhd_chn07 : 1; /* [7] */ -+ unsigned int para_up_vhd_chn08 : 1; /* [8] */ -+ unsigned int para_up_vhd_chn09 : 1; /* [9] */ -+ unsigned int para_up_vhd_chn10 : 1; /* [10] */ -+ unsigned int para_up_vhd_chn11 : 1; /* [11] */ -+ unsigned int para_up_vhd_chn12 : 1; /* [12] */ -+ unsigned int para_up_vhd_chn13 : 1; /* [13] */ -+ unsigned int para_up_vhd_chn14 : 1; /* [14] */ -+ unsigned int para_up_vhd_chn15 : 1; /* [15] */ -+ unsigned int para_up_vhd_chn16 : 1; /* [16] */ -+ unsigned int para_up_vhd_chn17 : 1; /* [17] */ -+ unsigned int para_up_vhd_chn18 : 1; /* [18] */ -+ unsigned int para_up_vhd_chn19 : 1; /* [19] */ -+ unsigned int para_up_vhd_chn20 : 1; /* [20] */ -+ unsigned int para_up_vhd_chn21 : 1; /* [21] */ -+ unsigned int para_up_vhd_chn22 : 1; /* [22] */ -+ unsigned int para_up_vhd_chn23 : 1; /* [23] */ -+ unsigned int para_up_vhd_chn24 : 1; /* [24] */ -+ unsigned int para_up_vhd_chn25 : 1; /* [25] */ -+ unsigned int para_up_vhd_chn26 : 1; /* [26] */ -+ unsigned int para_up_vhd_chn27 : 1; /* [27] */ -+ unsigned int para_up_vhd_chn28 : 1; /* [28] */ -+ unsigned int para_up_vhd_chn29 : 1; /* [29] */ -+ unsigned int para_up_vhd_chn30 : 1; /* [30] */ -+ unsigned int para_up_vhd_chn31 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_para_up_vhd; -+ -+/* Define the union u_para_up_vsd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_up_vsd_chn00 : 1; /* [0] */ -+ unsigned int para_up_vsd_chn01 : 1; /* [1] */ -+ unsigned int para_up_vsd_chn02 : 1; /* [2] */ -+ unsigned int para_up_vsd_chn03 : 1; /* [3] */ -+ unsigned int para_up_vsd_chn04 : 1; /* [4] */ -+ unsigned int para_up_vsd_chn05 : 1; /* [5] */ -+ unsigned int para_up_vsd_chn06 : 1; /* [6] */ -+ unsigned int para_up_vsd_chn07 : 1; /* [7] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_para_up_vsd; -+ -+/* Define the union u_para_conflict_clr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_conflict_clr_hd : 1; /* [0] */ -+ unsigned int para_conflict_clr_sd : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_para_conflict_clr; -+ -+/* Define the union u_para_conflict_sta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_conflict_hd : 1; /* [0] */ -+ unsigned int para_conflict_sd : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_para_conflict_sta; -+ -+/* Define the union u_v0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ctrl; -+ -+/* Define the union u_v0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_upd; -+ -+/* Define the union u_v0_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_0reso_read; -+ -+/* Define the union u_v0_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ireso; -+ -+/* Define the union u_v0_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_dfpos; -+ -+/* Define the union u_v0_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_dlpos; -+ -+/* Define the union u_v0_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_vfpos; -+ -+/* Define the union u_v0_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_vlpos; -+ -+/* Define the union u_v0_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_bk; -+ -+/* Define the union u_v0_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_alpha; -+ -+/* Define the union u_v0_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mute_bk; -+ -+/* Define the union u_v0_rimwidth */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_width : 5; /* [4..0] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_rimwidth; -+ -+/* Define the union u_v0_rimcol0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_v0 : 10; /* [9..0] */ -+ unsigned int v0_rim_u0 : 10; /* [19..10] */ -+ unsigned int v0_rim_y0 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_rimcol0; -+ -+/* Define the union u_v0_rimcol1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_v1 : 10; /* [9..0] */ -+ unsigned int v0_rim_u1 : 10; /* [19..10] */ -+ unsigned int v0_rim_y1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_rimcol1; -+ -+/* Define the union u_v0_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_ctrl; -+ -+/* Define the union u_v0_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef00; -+ -+/* Define the union u_v0_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef01; -+ -+/* Define the union u_v0_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef02; -+ -+/* Define the union u_v0_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef10; -+ -+/* Define the union u_v0_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef11; -+ -+/* Define the union u_v0_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef12; -+ -+/* Define the union u_v0_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef20; -+ -+/* Define the union u_v0_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef21; -+ -+/* Define the union u_v0_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_coef22; -+ -+/* Define the union u_v0_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_scale; -+ -+/* Define the union u_v0_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_idc0; -+ -+/* Define the union u_v0_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_idc1; -+ -+/* Define the union u_v0_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_idc2; -+ -+/* Define the union u_v0_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_odc0; -+ -+/* Define the union u_v0_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_odc1; -+ -+/* Define the union u_v0_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_odc2; -+ -+/* Define the union u_v0_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_min_y; -+ -+/* Define the union u_v0_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_min_c; -+ -+/* Define the union u_v0_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_max_y; -+ -+/* Define the union u_v0_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_max_c; -+ -+/* Define the union u_v0_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef00; -+ -+/* Define the union u_v0_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef01; -+ -+/* Define the union u_v0_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef02; -+ -+/* Define the union u_v0_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef10; -+ -+/* Define the union u_v0_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef11; -+ -+/* Define the union u_v0_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef12; -+ -+/* Define the union u_v0_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef20; -+ -+/* Define the union u_v0_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef21; -+ -+/* Define the union u_v0_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_coef22; -+ -+/* Define the union u_v0_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_scale; -+ -+/* Define the union u_v0_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_idc0; -+ -+/* Define the union u_v0_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_idc1; -+ -+/* Define the union u_v0_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_idc2; -+ -+/* Define the union u_v0_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_odc0; -+ -+/* Define the union u_v0_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_odc1; -+ -+/* Define the union u_v0_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_odc2; -+ -+/* Define the union u_v0_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_min_y; -+ -+/* Define the union u_v0_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_min_c; -+ -+/* Define the union u_v0_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_max_y; -+ -+/* Define the union u_v0_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc2_max_c; -+ -+/* Define the union u_v0_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_v0_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_ot_pp_csc_ink_pos; -+ -+/* Define the union u_v0_zme_hinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int hzme_ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hinfo; -+ -+/* Define the union u_v0_zme_hsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int chfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int non_lnr_en : 1; /* [27] */ -+ unsigned int chmid_en : 1; /* [28] */ -+ unsigned int lhmid_en : 1; /* [29] */ -+ unsigned int chfir_en : 1; /* [30] */ -+ unsigned int lhfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hsp; -+ -+/* Define the union u_v0_zme_hloffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hloffset; -+ -+/* Define the union u_v0_zme_hcoffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hcoffset; -+ -+/* Define the union u_v0_zme_hzone0delta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int zone0_delta : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hzone0delta; -+ -+/* Define the union u_v0_zme_hzone2delta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int zone2_delta : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hzone2delta; -+ -+/* Define the union u_v0_zme_hzoneend */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int zone0_end : 12; /* [11..0] */ -+ unsigned int zone1_end : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hzoneend; -+ -+/* Define the union u_v0_zme_hl_shootctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hl_coring : 8; /* [7..0] */ -+ unsigned int hl_gain : 6; /* [13..8] */ -+ unsigned int hl_coringadj_en : 1; /* [14] */ -+ unsigned int hl_flatdect_mode : 1; /* [15] */ -+ unsigned int hl_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int hl_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hl_shootctrl; -+ -+/* Define the union u_v0_zme_hc_shootctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hc_coring : 8; /* [7..0] */ -+ unsigned int hc_gain : 6; /* [13..8] */ -+ unsigned int hc_coringadj_en : 1; /* [14] */ -+ unsigned int hc_flatdect_mode : 1; /* [15] */ -+ unsigned int hc_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int hc_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hc_shootctrl; -+ -+/* Define the union u_v0_zme_hcoef_ren */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_hf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hcoef_ren; -+ -+/* Define the union u_v0_zme_hcoef_rdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_hcoef_rdata; -+ -+/* Define the union u_v0_zme_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vinfo; -+ -+/* Define the union u_v0_zme_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int graphdet_en : 1; /* [16] */ -+ unsigned int reserved_0 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int vfir_1tap_en : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int lvmid_en : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int lvfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vsp; -+ -+/* Define the union u_v0_zme_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int vluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_voffset; -+ -+/* Define the union u_v0_zme_vboffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int vbluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vboffset; -+ -+/* Define the union u_v0_zme_vl_shootctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vl_coring : 8; /* [7..0] */ -+ unsigned int vl_gain : 6; /* [13..8] */ -+ unsigned int vl_coringadj_en : 1; /* [14] */ -+ unsigned int vl_flatdect_mode : 1; /* [15] */ -+ unsigned int vl_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int vl_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vl_shootctrl; -+ -+/* Define the union u_v0_zme_vc_shootctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vc_coring : 8; /* [7..0] */ -+ unsigned int vc_gain : 6; /* [13..8] */ -+ unsigned int vc_coringadj_en : 1; /* [14] */ -+ unsigned int vc_flatdect_mode : 1; /* [15] */ -+ unsigned int vc_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int vc_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vc_shootctrl; -+ -+/* Define the union u_v0_zme_vcoef_ren */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_vf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vcoef_ren; -+ -+/* Define the union u_v0_zme_vcoef_rdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_zme_vcoef_rdata; -+ -+/* Define the union u_v0_hfir_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_hfir_ctrl; -+ -+/* Define the union u_v0_hfircoef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_hfircoef01; -+ -+/* Define the union u_v0_hfircoef23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_hfircoef23; -+ -+/* Define the union u_v0_hfircoef45 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_hfircoef45; -+ -+/* Define the union u_v0_hfircoef67 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_hfircoef67; -+ -+/* Define the union u_v1_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ctrl; -+ -+/* Define the union u_v1_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_upd; -+ -+/* Define the union u_v1_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_0reso_read; -+ -+/* Define the union u_v1_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ireso; -+ -+/* Define the union u_v1_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_dfpos; -+ -+/* Define the union u_v1_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_dlpos; -+ -+/* Define the union u_v1_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_vfpos; -+ -+/* Define the union u_v1_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_vlpos; -+ -+/* Define the union u_v1_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_bk; -+ -+/* Define the union u_v1_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_alpha; -+ -+/* Define the union u_v1_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mute_bk; -+ -+/* Define the union u_v1_rimwidth */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_width : 5; /* [4..0] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_rimwidth; -+ -+/* Define the union u_v1_rimcol0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_v0 : 10; /* [9..0] */ -+ unsigned int v0_rim_u0 : 10; /* [19..10] */ -+ unsigned int v0_rim_y0 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_rimcol0; -+ -+/* Define the union u_v1_rimcol1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_v1 : 10; /* [9..0] */ -+ unsigned int v0_rim_u1 : 10; /* [19..10] */ -+ unsigned int v0_rim_y1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_rimcol1; -+ -+/* Define the union u_v1_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_ctrl; -+ -+/* Define the union u_v1_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef00; -+ -+/* Define the union u_v1_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef01; -+ -+/* Define the union u_v1_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef02; -+ -+/* Define the union u_v1_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef10; -+ -+/* Define the union u_v1_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef11; -+ -+/* Define the union u_v1_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef12; -+ -+/* Define the union u_v1_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef20; -+ -+/* Define the union u_v1_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef21; -+ -+/* Define the union u_v1_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_coef22; -+ -+/* Define the union u_v1_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_scale; -+ -+/* Define the union u_v1_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_idc0; -+ -+/* Define the union u_v1_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_idc1; -+ -+/* Define the union u_v1_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_idc2; -+ -+/* Define the union u_v1_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_odc0; -+ -+/* Define the union u_v1_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_odc1; -+ -+/* Define the union u_v1_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_odc2; -+ -+/* Define the union u_v1_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_min_y; -+ -+/* Define the union u_v1_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_min_c; -+ -+/* Define the union u_v1_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_max_y; -+ -+/* Define the union u_v1_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_max_c; -+ -+/* Define the union u_v1_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef00; -+ -+/* Define the union u_v1_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef01; -+ -+/* Define the union u_v1_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef02; -+ -+/* Define the union u_v1_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef10; -+ -+/* Define the union u_v1_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef11; -+ -+/* Define the union u_v1_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef12; -+ -+/* Define the union u_v1_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef20; -+ -+/* Define the union u_v1_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef21; -+ -+/* Define the union u_v1_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_coef22; -+ -+/* Define the union u_v1_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_scale; -+ -+/* Define the union u_v1_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_idc0; -+ -+/* Define the union u_v1_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_idc1; -+ -+/* Define the union u_v1_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_idc2; -+ -+/* Define the union u_v1_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_odc0; -+ -+/* Define the union u_v1_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_odc1; -+ -+/* Define the union u_v1_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_odc2; -+ -+/* Define the union u_v1_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_min_y; -+ -+/* Define the union u_v1_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_min_c; -+ -+/* Define the union u_v1_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_max_y; -+ -+/* Define the union u_v1_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc2_max_c; -+ -+/* Define the union u_v1_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_v1_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_ot_pp_csc_ink_pos; -+ -+/* Define the union u_v1_cvfir_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_vinfo; -+ -+/* Define the union u_v1_cvfir_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_vsp; -+ -+/* Define the union u_v1_cvfir_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_voffset; -+ -+/* Define the union u_v1_cvfir_vboffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_vboffset; -+ -+/* Define the union u_v1_cvfir_vcoef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_vcoef0; -+ -+/* Define the union u_v1_cvfir_vcoef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_vcoef1; -+ -+/* Define the union u_v1_cvfir_vcoef2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_cvfir_vcoef2; -+ -+/* Define the union u_v1_hfir_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_hfir_ctrl; -+ -+/* Define the union u_v1_hfircoef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_hfircoef01; -+ -+/* Define the union u_v1_hfircoef23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_hfircoef23; -+ -+/* Define the union u_v1_hfircoef45 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_hfircoef45; -+ -+/* Define the union u_v1_hfircoef67 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_hfircoef67; -+ -+/* Define the union u_v2_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ctrl; -+ -+/* Define the union u_v2_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_upd; -+ -+/* Define the union u_v2_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_0reso_read; -+ -+/* Define the union u_v2_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ireso; -+ -+/* Define the union u_v2_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_dfpos; -+ -+/* Define the union u_v2_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_dlpos; -+ -+/* Define the union u_v2_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_vfpos; -+ -+/* Define the union u_v2_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_vlpos; -+ -+/* Define the union u_v2_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_bk; -+ -+/* Define the union u_v2_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_alpha; -+ -+/* Define the union u_v2_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_mute_bk; -+ -+/* Define the union u_v2_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_ctrl; -+ -+/* Define the union u_v2_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef00; -+ -+/* Define the union u_v2_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef01; -+ -+/* Define the union u_v2_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef02; -+ -+/* Define the union u_v2_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef10; -+ -+/* Define the union u_v2_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef11; -+ -+/* Define the union u_v2_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef12; -+ -+/* Define the union u_v2_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef20; -+ -+/* Define the union u_v2_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef21; -+ -+/* Define the union u_v2_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_coef22; -+ -+/* Define the union u_v2_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_scale; -+ -+/* Define the union u_v2_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_idc0; -+ -+/* Define the union u_v2_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_idc1; -+ -+/* Define the union u_v2_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_idc2; -+ -+/* Define the union u_v2_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_odc0; -+ -+/* Define the union u_v2_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_odc1; -+ -+/* Define the union u_v2_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_odc2; -+ -+/* Define the union u_v2_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_min_y; -+ -+/* Define the union u_v2_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_min_c; -+ -+/* Define the union u_v2_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_max_y; -+ -+/* Define the union u_v2_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_max_c; -+ -+/* Define the union u_v2_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef00; -+ -+/* Define the union u_v2_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef01; -+ -+/* Define the union u_v2_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef02; -+ -+/* Define the union u_v2_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef10; -+ -+/* Define the union u_v2_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef11; -+ -+/* Define the union u_v2_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef12; -+ -+/* Define the union u_v2_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef20; -+ -+/* Define the union u_v2_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef21; -+ -+/* Define the union u_v2_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_coef22; -+ -+/* Define the union u_v2_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_scale; -+ -+/* Define the union u_v2_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_idc0; -+ -+/* Define the union u_v2_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_idc1; -+ -+/* Define the union u_v2_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_idc2; -+ -+/* Define the union u_v2_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_odc0; -+ -+/* Define the union u_v2_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_odc1; -+ -+/* Define the union u_v2_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_odc2; -+ -+/* Define the union u_v2_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_min_y; -+ -+/* Define the union u_v2_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_min_c; -+ -+/* Define the union u_v2_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_max_y; -+ -+/* Define the union u_v2_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc2_max_c; -+ -+/* Define the union u_v2_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_v2_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_ot_pp_csc_ink_pos; -+ -+/* Define the union u_v2_cvfir_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_vinfo; -+ -+/* Define the union u_v2_cvfir_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_vsp; -+ -+/* Define the union u_v2_cvfir_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_voffset; -+ -+/* Define the union u_v2_cvfir_vboffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_vboffset; -+ -+/* Define the union u_v2_cvfir_vcoef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_vcoef0; -+ -+/* Define the union u_v2_cvfir_vcoef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_vcoef1; -+ -+/* Define the union u_v2_cvfir_vcoef2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_cvfir_vcoef2; -+ -+/* Define the union u_v2_hfir_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_hfir_ctrl; -+ -+/* Define the union u_v2_hfircoef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_hfircoef01; -+ -+/* Define the union u_v2_hfircoef23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_hfircoef23; -+ -+/* Define the union u_v2_hfircoef45 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_hfircoef45; -+ -+/* Define the union u_v2_hfircoef67 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_hfircoef67; -+ -+/* Define the union u_v3_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ctrl; -+ -+/* Define the union u_v3_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_upd; -+ -+/* Define the union u_v3_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_0reso_read; -+ -+/* Define the union u_v3_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ireso; -+ -+/* Define the union u_v3_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_dfpos; -+ -+/* Define the union u_v3_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_dlpos; -+ -+/* Define the union u_v3_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_vfpos; -+ -+/* Define the union u_v3_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_vlpos; -+ -+/* Define the union u_v3_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_bk; -+ -+/* Define the union u_v3_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_alpha; -+ -+/* Define the union u_v3_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_mute_bk; -+ -+/* Define the union u_v3_rimwidth */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_width : 5; /* [4..0] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_rimwidth; -+ -+/* Define the union u_v3_rimcol0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_v0 : 10; /* [9..0] */ -+ unsigned int v0_rim_u0 : 10; /* [19..10] */ -+ unsigned int v0_rim_y0 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_rimcol0; -+ -+/* Define the union u_v3_rimcol1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int v0_rim_v1 : 10; /* [9..0] */ -+ unsigned int v0_rim_u1 : 10; /* [19..10] */ -+ unsigned int v0_rim_y1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_rimcol1; -+ -+/* Define the union u_v3_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_ctrl; -+ -+/* Define the union u_v3_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef00; -+ -+/* Define the union u_v3_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef01; -+ -+/* Define the union u_v3_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef02; -+ -+/* Define the union u_v3_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef10; -+ -+/* Define the union u_v3_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef11; -+ -+/* Define the union u_v3_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef12; -+ -+/* Define the union u_v3_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef20; -+ -+/* Define the union u_v3_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef21; -+ -+/* Define the union u_v3_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_coef22; -+ -+/* Define the union u_v3_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_scale; -+ -+/* Define the union u_v3_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_idc0; -+ -+/* Define the union u_v3_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_idc1; -+ -+/* Define the union u_v3_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_idc2; -+ -+/* Define the union u_v3_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_odc0; -+ -+/* Define the union u_v3_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_odc1; -+ -+/* Define the union u_v3_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_odc2; -+ -+/* Define the union u_v3_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_min_y; -+ -+/* Define the union u_v3_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_min_c; -+ -+/* Define the union u_v3_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_max_y; -+ -+/* Define the union u_v3_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_max_c; -+ -+/* Define the union u_v3_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef00; -+ -+/* Define the union u_v3_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef01; -+ -+/* Define the union u_v3_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef02; -+ -+/* Define the union u_v3_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef10; -+ -+/* Define the union u_v3_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef11; -+ -+/* Define the union u_v3_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef12; -+ -+/* Define the union u_v3_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef20; -+ -+/* Define the union u_v3_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef21; -+ -+/* Define the union u_v3_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_coef22; -+ -+/* Define the union u_v3_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_scale; -+ -+/* Define the union u_v3_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_idc0; -+ -+/* Define the union u_v3_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_idc1; -+ -+/* Define the union u_v3_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_idc2; -+ -+/* Define the union u_v3_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_odc0; -+ -+/* Define the union u_v3_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_odc1; -+ -+/* Define the union u_v3_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_odc2; -+ -+/* Define the union u_v3_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_min_y; -+ -+/* Define the union u_v3_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_min_c; -+ -+/* Define the union u_v3_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_max_y; -+ -+/* Define the union u_v3_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc2_max_c; -+ -+/* Define the union u_v3_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_v3_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_ot_pp_csc_ink_pos; -+ -+/* Define the union u_v3_hfir_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_hfir_ctrl; -+ -+/* Define the union u_v3_hfircoef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_hfircoef01; -+ -+/* Define the union u_v3_hfircoef23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_hfircoef23; -+ -+/* Define the union u_v3_hfircoef45 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_hfircoef45; -+ -+/* Define the union u_v3_hfircoef67 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v3_hfircoef67; -+ -+/* Define the union u_vp0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_upd; -+ -+/* Define the union u_vp0_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_ireso; -+ -+/* Define the union u_vp0_lbox_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_lbox_ctrl; -+ -+/* Define the union u_vp0_galpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_galpha; -+ -+/* Define the union u_vp0_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 12; /* [11..0] */ -+ unsigned int disp_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_dfpos; -+ -+/* Define the union u_vp0_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 12; /* [11..0] */ -+ unsigned int disp_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_dlpos; -+ -+/* Define the union u_vp0_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 12; /* [11..0] */ -+ unsigned int video_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_vfpos; -+ -+/* Define the union u_vp0_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 12; /* [11..0] */ -+ unsigned int video_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_vlpos; -+ -+/* Define the union u_vp0_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_bk; -+ -+/* Define the union u_vp0_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_alpha; -+ -+/* Define the union u_vp0_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vp0_mute_bk; -+ -+/* Define the union u_g0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g0_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ctrl; -+ -+/* Define the union u_g0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_upd; -+ -+/* Define the union u_g0_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_0reso_read; -+ -+/* Define the union u_g0_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ireso; -+ -+/* Define the union u_g0_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_dfpos; -+ -+/* Define the union u_g0_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_dlpos; -+ -+/* Define the union u_g0_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_vfpos; -+ -+/* Define the union u_g0_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_vlpos; -+ -+/* Define the union u_g0_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_bk; -+ -+/* Define the union u_g0_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_alpha; -+ -+/* Define the union u_g0_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_mute_bk; -+ -+/* Define the union u_g0_lbox_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_lbox_ctrl; -+ -+/* Define the union u_g0_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_ctrl; -+ -+/* Define the union u_g0_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef00; -+ -+/* Define the union u_g0_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef01; -+ -+/* Define the union u_g0_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef02; -+ -+/* Define the union u_g0_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef10; -+ -+/* Define the union u_g0_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef11; -+ -+/* Define the union u_g0_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef12; -+ -+/* Define the union u_g0_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef20; -+ -+/* Define the union u_g0_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef21; -+ -+/* Define the union u_g0_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_coef22; -+ -+/* Define the union u_g0_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_scale; -+ -+/* Define the union u_g0_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_idc0; -+ -+/* Define the union u_g0_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_idc1; -+ -+/* Define the union u_g0_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_idc2; -+ -+/* Define the union u_g0_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_odc0; -+ -+/* Define the union u_g0_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_odc1; -+ -+/* Define the union u_g0_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_odc2; -+ -+/* Define the union u_g0_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_min_y; -+ -+/* Define the union u_g0_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_min_c; -+ -+/* Define the union u_g0_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_max_y; -+ -+/* Define the union u_g0_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_max_c; -+ -+/* Define the union u_g0_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef00; -+ -+/* Define the union u_g0_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef01; -+ -+/* Define the union u_g0_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef02; -+ -+/* Define the union u_g0_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef10; -+ -+/* Define the union u_g0_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef11; -+ -+/* Define the union u_g0_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef12; -+ -+/* Define the union u_g0_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef20; -+ -+/* Define the union u_g0_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef21; -+ -+/* Define the union u_g0_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_coef22; -+ -+/* Define the union u_g0_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_scale; -+ -+/* Define the union u_g0_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_idc0; -+ -+/* Define the union u_g0_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_idc1; -+ -+/* Define the union u_g0_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_idc2; -+ -+/* Define the union u_g0_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_odc0; -+ -+/* Define the union u_g0_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_odc1; -+ -+/* Define the union u_g0_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_odc2; -+ -+/* Define the union u_g0_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_min_y; -+ -+/* Define the union u_g0_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_min_c; -+ -+/* Define the union u_g0_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_max_y; -+ -+/* Define the union u_g0_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc2_max_c; -+ -+/* Define the union u_g0_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_g0_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_ot_pp_csc_ink_pos; -+ -+/* Define the union u_g0_dof_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int dof_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_dof_ctrl; -+ -+/* Define the union u_g0_dof_step */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int left_step : 8; /* [7..0] */ -+ unsigned int right_step : 8; /* [15..8] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_dof_step; -+ -+/* Define the union u_g0_dof_bkg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dof_bk_cr : 10; /* [9..0] */ -+ unsigned int dof_bk_cb : 10; /* [19..10] */ -+ unsigned int dof_bk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_dof_bkg; -+ -+/* Define the union u_g0_dof_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dof_bk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_dof_alpha; -+ -+/* Define the union u_g0_zme_hinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_hinfo; -+ -+/* Define the union u_g0_zme_hsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int ahfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int chfir_mid_en : 1; /* [28] */ -+ unsigned int lhfir_mid_en : 1; /* [29] */ -+ unsigned int ahfir_mid_en : 1; /* [30] */ -+ unsigned int hfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_hsp; -+ -+/* Define the union u_g0_zme_hloffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_hloffset; -+ -+/* Define the union u_g0_zme_hcoffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_hcoffset; -+ -+/* Define the union u_g0_zme_coef_ren */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int apb_g0_vf_lren : 1; /* [1] */ -+ unsigned int reserved_1 : 1; /* [2] */ -+ unsigned int apb_g0_hf_lren : 1; /* [3] */ -+ unsigned int reserved_2 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_coef_ren; -+ -+/* Define the union u_g0_zme_coef_rdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_coef_rdata; -+ -+/* Define the union u_g0_zme_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int reserved_0 : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_vinfo; -+ -+/* Define the union u_g0_zme_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 9; /* [24..16] */ -+ unsigned int vafir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int reserved_1 : 1; /* [27] */ -+ unsigned int cvfir_mid_en : 1; /* [28] */ -+ unsigned int lvfir_mid_en : 1; /* [29] */ -+ unsigned int avfir_mid_en : 1; /* [30] */ -+ unsigned int vfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_vsp; -+ -+/* Define the union u_g0_zme_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbtm_offset : 16; /* [15..0] */ -+ unsigned int vtp_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g0_zme_voffset; -+ -+/* Define the union u_g1_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ctrl; -+ -+/* Define the union u_g1_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_upd; -+ -+/* Define the union u_g1_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_0reso_read; -+ -+/* Define the union u_g1_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ireso; -+ -+/* Define the union u_g1_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_dfpos; -+ -+/* Define the union u_g1_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_dlpos; -+ -+/* Define the union u_g1_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_vfpos; -+ -+/* Define the union u_g1_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_vlpos; -+ -+/* Define the union u_g1_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_bk; -+ -+/* Define the union u_g1_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_alpha; -+ -+/* Define the union u_g1_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_mute_bk; -+ -+/* Define the union u_g1_lbox_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_lbox_ctrl; -+ -+/* Define the union u_g1_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_ctrl; -+ -+/* Define the union u_g1_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef00; -+ -+/* Define the union u_g1_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef01; -+ -+/* Define the union u_g1_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef02; -+ -+/* Define the union u_g1_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef10; -+ -+/* Define the union u_g1_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef11; -+ -+/* Define the union u_g1_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef12; -+ -+/* Define the union u_g1_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef20; -+ -+/* Define the union u_g1_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef21; -+ -+/* Define the union u_g1_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_coef22; -+ -+/* Define the union u_g1_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_scale; -+ -+/* Define the union u_g1_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_idc0; -+ -+/* Define the union u_g1_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_idc1; -+ -+/* Define the union u_g1_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_idc2; -+ -+/* Define the union u_g1_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_odc0; -+ -+/* Define the union u_g1_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_odc1; -+ -+/* Define the union u_g1_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_odc2; -+ -+/* Define the union u_g1_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_min_y; -+ -+/* Define the union u_g1_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_min_c; -+ -+/* Define the union u_g1_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_max_y; -+ -+/* Define the union u_g1_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_max_c; -+ -+/* Define the union u_g1_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef00; -+ -+/* Define the union u_g1_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef01; -+ -+/* Define the union u_g1_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef02; -+ -+/* Define the union u_g1_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef10; -+ -+/* Define the union u_g1_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef11; -+ -+/* Define the union u_g1_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef12; -+ -+/* Define the union u_g1_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef20; -+ -+/* Define the union u_g1_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef21; -+ -+/* Define the union u_g1_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_coef22; -+ -+/* Define the union u_g1_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_scale; -+ -+/* Define the union u_g1_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_idc0; -+ -+/* Define the union u_g1_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_idc1; -+ -+/* Define the union u_g1_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_idc2; -+ -+/* Define the union u_g1_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_odc0; -+ -+/* Define the union u_g1_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_odc1; -+ -+/* Define the union u_g1_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_odc2; -+ -+/* Define the union u_g1_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_min_y; -+ -+/* Define the union u_g1_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_min_c; -+ -+/* Define the union u_g1_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_max_y; -+ -+/* Define the union u_g1_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc2_max_c; -+ -+/* Define the union u_g1_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_g1_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_ot_pp_csc_ink_pos; -+ -+/* Define the union u_g1_zme_hinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_hinfo; -+ -+/* Define the union u_g1_zme_hsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int ahfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int chfir_mid_en : 1; /* [28] */ -+ unsigned int lhfir_mid_en : 1; /* [29] */ -+ unsigned int ahfir_mid_en : 1; /* [30] */ -+ unsigned int hfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_hsp; -+ -+/* Define the union u_g1_zme_hloffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_hloffset; -+ -+/* Define the union u_g1_zme_hcoffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_hcoffset; -+ -+/* Define the union u_g1_zme_coef_ren */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int apb_g1_vf_lren : 1; /* [1] */ -+ unsigned int reserved_1 : 1; /* [2] */ -+ unsigned int apb_g1_hf_lren : 1; /* [3] */ -+ unsigned int reserved_2 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_coef_ren; -+ -+/* Define the union u_g1_zme_coef_rdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_coef_rdata; -+ -+/* Define the union u_g1_zme_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int reserved_0 : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_vinfo; -+ -+/* Define the union u_g1_zme_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 9; /* [24..16] */ -+ unsigned int vafir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int reserved_1 : 1; /* [27] */ -+ unsigned int cvfir_mid_en : 1; /* [28] */ -+ unsigned int lvfir_mid_en : 1; /* [29] */ -+ unsigned int avfir_mid_en : 1; /* [30] */ -+ unsigned int vfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_vsp; -+ -+/* Define the union u_g1_zme_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbtm_offset : 16; /* [15..0] */ -+ unsigned int vtp_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_zme_voffset; -+ -+/* Define the union u_g2_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ctrl; -+ -+/* Define the union u_g2_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_upd; -+ -+/* Define the union u_g2_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_0reso_read; -+ -+/* Define the union u_g2_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ireso; -+ -+/* Define the union u_g2_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_dfpos; -+ -+/* Define the union u_g2_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_dlpos; -+ -+/* Define the union u_g2_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_vfpos; -+ -+/* Define the union u_g2_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_vlpos; -+ -+/* Define the union u_g2_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_bk; -+ -+/* Define the union u_g2_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_alpha; -+ -+/* Define the union u_g2_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_mute_bk; -+ -+/* Define the union u_g2_lbox_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_lbox_ctrl; -+ -+/* Define the union u_g2_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_ctrl; -+ -+/* Define the union u_g2_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef00; -+ -+/* Define the union u_g2_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef01; -+ -+/* Define the union u_g2_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef02; -+ -+/* Define the union u_g2_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef10; -+ -+/* Define the union u_g2_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef11; -+ -+/* Define the union u_g2_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef12; -+ -+/* Define the union u_g2_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef20; -+ -+/* Define the union u_g2_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef21; -+ -+/* Define the union u_g2_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_coef22; -+ -+/* Define the union u_g2_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_scale; -+ -+/* Define the union u_g2_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_idc0; -+ -+/* Define the union u_g2_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_idc1; -+ -+/* Define the union u_g2_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_idc2; -+ -+/* Define the union u_g2_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_odc0; -+ -+/* Define the union u_g2_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_odc1; -+ -+/* Define the union u_g2_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_odc2; -+ -+/* Define the union u_g2_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_min_y; -+ -+/* Define the union u_g2_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_min_c; -+ -+/* Define the union u_g2_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_max_y; -+ -+/* Define the union u_g2_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_max_c; -+ -+/* Define the union u_g2_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef00; -+ -+/* Define the union u_g2_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef01; -+ -+/* Define the union u_g2_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef02; -+ -+/* Define the union u_g2_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef10; -+ -+/* Define the union u_g2_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef11; -+ -+/* Define the union u_g2_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef12; -+ -+/* Define the union u_g2_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef20; -+ -+/* Define the union u_g2_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef21; -+ -+/* Define the union u_g2_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_coef22; -+ -+/* Define the union u_g2_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_scale; -+ -+/* Define the union u_g2_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_idc0; -+ -+/* Define the union u_g2_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_idc1; -+ -+/* Define the union u_g2_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_idc2; -+ -+/* Define the union u_g2_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_odc0; -+ -+/* Define the union u_g2_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_odc1; -+ -+/* Define the union u_g2_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_odc2; -+ -+/* Define the union u_g2_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_min_y; -+ -+/* Define the union u_g2_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_min_c; -+ -+/* Define the union u_g2_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_max_y; -+ -+/* Define the union u_g2_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc2_max_c; -+ -+/* Define the union u_g2_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_g2_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g2_ot_pp_csc_ink_pos; -+ -+/* Define the union u_g3_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ctrl; -+ -+/* Define the union u_g3_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_upd; -+ -+/* Define the union u_g3_0reso_read */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_0reso_read; -+ -+/* Define the union u_g3_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ireso; -+ -+/* Define the union u_g3_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_dfpos; -+ -+/* Define the union u_g3_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_dlpos; -+ -+/* Define the union u_g3_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_vfpos; -+ -+/* Define the union u_g3_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_vlpos; -+ -+/* Define the union u_g3_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_bk; -+ -+/* Define the union u_g3_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_alpha; -+ -+/* Define the union u_g3_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_mute_bk; -+ -+/* Define the union u_g3_lbox_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_lbox_ctrl; -+ -+/* Define the union u_g3_ot_pp_csc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_ctrl; -+ -+/* Define the union u_g3_ot_pp_csc_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef00; -+ -+/* Define the union u_g3_ot_pp_csc_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef01; -+ -+/* Define the union u_g3_ot_pp_csc_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef02; -+ -+/* Define the union u_g3_ot_pp_csc_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef10; -+ -+/* Define the union u_g3_ot_pp_csc_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef11; -+ -+/* Define the union u_g3_ot_pp_csc_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef12; -+ -+/* Define the union u_g3_ot_pp_csc_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef20; -+ -+/* Define the union u_g3_ot_pp_csc_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef21; -+ -+/* Define the union u_g3_ot_pp_csc_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_coef22; -+ -+/* Define the union u_g3_ot_pp_csc_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_scale; -+ -+/* Define the union u_g3_ot_pp_csc_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_idc0; -+ -+/* Define the union u_g3_ot_pp_csc_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_idc1; -+ -+/* Define the union u_g3_ot_pp_csc_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_idc2; -+ -+/* Define the union u_g3_ot_pp_csc_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_odc0; -+ -+/* Define the union u_g3_ot_pp_csc_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_odc1; -+ -+/* Define the union u_g3_ot_pp_csc_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_odc2; -+ -+/* Define the union u_g3_ot_pp_csc_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_min_y; -+ -+/* Define the union u_g3_ot_pp_csc_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_min_c; -+ -+/* Define the union u_g3_ot_pp_csc_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_max_y; -+ -+/* Define the union u_g3_ot_pp_csc_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_max_c; -+ -+/* Define the union u_g3_ot_pp_csc2_coef00 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef00; -+ -+/* Define the union u_g3_ot_pp_csc2_coef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef01; -+ -+/* Define the union u_g3_ot_pp_csc2_coef02 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef02; -+ -+/* Define the union u_g3_ot_pp_csc2_coef10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef10; -+ -+/* Define the union u_g3_ot_pp_csc2_coef11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef11; -+ -+/* Define the union u_g3_ot_pp_csc2_coef12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef12; -+ -+/* Define the union u_g3_ot_pp_csc2_coef20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef20; -+ -+/* Define the union u_g3_ot_pp_csc2_coef21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef21; -+ -+/* Define the union u_g3_ot_pp_csc2_coef22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_coef22; -+ -+/* Define the union u_g3_ot_pp_csc2_scale */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_scale; -+ -+/* Define the union u_g3_ot_pp_csc2_idc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_idc0; -+ -+/* Define the union u_g3_ot_pp_csc2_idc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_idc1; -+ -+/* Define the union u_g3_ot_pp_csc2_idc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_idc2; -+ -+/* Define the union u_g3_ot_pp_csc2_odc0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_odc0; -+ -+/* Define the union u_g3_ot_pp_csc2_odc1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_odc1; -+ -+/* Define the union u_g3_ot_pp_csc2_odc2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_odc2; -+ -+/* Define the union u_g3_ot_pp_csc2_min_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_min_y; -+ -+/* Define the union u_g3_ot_pp_csc2_min_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_min_c; -+ -+/* Define the union u_g3_ot_pp_csc2_max_y */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_max_y; -+ -+/* Define the union u_g3_ot_pp_csc2_max_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc2_max_c; -+ -+/* Define the union u_g3_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_ink_ctrl; -+ -+/* Define the union u_g3_ot_pp_csc_ink_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_ot_pp_csc_ink_pos; -+ -+/* define the union reg_osb_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_v : 10; /* [9..0] */ -+ unsigned int osb_bk_u : 10; /* [19..10] */ -+ unsigned int osb_bk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int osb_mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_osb_mute_bk; -+ -+/* define the union reg_osb_bk_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_osb_bk_alpha; -+ -+/* define the union reg_osb_coef_rd_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_osb_coef_rd_en; -+ -+/* Define the union u_gp0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_upd; -+ -+/* Define the union u_gp0_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_ireso; -+ -+/* Define the union u_gp0_lbox_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_lbox_ctrl; -+ -+/* Define the union u_gp0_galpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_galpha; -+ -+/* Define the union u_gp0_dfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 12; /* [11..0] */ -+ unsigned int disp_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_dfpos; -+ -+/* Define the union u_gp0_dlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 12; /* [11..0] */ -+ unsigned int disp_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_dlpos; -+ -+/* Define the union u_gp0_vfpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 12; /* [11..0] */ -+ unsigned int video_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_vfpos; -+ -+/* Define the union u_gp0_vlpos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 12; /* [11..0] */ -+ unsigned int video_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_vlpos; -+ -+/* Define the union u_gp0_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_bk; -+ -+/* Define the union u_gp0_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_alpha; -+ -+/* Define the union u_gp0_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_mute_bk; -+ -+/* Define the union u_gp0_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_idc; -+ -+/* Define the union u_gp0_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_odc; -+ -+/* Define the union u_gp0_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_iodc; -+ -+/* Define the union u_gp0_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_p0; -+ -+/* Define the union u_gp0_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_p1; -+ -+/* Define the union u_gp0_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_p2; -+ -+/* Define the union u_gp0_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_p3; -+ -+/* Define the union u_gp0_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gp0_csc_p4; -+ -+/* Define the union u_wbc_g0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int auto_stop_en : 1; /* [10] */ -+ unsigned int reserved_0 : 15; /* [25..11] */ -+ unsigned int format_out : 2; /* [27..26] */ -+ unsigned int reserved_1 : 3; /* [30..28] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_ctrl; -+ -+/* Define the union u_wbc_g0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_upd; -+ -+/* Define the union u_wbc_g0_cmp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cmp_lossy_en : 1; /* [0] */ -+ unsigned int reserved_0 : 3; /* [3..1] */ -+ unsigned int cmp_drr : 4; /* [7..4] */ -+ unsigned int reserved_1 : 23; /* [30..8] */ -+ unsigned int cmp_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_cmp; -+ -+/* Define the union u_wbc_g0_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbcstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_stride; -+ -+/* Define the union u_wbc_g0_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_oreso; -+ -+/* Define the union u_wbc_g0_fcrop */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wfcrop : 12; /* [11..0] */ -+ unsigned int hfcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_fcrop; -+ -+/* Define the union u_wbc_g0_lcrop */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wlcrop : 12; /* [11..0] */ -+ unsigned int hlcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_g0_lcrop; -+ -+/* Define the union u_wbc_gp0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int auto_stop_en : 1; /* [10] */ -+ unsigned int reserved_0 : 1; /* [11] */ -+ unsigned int wbc_vtthd_mode : 1; /* [12] */ -+ unsigned int reserved_1 : 5; /* [17..13] */ -+ unsigned int three_d_mode : 2; /* [19..18] */ -+ unsigned int reserved_2 : 3; /* [22..20] */ -+ unsigned int flip_en : 1; /* [23] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int mode_out : 2; /* [29..28] */ -+ unsigned int reserved_3 : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_ctrl; -+ -+/* Define the union u_wbc_gp0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_upd; -+ -+/* Define the union u_wbc_gp0_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbclstride : 16; /* [15..0] */ -+ unsigned int wbccstride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_stride; -+ -+/* Define the union u_wbc_gp0_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_oreso; -+ -+/* Define the union u_wbc_gp0_fcrop */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wfcrop : 12; /* [11..0] */ -+ unsigned int hfcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_fcrop; -+ -+/* Define the union u_wbc_gp0_lcrop */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wlcrop : 12; /* [11..0] */ -+ unsigned int hlcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_lcrop; -+ -+/* Define the union u_wbc_gp0_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int dither_round : 1; /* [29] */ -+ unsigned int dither_mode : 1; /* [30] */ -+ unsigned int dither_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_dither_ctrl; -+ -+/* Define the union u_wbc_gp0_dither_coef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_coef0 : 8; /* [7..0] */ -+ unsigned int dither_coef1 : 8; /* [15..8] */ -+ unsigned int dither_coef2 : 8; /* [23..16] */ -+ unsigned int dither_coef3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_dither_coef0; -+ -+/* Define the union u_wbc_gp0_dither_coef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_coef4 : 8; /* [7..0] */ -+ unsigned int dither_coef5 : 8; /* [15..8] */ -+ unsigned int dither_coef6 : 8; /* [23..16] */ -+ unsigned int dither_coef7 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_dither_coef1; -+ -+/* Define the union u_wbc_gp0_hpzme */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int hpzme_mode : 1; /* [29] */ -+ unsigned int hpzme_mid_en : 1; /* [30] */ -+ unsigned int hpzme_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_gp0_hpzme; -+ -+/* Define the union u_wbc_me_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 10; /* [19..10] */ -+ unsigned int ofl_master : 1; /* [20] */ -+ unsigned int reserved_1 : 2; /* [22..21] */ -+ unsigned int mad_data_mode : 1; /* [23] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int reserved_2 : 1; /* [28] */ -+ unsigned int c_wbc_en : 1; /* [29] */ -+ unsigned int reserved_3 : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_ctrl; -+ -+/* Define the union u_wbc_me_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_upd; -+ -+/* Define the union u_wbc_me_wlen_sel */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wlen_sel : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_wlen_sel; -+ -+/* Define the union u_wbc_me_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbclstride : 16; /* [15..0] */ -+ unsigned int wbccstride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_stride; -+ -+/* Define the union u_wbc_me_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_oreso; -+ -+/* Define the union u_wbc_me_smmu_bypass */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int l_bypass : 1; /* [0] */ -+ unsigned int c_bypass : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_smmu_bypass; -+ -+/* Define the union u_wbc_me_paraup */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_hlcoef_upd : 1; /* [0] */ -+ unsigned int wbc_hccoef_upd : 1; /* [1] */ -+ unsigned int wbc_vlcoef_upd : 1; /* [2] */ -+ unsigned int wbc_vccoef_upd : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_paraup; -+ -+/* Define the union u_wbc_me_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int dither_round : 1; /* [29] */ -+ unsigned int dither_mode : 1; /* [30] */ -+ unsigned int dither_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_dither_ctrl; -+ -+/* Define the union u_wbc_me_dither_coef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_coef0 : 8; /* [7..0] */ -+ unsigned int dither_coef1 : 8; /* [15..8] */ -+ unsigned int dither_coef2 : 8; /* [23..16] */ -+ unsigned int dither_coef3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_dither_coef0; -+ -+/* Define the union u_wbc_me_dither_coef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_coef4 : 8; /* [7..0] */ -+ unsigned int dither_coef5 : 8; /* [15..8] */ -+ unsigned int dither_coef6 : 8; /* [23..16] */ -+ unsigned int dither_coef7 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_dither_coef1; -+ -+/* Define the union u_wbc_me_zme_hsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int hchfir_en : 1; /* [25] */ -+ unsigned int hlfir_en : 1; /* [26] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int hchmid_en : 1; /* [28] */ -+ unsigned int hlmid_en : 1; /* [29] */ -+ unsigned int hchmsc_en : 1; /* [30] */ -+ unsigned int hlmsc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_hsp; -+ -+/* Define the union u_wbc_me_zme_hloffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hor_loffset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_hloffset; -+ -+/* Define the union u_wbc_me_zme_hcoffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hor_coffset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_hcoffset; -+ -+/* Define the union u_wbc_me_zme_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 19; /* [18..0] */ -+ unsigned int zme_in_fmt : 2; /* [20..19] */ -+ unsigned int zme_out_fmt : 2; /* [22..21] */ -+ unsigned int vchfir_en : 1; /* [23] */ -+ unsigned int vlfir_en : 1; /* [24] */ -+ unsigned int reserved_1 : 3; /* [27..25] */ -+ unsigned int vchmid_en : 1; /* [28] */ -+ unsigned int vlmid_en : 1; /* [29] */ -+ unsigned int vchmsc_en : 1; /* [30] */ -+ unsigned int vlmsc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_vsp; -+ -+/* Define the union u_wbc_me_zme_vsr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_vsr; -+ -+/* Define the union u_wbc_me_zme_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int vluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_voffset; -+ -+/* Define the union u_wbc_me_zme_vboffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int vbluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_me_zme_vboffset; -+ -+/* Define the union u_wbc_fi_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 3; /* [12..10] */ -+ unsigned int addr_mode : 1; /* [13] */ -+ unsigned int fsize_mode : 1; /* [14] */ -+ unsigned int tnr_nrds_en : 1; /* [15] */ -+ unsigned int reserved_1 : 4; /* [19..16] */ -+ unsigned int ofl_master : 1; /* [20] */ -+ unsigned int data_width : 1; /* [21] */ -+ unsigned int reserved_2 : 2; /* [23..22] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int reserved_3 : 2; /* [29..28] */ -+ unsigned int cmp_en : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_ctrl; -+ -+/* Define the union u_wbc_fi_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_upd; -+ -+/* Define the union u_wbc_fi_wlen_sel */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wlen_sel : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_wlen_sel; -+ -+/* Define the union u_wbc_fi_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbclstride : 16; /* [15..0] */ -+ unsigned int wbccstride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_stride; -+ -+/* Define the union u_wbc_fi_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_oreso; -+ -+/* Define the union u_wbc_fi_smmu_bypass */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int l_bypass : 1; /* [0] */ -+ unsigned int c_bypass : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_smmu_bypass; -+ -+/* Define the union u_wbc_fi_frame_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_size : 23; /* [22..0] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_frame_size; -+ -+/* Define the union u_wbc_fi_hcds */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int hchfir_en : 1; /* [29] */ -+ unsigned int hchmid_en : 1; /* [30] */ -+ unsigned int hcds_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_hcds; -+ -+/* Define the union u_wbc_fi_hcds_coef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int coef1 : 10; /* [19..10] */ -+ unsigned int coef2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_hcds_coef0; -+ -+/* Define the union u_wbc_fi_hcds_coef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef3 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_hcds_coef1; -+ -+/* Define the union u_wbc_fi_cmp_mb */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mb_bits : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_mb; -+ -+/* Define the union u_wbc_fi_cmp_max_min */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int min_bits_cnt : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int max_bits_cnt : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_max_min; -+ -+/* Define the union u_wbc_fi_cmp_adj_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int adj_sad_thr : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int adj_sad_bit_thr : 8; /* [23..16] */ -+ unsigned int adj_spec_bit_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_adj_thr; -+ -+/* Define the union u_wbc_fi_cmp_big_grad */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int big_grad_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int big_grad_num_thr : 5; /* [12..8] */ -+ unsigned int reserved_1 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_big_grad; -+ -+/* Define the union u_wbc_fi_cmp_blk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smth_thr : 6; /* [5..0] */ -+ unsigned int reserved_0 : 2; /* [7..6] */ -+ unsigned int blk_comp_thr : 3; /* [10..8] */ -+ unsigned int reserved_1 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_blk; -+ -+/* Define the union u_wbc_fi_cmp_graphic_judge */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int graphic_en : 1; /* [0] */ -+ unsigned int reserved_0 : 15; /* [15..1] */ -+ unsigned int video_sad_thr : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_graphic_judge; -+ -+/* Define the union u_wbc_fi_cmp_rc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int sadbits_ngain : 3; /* [2..0] */ -+ unsigned int reserved_0 : 5; /* [7..3] */ -+ unsigned int rc_smth_gain : 3; /* [10..8] */ -+ unsigned int reserved_1 : 5; /* [15..11] */ -+ unsigned int max_trow_bits : 6; /* [21..16] */ -+ unsigned int reserved_2 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_rc; -+ -+/* Define the union u_wbc_fi_cmp_frame_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_size : 21; /* [20..0] */ -+ unsigned int reserved_0 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_fi_cmp_frame_size; -+ -+/* Define the union u_wbc_cmp_glb_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int is_lossless : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int dw_mode : 1; /* [2] */ -+ unsigned int sep_cmp_en : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_glb_info; -+ -+/* Define the union u_wbc_cmp_framesize */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_width : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int frame_height : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_framesize; -+ -+/* Define the union u_wbc_cmp_rc_cfg0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mb_bits_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int min_mb_bits_y : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg0; -+ -+/* Define the union u_wbc_cmp_rc_cfg2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_qp_y : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int sad_bits_ngain : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int rc_smth_ngain : 3; /* [18..16] */ -+ unsigned int reserved_2 : 5; /* [23..19] */ -+ unsigned int max_trow_bits : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg2; -+ -+/* Define the union u_wbc_cmp_rc_cfg3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_sad_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int min_sad_thr : 7; /* [22..16] */ -+ unsigned int reserved_1 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg3; -+ -+/* Define the union u_wbc_cmp_rc_cfg4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smth_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int still_thr : 7; /* [14..8] */ -+ unsigned int reserved_1 : 1; /* [15] */ -+ unsigned int big_grad_thr : 10; /* [25..16] */ -+ unsigned int reserved_2 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg4; -+ -+/* Define the union u_wbc_cmp_rc_cfg5 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smth_pix_num_thr : 6; /* [5..0] */ -+ unsigned int reserved_0 : 2; /* [7..6] */ -+ unsigned int still_pix_num_thr : 6; /* [13..8] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_2 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg5; -+ -+/* Define the union u_wbc_cmp_rc_cfg6 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int noise_sad : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int pix_diff_thr : 9; /* [24..16] */ -+ unsigned int reserved_1 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg6; -+ -+/* Define the union u_wbc_cmp_rc_cfg7 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg7; -+ -+/* Define the union u_wbc_cmp_rc_cfg8 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr_y : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr_y : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr_y : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr_y : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg8; -+ -+/* Define the union u_wbc_cmp_rc_cfg10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int est_err_gain : 5; /* [4..0] */ -+ unsigned int reserved_0 : 11; /* [15..5] */ -+ unsigned int max_est_err_level : 9; /* [24..16] */ -+ unsigned int max_vbv_buf_loss_thr : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_rc_cfg10; -+ -+/* Define the union u_wbc_cmp_outsize0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_size0_reg : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_outsize0; -+ -+/* Define the union u_wbc_cmp_max_row */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_size1_reg : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_max_row; -+ -+/* Define the union u_wbc_bmp_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 10; /* [19..10] */ -+ unsigned int ofl_master : 1; /* [20] */ -+ unsigned int data_width : 1; /* [21] */ -+ unsigned int reserved_1 : 2; /* [23..22] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int reserved_2 : 3; /* [30..28] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_bmp_ctrl; -+ -+/* Define the union u_wbc_bmp_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_bmp_upd; -+ -+/* Define the union u_wbc_bmp_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_bmp_oreso; -+ -+/* Define the union u_wbc_bmp_sum */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bmp_sum : 25; /* [24..0] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_bmp_sum; -+ -+/* Define the union u_wbc_dhd0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int p2i_en : 1; /* [0] */ -+ unsigned int root_path : 2; /* [2..1] */ -+ unsigned int reserved_0 : 19; /* [21..3] */ -+ unsigned int mode_out : 2; /* [23..22] */ -+ unsigned int three_d_mode : 2; /* [25..24] */ -+ unsigned int auto_stop_en : 1; /* [26] */ -+ unsigned int wbc_vtthd_mode : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_dhd0_ctrl; -+ -+/* Define the union u_wbc_dhd0_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_dhd0_upd; -+ -+/* Define the union u_wbc_dhd0_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_dhd0_oreso; -+ -+/* Define the union u_wd_hpzme_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_en : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hpzme_ctrl; -+ -+/* Define the union u_wd_hpzmecoef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hpzmecoef01; -+ -+/* Define the union u_wd_hpzmecoef23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hpzmecoef23; -+ -+/* Define the union u_wd_hpzmecoef45 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hpzmecoef45; -+ -+/* Define the union u_wd_hpzmecoef67 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hpzmecoef67; -+ -+/* Define the union u_wd_hcds_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_en : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hcds_ctrl; -+ -+/* Define the union u_wd_hcdscoef01 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hcdscoef01; -+ -+/* Define the union u_wd_hcdscoef23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hcdscoef23; -+ -+/* Define the union u_wd_hcdscoef45 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hcdscoef45; -+ -+/* Define the union u_wd_hcdscoef67 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_hcdscoef67; -+ -+/* Define the union u_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_ctrl; -+ -+/* Define the union u_dither_sed_y0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_y0; -+ -+/* Define the union u_dither_sed_u0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_u0; -+ -+/* Define the union u_dither_sed_v0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_v0; -+ -+/* Define the union u_dither_sed_w0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_w0; -+ -+/* Define the union u_dither_sed_y1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_y1; -+ -+/* Define the union u_dither_sed_u1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_u1; -+ -+/* Define the union u_dither_sed_v1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_v1; -+ -+/* Define the union u_dither_sed_w1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_w1; -+ -+/* Define the union u_dither_sed_y2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_y2; -+ -+/* Define the union u_dither_sed_u2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_u2; -+ -+/* Define the union u_dither_sed_v2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_v2; -+ -+/* Define the union u_dither_sed_w2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_w2; -+ -+/* Define the union u_dither_sed_y3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_y3; -+ -+/* Define the union u_dither_sed_u3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_u3; -+ -+/* Define the union u_dither_sed_v3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_v3; -+ -+/* Define the union u_dither_sed_w3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_sed_w3; -+ -+/* Define the union u_dither_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dither_thr; -+ -+/* Define the union u_wd_zme_hinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int hzme_ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hinfo; -+ -+/* Define the union u_wd_zme_hsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int chfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int non_lnr_en : 1; /* [27] */ -+ unsigned int chmid_en : 1; /* [28] */ -+ unsigned int lhmid_en : 1; /* [29] */ -+ unsigned int chfir_en : 1; /* [30] */ -+ unsigned int lhfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hsp; -+ -+/* Define the union u_wd_zme_hloffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hloffset; -+ -+/* Define the union u_wd_zme_hcoffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hcoffset; -+ -+/* Define the union u_wd_zme_hcoef_ren */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_hf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hcoef_ren; -+ -+/* Define the union u_wd_zme_hcoef_rdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hcoef_rdata; -+ -+/* Define the union u_wd_zme_hdraw */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hdraw_mode : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hdraw; -+ -+/* Define the union u_wd_zme_hratio */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hratio : 27; /* [26..0] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_hratio; -+ -+/* Define the union u_wd_zme_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vinfo; -+ -+/* Define the union u_wd_zme_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 16; /* [15..0] */ -+ unsigned int graphdet_en : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int vfir_1tap_en : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int lvmid_en : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int lvfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vsp; -+ -+/* Define the union u_wd_zme_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int vluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_voffset; -+ -+/* Define the union u_wd_zme_vboffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int vbluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vboffset; -+ -+/* Define the union u_wd_zme_vcoef_ren */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_vf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vcoef_ren; -+ -+/* Define the union u_wd_zme_vcoef_rdata */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vcoef_rdata; -+ -+/* Define the union u_wd_zme_vdraw */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vdraw_mode : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vdraw; -+ -+/* Define the union u_wd_zme_vratio */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 19; /* [18..0] */ -+ unsigned int reserved_0 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wd_zme_vratio; -+ -+/* Define the union u_dhd0_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int disp_mode : 3; /* [3..1] */ -+ unsigned int iop : 1; /* [4] */ -+ unsigned int intf_ivs : 1; /* [5] */ -+ unsigned int intf_ihs : 1; /* [6] */ -+ unsigned int intf_idv : 1; /* [7] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int hdmi420c_sel : 1; /* [9] */ -+ unsigned int hdmi420_en : 1; /* [10] */ -+ unsigned int uf_offline_en : 1; /* [11] */ -+ unsigned int reserved_1 : 2; /* [13..12] */ -+ unsigned int hdmi_mode : 1; /* [14] */ -+ unsigned int twochn_debug : 1; /* [15] */ -+ unsigned int twochn_en : 1; /* [16] */ -+ unsigned int reserved_2 : 1; /* [17] */ -+ unsigned int cbar_mode : 1; /* [18] */ -+ unsigned int sin_en : 1; /* [19] */ -+ unsigned int fpga_lmt_width : 7; /* [26..20] */ -+ unsigned int fpga_lmt_en : 1; /* [27] */ -+ unsigned int p2i_en : 1; /* [28] */ -+ unsigned int cbar_sel : 1; /* [29] */ -+ unsigned int cbar_en : 1; /* [30] */ -+ unsigned int intf_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ctrl; -+ -+/* Define the union u_dhd0_vsync1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vact : 16; /* [15..0] */ -+ unsigned int vbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vsync1; -+ -+/* Define the union u_dhd0_vsync2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vsync2; -+ -+/* Define the union u_dhd0_hsync1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hact : 16; /* [15..0] */ -+ unsigned int hbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_hsync1; -+ -+/* Define the union u_dhd0_hsync2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfb : 16; /* [15..0] */ -+ unsigned int hmid : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_hsync2; -+ -+/* Define the union u_dhd0_vplus1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bvact : 16; /* [15..0] */ -+ unsigned int bvbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vplus1; -+ -+/* Define the union u_dhd0_vplus2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bvfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vplus2; -+ -+/* Define the union u_dhd0_pwr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hpw : 16; /* [15..0] */ -+ unsigned int vpw : 8; /* [23..16] */ -+ unsigned int reserved_0 : 3; /* [26..24] */ -+ unsigned int multichn_en : 2; /* [28..27] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_pwr; -+ -+/* Define the union u_dhd0_vtthd3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vtmgthd3 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd3_mode : 1; /* [15] */ -+ unsigned int vtmgthd4 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd4_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vtthd3; -+ -+/* Define the union u_dhd0_vtthd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vtmgthd1 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd1_mode : 1; /* [15] */ -+ unsigned int vtmgthd2 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd2_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vtthd; -+ -+/* Define the union u_dhd0_parathd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int dfs_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_parathd; -+ -+/* Define the union u_dhd0_precharge_thd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tcon_precharge_thd : 17; /* [16..0] */ -+ unsigned int reserved_0 : 3; /* [19..17] */ -+ unsigned int vsync_te_mode : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_precharge_thd; -+ -+/* Define the union u_dhd0_start_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int start_pos : 8; /* [7..0] */ -+ unsigned int timing_start_pos : 8; /* [15..8] */ -+ unsigned int fi_start_pos : 4; /* [19..16] */ -+ unsigned int req_start_pos : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_start_pos; -+ -+/* Define the union u_dhd0_start_pos1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_start_pos1 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_start_pos1; -+ -+/* Define the union u_dhd0_paraup */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int paraup_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_paraup; -+ -+/* Define the union u_dhd0_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lcd_dv_inv : 1; /* [0] */ -+ unsigned int lcd_hs_inv : 1; /* [1] */ -+ unsigned int lcd_vs_inv : 1; /* [2] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int vga_dv_inv : 1; /* [4] */ -+ unsigned int vga_hs_inv : 1; /* [5] */ -+ unsigned int vga_vs_inv : 1; /* [6] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int hdmi_dv_inv : 1; /* [8] */ -+ unsigned int hdmi_hs_inv : 1; /* [9] */ -+ unsigned int hdmi_vs_inv : 1; /* [10] */ -+ unsigned int hdmi_f_inv : 1; /* [11] */ -+ unsigned int date_dv_inv : 1; /* [12] */ -+ unsigned int date_hs_inv : 1; /* [13] */ -+ unsigned int date_vs_inv : 1; /* [14] */ -+ unsigned int date_f_inv : 1; /* [15] */ -+ unsigned int reserved_2 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_sync_inv; -+ -+/* Define the union u_dhd0_clk_dv_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int intf_clk_mux : 1; /* [0] */ -+ unsigned int intf_dv_mux : 1; /* [1] */ -+ unsigned int no_active_area_pos : 16; /* [17..2] */ -+ unsigned int reserved_0 : 14; /* [31..18] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_clk_dv_ctrl; -+ -+/* Define the union u_dhd0_rgb_fix_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fix_b : 10; /* [9..0] */ -+ unsigned int fix_g : 10; /* [19..10] */ -+ unsigned int fix_r : 10; /* [29..20] */ -+ unsigned int rgb_fix_mux : 1; /* [30] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_rgb_fix_ctrl; -+ -+/* Define the union u_dhd0_lockcfg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int measure_en : 1; /* [0] */ -+ unsigned int lock_cnt_en : 1; /* [1] */ -+ unsigned int vdp_measure_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_lockcfg; -+ -+/* Define the union u_dhd0_intf_chksum_high1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int r0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_intf_chksum_high1; -+ -+/* Define the union u_dhd0_intf_chksum_high2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int r1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_intf_chksum_high2; -+ -+/* Define the union u_dhd0_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vback_blank : 1; /* [0] */ -+ unsigned int vblank : 1; /* [1] */ -+ unsigned int bottom_field : 1; /* [2] */ -+ unsigned int vcnt : 13; /* [15..3] */ -+ unsigned int count_int : 8; /* [23..16] */ -+ unsigned int dhd_even : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_state; -+ -+/* Define the union u_dhd0_uf_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ud_first_cnt : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int start_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_uf_state; -+ -+/* Define the union u_vo_mux */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mipi_sel : 4; /* [3..0] */ -+ unsigned int lcd_sel : 4; /* [7..4] */ -+ unsigned int bt_sel : 4; /* [11..8] */ -+ unsigned int sddate_sel : 4; /* [15..12] */ -+ unsigned int hdmi_sel : 4; /* [19..16] */ -+ unsigned int hdmi1_sel : 4; /* [23..20] */ -+ unsigned int vga_sel : 4; /* [27..24] */ -+ unsigned int digital_sel : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_mux; -+ -+/* Define the union u_vo_mux_sync */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int sync_dv : 1; /* [0] */ -+ unsigned int sync_hsync : 1; /* [1] */ -+ unsigned int sync_vsync : 1; /* [2] */ -+ unsigned int sync_field : 1; /* [3] */ -+ unsigned int reserved_0 : 27; /* [30..4] */ -+ unsigned int sync_test_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_mux_sync; -+ -+/* Define the union u_vo_mux_data */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vomux_data : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vo_mux_data; -+ -+/* Define the union u_dhd0_vsync_te_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vsync_te_start_sta : 8; /* [7..0] */ -+ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ -+ unsigned int vsync_te_end_sta : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vsync_te_state; -+ -+/* Define the union u_dhd0_vsync_te_state1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vsync_te_vfb : 16; /* [15..0] */ -+ unsigned int vsync_te_width : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_vsync_te_state1; -+ -+/* Define the union u_dhd0_ccdoimgmod */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int img_mode : 7; /* [6..0] */ -+ unsigned int img_right : 1; /* [7] */ -+ unsigned int img_id : 2; /* [9..8] */ -+ unsigned int slave_mode : 1; /* [10] */ -+ unsigned int ccd_en : 1; /* [11] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int vbi_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ccdoimgmod; -+ -+/* Define the union u_dhd0_ccdoposmskh */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int p32_en : 1; /* [0] */ -+ unsigned int p33_en : 1; /* [1] */ -+ unsigned int p34_en : 1; /* [2] */ -+ unsigned int p35_en : 1; /* [3] */ -+ unsigned int p36_en : 1; /* [4] */ -+ unsigned int p37_en : 1; /* [5] */ -+ unsigned int p38_en : 1; /* [6] */ -+ unsigned int p39_en : 1; /* [7] */ -+ unsigned int p40_en : 1; /* [8] */ -+ unsigned int p41_en : 1; /* [9] */ -+ unsigned int p42_en : 1; /* [10] */ -+ unsigned int p43_en : 1; /* [11] */ -+ unsigned int p44_en : 1; /* [12] */ -+ unsigned int p45_en : 1; /* [13] */ -+ unsigned int p46_en : 1; /* [14] */ -+ unsigned int p47_en : 1; /* [15] */ -+ unsigned int p48_en : 1; /* [16] */ -+ unsigned int p49_en : 1; /* [17] */ -+ unsigned int p50_en : 1; /* [18] */ -+ unsigned int p51_en : 1; /* [19] */ -+ unsigned int p52_en : 1; /* [20] */ -+ unsigned int p53_en : 1; /* [21] */ -+ unsigned int p54_en : 1; /* [22] */ -+ unsigned int p55_en : 1; /* [23] */ -+ unsigned int p56_en : 1; /* [24] */ -+ unsigned int p57_en : 1; /* [25] */ -+ unsigned int p58_en : 1; /* [26] */ -+ unsigned int p59_en : 1; /* [27] */ -+ unsigned int p60_en : 1; /* [28] */ -+ unsigned int p61_en : 1; /* [29] */ -+ unsigned int p62_en : 1; /* [30] */ -+ unsigned int p63_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ccdoposmskh; -+ -+/* Define the union u_dhd0_ccdoposmskl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int p0_en : 1; /* [0] */ -+ unsigned int p1_en : 1; /* [1] */ -+ unsigned int p2_en : 1; /* [2] */ -+ unsigned int p3_en : 1; /* [3] */ -+ unsigned int p4_en : 1; /* [4] */ -+ unsigned int p5_en : 1; /* [5] */ -+ unsigned int p6_en : 1; /* [6] */ -+ unsigned int p7_en : 1; /* [7] */ -+ unsigned int p8_en : 1; /* [8] */ -+ unsigned int p9_en : 1; /* [9] */ -+ unsigned int p10_en : 1; /* [10] */ -+ unsigned int p11_en : 1; /* [11] */ -+ unsigned int p12_en : 1; /* [12] */ -+ unsigned int p13_en : 1; /* [13] */ -+ unsigned int p14_en : 1; /* [14] */ -+ unsigned int p15_en : 1; /* [15] */ -+ unsigned int p16_en : 1; /* [16] */ -+ unsigned int p17_en : 1; /* [17] */ -+ unsigned int p18_en : 1; /* [18] */ -+ unsigned int p19_en : 1; /* [19] */ -+ unsigned int p20_en : 1; /* [20] */ -+ unsigned int p21_en : 1; /* [21] */ -+ unsigned int p22_en : 1; /* [22] */ -+ unsigned int p23_en : 1; /* [23] */ -+ unsigned int p24_en : 1; /* [24] */ -+ unsigned int p25_en : 1; /* [25] */ -+ unsigned int p26_en : 1; /* [26] */ -+ unsigned int p27_en : 1; /* [27] */ -+ unsigned int p28_en : 1; /* [28] */ -+ unsigned int p29_en : 1; /* [29] */ -+ unsigned int p30_en : 1; /* [30] */ -+ unsigned int p31_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ccdoposmskl; -+ -+/* Define the union u_dhd0_dacdet1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vdac_det_high : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int det_line : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_dacdet1; -+ -+/* Define the union u_dhd0_dacdet2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int det_pixel_sta : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int det_pixel_wid : 11; /* [26..16] */ -+ unsigned int reserved_1 : 4; /* [30..27] */ -+ unsigned int vdac_det_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_dacdet2; -+ -+/* Define the union u_dhd0_ccd_info1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int img_mode : 7; /* [6..0] */ -+ unsigned int img_right : 1; /* [7] */ -+ unsigned int img_id : 2; /* [9..8] */ -+ unsigned int reserved_0 : 1; /* [10] */ -+ unsigned int ccd_en : 1; /* [11] */ -+ unsigned int reserved_1 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ccd_info1; -+ -+/* Define the union u_dhd0_ccd_info2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int p32_en : 1; /* [0] */ -+ unsigned int p33_en : 1; /* [1] */ -+ unsigned int p34_en : 1; /* [2] */ -+ unsigned int p35_en : 1; /* [3] */ -+ unsigned int p36_en : 1; /* [4] */ -+ unsigned int p37_en : 1; /* [5] */ -+ unsigned int p38_en : 1; /* [6] */ -+ unsigned int p39_en : 1; /* [7] */ -+ unsigned int p40_en : 1; /* [8] */ -+ unsigned int p41_en : 1; /* [9] */ -+ unsigned int p42_en : 1; /* [10] */ -+ unsigned int p43_en : 1; /* [11] */ -+ unsigned int p44_en : 1; /* [12] */ -+ unsigned int p45_en : 1; /* [13] */ -+ unsigned int p46_en : 1; /* [14] */ -+ unsigned int p47_en : 1; /* [15] */ -+ unsigned int p48_en : 1; /* [16] */ -+ unsigned int p49_en : 1; /* [17] */ -+ unsigned int p50_en : 1; /* [18] */ -+ unsigned int p51_en : 1; /* [19] */ -+ unsigned int p52_en : 1; /* [20] */ -+ unsigned int p53_en : 1; /* [21] */ -+ unsigned int p54_en : 1; /* [22] */ -+ unsigned int p55_en : 1; /* [23] */ -+ unsigned int p56_en : 1; /* [24] */ -+ unsigned int p57_en : 1; /* [25] */ -+ unsigned int p58_en : 1; /* [26] */ -+ unsigned int p59_en : 1; /* [27] */ -+ unsigned int p60_en : 1; /* [28] */ -+ unsigned int p61_en : 1; /* [29] */ -+ unsigned int p62_en : 1; /* [30] */ -+ unsigned int p63_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ccd_info2; -+ -+/* Define the union u_dhd0_ccd_info3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int p0_en : 1; /* [0] */ -+ unsigned int p1_en : 1; /* [1] */ -+ unsigned int p2_en : 1; /* [2] */ -+ unsigned int p3_en : 1; /* [3] */ -+ unsigned int p4_en : 1; /* [4] */ -+ unsigned int p5_en : 1; /* [5] */ -+ unsigned int p6_en : 1; /* [6] */ -+ unsigned int p7_en : 1; /* [7] */ -+ unsigned int p8_en : 1; /* [8] */ -+ unsigned int p9_en : 1; /* [9] */ -+ unsigned int p10_en : 1; /* [10] */ -+ unsigned int p11_en : 1; /* [11] */ -+ unsigned int p12_en : 1; /* [12] */ -+ unsigned int p13_en : 1; /* [13] */ -+ unsigned int p14_en : 1; /* [14] */ -+ unsigned int p15_en : 1; /* [15] */ -+ unsigned int p16_en : 1; /* [16] */ -+ unsigned int p17_en : 1; /* [17] */ -+ unsigned int p18_en : 1; /* [18] */ -+ unsigned int p19_en : 1; /* [19] */ -+ unsigned int p20_en : 1; /* [20] */ -+ unsigned int p21_en : 1; /* [21] */ -+ unsigned int p22_en : 1; /* [22] */ -+ unsigned int p23_en : 1; /* [23] */ -+ unsigned int p24_en : 1; /* [24] */ -+ unsigned int p25_en : 1; /* [25] */ -+ unsigned int p26_en : 1; /* [26] */ -+ unsigned int p27_en : 1; /* [27] */ -+ unsigned int p28_en : 1; /* [28] */ -+ unsigned int p29_en : 1; /* [29] */ -+ unsigned int p30_en : 1; /* [30] */ -+ unsigned int p31_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd0_ccd_info3; -+ -+/* Define the union u_intf_hdmi_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int hdmi_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_hdmi_ctrl; -+ -+/* Define the union u_intf_hdmi_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_hdmi_upd; -+ -+/* Define the union u_intf_hdmi_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_hdmi_sync_inv; -+ -+/* Define the union u_hdmi_intf_chksum_high */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int r0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_intf_chksum_high; -+ -+/* Define the union u_hdmi_intf1_chksum_high */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int r1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_intf1_chksum_high; -+ -+/* Define the union u_hdmi_hfir_coef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_hfir_coef0; -+ -+/* Define the union u_hdmi_hfir_coef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_hfir_coef1; -+ -+/* Define the union u_hdmi_hfir_coef2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_hfir_coef2; -+ -+/* Define the union u_hdmi_hfir_coef3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_hfir_coef3; -+ -+/* Define the union u_hdmi_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_idc; -+ -+/* Define the union u_hdmi_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_odc; -+ -+/* Define the union u_hdmi_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_iodc; -+ -+/* Define the union u_hdmi_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_p0; -+ -+/* Define the union u_hdmi_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_p1; -+ -+/* Define the union u_hdmi_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_p2; -+ -+/* Define the union u_hdmi_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_p3; -+ -+/* Define the union u_hdmi_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi_csc_p4; -+ -+/* Define the union u_intf_mipi_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_mipi_ctrl; -+ -+/* Define the union u_intf_mipi_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_mipi_upd; -+ -+/* Define the union u_intf_mipi_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_mipi_sync_inv; -+ -+/* Define the union u_mipi_intf_chksum_high */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int b0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int r0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mipi_intf_chksum_high; -+ -+/* Define the union u_mipi_intf1_chksum_high */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int b1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int r1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mipi_intf1_chksum_high; -+ -+/* Define the union u_mipi_hfir_coef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mipi_hfir_coef0; -+ -+/* Define the union u_mipi_hfir_coef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mipi_hfir_coef1; -+ -+/* Define the union u_mipi_hfir_coef2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mipi_hfir_coef2; -+ -+/* Define the union u_mipi_hfir_coef3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mipi_hfir_coef3; -+ -+/* Define the union u_intf_bt_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 16; /* [15..0] */ -+ unsigned int data_width : 1; /* [16] */ -+ unsigned int bit_inv : 1; /* [17] */ -+ unsigned int uv_mode : 1; /* [18] */ -+ unsigned int yc_mode : 1; /* [19] */ -+ unsigned int reserved_1 : 10; /* [29..20] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_bt_ctrl; -+ -+/* Define the union u_intf_bt_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_bt_upd; -+ -+/* Define the union u_intf_bt_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_bt_sync_inv; -+ -+/* Define the union u_bt_clip0_l */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int clip_cl0 : 10; /* [9..0] */ -+ unsigned int clip_cl1 : 10; /* [19..10] */ -+ unsigned int clip_cl2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int clip_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_clip0_l; -+ -+/* Define the union u_bt_clip0_h */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int clip_ch0 : 10; /* [9..0] */ -+ unsigned int clip_ch1 : 10; /* [19..10] */ -+ unsigned int clip_ch2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_clip0_h; -+ -+/* Define the union u_bt_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_ctrl; -+ -+/* Define the union u_bt_dither_sed_y0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_y0; -+ -+/* Define the union u_bt_dither_sed_u0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_u0; -+ -+/* Define the union u_bt_dither_sed_v0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_v0; -+ -+/* Define the union u_bt_dither_sed_w0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_w0; -+ -+/* Define the union u_bt_dither_sed_y1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_y1; -+ -+/* Define the union u_bt_dither_sed_u1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_u1; -+ -+/* Define the union u_bt_dither_sed_v1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_v1; -+ -+/* Define the union u_bt_dither_sed_w1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_w1; -+ -+/* Define the union u_bt_dither_sed_y2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_y2; -+ -+/* Define the union u_bt_dither_sed_u2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_u2; -+ -+/* Define the union u_bt_dither_sed_v2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_v2; -+ -+/* Define the union u_bt_dither_sed_w2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_w2; -+ -+/* Define the union u_bt_dither_sed_y3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_y3; -+ -+/* Define the union u_bt_dither_sed_u3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_u3; -+ -+/* Define the union u_bt_dither_sed_v3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_v3; -+ -+/* Define the union u_bt_dither_sed_w3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_sed_w3; -+ -+/* Define the union u_bt_dither_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_bt_dither_thr; -+ -+/* Define the union u_intf_lcd_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 20; /* [19..0] */ -+ unsigned int lcd_format : 4; /* [23..20] */ -+ unsigned int lcd_bit_inv : 1; /* [24] */ -+ unsigned int lcd_comp_order : 1; /* [25] */ -+ unsigned int lcd_serial_perd : 1; /* [26] */ -+ unsigned int reserved_1 : 3; /* [29..27] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_lcd_ctrl; -+ -+/* Define the union u_intf_lcd_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_lcd_upd; -+ -+/* Define the union u_intf_lcd_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_lcd_sync_inv; -+ -+/* Define the union u_lcd_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_ctrl; -+ -+/* Define the union u_lcd_dither_sed_y0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_y0; -+ -+/* Define the union u_lcd_dither_sed_u0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_u0; -+ -+/* Define the union u_lcd_dither_sed_v0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_v0; -+ -+/* Define the union u_lcd_dither_sed_w0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_w0; -+ -+/* Define the union u_lcd_dither_sed_y1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_y1; -+ -+/* Define the union u_lcd_dither_sed_u1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_u1; -+ -+/* Define the union u_lcd_dither_sed_v1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_v1; -+ -+/* Define the union u_lcd_dither_sed_w1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_w1; -+ -+/* Define the union u_lcd_dither_sed_y2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_y2; -+ -+/* Define the union u_lcd_dither_sed_u2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_u2; -+ -+/* Define the union u_lcd_dither_sed_v2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_v2; -+ -+/* Define the union u_lcd_dither_sed_w2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_w2; -+ -+/* Define the union u_lcd_dither_sed_y3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_y3; -+ -+/* Define the union u_lcd_dither_sed_u3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_u3; -+ -+/* Define the union u_lcd_dither_sed_v3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_v3; -+ -+/* Define the union u_lcd_dither_sed_w3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_sed_w3; -+ -+/* Define the union u_lcd_dither_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_lcd_dither_thr; -+ -+/* Define the union u_intf_hdmi1_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int hdmi_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_hdmi1_ctrl; -+ -+/* Define the union u_intf_hdmi1_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_hdmi1_upd; -+ -+/* Define the union u_intf_hdmi1_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_hdmi1_sync_inv; -+ -+/* Define the union u_hdmi1_intf_chksum_high */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int r0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi1_intf_chksum_high; -+ -+/* Define the union u_hdmi1_intf1_chksum_high */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int r1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi1_intf1_chksum_high; -+ -+/* Define the union u_hdmi1_hfir_coef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi1_hfir_coef0; -+ -+/* Define the union u_hdmi1_hfir_coef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi1_hfir_coef1; -+ -+/* Define the union u_hdmi1_hfir_coef2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi1_hfir_coef2; -+ -+/* Define the union u_hdmi1_hfir_coef3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_hdmi1_hfir_coef3; -+ -+/* Define the union u_intf_vga_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 24; /* [23..0] */ -+ unsigned int yc_mode : 1; /* [24] */ -+ unsigned int lcd_parallel_mode : 1; /* [25] */ -+ unsigned int lcd_data_inv : 1; /* [26] */ -+ unsigned int lcd_parallel_order : 1; /* [27] */ -+ unsigned int lcd_serial_perd : 1; /* [28] */ -+ unsigned int lcd_serial_mode : 1; /* [29] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_vga_ctrl; -+ -+/* Define the union u_intf_vga_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_vga_upd; -+ -+/* Define the union u_intf_vga_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_vga_sync_inv; -+ -+/* Define the union u_vga_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_idc; -+ -+/* Define the union u_vga_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_odc; -+ -+/* Define the union u_vga_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_iodc; -+ -+/* Define the union u_vga_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_p0; -+ -+/* Define the union u_vga_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_p1; -+ -+/* Define the union u_vga_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_p2; -+ -+/* Define the union u_vga_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_p3; -+ -+/* Define the union u_vga_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_csc_p4; -+ -+/* Define the union u_vga_hspcfg0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_tmp0 : 8; /* [7..0] */ -+ unsigned int hsp_hf0_tmp1 : 8; /* [15..8] */ -+ unsigned int hsp_hf0_tmp2 : 8; /* [23..16] */ -+ unsigned int hsp_hf0_tmp3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg0; -+ -+/* Define the union u_vga_hspcfg1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_coring : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int hsp_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg1; -+ -+/* Define the union u_vga_hspcfg5 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_gainpos : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int hsp_hf0_gainneg : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg5; -+ -+/* Define the union u_vga_hspcfg6 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_overth : 8; /* [7..0] */ -+ unsigned int hsp_hf0_underth : 8; /* [15..8] */ -+ unsigned int hsp_hf0_mixratio : 8; /* [23..16] */ -+ unsigned int reserved_0 : 4; /* [27..24] */ -+ unsigned int hsp_hf0_winsize : 3; /* [30..28] */ -+ unsigned int hsp_hf0_adpshoot_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg6; -+ -+/* Define the union u_vga_hspcfg7 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_tmp0 : 8; /* [7..0] */ -+ unsigned int hsp_hf1_tmp1 : 8; /* [15..8] */ -+ unsigned int hsp_hf1_tmp2 : 8; /* [23..16] */ -+ unsigned int hsp_hf1_tmp3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg7; -+ -+/* Define the union u_vga_hspcfg8 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_coring : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg8; -+ -+/* Define the union u_vga_hspcfg12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_gainpos : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int hsp_hf1_gainneg : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg12; -+ -+/* Define the union u_vga_hspcfg13 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_overth : 8; /* [7..0] */ -+ unsigned int hsp_hf1_underth : 8; /* [15..8] */ -+ unsigned int hsp_hf1_mixratio : 8; /* [23..16] */ -+ unsigned int reserved_0 : 4; /* [27..24] */ -+ unsigned int hsp_hf1_winsize : 3; /* [30..28] */ -+ unsigned int hsp_hf1_adpshoot_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg13; -+ -+/* Define the union u_vga_hspcfg14 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_cdti_gain : 8; /* [7..0] */ -+ unsigned int hsp_ldti_gain : 8; /* [15..8] */ -+ unsigned int hsp_lti_ratio : 8; /* [23..16] */ -+ unsigned int hsp_hf_shootdiv : 3; /* [26..24] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int hsp_ctih_en : 1; /* [28] */ -+ unsigned int hsp_ltih_en : 1; /* [29] */ -+ unsigned int hsp_h1_en : 1; /* [30] */ -+ unsigned int hsp_h0_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg14; -+ -+/* Define the union u_vga_hspcfg15 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hsp_glb_underth : 9; /* [8..0] */ -+ unsigned int reserved_0 : 1; /* [9] */ -+ unsigned int hsp_glb_overth : 9; /* [18..10] */ -+ unsigned int reserved_1 : 1; /* [19] */ -+ unsigned int hsp_peak_ratio : 8; /* [27..20] */ -+ unsigned int reserved_2 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vga_hspcfg15; -+ -+/* Define the union u_intf_date_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 23; /* [22..0] */ -+ unsigned int uv_mode : 1; /* [23] */ -+ unsigned int yc_mode : 1; /* [24] */ -+ unsigned int lcd_parallel_mode : 1; /* [25] */ -+ unsigned int lcd_data_inv : 1; /* [26] */ -+ unsigned int lcd_parallel_order : 1; /* [27] */ -+ unsigned int lcd_serial_perd : 1; /* [28] */ -+ unsigned int lcd_serial_mode : 1; /* [29] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_date_ctrl; -+ -+/* Define the union u_intf_date_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_date_upd; -+ -+/* Define the union u_intf_date_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf_date_sync_inv; -+ -+/* Define the union u_date_clip0_l */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int clip_cl0 : 10; /* [9..0] */ -+ unsigned int clip_cl1 : 10; /* [19..10] */ -+ unsigned int clip_cl2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int clip_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_clip0_l; -+ -+/* Define the union u_date_clip0_h */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int clip_ch0 : 10; /* [9..0] */ -+ unsigned int clip_ch1 : 10; /* [19..10] */ -+ unsigned int clip_ch2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_clip0_h; -+ -+/* Define the union u_intf0_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_ctrl; -+ -+/* Define the union u_intf0_dither_sed_y0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_y0; -+ -+/* Define the union u_intf0_dither_sed_u0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_u0; -+ -+/* Define the union u_intf0_dither_sed_v0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_v0; -+ -+/* Define the union u_intf0_dither_sed_w0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_w0; -+ -+/* Define the union u_intf0_dither_sed_y1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_y1; -+ -+/* Define the union u_intf0_dither_sed_u1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_u1; -+ -+/* Define the union u_intf0_dither_sed_v1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_v1; -+ -+/* Define the union u_intf0_dither_sed_w1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_w1; -+ -+/* Define the union u_intf0_dither_sed_y2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_y2; -+ -+/* Define the union u_intf0_dither_sed_u2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_u2; -+ -+/* Define the union u_intf0_dither_sed_v2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_v2; -+ -+/* Define the union u_intf0_dither_sed_w2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_w2; -+ -+/* Define the union u_intf0_dither_sed_y3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_y3; -+ -+/* Define the union u_intf0_dither_sed_u3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_u3; -+ -+/* Define the union u_intf0_dither_sed_v3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_v3; -+ -+/* Define the union u_intf0_dither_sed_w3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_sed_w3; -+ -+/* Define the union u_intf0_dither_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf0_dither_thr; -+ -+/* Define the union u_dhd1_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int disp_mode : 3; /* [3..1] */ -+ unsigned int iop : 1; /* [4] */ -+ unsigned int intf_ivs : 1; /* [5] */ -+ unsigned int intf_ihs : 1; /* [6] */ -+ unsigned int intf_idv : 1; /* [7] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int hdmi420c_sel : 1; /* [9] */ -+ unsigned int hdmi420_en : 1; /* [10] */ -+ unsigned int uf_offline_en : 1; /* [11] */ -+ unsigned int reserved_1 : 2; /* [13..12] */ -+ unsigned int hdmi_mode : 1; /* [14] */ -+ unsigned int twochn_debug : 1; /* [15] */ -+ unsigned int twochn_en : 1; /* [16] */ -+ unsigned int reserved_2 : 1; /* [17] */ -+ unsigned int cbar_mode : 1; /* [18] */ -+ unsigned int sin_en : 1; /* [19] */ -+ unsigned int fpga_lmt_width : 7; /* [26..20] */ -+ unsigned int fpga_lmt_en : 1; /* [27] */ -+ unsigned int p2i_en : 1; /* [28] */ -+ unsigned int cbar_sel : 1; /* [29] */ -+ unsigned int cbar_en : 1; /* [30] */ -+ unsigned int intf_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_ctrl; -+ -+/* Define the union u_dhd1_vsync1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vact : 16; /* [15..0] */ -+ unsigned int vbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vsync1; -+ -+/* Define the union u_dhd1_vsync2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vsync2; -+ -+/* Define the union u_dhd1_hsync1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hact : 16; /* [15..0] */ -+ unsigned int hbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_hsync1; -+ -+/* Define the union u_dhd1_hsync2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfb : 16; /* [15..0] */ -+ unsigned int hmid : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_hsync2; -+ -+/* Define the union u_dhd1_vplus1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bvact : 16; /* [15..0] */ -+ unsigned int bvbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vplus1; -+ -+/* Define the union u_dhd1_vplus2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bvfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vplus2; -+ -+/* Define the union u_dhd1_pwr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hpw : 16; /* [15..0] */ -+ unsigned int vpw : 8; /* [23..16] */ -+ unsigned int reserved_0 : 3; /* [26..24] */ -+ unsigned int multichn_en : 2; /* [28..27] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_pwr; -+ -+/* Define the union u_dhd1_vtthd3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vtmgthd3 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd3_mode : 1; /* [15] */ -+ unsigned int vtmgthd4 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd4_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vtthd3; -+ -+/* Define the union u_dhd1_vtthd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vtmgthd1 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd1_mode : 1; /* [15] */ -+ unsigned int vtmgthd2 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd2_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vtthd; -+ -+/* Define the union u_dhd1_parathd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int dfs_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_parathd; -+ -+/* Define the union u_dhd1_precharge_thd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tcon_precharge_thd : 17; /* [16..0] */ -+ unsigned int reserved_0 : 3; /* [19..17] */ -+ unsigned int vsync_te_mode : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_precharge_thd; -+ -+/* Define the union u_dhd1_start_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int start_pos : 8; /* [7..0] */ -+ unsigned int timing_start_pos : 8; /* [15..8] */ -+ unsigned int fi_start_pos : 4; /* [19..16] */ -+ unsigned int req_start_pos : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_start_pos; -+ -+/* Define the union u_dhd1_start_pos1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_start_pos1 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_start_pos1; -+ -+/* Define the union u_dhd1_paraup */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int paraup_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_paraup; -+ -+/* Define the union u_dhd1_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lcd_dv_inv : 1; /* [0] */ -+ unsigned int lcd_hs_inv : 1; /* [1] */ -+ unsigned int lcd_vs_inv : 1; /* [2] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int vga_dv_inv : 1; /* [4] */ -+ unsigned int vga_hs_inv : 1; /* [5] */ -+ unsigned int vga_vs_inv : 1; /* [6] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int hdmi_dv_inv : 1; /* [8] */ -+ unsigned int hdmi_hs_inv : 1; /* [9] */ -+ unsigned int hdmi_vs_inv : 1; /* [10] */ -+ unsigned int hdmi_f_inv : 1; /* [11] */ -+ unsigned int date_dv_inv : 1; /* [12] */ -+ unsigned int date_hs_inv : 1; /* [13] */ -+ unsigned int date_vs_inv : 1; /* [14] */ -+ unsigned int date_f_inv : 1; /* [15] */ -+ unsigned int reserved_2 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_sync_inv; -+ -+/* Define the union u_dhd1_clk_dv_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int intf_clk_mux : 1; /* [0] */ -+ unsigned int intf_dv_mux : 1; /* [1] */ -+ unsigned int no_active_area_pos : 16; /* [17..2] */ -+ unsigned int reserved_0 : 14; /* [31..18] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_clk_dv_ctrl; -+ -+/* Define the union u_dhd1_rgb_fix_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fix_b : 10; /* [9..0] */ -+ unsigned int fix_g : 10; /* [19..10] */ -+ unsigned int fix_r : 10; /* [29..20] */ -+ unsigned int rgb_fix_mux : 1; /* [30] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_rgb_fix_ctrl; -+ -+/* Define the union u_dhd1_lockcfg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int measure_en : 1; /* [0] */ -+ unsigned int lock_cnt_en : 1; /* [1] */ -+ unsigned int vdp_measure_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_lockcfg; -+ -+/* Define the union u_dhd1_intf_chksum_high1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int y0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_intf_chksum_high1; -+ -+/* Define the union u_dhd1_intf_chksum_high2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int y1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_intf_chksum_high2; -+ -+/* Define the union u_dhd1_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vback_blank : 1; /* [0] */ -+ unsigned int vblank : 1; /* [1] */ -+ unsigned int bottom_field : 1; /* [2] */ -+ unsigned int vcnt : 13; /* [15..3] */ -+ unsigned int count_int : 8; /* [23..16] */ -+ unsigned int dhd_even : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_state; -+ -+/* Define the union u_dhd1_uf_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ud_first_cnt : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int start_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_uf_state; -+ -+/* Define the union u_dhd1_vsync_te_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vsync_te_start_sta : 8; /* [7..0] */ -+ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ -+ unsigned int vsync_te_end_sta : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vsync_te_state; -+ -+/* Define the union u_dhd1_vsync_te_state1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vsync_te_vfb : 16; /* [15..0] */ -+ unsigned int vsync_te_width : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd1_vsync_te_state1; -+ -+/* Define the union u_intf1_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_ctrl; -+ -+/* Define the union u_intf1_dither_sed_y0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_y0; -+ -+/* Define the union u_intf1_dither_sed_u0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_u0; -+ -+/* Define the union u_intf1_dither_sed_v0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_v0; -+ -+/* Define the union u_intf1_dither_sed_w0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_w0; -+ -+/* Define the union u_intf1_dither_sed_y1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_y1; -+ -+/* Define the union u_intf1_dither_sed_u1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_u1; -+ -+/* Define the union u_intf1_dither_sed_v1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_v1; -+ -+/* Define the union u_intf1_dither_sed_w1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_w1; -+ -+/* Define the union u_intf1_dither_sed_y2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_y2; -+ -+/* Define the union u_intf1_dither_sed_u2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_u2; -+ -+/* Define the union u_intf1_dither_sed_v2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_v2; -+ -+/* Define the union u_intf1_dither_sed_w2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_w2; -+ -+/* Define the union u_intf1_dither_sed_y3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_y3; -+ -+/* Define the union u_intf1_dither_sed_u3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_u3; -+ -+/* Define the union u_intf1_dither_sed_v3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_v3; -+ -+/* Define the union u_intf1_dither_sed_w3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_sed_w3; -+ -+/* Define the union u_intf1_dither_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf1_dither_thr; -+ -+/* Define the union u_dhd2_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int disp_mode : 3; /* [3..1] */ -+ unsigned int iop : 1; /* [4] */ -+ unsigned int intf_ivs : 1; /* [5] */ -+ unsigned int intf_ihs : 1; /* [6] */ -+ unsigned int intf_idv : 1; /* [7] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int hdmi420c_sel : 1; /* [9] */ -+ unsigned int hdmi420_en : 1; /* [10] */ -+ unsigned int uf_offline_en : 1; /* [11] */ -+ unsigned int reserved_1 : 2; /* [13..12] */ -+ unsigned int hdmi_mode : 1; /* [14] */ -+ unsigned int twochn_debug : 1; /* [15] */ -+ unsigned int twochn_en : 1; /* [16] */ -+ unsigned int reserved_2 : 1; /* [17] */ -+ unsigned int cbar_mode : 1; /* [18] */ -+ unsigned int sin_en : 1; /* [19] */ -+ unsigned int fpga_lmt_width : 7; /* [26..20] */ -+ unsigned int fpga_lmt_en : 1; /* [27] */ -+ unsigned int p2i_en : 1; /* [28] */ -+ unsigned int cbar_sel : 1; /* [29] */ -+ unsigned int cbar_en : 1; /* [30] */ -+ unsigned int intf_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_ctrl; -+ -+/* Define the union u_dhd2_vsync1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vact : 16; /* [15..0] */ -+ unsigned int vbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vsync1; -+ -+/* Define the union u_dhd2_vsync2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vsync2; -+ -+/* Define the union u_dhd2_hsync1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hact : 16; /* [15..0] */ -+ unsigned int hbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_hsync1; -+ -+/* Define the union u_dhd2_hsync2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hfb : 16; /* [15..0] */ -+ unsigned int hmid : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_hsync2; -+ -+/* Define the union u_dhd2_vplus1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bvact : 16; /* [15..0] */ -+ unsigned int bvbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vplus1; -+ -+/* Define the union u_dhd2_vplus2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bvfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vplus2; -+ -+/* Define the union u_dhd2_pwr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int hpw : 16; /* [15..0] */ -+ unsigned int vpw : 8; /* [23..16] */ -+ unsigned int reserved_0 : 3; /* [26..24] */ -+ unsigned int multichn_en : 2; /* [28..27] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_pwr; -+ -+/* Define the union u_dhd2_vtthd3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vtmgthd3 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd3_mode : 1; /* [15] */ -+ unsigned int vtmgthd4 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd4_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vtthd3; -+ -+/* Define the union u_dhd2_vtthd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vtmgthd1 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd1_mode : 1; /* [15] */ -+ unsigned int vtmgthd2 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd2_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vtthd; -+ -+/* Define the union u_dhd2_parathd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int dfs_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_parathd; -+ -+/* Define the union u_dhd2_precharge_thd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tcon_precharge_thd : 17; /* [16..0] */ -+ unsigned int reserved_0 : 3; /* [19..17] */ -+ unsigned int vsync_te_mode : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_precharge_thd; -+ -+/* Define the union u_dhd2_start_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int start_pos : 8; /* [7..0] */ -+ unsigned int timing_start_pos : 8; /* [15..8] */ -+ unsigned int fi_start_pos : 4; /* [19..16] */ -+ unsigned int req_start_pos : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_start_pos; -+ -+/* Define the union u_dhd2_start_pos1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_start_pos1 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_start_pos1; -+ -+/* Define the union u_dhd2_paraup */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int paraup_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_paraup; -+ -+/* Define the union u_dhd2_sync_inv */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lcd_dv_inv : 1; /* [0] */ -+ unsigned int lcd_hs_inv : 1; /* [1] */ -+ unsigned int lcd_vs_inv : 1; /* [2] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int vga_dv_inv : 1; /* [4] */ -+ unsigned int vga_hs_inv : 1; /* [5] */ -+ unsigned int vga_vs_inv : 1; /* [6] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int hdmi_dv_inv : 1; /* [8] */ -+ unsigned int hdmi_hs_inv : 1; /* [9] */ -+ unsigned int hdmi_vs_inv : 1; /* [10] */ -+ unsigned int hdmi_f_inv : 1; /* [11] */ -+ unsigned int date_dv_inv : 1; /* [12] */ -+ unsigned int date_hs_inv : 1; /* [13] */ -+ unsigned int date_vs_inv : 1; /* [14] */ -+ unsigned int date_f_inv : 1; /* [15] */ -+ unsigned int reserved_2 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_sync_inv; -+ -+/* Define the union u_dhd2_clk_dv_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int intf_clk_mux : 1; /* [0] */ -+ unsigned int intf_dv_mux : 1; /* [1] */ -+ unsigned int no_active_area_pos : 16; /* [17..2] */ -+ unsigned int reserved_0 : 14; /* [31..18] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_clk_dv_ctrl; -+ -+/* Define the union u_dhd2_rgb_fix_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fix_b : 10; /* [9..0] */ -+ unsigned int fix_g : 10; /* [19..10] */ -+ unsigned int fix_r : 10; /* [29..20] */ -+ unsigned int rgb_fix_mux : 1; /* [30] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_rgb_fix_ctrl; -+ -+/* Define the union u_dhd2_lockcfg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int measure_en : 1; /* [0] */ -+ unsigned int lock_cnt_en : 1; /* [1] */ -+ unsigned int vdp_measure_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_lockcfg; -+ -+/* Define the union u_dhd2_intf_chksum_high1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int y0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_intf_chksum_high1; -+ -+/* Define the union u_dhd2_intf_chksum_high2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int y1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_intf_chksum_high2; -+ -+/* Define the union u_dhd2_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vback_blank : 1; /* [0] */ -+ unsigned int vblank : 1; /* [1] */ -+ unsigned int bottom_field : 1; /* [2] */ -+ unsigned int vcnt : 13; /* [15..3] */ -+ unsigned int count_int : 8; /* [23..16] */ -+ unsigned int dhd_even : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_state; -+ -+/* Define the union u_dhd2_uf_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ud_first_cnt : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int start_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_uf_state; -+ -+/* Define the union u_dhd2_vsync_te_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vsync_te_start_sta : 8; /* [7..0] */ -+ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ -+ unsigned int vsync_te_end_sta : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vsync_te_state; -+ -+/* Define the union u_dhd2_vsync_te_state1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vsync_te_vfb : 16; /* [15..0] */ -+ unsigned int vsync_te_width : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_dhd2_vsync_te_state1; -+ -+/* Define the union u_intf2_dither_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_ctrl; -+ -+/* Define the union u_intf2_dither_sed_y0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_y0; -+ -+/* Define the union u_intf2_dither_sed_u0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_u0; -+ -+/* Define the union u_intf2_dither_sed_v0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_v0; -+ -+/* Define the union u_intf2_dither_sed_w0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_w0; -+ -+/* Define the union u_intf2_dither_sed_y1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_y1; -+ -+/* Define the union u_intf2_dither_sed_u1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_u1; -+ -+/* Define the union u_intf2_dither_sed_v1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_v1; -+ -+/* Define the union u_intf2_dither_sed_w1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_w1; -+ -+/* Define the union u_intf2_dither_sed_y2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_y2; -+ -+/* Define the union u_intf2_dither_sed_u2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_u2; -+ -+/* Define the union u_intf2_dither_sed_v2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_v2; -+ -+/* Define the union u_intf2_dither_sed_w2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_w2; -+ -+/* Define the union u_intf2_dither_sed_y3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_y3; -+ -+/* Define the union u_intf2_dither_sed_u3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_u3; -+ -+/* Define the union u_intf2_dither_sed_v3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_v3; -+ -+/* Define the union u_intf2_dither_sed_w3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_sed_w3; -+ -+/* Define the union u_intf2_dither_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_intf2_dither_thr; -+ -+/* Define the union u_date_coeff0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt_seq : 1; /* [0] */ -+ unsigned int chgain_en : 1; /* [1] */ -+ unsigned int sylp_en : 1; /* [2] */ -+ unsigned int chlp_en : 1; /* [3] */ -+ unsigned int oversam2_en : 1; /* [4] */ -+ unsigned int lunt_en : 1; /* [5] */ -+ unsigned int oversam_en : 2; /* [7..6] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int luma_dl : 4; /* [12..9] */ -+ unsigned int agc_amp_sel : 1; /* [13] */ -+ unsigned int length_sel : 1; /* [14] */ -+ unsigned int sync_mode_scart : 1; /* [15] */ -+ unsigned int sync_mode_sel : 2; /* [17..16] */ -+ unsigned int style_sel : 4; /* [21..18] */ -+ unsigned int fm_sel : 1; /* [22] */ -+ unsigned int vbi_lpf_en : 1; /* [23] */ -+ unsigned int rgb_en : 1; /* [24] */ -+ unsigned int scanline : 1; /* [25] */ -+ unsigned int pbpr_lpf_en : 1; /* [26] */ -+ unsigned int pal_half_en : 1; /* [27] */ -+ unsigned int reserved_1 : 1; /* [28] */ -+ unsigned int dis_ire : 1; /* [29] */ -+ unsigned int clpf_sel : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff0; -+ -+/* Define the union u_date_coeff1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dac_test : 10; /* [9..0] */ -+ unsigned int date_test_mode : 2; /* [11..10] */ -+ unsigned int date_test_en : 1; /* [12] */ -+ unsigned int amp_outside : 10; /* [22..13] */ -+ unsigned int c_limit_en : 1; /* [23] */ -+ unsigned int cc_seq : 1; /* [24] */ -+ unsigned int cgms_seq : 1; /* [25] */ -+ unsigned int vps_seq : 1; /* [26] */ -+ unsigned int wss_seq : 1; /* [27] */ -+ unsigned int cvbs_limit_en : 1; /* [28] */ -+ unsigned int c_gain : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff1; -+ -+/* Define the union u_date_coeff3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef03 : 26; /* [25..0] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff3; -+ -+/* Define the union u_date_coeff4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef04 : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff4; -+ -+/* Define the union u_date_coeff5 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef05 : 29; /* [28..0] */ -+ unsigned int reserved_0 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff5; -+ -+/* Define the union u_date_coeff6 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int coef06_1 : 23; /* [22..0] */ -+ unsigned int reserved_0 : 8; /* [30..23] */ -+ unsigned int coef06_0 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff6; -+ -+/* Define the union u_date_coeff7 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt07_enf2 : 1; /* [0] */ -+ unsigned int tt08_enf2 : 1; /* [1] */ -+ unsigned int tt09_enf2 : 1; /* [2] */ -+ unsigned int tt10_enf2 : 1; /* [3] */ -+ unsigned int tt11_enf2 : 1; /* [4] */ -+ unsigned int tt12_enf2 : 1; /* [5] */ -+ unsigned int tt13_enf2 : 1; /* [6] */ -+ unsigned int tt14_enf2 : 1; /* [7] */ -+ unsigned int tt15_enf2 : 1; /* [8] */ -+ unsigned int tt16_enf2 : 1; /* [9] */ -+ unsigned int tt17_enf2 : 1; /* [10] */ -+ unsigned int tt18_enf2 : 1; /* [11] */ -+ unsigned int tt19_enf2 : 1; /* [12] */ -+ unsigned int tt20_enf2 : 1; /* [13] */ -+ unsigned int tt21_enf2 : 1; /* [14] */ -+ unsigned int tt22_enf2 : 1; /* [15] */ -+ unsigned int tt07_enf1 : 1; /* [16] */ -+ unsigned int tt08_enf1 : 1; /* [17] */ -+ unsigned int tt09_enf1 : 1; /* [18] */ -+ unsigned int tt10_enf1 : 1; /* [19] */ -+ unsigned int tt11_enf1 : 1; /* [20] */ -+ unsigned int tt12_enf1 : 1; /* [21] */ -+ unsigned int tt13_enf1 : 1; /* [22] */ -+ unsigned int tt14_enf1 : 1; /* [23] */ -+ unsigned int tt15_enf1 : 1; /* [24] */ -+ unsigned int tt16_enf1 : 1; /* [25] */ -+ unsigned int tt17_enf1 : 1; /* [26] */ -+ unsigned int tt18_enf1 : 1; /* [27] */ -+ unsigned int tt19_enf1 : 1; /* [28] */ -+ unsigned int tt20_enf1 : 1; /* [29] */ -+ unsigned int tt21_enf1 : 1; /* [30] */ -+ unsigned int tt22_enf1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff7; -+ -+/* Define the union u_date_coeff10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt_pktoff : 8; /* [7..0] */ -+ unsigned int tt_mode : 2; /* [9..8] */ -+ unsigned int tt_highest : 1; /* [10] */ -+ unsigned int full_page : 1; /* [11] */ -+ unsigned int nabts_100ire : 1; /* [12] */ -+ unsigned int reserved_0 : 18; /* [30..13] */ -+ unsigned int tt_ready : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff10; -+ -+/* Define the union u_date_coeff11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int date_clf2 : 10; /* [9..0] */ -+ unsigned int date_clf1 : 10; /* [19..10] */ -+ unsigned int cc_enf2 : 1; /* [20] */ -+ unsigned int cc_enf1 : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff11; -+ -+/* Define the union u_date_coeff12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cc_f2data : 16; /* [15..0] */ -+ unsigned int cc_f1data : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff12; -+ -+/* Define the union u_date_coeff13 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cg_f1data : 20; /* [19..0] */ -+ unsigned int cg_enf2 : 1; /* [20] */ -+ unsigned int cg_enf1 : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff13; -+ -+/* Define the union u_date_coeff14 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cg_f2data : 20; /* [19..0] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff14; -+ -+/* Define the union u_date_coeff15 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wss_data : 14; /* [13..0] */ -+ unsigned int wss_en : 1; /* [14] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff15; -+ -+/* Define the union u_date_coeff16 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vps_data : 24; /* [23..0] */ -+ unsigned int vps_en : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff16; -+ -+/* Define the union u_date_coeff19 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vps_data : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff19; -+ -+/* Define the union u_date_coeff20 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt05_enf2 : 1; /* [0] */ -+ unsigned int tt06_enf2 : 1; /* [1] */ -+ unsigned int tt06_enf1 : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff20; -+ -+/* Define the union u_date_coeff21 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dac0_in_sel : 3; /* [2..0] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int dac1_in_sel : 3; /* [6..4] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int dac2_in_sel : 3; /* [10..8] */ -+ unsigned int reserved_2 : 1; /* [11] */ -+ unsigned int dac3_in_sel : 3; /* [14..12] */ -+ unsigned int reserved_3 : 1; /* [15] */ -+ unsigned int dac4_in_sel : 3; /* [18..16] */ -+ unsigned int reserved_4 : 1; /* [19] */ -+ unsigned int dac5_in_sel : 3; /* [22..20] */ -+ unsigned int reserved_5 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff21; -+ -+/* Define the union u_date_coeff22 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int video_phase_delta : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff22; -+ -+/* Define the union u_date_coeff23 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dac0_out_dly : 3; /* [2..0] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int dac1_out_dly : 3; /* [6..4] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int dac2_out_dly : 3; /* [10..8] */ -+ unsigned int reserved_2 : 1; /* [11] */ -+ unsigned int dac3_out_dly : 3; /* [14..12] */ -+ unsigned int reserved_3 : 1; /* [15] */ -+ unsigned int dac4_out_dly : 3; /* [18..16] */ -+ unsigned int reserved_4 : 1; /* [19] */ -+ unsigned int dac5_out_dly : 3; /* [22..20] */ -+ unsigned int reserved_5 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff23; -+ -+/* Define the union u_date_coeff25 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_n_coef : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int x_n_1_coef : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff25; -+ -+/* Define the union u_date_coeff26 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int x_n_1_coef : 13; /* [12..0] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff26; -+ -+/* Define the union u_date_coeff27 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int y_n_coef : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int y_n_1_coef : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff27; -+ -+/* Define the union u_date_coeff28 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int pixel_begin1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int pixel_begin2 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff28; -+ -+/* Define the union u_date_coeff29 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int pixel_end : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff29; -+ -+/* Define the union u_date_coeff30 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int g_secam : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff30; -+ -+/* Define the union u_date_isrmask */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt_mask : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_isrmask; -+ -+/* Define the union u_date_isrstate */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt_status : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_isrstate; -+ -+/* Define the union u_date_isr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tt_int : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_isr; -+ -+/* Define the union u_date_coeff37 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fir_y1_coeff0 : 8; /* [7..0] */ -+ unsigned int fir_y1_coeff1 : 8; /* [15..8] */ -+ unsigned int fir_y1_coeff2 : 8; /* [23..16] */ -+ unsigned int fir_y1_coeff3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff37; -+ -+/* Define the union u_date_coeff38 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fir_y2_coeff0 : 16; /* [15..0] */ -+ unsigned int fir_y2_coeff1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff38; -+ -+/* Define the union u_date_coeff39 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fir_y2_coeff2 : 16; /* [15..0] */ -+ unsigned int fir_y2_coeff3 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff39; -+ -+/* Define the union u_date_coeff40 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fir_c1_coeff0 : 8; /* [7..0] */ -+ unsigned int fir_c1_coeff1 : 8; /* [15..8] */ -+ unsigned int fir_c1_coeff2 : 8; /* [23..16] */ -+ unsigned int fir_c1_coeff3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff40; -+ -+/* Define the union u_date_coeff41 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fir_c2_coeff0 : 16; /* [15..0] */ -+ unsigned int fir_c2_coeff1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff41; -+ -+/* Define the union u_date_coeff42 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int fir_c2_coeff2 : 16; /* [15..0] */ -+ unsigned int fir_c2_coeff3 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff42; -+ -+/* Define the union u_date_dacdet1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vdac_det_high : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int det_line : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_dacdet1; -+ -+/* Define the union u_date_dacdet2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int det_pixel_sta : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int det_pixel_wid : 11; /* [26..16] */ -+ unsigned int reserved_1 : 4; /* [30..27] */ -+ unsigned int vdac_det_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_dacdet2; -+ -+/* Define the union u_date_coeff50 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff50; -+ -+/* Define the union u_date_coeff51 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff51; -+ -+/* Define the union u_date_coeff52 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff52; -+ -+/* Define the union u_date_coeff53 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff53; -+ -+/* Define the union u_date_coeff54 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff54; -+ -+/* Define the union u_date_coeff55 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_date_coeff55; -+ -+/* Define the union u_mac_outstanding */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mstr0_routstanding : 4; /* [3..0] */ -+ unsigned int mstr0_woutstanding : 4; /* [7..4] */ -+ unsigned int mstr1_routstanding : 4; /* [11..8] */ -+ unsigned int mstr1_woutstanding : 4; /* [15..12] */ -+ unsigned int mstr2_routstanding : 4; /* [19..16] */ -+ unsigned int mstr2_woutstanding : 4; /* [23..20] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_outstanding; -+ -+/* Define the union u_mac_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int split_mode : 4; /* [3..0] */ -+ unsigned int arb_mode : 4; /* [7..4] */ -+ unsigned int mid_enable : 1; /* [8] */ -+ unsigned int reserved_0 : 3; /* [11..9] */ -+ unsigned int wport_sel : 4; /* [15..12] */ -+ unsigned int reserved_1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_ctrl; -+ -+/* Define the union u_mac_rchn_prio */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_prio : 1; /* [0] */ -+ unsigned int v0l_prio : 1; /* [1] */ -+ unsigned int v0c_prio : 1; /* [2] */ -+ unsigned int v0lh_prio : 1; /* [3] */ -+ unsigned int v0ch_prio : 1; /* [4] */ -+ unsigned int v1l_prio : 1; /* [5] */ -+ unsigned int v1c_prio : 1; /* [6] */ -+ unsigned int v1lh_prio : 1; /* [7] */ -+ unsigned int v1ch_prio : 1; /* [8] */ -+ unsigned int g0ar_prio : 1; /* [9] */ -+ unsigned int g0gb_prio : 1; /* [10] */ -+ unsigned int g1ar_prio : 1; /* [11] */ -+ unsigned int g1gb_prio : 1; /* [12] */ -+ unsigned int v2l_prio : 1; /* [13] */ -+ unsigned int v2c_prio : 1; /* [14] */ -+ unsigned int v2lh_prio : 1; /* [15] */ -+ unsigned int v2ch_prio : 1; /* [16] */ -+ unsigned int g3ar_prio : 1; /* [17] */ -+ unsigned int g3gb_prio : 1; /* [18] */ -+ unsigned int reserved_0 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_rchn_prio; -+ -+/* Define the union u_mac_wchn_prio */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbcl_prio : 1; /* [0] */ -+ unsigned int wbcc_prio : 1; /* [1] */ -+ unsigned int wbclh_prio : 1; /* [2] */ -+ unsigned int wbcch_prio : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_wchn_prio; -+ -+/* Define the union u_mac_rchn_sel0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int para_sel : 2; /* [1..0] */ -+ unsigned int v0l_sel : 2; /* [3..2] */ -+ unsigned int v0c_sel : 2; /* [5..4] */ -+ unsigned int v0lh_sel : 2; /* [7..6] */ -+ unsigned int v0ch_sel : 2; /* [9..8] */ -+ unsigned int v1l_sel : 2; /* [11..10] */ -+ unsigned int v1c_sel : 2; /* [13..12] */ -+ unsigned int v1lh_sel : 2; /* [15..14] */ -+ unsigned int v1ch_sel : 2; /* [17..16] */ -+ unsigned int g0ar_sel : 2; /* [19..18] */ -+ unsigned int g0gb_sel : 2; /* [21..20] */ -+ unsigned int g1ar_sel : 2; /* [23..22] */ -+ unsigned int g1gb_sel : 2; /* [25..24] */ -+ unsigned int v2_sel : 2; /* [27..26] */ -+ unsigned int g3_sel : 2; /* [29..28] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_rchn_sel0; -+ -+/* Define the union u_mac_wchn_sel0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbcl_sel : 2; /* [1..0] */ -+ unsigned int wbcc_sel : 2; /* [3..2] */ -+ unsigned int wbclh_sel : 2; /* [5..4] */ -+ unsigned int wbcch_sel : 2; /* [7..6] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_wchn_sel0; -+ -+/* Define the union u_mac_bus_err_clr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int bus_error_clr : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_bus_err_clr; -+ -+/* Define the union u_mac_bus_err */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mst0_r_error : 1; /* [0] */ -+ unsigned int mst0_w_error : 1; /* [1] */ -+ unsigned int mst1_r_error : 1; /* [2] */ -+ unsigned int mst1_w_error : 1; /* [3] */ -+ unsigned int mst2_r_error : 1; /* [4] */ -+ unsigned int mst2_w_error : 1; /* [5] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_bus_err; -+ -+/* Define the union u_mac_debug_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int axi_det_enable : 1; /* [0] */ -+ unsigned int reserved_0 : 3; /* [3..1] */ -+ unsigned int fifo_det_mode : 4; /* [7..4] */ -+ unsigned int reserved_1 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_debug_ctrl; -+ -+/* Define the union u_mac_debug_clr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int axi_det_clr : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_mac_debug_clr; -+ -+/* Define the union u_vid_read_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int chm_rmode : 3; /* [2..0] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int lm_rmode : 3; /* [6..4] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int chm_draw_mode : 2; /* [9..8] */ -+ unsigned int lm_draw_mode : 2; /* [11..10] */ -+ unsigned int flip_en : 1; /* [12] */ -+ unsigned int chm_copy_en : 1; /* [13] */ -+ unsigned int reserved_2 : 2; /* [15..14] */ -+ unsigned int mute_en : 1; /* [16] */ -+ unsigned int mute_req_en : 1; /* [17] */ -+ unsigned int vicap_mute_en : 1; /* [18] */ -+ unsigned int mrg_enable : 1; /* [19] */ -+ unsigned int mrg_mute_mode : 1; /* [20] */ -+ unsigned int fdr_ck_gt_en : 1; /* [21] */ -+ unsigned int reserved_3 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_read_ctrl; -+ -+/* Define the union u_vid_mac_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_ctrl : 2; /* [1..0] */ -+ unsigned int req_len : 2; /* [3..2] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int ofl_master : 1; /* [8] */ -+ unsigned int reserved_1 : 22; /* [30..9] */ -+ unsigned int pre_rd_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_mac_ctrl; -+ -+/* Define the union u_vid_out_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int draw_pixel_mode : 3; /* [2..0] */ -+ unsigned int draw_pixel_en : 1; /* [3] */ -+ unsigned int uv_order_en : 1; /* [4] */ -+ unsigned int single_port_mode : 1; /* [5] */ -+ unsigned int testpattern_en : 1; /* [6] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_out_ctrl; -+ -+/* Define the union u_vid_mute_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_mute_alpha; -+ -+/* Define the union u_vid_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_mute_bk; -+ -+/* Define the union u_vid_src_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int data_type : 3; /* [2..0] */ -+ unsigned int data_fmt : 2; /* [4..3] */ -+ unsigned int reserved_0 : 3; /* [7..5] */ -+ unsigned int data_width : 2; /* [9..8] */ -+ unsigned int reserved_1 : 2; /* [11..10] */ -+ unsigned int field_type : 1; /* [12] */ -+ unsigned int reserved_2 : 3; /* [15..13] */ -+ unsigned int disp_mode : 4; /* [19..16] */ -+ unsigned int dcmp_en : 2; /* [21..20] */ -+ unsigned int reserved_3 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_src_info; -+ -+/* Define the union u_vid_src_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int src_w : 16; /* [15..0] */ -+ unsigned int src_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_src_reso; -+ -+/* Define the union u_vid_src_crop */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int src_crop_x : 16; /* [15..0] */ -+ unsigned int src_crop_y : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_src_crop; -+ -+/* Define the union u_vid_in_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ireso_w : 16; /* [15..0] */ -+ unsigned int ireso_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_in_reso; -+ -+/* Define the union u_vid_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lm_stride : 16; /* [15..0] */ -+ unsigned int chm_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_stride; -+ -+/* Define the union u_vid_2bit_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lm_tile_stride : 16; /* [15..0] */ -+ unsigned int chm_tile_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_2bit_stride; -+ -+/* Define the union u_vid_head_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lm_head_stride : 16; /* [15..0] */ -+ unsigned int chm_head_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_head_stride; -+ -+/* Define the union u_vid_smmu_bypass */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lm_bypass_2d : 1; /* [0] */ -+ unsigned int chm_bypass_2d : 1; /* [1] */ -+ unsigned int lm_bypass_3d : 1; /* [2] */ -+ unsigned int chm_bypass_3d : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_smmu_bypass; -+ -+/* Define the union u_vid_testpat_cfg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tp_speed : 10; /* [9..0] */ -+ unsigned int reserved_0 : 2; /* [11..10] */ -+ unsigned int tp_line_w : 1; /* [12] */ -+ unsigned int tp_color_mode : 1; /* [13] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int tp_mode : 2; /* [17..16] */ -+ unsigned int reserved_2 : 14; /* [31..18] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_testpat_cfg; -+ -+/* Define the union u_vid_testpat_seed */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tp_seed : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_testpat_seed; -+ -+/* Define the union u_vid_dcmp_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int c_is_lossless : 1; /* [0] */ -+ unsigned int l_is_lossless : 1; /* [1] */ -+ unsigned int c_cmp_mode : 1; /* [2] */ -+ unsigned int l_cmp_mode : 1; /* [3] */ -+ unsigned int c_cmp_rate : 2; /* [5..4] */ -+ unsigned int l_cmp_rate : 2; /* [7..6] */ -+ unsigned int mem_mode : 1; /* [8] */ -+ unsigned int reserved_0 : 23; /* [31..9] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vid_dcmp_ctrl; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_glb_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int is_lossless : 1; /* [1] */ -+ unsigned int cmp_mode : 1; /* [2] */ -+ unsigned int max_mb_qp_y : 3; /* [5..3] */ -+ unsigned int reserved_0 : 10; /* [15..6] */ -+ unsigned int max_mb_qp_c : 3; /* [18..16] */ -+ unsigned int seg_en : 1; /* [19] */ -+ unsigned int bit_depth : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_glb_info; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_frame_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_height : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_width : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_frame_size; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_error_sta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dcmp_error : 1; /* [0] */ -+ unsigned int forgive : 1; /* [1] */ -+ unsigned int consume : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_error_sta; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_glb_info_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int is_lossless : 1; /* [1] */ -+ unsigned int cmp_mode : 1; /* [2] */ -+ unsigned int max_mb_qp_y : 3; /* [5..3] */ -+ unsigned int reserved_0 : 10; /* [15..6] */ -+ unsigned int max_mb_qp_c : 3; /* [18..16] */ -+ unsigned int seg_en : 1; /* [19] */ -+ unsigned int bit_depth : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_glb_info_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_frame_size_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_height : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_width : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_frame_size_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_dcmp_error_sta_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dcmp_error : 1; /* [0] */ -+ unsigned int forgive : 1; /* [1] */ -+ unsigned int consume : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_dcmp_error_sta_c; -+ -+/* Define the union u_gfx_read_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int read_mode : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int draw_mode : 2; /* [5..4] */ -+ unsigned int reserved_1 : 2; /* [7..6] */ -+ unsigned int flip_en : 1; /* [8] */ -+ unsigned int reserved_2 : 1; /* [9] */ -+ unsigned int mute_en : 1; /* [10] */ -+ unsigned int mute_req_en : 1; /* [11] */ -+ unsigned int fdr_ck_gt_en : 1; /* [12] */ -+ unsigned int reserved_3 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_read_ctrl; -+ -+/* Define the union u_gfx_mac_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_ctrl : 2; /* [1..0] */ -+ unsigned int req_len : 2; /* [3..2] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int ofl_master : 1; /* [8] */ -+ unsigned int dcmp_thd_close : 1; /* [9] */ -+ unsigned int dcmp_mute_ctrl : 1; /* [10] */ -+ unsigned int reserved_1 : 13; /* [23..11] */ -+ unsigned int req_ld_mode : 2; /* [25..24] */ -+ unsigned int reserved_2 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_mac_ctrl; -+ -+/* Define the union u_gfx_out_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int palpha_range : 1; /* [0] */ -+ unsigned int palpha_en : 1; /* [1] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int key_mode : 1; /* [4] */ -+ unsigned int enable : 1; /* [5] */ -+ unsigned int reserved_1 : 2; /* [7..6] */ -+ unsigned int bitext : 2; /* [9..8] */ -+ unsigned int premulti_en : 1; /* [10] */ -+ unsigned int testpattern_en : 1; /* [11] */ -+ unsigned int reserved_2 : 20; /* [31..12] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_out_ctrl; -+ -+/* Define the union u_gfx_mute_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_mute_alpha; -+ -+/* Define the union u_gfx_mute_bk */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_mute_bk; -+ -+/* Define the union u_gfx_smmu_bypass */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smmu_bypass_2d : 1; /* [0] */ -+ unsigned int smmu_bypass_3d : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_smmu_bypass; -+ -+/* Define the union u_gfx_1555_alpha */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int alpha_0 : 8; /* [7..0] */ -+ unsigned int alpha_1 : 8; /* [15..8] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_1555_alpha; -+ -+/* Define the union u_gfx_src_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ifmt : 8; /* [7..0] */ -+ unsigned int reserved_0 : 8; /* [15..8] */ -+ unsigned int disp_mode : 4; /* [19..16] */ -+ unsigned int dcmp_en : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_src_info; -+ -+/* Define the union u_gfx_src_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int src_w : 16; /* [15..0] */ -+ unsigned int src_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_src_reso; -+ -+/* Define the union u_gfx_src_crop */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int src_crop_x : 16; /* [15..0] */ -+ unsigned int src_crop_y : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_src_crop; -+ -+/* Define the union u_gfx_ireso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ireso_w : 16; /* [15..0] */ -+ unsigned int ireso_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ireso; -+ -+/* Define the union u_gfx_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int surface_stride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_stride; -+ -+/* Define the union u_gfx_ckey_max */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int key_b_max : 8; /* [7..0] */ -+ unsigned int key_g_max : 8; /* [15..8] */ -+ unsigned int key_r_max : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ckey_max; -+ -+/* Define the union u_gfx_ckey_min */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int key_b_min : 8; /* [7..0] */ -+ unsigned int key_g_min : 8; /* [15..8] */ -+ unsigned int key_r_min : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ckey_min; -+ -+/* Define the union u_gfx_ckey_mask */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int key_b_msk : 8; /* [7..0] */ -+ unsigned int key_g_msk : 8; /* [15..8] */ -+ unsigned int key_r_msk : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ckey_mask; -+ -+/* Define the union u_gfx_testpat_cfg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tp_speed : 10; /* [9..0] */ -+ unsigned int reserved_0 : 2; /* [11..10] */ -+ unsigned int tp_line_w : 1; /* [12] */ -+ unsigned int tp_color_mode : 1; /* [13] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int tp_mode : 2; /* [17..16] */ -+ unsigned int reserved_2 : 14; /* [31..18] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_testpat_cfg; -+ -+/* Define the union u_gfx_testpat_seed */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int tp_seed : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_testpat_seed; -+ -+/* Define the union u_gfx_ld_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hw_mute_clr : 1; /* [1] */ -+ unsigned int ld_mute_en : 1; /* [2] */ -+ unsigned int ld_err_mute_en : 1; /* [3] */ -+ unsigned int reserved_1 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ld_ctrl; -+ -+/* Define the union u_gfx_ld_smute_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved : 31; /* [30..0] */ -+ unsigned int sw_mute_clr : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ld_smute_ctrl; -+ -+/* Define the union u_gfx_ld_err_sta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ld_err_clr : 1; /* [0] */ -+ unsigned int reserved : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_ld_err_sta; -+ -+ -+ -+ -+/* define the union reg_vdp_v3r2_line_osd_dcmp_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int conv_en : 1; /* [2] */ -+ unsigned int is_lossless : 1; /* [3] */ -+ unsigned int osd_mode : 2; /* [5..4] */ -+ unsigned int max_mb_qp : 3; /* [8..6] */ -+ unsigned int excess_err_mask : 1; /* [9] */ -+ unsigned int rw_reg_add : 6; /* [15..10] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_line_osd_dcmp_glb_info; -+ -+/* define the union reg_vdp_v3r2_line_osd_dcmp_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_height : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_line_osd_dcmp_frame_size; -+ -+/* define the union reg_vdp_v3r2_line_osd_dcmp_error_sta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dcmp_error : 1; /* [0] */ -+ unsigned int o_pix_forgive : 1; /* [1] */ -+ unsigned int o_pix_consume : 1; /* [2] */ -+ unsigned int o_mb_qp_error : 1; /* [3] */ -+ unsigned int o_dcmp_excess_err : 1; /* [4] */ -+ unsigned int o_dcmp_err_add : 5; /* [9..5] */ -+ unsigned int o_dcmp_debug : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_line_osd_dcmp_error_sta; -+ -+ -+/* Define the union u_wbc_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 4; /* [3..0] */ -+ unsigned int data_width : 1; /* [4] */ -+ unsigned int reserved_1 : 3; /* [7..5] */ -+ unsigned int uv_order : 1; /* [8] */ -+ unsigned int flip_en : 1; /* [9] */ -+ unsigned int align_mode : 1; /* [10] */ -+ unsigned int reserved_2 : 3; /* [13..11] */ -+ unsigned int cap_ck_gt_en : 1; /* [14] */ -+ unsigned int reserved_3 : 14; /* [28..15] */ -+ unsigned int wbc_cmp_en : 1; /* [29] */ -+ unsigned int reserved_4 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_ctrl; -+ -+/* Define the union u_wbc_mac_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 2; /* [11..10] */ -+ unsigned int wbc_len : 2; /* [13..12] */ -+ unsigned int reserved_1 : 18; /* [31..14] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_mac_ctrl; -+ -+/* Define the union u_wbc_smmu_bypass */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int l_bypass : 1; /* [0] */ -+ unsigned int c_bypass : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_smmu_bypass; -+ -+/* Define the union u_wbc_lowdlyctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wb_per_line_num : 12; /* [11..0] */ -+ unsigned int partfns_line_num : 12; /* [23..12] */ -+ unsigned int reserved_0 : 6; /* [29..24] */ -+ unsigned int lowdly_test : 1; /* [30] */ -+ unsigned int lowdly_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_lowdlyctrl; -+ -+/* Define the union u_wbc_lowdlysta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int part_finish : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_lowdlysta; -+ -+/* Define the union u_wbc_ystride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_ystride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_ystride; -+ -+/* Define the union u_wbc_cstride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_cstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cstride; -+ -+/* Define the union u_wbc_ynstride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_ynstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_ynstride; -+ -+/* Define the union u_wbc_cnstride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_cnstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cnstride; -+ -+/* Define the union u_wbc_sta */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_l_busy : 1; /* [0] */ -+ unsigned int wbc_c_busy : 1; /* [1] */ -+ unsigned int wbc_lh_busy : 1; /* [2] */ -+ unsigned int wbc_ch_busy : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_sta; -+ -+/* Define the union u_wbc_line_num */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int wbc_l_linenum : 16; /* [15..0] */ -+ unsigned int wbc_c_linenum : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_line_num; -+ -+/* Define the union u_wbc_cap_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cap_width : 16; /* [15..0] */ -+ unsigned int cap_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cap_reso; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_glb_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int is_lossless : 1; /* [2] */ -+ unsigned int chroma_en : 1; /* [3] */ -+ unsigned int esl_qp : 3; /* [6..4] */ -+ unsigned int bit_depth : 1; /* [7] */ -+ unsigned int mirror_en : 1; /* [8] */ -+ unsigned int seg_en : 1; /* [9] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_glb_info; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_frame_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_width : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_height : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_frame_size; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int big_grad_thr : 8; /* [7..0] */ -+ unsigned int diff_thr : 8; /* [15..8] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg0; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg1; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int buffer_init_bits : 16; /* [15..0] */ -+ unsigned int buffer_size : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg12; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg13 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int budget_mb_bits : 10; /* [9..0] */ -+ unsigned int budget_mb_bits_last : 10; /* [19..10] */ -+ unsigned int min_mb_bits : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg13; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg16 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smooth_status_thr : 4; /* [3..0] */ -+ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ -+ unsigned int max_mb_qp : 3; /* [14..12] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg16; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_glb_st */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_left_bits_buffer : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_glb_st; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_glb_info_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int is_lossless : 1; /* [2] */ -+ unsigned int chroma_en : 1; /* [3] */ -+ unsigned int esl_qp : 3; /* [6..4] */ -+ unsigned int bit_depth : 1; /* [7] */ -+ unsigned int mirror_en : 1; /* [8] */ -+ unsigned int seg_en : 1; /* [9] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_glb_info_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_frame_size_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_width : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_height : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_frame_size_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg0_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int big_grad_thr : 8; /* [7..0] */ -+ unsigned int diff_thr : 8; /* [15..8] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg0_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg1_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg1_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg12_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int buffer_init_bits : 16; /* [15..0] */ -+ unsigned int buffer_size : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg12_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg13_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int budget_mb_bits : 10; /* [9..0] */ -+ unsigned int budget_mb_bits_last : 10; /* [19..10] */ -+ unsigned int min_mb_bits : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg13_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_rc_cfg16_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smooth_status_thr : 4; /* [3..0] */ -+ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ -+ unsigned int max_mb_qp : 3; /* [14..12] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_rc_cfg16_c; -+ -+/* Define the union u_vdp_v3r2_lineseg_cmp_glb_st_c */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_left_bits_buffer : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_vdp_v3r2_lineseg_cmp_glb_st_c; -+ -+/* Define the union u_wbc_cmp_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 17; /* [26..10] */ -+ unsigned int mem_mode : 1; /* [27] */ -+ unsigned int data_width : 1; /* [28] */ -+ unsigned int reserved_1 : 1; /* [29] */ -+ unsigned int l_cmp_en : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_ctrl; -+ -+/* Define the union u_wbc_cmp_upd */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_upd; -+ -+/* Define the union u_wbc_cmp_height */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int c_max_height : 13; /* [12..0] */ -+ unsigned int l_max_height : 13; /* [25..13] */ -+ unsigned int addr_mode : 1; /* [26] */ -+ unsigned int fsize_mode : 1; /* [27] */ -+ unsigned int rgb_cmp_mode : 2; /* [29..28] */ -+ unsigned int pause_mode : 1; /* [30] */ -+ unsigned int buffer_mode : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_height; -+ -+/* Define the union u_wbc_cmp_oreso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_cmp_oreso; -+ -+/* Define the union u_wbc_od_state */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int addr_err : 1; /* [0] */ -+ unsigned int he_addr_err0 : 1; /* [1] */ -+ unsigned int he_addr_err1 : 1; /* [2] */ -+ unsigned int he_addr_err2 : 1; /* [3] */ -+ unsigned int w_addr_err : 1; /* [4] */ -+ unsigned int he_fsize_err0 : 1; /* [5] */ -+ unsigned int he_fsize_err1 : 1; /* [6] */ -+ unsigned int he_fsize_err2 : 1; /* [7] */ -+ unsigned int w_fsize_err : 1; /* [8] */ -+ unsigned int he_fsize_war0 : 1; /* [9] */ -+ unsigned int he_fsize_war1 : 1; /* [10] */ -+ unsigned int he_fsize_war2 : 1; /* [11] */ -+ unsigned int w_fsize_war : 1; /* [12] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_wbc_od_state; -+ -+/* Define the union u_od_pic_osd_glb_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int is_lossless : 1; /* [0] */ -+ unsigned int is_lossless_a : 1; /* [1] */ -+ unsigned int cmp_mode : 1; /* [2] */ -+ unsigned int source_mode : 3; /* [5..3] */ -+ unsigned int part_cmp_en : 1; /* [6] */ -+ unsigned int top_pred_en : 1; /* [7] */ -+ unsigned int graphic_en : 1; /* [8] */ -+ unsigned int reserved_0 : 23; /* [31..9] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_glb_info; -+ -+/* Define the union u_od_pic_osd_frame_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_width : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int frame_height : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_frame_size; -+ -+/* Define the union u_od_pic_osd_rc_cfg0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mb_bits : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int min_mb_bits : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg0; -+ -+/* Define the union u_od_pic_osd_rc_cfg1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_qp : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int sad_bits_gain : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int rc_smth_ngain : 3; /* [18..16] */ -+ unsigned int reserved_2 : 5; /* [23..19] */ -+ unsigned int max_trow_bits : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg1; -+ -+/* Define the union u_od_pic_osd_rc_cfg2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_sad_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int min_sad_thr : 7; /* [22..16] */ -+ unsigned int reserved_1 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg2; -+ -+/* Define the union u_od_pic_osd_rc_cfg3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smth_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int still_thr : 7; /* [14..8] */ -+ unsigned int reserved_1 : 1; /* [15] */ -+ unsigned int big_grad_thr : 10; /* [25..16] */ -+ unsigned int reserved_2 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg3; -+ -+/* Define the union u_od_pic_osd_rc_cfg4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int smth_pix_num_thr : 6; /* [5..0] */ -+ unsigned int reserved_0 : 2; /* [7..6] */ -+ unsigned int still_pix_num_thr : 6; /* [13..8] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_2 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg4; -+ -+/* Define the union u_od_pic_osd_rc_cfg5 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int noise_sad : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int pix_diff_thr : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg5; -+ -+/* Define the union u_od_pic_osd_rc_cfg6 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg6; -+ -+/* Define the union u_od_pic_osd_rc_cfg7 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg7; -+ -+/* Define the union u_od_pic_osd_rc_cfg8 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int est_err_gain : 5; /* [4..0] */ -+ unsigned int reserved_0 : 11; /* [15..5] */ -+ unsigned int max_est_err_level : 9; /* [24..16] */ -+ unsigned int reserved_1 : 7; /* [31..25] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg8; -+ -+/* Define the union u_od_pic_osd_rc_cfg9 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 16; /* [15..0] */ -+ unsigned int vbv_buf_loss1_thr : 7; /* [22..16] */ -+ unsigned int reserved_1 : 1; /* [23] */ -+ unsigned int vbv_buf_loss2_thr : 7; /* [30..24] */ -+ unsigned int reserved_2 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg9; -+ -+/* Define the union u_od_pic_osd_rc_cfg10 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int qp_thr0 : 3; /* [2..0] */ -+ unsigned int reserved_0 : 5; /* [7..3] */ -+ unsigned int qp_thr1 : 3; /* [10..8] */ -+ unsigned int reserved_1 : 5; /* [15..11] */ -+ unsigned int qp_thr2 : 3; /* [18..16] */ -+ unsigned int reserved_2 : 13; /* [31..19] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg10; -+ -+/* Define the union u_od_pic_osd_rc_cfg11 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int grph_bias_bit_thr0 : 8; /* [7..0] */ -+ unsigned int grph_bias_bit_thr1 : 8; /* [15..8] */ -+ unsigned int grph_ideal_bit_thr : 10; /* [25..16] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg11; -+ -+/* Define the union u_od_pic_osd_rc_cfg12 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int force_rc_en : 1; /* [0] */ -+ unsigned int reserved_0 : 7; /* [7..1] */ -+ unsigned int forcerc_bits_diff_thr : 8; /* [15..8] */ -+ unsigned int reserved_1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg12; -+ -+/* Define the union u_od_pic_osd_rc_cfg13 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int maxdiff_ctrl_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg13; -+ -+/* Define the union u_od_pic_osd_rc_cfg14 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mb_bits_cap : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int init_buf_bits_cap : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg14; -+ -+/* Define the union u_od_pic_osd_rc_cfg15 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int lfw_mb_len : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int cmplx_sad_thr : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int err_thr0 : 4; /* [19..16] */ -+ unsigned int reserved_2 : 4; /* [23..20] */ -+ unsigned int err_thr1 : 4; /* [27..24] */ -+ unsigned int reserved_3 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg15; -+ -+/* Define the union u_od_pic_osd_rc_cfg16 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int sim_num_thr : 3; /* [2..0] */ -+ unsigned int reserved_0 : 5; /* [7..3] */ -+ unsigned int sum_y_err_thr : 7; /* [14..8] */ -+ unsigned int reserved_1 : 1; /* [15] */ -+ unsigned int sum_c_err_thr : 7; /* [22..16] */ -+ unsigned int reserved_2 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg16; -+ -+/* Define the union u_od_pic_osd_rc_cfg17 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cpmlx_sad_thr_y : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int smpl_sad_thr_c : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int smpl_sumsad_thr_y : 8; /* [23..16] */ -+ unsigned int smpl_sumsad_thr_c : 8; /* [31..24] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg17; -+ -+/* Define the union u_od_pic_osd_rc_cfg18 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int future_sad_y_thr0 : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int future_sad_c_thr0 : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int future_sad_y_thr1 : 4; /* [19..16] */ -+ unsigned int reserved_2 : 4; /* [23..20] */ -+ unsigned int future_sad_c_thr1 : 4; /* [27..24] */ -+ unsigned int reserved_3 : 4; /* [31..28] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg18; -+ -+/* Define the union u_od_pic_osd_rc_cfg19 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cmplx_sumsad_thr_y : 8; /* [7..0] */ -+ unsigned int cmplx_sumsad_thr_c : 8; /* [15..8] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_rc_cfg19; -+ -+/* Define the union u_od_pic_osd_stat_thr */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_gap_bw_row_len_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_stat_thr; -+ -+/* Define the union u_od_pic_osd_pcmp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int pcmp_start_hpos : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int pcmp_end_hpos : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_pcmp; -+ -+/* Define the union u_od_pic_osd_bs_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_size_reg : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_bs_size; -+ -+/* Define the union u_od_pic_osd_worst_row */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_frm_row_len : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_worst_row; -+ -+/* Define the union u_od_pic_osd_best_row */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int min_frm_row_len : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_best_row; -+ -+/* Define the union u_od_pic_osd_stat_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int max_gap_bw_row_len_cnt : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_od_pic_osd_stat_info; -+ -+/* Define the union u_v0_mrg_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ -+ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ -+ unsigned int reserved_0 : 12; /* [19..8] */ -+ unsigned int mrg_edge_en : 1; /* [20] */ -+ unsigned int reserved_1 : 4; /* [24..21] */ -+ unsigned int mrg_edge_typ : 1; /* [25] */ -+ unsigned int reserved_2 : 2; /* [27..26] */ -+ unsigned int mrg_crop_en : 1; /* [28] */ -+ unsigned int mrg_dcmp_en : 1; /* [29] */ -+ unsigned int mrg_mute_en : 1; /* [30] */ -+ unsigned int mrg_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_ctrl; -+ -+/* Define the union u_v0_mrg_disp_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_xpos : 16; /* [15..0] */ -+ unsigned int mrg_ypos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_disp_pos; -+ -+/* Define the union u_v0_mrg_disp_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_width : 16; /* [15..0] */ -+ unsigned int mrg_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_disp_reso; -+ -+/* Define the union u_v0_mrg_src_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_src_width : 16; /* [15..0] */ -+ unsigned int mrg_src_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_src_reso; -+ -+/* Define the union u_v0_mrg_src_offset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_src_hoffset : 16; /* [15..0] */ -+ unsigned int mrg_src_voffset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_src_offset; -+ -+/* Define the union u_v0_mrg_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_c_stride : 16; /* [15..0] */ -+ unsigned int mrg_y_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_stride; -+ -+/* Define the union u_v0_mrg_hstride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_ch_stride : 16; /* [15..0] */ -+ unsigned int mrg_yh_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_hstride; -+ -+/* Define the union u_v0_mrg_read_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rd_region : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_read_ctrl; -+ -+/* Define the union u_v0_mrg_read_en */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_mrg_read_en; -+ -+/* Define the union u_v1_mrg_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ -+ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ -+ unsigned int reserved_0 : 12; /* [19..8] */ -+ unsigned int mrg_edge_en : 1; /* [20] */ -+ unsigned int reserved_1 : 4; /* [24..21] */ -+ unsigned int mrg_edge_typ : 1; /* [25] */ -+ unsigned int reserved_2 : 2; /* [27..26] */ -+ unsigned int mrg_crop_en : 1; /* [28] */ -+ unsigned int mrg_dcmp_en : 1; /* [29] */ -+ unsigned int mrg_mute_en : 1; /* [30] */ -+ unsigned int mrg_en : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_ctrl; -+ -+/* Define the union u_v1_mrg_disp_pos */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_xpos : 16; /* [15..0] */ -+ unsigned int mrg_ypos : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_disp_pos; -+ -+/* Define the union u_v1_mrg_disp_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_width : 16; /* [15..0] */ -+ unsigned int mrg_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_disp_reso; -+ -+/* Define the union u_v1_mrg_src_reso */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_src_width : 16; /* [15..0] */ -+ unsigned int mrg_src_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_src_reso; -+ -+/* Define the union u_v1_mrg_src_offset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_src_hoffset : 16; /* [15..0] */ -+ unsigned int mrg_src_voffset : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_src_offset; -+ -+/* Define the union u_v1_mrg_stride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_c_stride : 16; /* [15..0] */ -+ unsigned int mrg_y_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_stride; -+ -+/* Define the union u_v1_mrg_hstride */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int mrg_ch_stride : 16; /* [15..0] */ -+ unsigned int mrg_yh_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_hstride; -+ -+/* Define the union u_v1_mrg_read_ctrl */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rd_region : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_read_ctrl; -+ -+/* Define the union u_v1_mrg_read_en */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_mrg_read_en; -+ -+/* define the union reg_osb_ctrl1_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mode_0 : 2; /* [1..0] */ -+ unsigned int thick_w_0 : 6; /* [7..2] */ -+ unsigned int arm_w_0 : 8; /* [15..8] */ -+ unsigned int edge_v_0 : 4; /* [19..16] */ -+ unsigned int edge_reg_0 : 4; /* [23..20] */ -+ unsigned int edge_y_0 : 4; /* [27..24] */ -+ unsigned int edge_alpha_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_osb_ctrl1_box_0; -+ -+/* define the union reg_osb_ctrl2_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int hend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_osb_ctrl2_box_0; -+ -+/* define the union reg_osb_ctrl3_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int vend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} u_osb_ctrl3_box_0; -+ -+/* Define the union u_v1_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_idc; -+ -+/* Define the union u_v1_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_odc; -+ -+/* Define the union u_v1_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_iodc; -+ -+/* Define the union u_v1_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_p0; -+ -+/* Define the union u_v1_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_p1; -+ -+/* Define the union u_v1_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_p2; -+ -+/* Define the union u_v1_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_p3; -+ -+/* Define the union u_v1_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc_p4; -+ -+/* Define the union u_v1_csc1_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_idc; -+ -+/* Define the union u_v1_csc1_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_odc; -+ -+/* Define the union u_v1_csc1_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_iodc; -+ -+/* Define the union u_v1_csc1_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_p0; -+ -+/* Define the union u_v1_csc1_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_p1; -+ -+/* Define the union u_v1_csc1_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_p2; -+ -+/* Define the union u_v1_csc1_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_p3; -+ -+/* Define the union u_v1_csc1_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v1_csc1_p4; -+ -+/* Define the union u_v2_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_idc; -+ -+/* Define the union u_v2_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_odc; -+ -+/* Define the union u_v2_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_iodc; -+ -+/* Define the union u_v2_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_p0; -+ -+/* Define the union u_v2_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_p1; -+ -+/* Define the union u_v2_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_p2; -+ -+/* Define the union u_v2_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_p3; -+ -+/* Define the union u_v2_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc_p4; -+ -+/* Define the union u_v2_csc1_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_idc; -+ -+/* Define the union u_v2_csc1_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_odc; -+ -+/* Define the union u_v2_csc1_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_iodc; -+ -+/* Define the union u_v2_csc1_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_p0; -+ -+/* Define the union u_v2_csc1_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_p1; -+ -+/* Define the union u_v2_csc1_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_p2; -+ -+/* Define the union u_v2_csc1_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_p3; -+ -+/* Define the union u_v2_csc1_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v2_csc1_p4; -+ -+/* Define the union u_g1_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_idc; -+ -+/* Define the union u_g1_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_odc; -+ -+/* Define the union u_g1_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_iodc; -+ -+/* Define the union u_g1_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_p0; -+ -+/* Define the union u_g1_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_p1; -+ -+/* Define the union u_g1_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_p2; -+ -+/* Define the union u_g1_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_p3; -+ -+/* Define the union u_g1_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc_p4; -+ -+/* Define the union u_g1_csc1_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_idc; -+ -+/* Define the union u_g1_csc1_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_odc; -+ -+/* Define the union u_g1_csc1_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_iodc; -+ -+/* Define the union u_g1_csc1_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_p0; -+ -+/* Define the union u_g1_csc1_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_p1; -+ -+/* Define the union u_g1_csc1_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_p2; -+ -+/* Define the union u_g1_csc1_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_p3; -+ -+/* Define the union u_g1_csc1_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g1_csc1_p4; -+ -+/* Define the union u_g3_csc_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_idc; -+ -+/* Define the union u_g3_csc_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_odc; -+ -+/* Define the union u_g3_csc_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_iodc; -+ -+/* Define the union u_g3_csc_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_p0; -+ -+/* Define the union u_g3_csc_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_p1; -+ -+/* Define the union u_g3_csc_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_p2; -+ -+/* Define the union u_g3_csc_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_p3; -+ -+/* Define the union u_g3_csc_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc_p4; -+ -+/* Define the union u_g3_csc1_idc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_idc; -+ -+/* Define the union u_g3_csc1_odc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_odc; -+ -+/* Define the union u_g3_csc1_iodc */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_iodc; -+ -+/* Define the union u_g3_csc1_p0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_p0; -+ -+/* Define the union u_g3_csc1_p1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_p1; -+ -+/* Define the union u_g3_csc1_p2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_p2; -+ -+/* Define the union u_g3_csc1_p3 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_p3; -+ -+/* Define the union u_g3_csc1_p4 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_g3_csc1_p4; -+ -+/* Define the union u_v0_cvfir_vinfo */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_vinfo; -+ -+/* Define the union u_v0_cvfir_vsp */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_vsp; -+ -+/* Define the union u_v0_cvfir_voffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_voffset; -+ -+/* Define the union u_v0_cvfir_vboffset */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_vboffset; -+ -+/* Define the union u_v0_cvfir_vcoef0 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_vcoef0; -+ -+/* Define the union u_v0_cvfir_vcoef1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_vcoef1; -+ -+/* Define the union u_v0_cvfir_vcoef2 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_v0_cvfir_vcoef2; -+ -+/* Define the union u_gfx_osd_glb_info */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int dcmp_en : 1; /* [0] */ -+ unsigned int is_lossless : 1; /* [1] */ -+ unsigned int is_lossless_a : 1; /* [2] */ -+ unsigned int cmp_mode : 1; /* [3] */ -+ unsigned int source_mode : 3; /* [6..4] */ -+ unsigned int tpred_en : 1; /* [7] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_osd_glb_info; -+ -+/* Define the union u_gfx_osd_frame_size */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int frame_width : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int frame_height : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_osd_frame_size; -+ -+/* Define the union u_gfx_osd_dbg_reg */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 30; /* [29..0] */ -+ unsigned int dcmp_err0 : 1; /* [30] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_osd_dbg_reg; -+ -+/* Define the union u_gfx_osd_dbg_reg1 */ -+typedef union { -+ /* Define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 30; /* [29..0] */ -+ unsigned int dcmp_err1 : 1; /* [30] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* Define an unsigned member */ -+ unsigned int u32; -+} u_gfx_osd_dbg_reg1; -+ -+/* Define the global struct */ -+typedef struct { -+ volatile u_voctrl voctrl; /* 0x0 */ -+ volatile u_vointsta vointsta; /* 0x4 */ -+ volatile u_vomskintsta vomskintsta; /* 0x8 */ -+ volatile u_vointmsk vointmsk; /* 0xc */ -+ volatile u_vodebug vodebug; /* 0x10 */ -+ volatile u_vointsta1 vointsta1; /* 0x14 */ -+ volatile u_vomskintsta1 vomskintsta1; /* 0x18 */ -+ volatile u_vointmsk1 vointmsk1; /* 0x1c */ -+ volatile unsigned int vdpversion1; /* 0x20 */ -+ volatile unsigned int vdpversion2; /* 0x24 */ -+ volatile u_volowpower_ctrl volowpower_ctrl; /* 0x28 */ -+ volatile u_voufsta voufsta; /* 0x2c */ -+ volatile u_voufclr voufclr; /* 0x30 */ -+ volatile u_vointproc_tim vointproc_tim; /* 0x34 */ -+ volatile unsigned int vofpgatest; /* 0x38 */ -+ volatile unsigned int reserved_0[3]; /* 0x3c~0x44 */ -+ volatile u_volowpower_ctrl1 volowpower_ctrl1; /* 0x48 */ -+ volatile u_vofpgadef vofpgadef; /* 0x4c */ -+ volatile u_volowpower_ctrl2 volowpower_ctrl2; /* 0x50 */ -+ volatile u_volowpower_ctrl3 volowpower_ctrl3; /* 0x54 */ -+ volatile unsigned int reserved_1[43]; /* 43:0x58~0x100 */ -+ volatile u_vomux_dac vomux_dac; /* 0x104 */ -+ volatile u_vomux_testsync vomux_testsync; /* 0x108 */ -+ volatile u_vomux_testdata vomux_testdata; /* 0x10c */ -+ volatile unsigned int reserved_2[4]; /* 4:0x110~0x11c */ -+ volatile u_vo_dac_ctrl vo_dac_ctrl; /* 0x120 */ -+ volatile u_vo_dac_otp vo_dac_otp; /* 0x124 */ -+ volatile unsigned int reserved_3[2]; /* 2:0x128~0x12c */ -+ volatile u_vo_dac0_ctrl vo_dac0_ctrl; /* 0x130 */ -+ volatile u_vo_dac1_ctrl vo_dac1_ctrl; /* 0x134 */ -+ volatile u_vo_dac2_ctrl vo_dac2_ctrl; /* 0x138 */ -+ volatile u_vo_dac3_ctrl vo_dac3_ctrl; /* 0x13c */ -+ volatile u_vo_dac_stat0 vo_dac_stat0; /* 0x140 */ -+ volatile unsigned int reserved_4[111]; /* 111:0x144~0x2fc */ -+ volatile u_cbm_bkg1 cbm_bkg1; /* 0x300 */ -+ volatile unsigned int reserved_5; /* 0x304 */ -+ volatile u_cbm_mix1 cbm_mix1; /* 0x308 */ -+ volatile unsigned int reserved_6[14]; /* 14:0x30c~0x340 */ -+ volatile u_wbc_bmp_thd wbc_bmp_thd; /* 0x344 */ -+ volatile unsigned int reserved_7[2]; /* 2:0x348~0x34c */ -+ volatile unsigned int cbm1_lay0_debug; /* 0x350 */ -+ volatile unsigned int cbm1_lay1_debug; /* 0x354 */ -+ volatile unsigned int cbm1_lay2_debug; /* 0x358 */ -+ volatile unsigned int cbm1_lay3_debug; /* 0x35c */ -+ volatile unsigned int cbm1_lay4_debug; /* 0x360 */ -+ volatile unsigned int cbm1_lay0_last_debug; /* 0x364 */ -+ volatile unsigned int cbm1_lay1_last_debug; /* 0x368 */ -+ volatile unsigned int cbm1_lay2_last_debug; /* 0x36c */ -+ volatile unsigned int cbm1_lay3_last_debug; /* 0x370 */ -+ volatile unsigned int cbm1_lay4_last_debug; /* 0x374 */ -+ volatile unsigned int reserved_8[2]; /* 2:0x378~0x37c */ -+ volatile u_cbm_bkg2 cbm_bkg2; /* 0x380 */ -+ volatile unsigned int reserved_9; /* 0x384 */ -+ volatile u_cbm_mix2 cbm_mix2; /* 0x388 */ -+ volatile unsigned int reserved_10[14]; /* 14:0x38c~0x3c0 */ -+ volatile u_hc_bmp_thd hc_bmp_thd; /* 0x3c4 */ -+ volatile unsigned int reserved_11[2]; /* 2:0x3c8~0x3cc */ -+ volatile unsigned int cbm2_lay0_debug; /* 0x3d0 */ -+ volatile unsigned int cbm2_lay1_debug; /* 0x3d4 */ -+ volatile unsigned int cbm2_lay2_debug; /* 0x3d8 */ -+ volatile unsigned int cbm2_lay3_debug; /* 0x3dc */ -+ volatile unsigned int cbm2_lay4_debug; /* 0x3e0 */ -+ volatile unsigned int cbm2_lay0_last_debug; /* 0x3e4 */ -+ volatile unsigned int cbm2_lay1_last_debug; /* 0x3e8 */ -+ volatile unsigned int cbm2_lay2_last_debug; /* 0x3ec */ -+ volatile unsigned int cbm2_lay3_last_debug; /* 0x3f0 */ -+ volatile unsigned int cbm2_lay4_last_debug; /* 0x3f4 */ -+ volatile unsigned int reserved_12[2]; /* 2:0x3f8~0x3fc */ -+ volatile u_cbm_bkg3 cbm_bkg3; /* 0x400 */ -+ volatile unsigned int reserved_13; /* 0x404 */ -+ volatile u_cbm_mix3 cbm_mix3; /* 0x408 */ -+ volatile unsigned int reserved_14[17]; /* 17:0x40c~0x44c */ -+ volatile unsigned int cbm3_lay0_debug; /* 0x450 */ -+ volatile unsigned int cbm3_lay1_debug; /* 0x454 */ -+ volatile unsigned int cbm3_lay2_debug; /* 0x458 */ -+ volatile unsigned int cbm3_lay3_debug; /* 0x45c */ -+ volatile unsigned int cbm3_lay4_debug; /* 0x460 */ -+ volatile unsigned int cbm3_lay0_last_debug; /* 0x464 */ -+ volatile unsigned int cbm3_lay1_last_debug; /* 0x468 */ -+ volatile unsigned int cbm3_lay2_last_debug; /* 0x46c */ -+ volatile unsigned int cbm3_lay3_last_debug; /* 0x470 */ -+ volatile unsigned int cbm3_lay4_last_debug; /* 0x474 */ -+ volatile unsigned int reserved_15[98]; /* 98:0x478~0x5fc */ -+ volatile u_mixv0_bkg mixv0_bkg; /* 0x600 */ -+ volatile unsigned int reserved_16; /* 0x604 */ -+ volatile u_mixv0_mix mixv0_mix; /* 0x608 */ -+ volatile unsigned int reserved_17[189]; /* 189:0x60c~0x8fc */ -+ volatile u_mixg0_bkg mixg0_bkg; /* 0x900 */ -+ volatile u_mixg0_bkalpha mixg0_bkalpha; /* 0x904 */ -+ volatile u_mixg0_mix mixg0_mix; /* 0x908 */ -+ volatile unsigned int reserved_18[189]; /* 189:0x90c~0xbfc */ -+ volatile u_link_ctrl link_ctrl; /* 0xc00 */ -+ volatile unsigned int reserved_19[63]; /* 63:0xc04~0xcfc */ -+ volatile u_vpss_ctrl vpss_ctrl; /* 0xd00 */ -+ volatile u_vpss_miscellaneous vpss_miscellaneous; /* 0xd04 */ -+ volatile u_vpss_ftconfig vpss_ftconfig; /* 0xd08 */ -+ volatile unsigned int reserved_20[5]; /* 5:0xd0c~0xd1c */ -+ volatile unsigned int vpss_version; /* 0xd20 */ -+ volatile unsigned int vpss_debug0; /* 0xd24 */ -+ volatile unsigned int vpss_debug1; /* 0xd28 */ -+ volatile unsigned int vpss_debug2; /* 0xd2c */ -+ volatile unsigned int vpss_debug3; /* 0xd30 */ -+ volatile unsigned int vpss_debug4; /* 0xd34 */ -+ volatile unsigned int vpss_debug5; /* 0xd38 */ -+ volatile unsigned int vpss_debug6; /* 0xd3c */ -+ volatile unsigned int reserved_21[48]; /* 48:0xd40~0xdfc */ -+ volatile unsigned int para_haddr_vhd_chn00; /* 0xe00 */ -+ volatile unsigned int para_addr_vhd_chn00; /* 0xe04 */ -+ volatile unsigned int para_haddr_vhd_chn01; /* 0xe08 */ -+ volatile unsigned int para_addr_vhd_chn01; /* 0xe0c */ -+ volatile unsigned int para_haddr_vhd_chn02; /* 0xe10 */ -+ volatile unsigned int para_addr_vhd_chn02; /* 0xe14 */ -+ volatile unsigned int para_haddr_vhd_chn03; /* 0xe18 */ -+ volatile unsigned int para_addr_vhd_chn03; /* 0xe1c */ -+ volatile unsigned int para_haddr_vhd_chn04; /* 0xe20 */ -+ volatile unsigned int para_addr_vhd_chn04; /* 0xe24 */ -+ volatile unsigned int para_haddr_vhd_chn05; /* 0xe28 */ -+ volatile unsigned int para_addr_vhd_chn05; /* 0xe2c */ -+ volatile unsigned int para_haddr_vhd_chn06; /* 0xe30 */ -+ volatile unsigned int para_addr_vhd_chn06; /* 0xe34 */ -+ volatile unsigned int para_haddr_vhd_chn07; /* 0xe38 */ -+ volatile unsigned int para_addr_vhd_chn07; /* 0xe3c */ -+ volatile unsigned int para_haddr_vhd_chn08; /* 0xe40 */ -+ volatile unsigned int para_addr_vhd_chn08; /* 0xe44 */ -+ volatile unsigned int para_haddr_vhd_chn09; /* 0xe48 */ -+ volatile unsigned int para_addr_vhd_chn09; /* 0xe4c */ -+ volatile unsigned int para_haddr_vhd_chn10; /* 0xe50 */ -+ volatile unsigned int para_addr_vhd_chn10; /* 0xe54 */ -+ volatile unsigned int para_haddr_vhd_chn11; /* 0xe58 */ -+ volatile unsigned int para_addr_vhd_chn11; /* 0xe5c */ -+ volatile unsigned int para_haddr_vhd_chn12; /* 0xe60 */ -+ volatile unsigned int para_addr_vhd_chn12; /* 0xe64 */ -+ volatile unsigned int para_haddr_vhd_chn13; /* 0xe68 */ -+ volatile unsigned int para_addr_vhd_chn13; /* 0xe6c */ -+ volatile unsigned int para_haddr_vhd_chn14; /* 0xe70 */ -+ volatile unsigned int para_addr_vhd_chn14; /* 0xe74 */ -+ volatile unsigned int para_haddr_vhd_chn15; /* 0xe78 */ -+ volatile unsigned int para_addr_vhd_chn15; /* 0xe7c */ -+ volatile unsigned int para_haddr_vhd_chn16; /* 0xe80 */ -+ volatile unsigned int para_addr_vhd_chn16; /* 0xe84 */ -+ volatile unsigned int para_haddr_vhd_chn17; /* 0xe88 */ -+ volatile unsigned int para_addr_vhd_chn17; /* 0xe8c */ -+ volatile unsigned int para_haddr_vhd_chn18; /* 0xe90 */ -+ volatile unsigned int para_addr_vhd_chn18; /* 0xe94 */ -+ volatile unsigned int para_haddr_vhd_chn19; /* 0xe98 */ -+ volatile unsigned int para_addr_vhd_chn19; /* 0xe9c */ -+ volatile unsigned int para_haddr_vhd_chn20; /* 0xea0 */ -+ volatile unsigned int para_addr_vhd_chn20; /* 0xea4 */ -+ volatile unsigned int para_haddr_vhd_chn21; /* 0xea8 */ -+ volatile unsigned int para_addr_vhd_chn21; /* 0xeac */ -+ volatile unsigned int para_haddr_vhd_chn22; /* 0xeb0 */ -+ volatile unsigned int para_addr_vhd_chn22; /* 0xeb4 */ -+ volatile unsigned int para_haddr_vhd_chn23; /* 0xeb8 */ -+ volatile unsigned int para_addr_vhd_chn23; /* 0xebc */ -+ volatile unsigned int para_haddr_vhd_chn24; /* 0xec0 */ -+ volatile unsigned int para_addr_vhd_chn24; /* 0xec4 */ -+ volatile unsigned int para_haddr_vhd_chn25; /* 0xec8 */ -+ volatile unsigned int para_addr_vhd_chn25; /* 0xecc */ -+ volatile unsigned int para_haddr_vhd_chn26; /* 0xed0 */ -+ volatile unsigned int para_addr_vhd_chn26; /* 0xed4 */ -+ volatile unsigned int para_haddr_vhd_chn27; /* 0xed8 */ -+ volatile unsigned int para_addr_vhd_chn27; /* 0xedc */ -+ volatile unsigned int para_haddr_vhd_chn28; /* 0xee0 */ -+ volatile unsigned int para_addr_vhd_chn28; /* 0xee4 */ -+ volatile unsigned int para_haddr_vhd_chn29; /* 0xee8 */ -+ volatile unsigned int para_addr_vhd_chn29; /* 0xeec */ -+ volatile unsigned int para_haddr_vhd_chn30; /* 0xef0 */ -+ volatile unsigned int para_addr_vhd_chn30; /* 0xef4 */ -+ volatile unsigned int para_haddr_vhd_chn31; /* 0xef8 */ -+ volatile unsigned int para_addr_vhd_chn31; /* 0xefc */ -+ volatile u_para_up_vhd para_up_vhd; /* 0xf00 */ -+ volatile unsigned int para_haddr_vsd_chn00; /* 0xf04 */ -+ volatile unsigned int para_addr_vsd_chn00; /* 0xf08 */ -+ volatile unsigned int para_haddr_vsd_chn01; /* 0xf0c */ -+ volatile unsigned int para_addr_vsd_chn01; /* 0xf10 */ -+ volatile unsigned int para_haddr_vsd_chn02; /* 0xf14 */ -+ volatile unsigned int para_addr_vsd_chn02; /* 0xf18 */ -+ volatile unsigned int para_haddr_vsd_chn03; /* 0xf1c */ -+ volatile unsigned int para_addr_vsd_chn03; /* 0xf20 */ -+ volatile unsigned int para_haddr_vsd_chn04; /* 0xf24 */ -+ volatile unsigned int para_addr_vsd_chn04; /* 0xf28 */ -+ volatile unsigned int para_haddr_vsd_chn05; /* 0xf2c */ -+ volatile unsigned int para_addr_vsd_chn05; /* 0xf30 */ -+ volatile unsigned int para_haddr_vsd_chn06; /* 0xf34 */ -+ volatile unsigned int para_addr_vsd_chn06; /* 0xf38 */ -+ volatile unsigned int para_haddr_vsd_chn07; /* 0xf3c */ -+ volatile unsigned int para_addr_vsd_chn07; /* 0xf40 */ -+ volatile u_para_up_vsd para_up_vsd; /* 0xf44 */ -+ volatile u_para_conflict_clr para_conflict_clr; /* 0xf48 */ -+ volatile u_para_conflict_sta para_conflict_sta; /* 0xf4c */ -+ volatile unsigned int reserved_22[44]; /* 44:0xf50~0xffc */ -+ volatile u_v0_ctrl v0_ctrl; /* 0x1000 */ -+ volatile u_v0_upd v0_upd; /* 0x1004 */ -+ volatile u_v0_0reso_read v0_0reso_read; /* 0x1008 */ -+ volatile unsigned int reserved_23; /* 0x100c */ -+ volatile u_v0_ireso v0_ireso; /* 0x1010 */ -+ volatile unsigned int reserved_24[27]; /* 27:0x1014~0x107c */ -+ volatile u_v0_dfpos v0_dfpos; /* 0x1080 */ -+ volatile u_v0_dlpos v0_dlpos; /* 0x1084 */ -+ volatile u_v0_vfpos v0_vfpos; /* 0x1088 */ -+ volatile u_v0_vlpos v0_vlpos; /* 0x108c */ -+ volatile u_v0_bk v0_bk; /* 0x1090 */ -+ volatile u_v0_alpha v0_alpha; /* 0x1094 */ -+ volatile u_v0_mute_bk v0_mute_bk; /* 0x1098 */ -+ volatile unsigned int reserved_25; /* 0x109c */ -+ volatile u_v0_rimwidth v0_rimwidth; /* 0x10a0 */ -+ volatile u_v0_rimcol0 v0_rimcol0; /* 0x10a4 */ -+ volatile u_v0_rimcol1 v0_rimcol1; /* 0x10a8 */ -+ volatile unsigned int reserved_26[85]; /* 85:0x10ac~0x11fc */ -+ volatile u_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; /* 0x1200 */ -+ volatile u_v0_ot_pp_csc_coef00 v0_ot_pp_csc_coef00; /* 0x1204 */ -+ volatile u_v0_ot_pp_csc_coef01 v0_ot_pp_csc_coef01; /* 0x1208 */ -+ volatile u_v0_ot_pp_csc_coef02 v0_ot_pp_csc_coef02; /* 0x120c */ -+ volatile u_v0_ot_pp_csc_coef10 v0_ot_pp_csc_coef10; /* 0x1210 */ -+ volatile u_v0_ot_pp_csc_coef11 v0_ot_pp_csc_coef11; /* 0x1214 */ -+ volatile u_v0_ot_pp_csc_coef12 v0_ot_pp_csc_coef12; /* 0x1218 */ -+ volatile u_v0_ot_pp_csc_coef20 v0_ot_pp_csc_coef20; /* 0x121c */ -+ volatile u_v0_ot_pp_csc_coef21 v0_ot_pp_csc_coef21; /* 0x1220 */ -+ volatile u_v0_ot_pp_csc_coef22 v0_ot_pp_csc_coef22; /* 0x1224 */ -+ volatile u_v0_ot_pp_csc_scale v0_ot_pp_csc_scale; /* 0x1228 */ -+ volatile u_v0_ot_pp_csc_idc0 v0_ot_pp_csc_idc0; /* 0x122c */ -+ volatile u_v0_ot_pp_csc_idc1 v0_ot_pp_csc_idc1; /* 0x1230 */ -+ volatile u_v0_ot_pp_csc_idc2 v0_ot_pp_csc_idc2; /* 0x1234 */ -+ volatile u_v0_ot_pp_csc_odc0 v0_ot_pp_csc_odc0; /* 0x1238 */ -+ volatile u_v0_ot_pp_csc_odc1 v0_ot_pp_csc_odc1; /* 0x123c */ -+ volatile u_v0_ot_pp_csc_odc2 v0_ot_pp_csc_odc2; /* 0x1240 */ -+ volatile u_v0_ot_pp_csc_min_y v0_ot_pp_csc_min_y; /* 0x1244 */ -+ volatile u_v0_ot_pp_csc_min_c v0_ot_pp_csc_min_c; /* 0x1248 */ -+ volatile u_v0_ot_pp_csc_max_y v0_ot_pp_csc_max_y; /* 0x124c */ -+ volatile u_v0_ot_pp_csc_max_c v0_ot_pp_csc_max_c; /* 0x1250 */ -+ volatile u_v0_ot_pp_csc2_coef00 v0_ot_pp_csc2_coef00; /* 0x1254 */ -+ volatile u_v0_ot_pp_csc2_coef01 v0_ot_pp_csc2_coef01; /* 0x1258 */ -+ volatile u_v0_ot_pp_csc2_coef02 v0_ot_pp_csc2_coef02; /* 0x125c */ -+ volatile u_v0_ot_pp_csc2_coef10 v0_ot_pp_csc2_coef10; /* 0x1260 */ -+ volatile u_v0_ot_pp_csc2_coef11 v0_ot_pp_csc2_coef11; /* 0x1264 */ -+ volatile u_v0_ot_pp_csc2_coef12 v0_ot_pp_csc2_coef12; /* 0x1268 */ -+ volatile u_v0_ot_pp_csc2_coef20 v0_ot_pp_csc2_coef20; /* 0x126c */ -+ volatile u_v0_ot_pp_csc2_coef21 v0_ot_pp_csc2_coef21; /* 0x1270 */ -+ volatile u_v0_ot_pp_csc2_coef22 v0_ot_pp_csc2_coef22; /* 0x1274 */ -+ volatile u_v0_ot_pp_csc2_scale v0_ot_pp_csc2_scale; /* 0x1278 */ -+ volatile u_v0_ot_pp_csc2_idc0 v0_ot_pp_csc2_idc0; /* 0x127c */ -+ volatile u_v0_ot_pp_csc2_idc1 v0_ot_pp_csc2_idc1; /* 0x1280 */ -+ volatile u_v0_ot_pp_csc2_idc2 v0_ot_pp_csc2_idc2; /* 0x1284 */ -+ volatile u_v0_ot_pp_csc2_odc0 v0_ot_pp_csc2_odc0; /* 0x1288 */ -+ volatile u_v0_ot_pp_csc2_odc1 v0_ot_pp_csc2_odc1; /* 0x128c */ -+ volatile u_v0_ot_pp_csc2_odc2 v0_ot_pp_csc2_odc2; /* 0x1290 */ -+ volatile u_v0_ot_pp_csc2_min_y v0_ot_pp_csc2_min_y; /* 0x1294 */ -+ volatile u_v0_ot_pp_csc2_min_c v0_ot_pp_csc2_min_c; /* 0x1298 */ -+ volatile u_v0_ot_pp_csc2_max_y v0_ot_pp_csc2_max_y; /* 0x129c */ -+ volatile u_v0_ot_pp_csc2_max_c v0_ot_pp_csc2_max_c; /* 0x12a0 */ -+ volatile unsigned int reserved_27[19]; /* 19:0x12a4~0x12ec */ -+ volatile u_v0_ot_pp_csc_ink_ctrl v0_ot_pp_csc_ink_ctrl; /* 0x12f0 */ -+ volatile u_v0_ot_pp_csc_ink_pos v0_ot_pp_csc_ink_pos; /* 0x12f4 */ -+ volatile unsigned int v0_ot_pp_csc_ink_data; /* 0x12f8 */ -+ volatile unsigned int v0_ot_pp_csc_ink_data2; /* 0x12fc */ -+ volatile u_v0_zme_hinfo v0_zme_hinfo; /* 0x1300 */ -+ volatile u_v0_zme_hsp v0_zme_hsp; /* 0x1304 */ -+ volatile u_v0_zme_hloffset v0_zme_hloffset; /* 0x1308 */ -+ volatile u_v0_zme_hcoffset v0_zme_hcoffset; /* 0x130c */ -+ volatile u_v0_zme_hzone0delta v0_zme_hzone0delta; /* 0x1310 */ -+ volatile u_v0_zme_hzone2delta v0_zme_hzone2delta; /* 0x1314 */ -+ volatile u_v0_zme_hzoneend v0_zme_hzoneend; /* 0x1318 */ -+ volatile u_v0_zme_hl_shootctrl v0_zme_hl_shootctrl; /* 0x131c */ -+ volatile u_v0_zme_hc_shootctrl v0_zme_hc_shootctrl; /* 0x1320 */ -+ volatile u_v0_zme_hcoef_ren v0_zme_hcoef_ren; /* 0x1324 */ -+ volatile u_v0_zme_hcoef_rdata v0_zme_hcoef_rdata; /* 0x1328 */ -+ volatile unsigned int reserved_28[53]; /* 53:0x132c~0x13fc */ -+ volatile u_v0_zme_vinfo v0_zme_vinfo; /* 0x1400 */ -+ volatile u_v0_zme_vsp v0_zme_vsp; /* 0x1404 */ -+ volatile u_v0_zme_voffset v0_zme_voffset; /* 0x1408 */ -+ volatile u_v0_zme_vboffset v0_zme_vboffset; /* 0x140c */ -+ volatile unsigned int reserved_29[3]; /* 3:0x1410~0x1418 */ -+ volatile u_v0_zme_vl_shootctrl v0_zme_vl_shootctrl; /* 0x141c */ -+ volatile u_v0_zme_vc_shootctrl v0_zme_vc_shootctrl; /* 0x1420 */ -+ volatile u_v0_zme_vcoef_ren v0_zme_vcoef_ren; /* 0x1424 */ -+ volatile u_v0_zme_vcoef_rdata v0_zme_vcoef_rdata; /* 0x1428 */ -+ volatile unsigned int reserved_30[53]; /* 53:0x142c~0x14fc */ -+ volatile u_v0_hfir_ctrl v0_hfir_ctrl; /* 0x1500 */ -+ volatile u_v0_hfircoef01 v0_hfircoef01; /* 0x1504 */ -+ volatile u_v0_hfircoef23 v0_hfircoef23; /* 0x1508 */ -+ volatile u_v0_hfircoef45 v0_hfircoef45; /* 0x150c */ -+ volatile u_v0_hfircoef67 v0_hfircoef67; /* 0x1510 */ -+ volatile unsigned int reserved_31[699]; /* 699:0x1514~0x1ffc */ -+ volatile u_v1_ctrl v1_ctrl; /* 0x2000 */ -+ volatile u_v1_upd v1_upd; /* 0x2004 */ -+ volatile u_v1_0reso_read v1_0reso_read; /* 0x2008 */ -+ volatile unsigned int reserved_32; /* 0x200c */ -+ volatile u_v1_ireso v1_ireso; /* 0x2010 */ -+ volatile unsigned int reserved_33[27]; /* 27:0x2014~0x207c */ -+ volatile u_v1_dfpos v1_dfpos; /* 0x2080 */ -+ volatile u_v1_dlpos v1_dlpos; /* 0x2084 */ -+ volatile u_v1_vfpos v1_vfpos; /* 0x2088 */ -+ volatile u_v1_vlpos v1_vlpos; /* 0x208c */ -+ volatile u_v1_bk v1_bk; /* 0x2090 */ -+ volatile u_v1_alpha v1_alpha; /* 0x2094 */ -+ volatile u_v1_mute_bk v1_mute_bk; /* 0x2098 */ -+ volatile unsigned int reserved_34; /* 0x209c */ -+ volatile u_v1_rimwidth v1_rimwidth; /* 0x20a0 */ -+ volatile u_v1_rimcol0 v1_rimcol0; /* 0x20a4 */ -+ volatile u_v1_rimcol1 v1_rimcol1; /* 0x20a8 */ -+ volatile unsigned int reserved_35[85]; /* 85:0x20ac~0x21fc */ -+ volatile u_v1_ot_pp_csc_ctrl v1_ot_pp_csc_ctrl; /* 0x2200 */ -+ volatile u_v1_ot_pp_csc_coef00 v1_ot_pp_csc_coef00; /* 0x2204 */ -+ volatile u_v1_ot_pp_csc_coef01 v1_ot_pp_csc_coef01; /* 0x2208 */ -+ volatile u_v1_ot_pp_csc_coef02 v1_ot_pp_csc_coef02; /* 0x220c */ -+ volatile u_v1_ot_pp_csc_coef10 v1_ot_pp_csc_coef10; /* 0x2210 */ -+ volatile u_v1_ot_pp_csc_coef11 v1_ot_pp_csc_coef11; /* 0x2214 */ -+ volatile u_v1_ot_pp_csc_coef12 v1_ot_pp_csc_coef12; /* 0x2218 */ -+ volatile u_v1_ot_pp_csc_coef20 v1_ot_pp_csc_coef20; /* 0x221c */ -+ volatile u_v1_ot_pp_csc_coef21 v1_ot_pp_csc_coef21; /* 0x2220 */ -+ volatile u_v1_ot_pp_csc_coef22 v1_ot_pp_csc_coef22; /* 0x2224 */ -+ volatile u_v1_ot_pp_csc_scale v1_ot_pp_csc_scale; /* 0x2228 */ -+ volatile u_v1_ot_pp_csc_idc0 v1_ot_pp_csc_idc0; /* 0x222c */ -+ volatile u_v1_ot_pp_csc_idc1 v1_ot_pp_csc_idc1; /* 0x2230 */ -+ volatile u_v1_ot_pp_csc_idc2 v1_ot_pp_csc_idc2; /* 0x2234 */ -+ volatile u_v1_ot_pp_csc_odc0 v1_ot_pp_csc_odc0; /* 0x2238 */ -+ volatile u_v1_ot_pp_csc_odc1 v1_ot_pp_csc_odc1; /* 0x223c */ -+ volatile u_v1_ot_pp_csc_odc2 v1_ot_pp_csc_odc2; /* 0x2240 */ -+ volatile u_v1_ot_pp_csc_min_y v1_ot_pp_csc_min_y; /* 0x2244 */ -+ volatile u_v1_ot_pp_csc_min_c v1_ot_pp_csc_min_c; /* 0x2248 */ -+ volatile u_v1_ot_pp_csc_max_y v1_ot_pp_csc_max_y; /* 0x224c */ -+ volatile u_v1_ot_pp_csc_max_c v1_ot_pp_csc_max_c; /* 0x2250 */ -+ volatile u_v1_ot_pp_csc2_coef00 v1_ot_pp_csc2_coef00; /* 0x2254 */ -+ volatile u_v1_ot_pp_csc2_coef01 v1_ot_pp_csc2_coef01; /* 0x2258 */ -+ volatile u_v1_ot_pp_csc2_coef02 v1_ot_pp_csc2_coef02; /* 0x225c */ -+ volatile u_v1_ot_pp_csc2_coef10 v1_ot_pp_csc2_coef10; /* 0x2260 */ -+ volatile u_v1_ot_pp_csc2_coef11 v1_ot_pp_csc2_coef11; /* 0x2264 */ -+ volatile u_v1_ot_pp_csc2_coef12 v1_ot_pp_csc2_coef12; /* 0x2268 */ -+ volatile u_v1_ot_pp_csc2_coef20 v1_ot_pp_csc2_coef20; /* 0x226c */ -+ volatile u_v1_ot_pp_csc2_coef21 v1_ot_pp_csc2_coef21; /* 0x2270 */ -+ volatile u_v1_ot_pp_csc2_coef22 v1_ot_pp_csc2_coef22; /* 0x2274 */ -+ volatile u_v1_ot_pp_csc2_scale v1_ot_pp_csc2_scale; /* 0x2278 */ -+ volatile u_v1_ot_pp_csc2_idc0 v1_ot_pp_csc2_idc0; /* 0x227c */ -+ volatile u_v1_ot_pp_csc2_idc1 v1_ot_pp_csc2_idc1; /* 0x2280 */ -+ volatile u_v1_ot_pp_csc2_idc2 v1_ot_pp_csc2_idc2; /* 0x2284 */ -+ volatile u_v1_ot_pp_csc2_odc0 v1_ot_pp_csc2_odc0; /* 0x2288 */ -+ volatile u_v1_ot_pp_csc2_odc1 v1_ot_pp_csc2_odc1; /* 0x228c */ -+ volatile u_v1_ot_pp_csc2_odc2 v1_ot_pp_csc2_odc2; /* 0x2290 */ -+ volatile u_v1_ot_pp_csc2_min_y v1_ot_pp_csc2_min_y; /* 0x2294 */ -+ volatile u_v1_ot_pp_csc2_min_c v1_ot_pp_csc2_min_c; /* 0x2298 */ -+ volatile u_v1_ot_pp_csc2_max_y v1_ot_pp_csc2_max_y; /* 0x229c */ -+ volatile u_v1_ot_pp_csc2_max_c v1_ot_pp_csc2_max_c; /* 0x22a0 */ -+ volatile unsigned int reserved_36[19]; /* 19:0x22a4~0x22ec */ -+ volatile u_v1_ot_pp_csc_ink_ctrl v1_ot_pp_csc_ink_ctrl; /* 0x22f0 */ -+ volatile u_v1_ot_pp_csc_ink_pos v1_ot_pp_csc_ink_pos; /* 0x22f4 */ -+ volatile unsigned int v1_ot_pp_csc_ink_data; /* 0x22f8 */ -+ volatile unsigned int v1_ot_pp_csc_ink_data2; /* 0x22fc */ -+ volatile unsigned int reserved_37[64]; /* 64:0x2300~0x23fc */ -+ volatile u_v1_cvfir_vinfo v1_cvfir_vinfo; /* 0x2400 */ -+ volatile u_v1_cvfir_vsp v1_cvfir_vsp; /* 0x2404 */ -+ volatile u_v1_cvfir_voffset v1_cvfir_voffset; /* 0x2408 */ -+ volatile u_v1_cvfir_vboffset v1_cvfir_vboffset; /* 0x240c */ -+ volatile unsigned int reserved_38[8]; /* 8:0x2410~0x242c */ -+ volatile u_v1_cvfir_vcoef0 v1_cvfir_vcoef0; /* 0x2430 */ -+ volatile u_v1_cvfir_vcoef1 v1_cvfir_vcoef1; /* 0x2434 */ -+ volatile u_v1_cvfir_vcoef2 v1_cvfir_vcoef2; /* 0x2438 */ -+ volatile unsigned int reserved_39[49]; /* 49:0x243c~0x24fc */ -+ volatile u_v1_hfir_ctrl v1_hfir_ctrl; /* 0x2500 */ -+ volatile u_v1_hfircoef01 v1_hfircoef01; /* 0x2504 */ -+ volatile u_v1_hfircoef23 v1_hfircoef23; /* 0x2508 */ -+ volatile u_v1_hfircoef45 v1_hfircoef45; /* 0x250c */ -+ volatile u_v1_hfircoef67 v1_hfircoef67; /* 0x2510 */ -+ volatile unsigned int reserved_40[699]; /* 699:0x2514~0x2ffc */ -+ volatile u_v2_ctrl v2_ctrl; /* 0x3000 */ -+ volatile u_v2_upd v2_upd; /* 0x3004 */ -+ volatile u_v2_0reso_read v2_0reso_read; /* 0x3008 */ -+ volatile unsigned int reserved_41; /* 0x300c */ -+ volatile u_v2_ireso v2_ireso; /* 0x3010 */ -+ volatile unsigned int reserved_42[27]; /* 27:0x3014~0x307c */ -+ volatile u_v2_dfpos v2_dfpos; /* 0x3080 */ -+ volatile u_v2_dlpos v2_dlpos; /* 0x3084 */ -+ volatile u_v2_vfpos v2_vfpos; /* 0x3088 */ -+ volatile u_v2_vlpos v2_vlpos; /* 0x308c */ -+ volatile u_v2_bk v2_bk; /* 0x3090 */ -+ volatile u_v2_alpha v2_alpha; /* 0x3094 */ -+ volatile u_v2_mute_bk v2_mute_bk; /* 0x3098 */ -+ volatile unsigned int reserved_43[89]; /* 89:0x309c~0x31fc */ -+ volatile u_v2_ot_pp_csc_ctrl v2_ot_pp_csc_ctrl; /* 0x3200 */ -+ volatile u_v2_ot_pp_csc_coef00 v2_ot_pp_csc_coef00; /* 0x3204 */ -+ volatile u_v2_ot_pp_csc_coef01 v2_ot_pp_csc_coef01; /* 0x3208 */ -+ volatile u_v2_ot_pp_csc_coef02 v2_ot_pp_csc_coef02; /* 0x320c */ -+ volatile u_v2_ot_pp_csc_coef10 v2_ot_pp_csc_coef10; /* 0x3210 */ -+ volatile u_v2_ot_pp_csc_coef11 v2_ot_pp_csc_coef11; /* 0x3214 */ -+ volatile u_v2_ot_pp_csc_coef12 v2_ot_pp_csc_coef12; /* 0x3218 */ -+ volatile u_v2_ot_pp_csc_coef20 v2_ot_pp_csc_coef20; /* 0x321c */ -+ volatile u_v2_ot_pp_csc_coef21 v2_ot_pp_csc_coef21; /* 0x3220 */ -+ volatile u_v2_ot_pp_csc_coef22 v2_ot_pp_csc_coef22; /* 0x3224 */ -+ volatile u_v2_ot_pp_csc_scale v2_ot_pp_csc_scale; /* 0x3228 */ -+ volatile u_v2_ot_pp_csc_idc0 v2_ot_pp_csc_idc0; /* 0x322c */ -+ volatile u_v2_ot_pp_csc_idc1 v2_ot_pp_csc_idc1; /* 0x3230 */ -+ volatile u_v2_ot_pp_csc_idc2 v2_ot_pp_csc_idc2; /* 0x3234 */ -+ volatile u_v2_ot_pp_csc_odc0 v2_ot_pp_csc_odc0; /* 0x3238 */ -+ volatile u_v2_ot_pp_csc_odc1 v2_ot_pp_csc_odc1; /* 0x323c */ -+ volatile u_v2_ot_pp_csc_odc2 v2_ot_pp_csc_odc2; /* 0x3240 */ -+ volatile u_v2_ot_pp_csc_min_y v2_ot_pp_csc_min_y; /* 0x3244 */ -+ volatile u_v2_ot_pp_csc_min_c v2_ot_pp_csc_min_c; /* 0x3248 */ -+ volatile u_v2_ot_pp_csc_max_y v2_ot_pp_csc_max_y; /* 0x324c */ -+ volatile u_v2_ot_pp_csc_max_c v2_ot_pp_csc_max_c; /* 0x3250 */ -+ volatile u_v2_ot_pp_csc2_coef00 v2_ot_pp_csc2_coef00; /* 0x3254 */ -+ volatile u_v2_ot_pp_csc2_coef01 v2_ot_pp_csc2_coef01; /* 0x3258 */ -+ volatile u_v2_ot_pp_csc2_coef02 v2_ot_pp_csc2_coef02; /* 0x325c */ -+ volatile u_v2_ot_pp_csc2_coef10 v2_ot_pp_csc2_coef10; /* 0x3260 */ -+ volatile u_v2_ot_pp_csc2_coef11 v2_ot_pp_csc2_coef11; /* 0x3264 */ -+ volatile u_v2_ot_pp_csc2_coef12 v2_ot_pp_csc2_coef12; /* 0x3268 */ -+ volatile u_v2_ot_pp_csc2_coef20 v2_ot_pp_csc2_coef20; /* 0x326c */ -+ volatile u_v2_ot_pp_csc2_coef21 v2_ot_pp_csc2_coef21; /* 0x3270 */ -+ volatile u_v2_ot_pp_csc2_coef22 v2_ot_pp_csc2_coef22; /* 0x3274 */ -+ volatile u_v2_ot_pp_csc2_scale v2_ot_pp_csc2_scale; /* 0x3278 */ -+ volatile u_v2_ot_pp_csc2_idc0 v2_ot_pp_csc2_idc0; /* 0x327c */ -+ volatile u_v2_ot_pp_csc2_idc1 v2_ot_pp_csc2_idc1; /* 0x3280 */ -+ volatile u_v2_ot_pp_csc2_idc2 v2_ot_pp_csc2_idc2; /* 0x3284 */ -+ volatile u_v2_ot_pp_csc2_odc0 v2_ot_pp_csc2_odc0; /* 0x3288 */ -+ volatile u_v2_ot_pp_csc2_odc1 v2_ot_pp_csc2_odc1; /* 0x328c */ -+ volatile u_v2_ot_pp_csc2_odc2 v2_ot_pp_csc2_odc2; /* 0x3290 */ -+ volatile u_v2_ot_pp_csc2_min_y v2_ot_pp_csc2_min_y; /* 0x3294 */ -+ volatile u_v2_ot_pp_csc2_min_c v2_ot_pp_csc2_min_c; /* 0x3298 */ -+ volatile u_v2_ot_pp_csc2_max_y v2_ot_pp_csc2_max_y; /* 0x329c */ -+ volatile u_v2_ot_pp_csc2_max_c v2_ot_pp_csc2_max_c; /* 0x32a0 */ -+ volatile unsigned int reserved_44[19]; /* 19:0x32a4~0x32ec */ -+ volatile u_v2_ot_pp_csc_ink_ctrl v2_ot_pp_csc_ink_ctrl; /* 0x32f0 */ -+ volatile u_v2_ot_pp_csc_ink_pos v2_ot_pp_csc_ink_pos; /* 0x32f4 */ -+ volatile unsigned int v2_ot_pp_csc_ink_data; /* 0x32f8 */ -+ volatile unsigned int v2_ot_pp_csc_ink_data2; /* 0x32fc */ -+ volatile unsigned int reserved_45[64]; /* 64:0x3300~0x33fc */ -+ volatile u_v2_cvfir_vinfo v2_cvfir_vinfo; /* 0x3400 */ -+ volatile u_v2_cvfir_vsp v2_cvfir_vsp; /* 0x3404 */ -+ volatile u_v2_cvfir_voffset v2_cvfir_voffset; /* 0x3408 */ -+ volatile u_v2_cvfir_vboffset v2_cvfir_vboffset; /* 0x340c */ -+ volatile unsigned int reserved_46[8]; /* 8:0x3410~0x342c */ -+ volatile u_v2_cvfir_vcoef0 v2_cvfir_vcoef0; /* 0x3430 */ -+ volatile u_v2_cvfir_vcoef1 v2_cvfir_vcoef1; /* 0x3434 */ -+ volatile u_v2_cvfir_vcoef2 v2_cvfir_vcoef2; /* 0x3438 */ -+ volatile unsigned int reserved_47[49]; /* 49:0x343c~0x34fc */ -+ volatile u_v2_hfir_ctrl v2_hfir_ctrl; /* 0x3500 */ -+ volatile u_v2_hfircoef01 v2_hfircoef01; /* 0x3504 */ -+ volatile u_v2_hfircoef23 v2_hfircoef23; /* 0x3508 */ -+ volatile u_v2_hfircoef45 v2_hfircoef45; /* 0x350c */ -+ volatile u_v2_hfircoef67 v2_hfircoef67; /* 0x3510 */ -+ volatile unsigned int reserved_48[699]; /* 699:0x3514~0x3ffc */ -+ volatile u_v3_ctrl v3_ctrl; /* 0x4000 */ -+ volatile u_v3_upd v3_upd; /* 0x4004 */ -+ volatile u_v3_0reso_read v3_0reso_read; /* 0x4008 */ -+ volatile unsigned int reserved_49; /* 0x400c */ -+ volatile u_v3_ireso v3_ireso; /* 0x4010 */ -+ volatile unsigned int reserved_50[27]; /* 27:0x4014~0x407c */ -+ volatile u_v3_dfpos v3_dfpos; /* 0x4080 */ -+ volatile u_v3_dlpos v3_dlpos; /* 0x4084 */ -+ volatile u_v3_vfpos v3_vfpos; /* 0x4088 */ -+ volatile u_v3_vlpos v3_vlpos; /* 0x408c */ -+ volatile u_v3_bk v3_bk; /* 0x4090 */ -+ volatile u_v3_alpha v3_alpha; /* 0x4094 */ -+ volatile u_v3_mute_bk v3_mute_bk; /* 0x4098 */ -+ volatile unsigned int reserved_51; /* 0x409c */ -+ volatile u_v3_rimwidth v3_rimwidth; /* 0x40a0 */ -+ volatile u_v3_rimcol0 v3_rimcol0; /* 0x40a4 */ -+ volatile u_v3_rimcol1 v3_rimcol1; /* 0x40a8 */ -+ volatile unsigned int reserved_52[85]; /* 85:0x40ac~0x41fc */ -+ volatile u_v3_ot_pp_csc_ctrl v3_ot_pp_csc_ctrl; /* 0x4200 */ -+ volatile u_v3_ot_pp_csc_coef00 v3_ot_pp_csc_coef00; /* 0x4204 */ -+ volatile u_v3_ot_pp_csc_coef01 v3_ot_pp_csc_coef01; /* 0x4208 */ -+ volatile u_v3_ot_pp_csc_coef02 v3_ot_pp_csc_coef02; /* 0x420c */ -+ volatile u_v3_ot_pp_csc_coef10 v3_ot_pp_csc_coef10; /* 0x4210 */ -+ volatile u_v3_ot_pp_csc_coef11 v3_ot_pp_csc_coef11; /* 0x4214 */ -+ volatile u_v3_ot_pp_csc_coef12 v3_ot_pp_csc_coef12; /* 0x4218 */ -+ volatile u_v3_ot_pp_csc_coef20 v3_ot_pp_csc_coef20; /* 0x421c */ -+ volatile u_v3_ot_pp_csc_coef21 v3_ot_pp_csc_coef21; /* 0x4220 */ -+ volatile u_v3_ot_pp_csc_coef22 v3_ot_pp_csc_coef22; /* 0x4224 */ -+ volatile u_v3_ot_pp_csc_scale v3_ot_pp_csc_scale; /* 0x4228 */ -+ volatile u_v3_ot_pp_csc_idc0 v3_ot_pp_csc_idc0; /* 0x422c */ -+ volatile u_v3_ot_pp_csc_idc1 v3_ot_pp_csc_idc1; /* 0x4230 */ -+ volatile u_v3_ot_pp_csc_idc2 v3_ot_pp_csc_idc2; /* 0x4234 */ -+ volatile u_v3_ot_pp_csc_odc0 v3_ot_pp_csc_odc0; /* 0x4238 */ -+ volatile u_v3_ot_pp_csc_odc1 v3_ot_pp_csc_odc1; /* 0x423c */ -+ volatile u_v3_ot_pp_csc_odc2 v3_ot_pp_csc_odc2; /* 0x4240 */ -+ volatile u_v3_ot_pp_csc_min_y v3_ot_pp_csc_min_y; /* 0x4244 */ -+ volatile u_v3_ot_pp_csc_min_c v3_ot_pp_csc_min_c; /* 0x4248 */ -+ volatile u_v3_ot_pp_csc_max_y v3_ot_pp_csc_max_y; /* 0x424c */ -+ volatile u_v3_ot_pp_csc_max_c v3_ot_pp_csc_max_c; /* 0x4250 */ -+ volatile u_v3_ot_pp_csc2_coef00 v3_ot_pp_csc2_coef00; /* 0x4254 */ -+ volatile u_v3_ot_pp_csc2_coef01 v3_ot_pp_csc2_coef01; /* 0x4258 */ -+ volatile u_v3_ot_pp_csc2_coef02 v3_ot_pp_csc2_coef02; /* 0x425c */ -+ volatile u_v3_ot_pp_csc2_coef10 v3_ot_pp_csc2_coef10; /* 0x4260 */ -+ volatile u_v3_ot_pp_csc2_coef11 v3_ot_pp_csc2_coef11; /* 0x4264 */ -+ volatile u_v3_ot_pp_csc2_coef12 v3_ot_pp_csc2_coef12; /* 0x4268 */ -+ volatile u_v3_ot_pp_csc2_coef20 v3_ot_pp_csc2_coef20; /* 0x426c */ -+ volatile u_v3_ot_pp_csc2_coef21 v3_ot_pp_csc2_coef21; /* 0x4270 */ -+ volatile u_v3_ot_pp_csc2_coef22 v3_ot_pp_csc2_coef22; /* 0x4274 */ -+ volatile u_v3_ot_pp_csc2_scale v3_ot_pp_csc2_scale; /* 0x4278 */ -+ volatile u_v3_ot_pp_csc2_idc0 v3_ot_pp_csc2_idc0; /* 0x427c */ -+ volatile u_v3_ot_pp_csc2_idc1 v3_ot_pp_csc2_idc1; /* 0x4280 */ -+ volatile u_v3_ot_pp_csc2_idc2 v3_ot_pp_csc2_idc2; /* 0x4284 */ -+ volatile u_v3_ot_pp_csc2_odc0 v3_ot_pp_csc2_odc0; /* 0x4288 */ -+ volatile u_v3_ot_pp_csc2_odc1 v3_ot_pp_csc2_odc1; /* 0x428c */ -+ volatile u_v3_ot_pp_csc2_odc2 v3_ot_pp_csc2_odc2; /* 0x4290 */ -+ volatile u_v3_ot_pp_csc2_min_y v3_ot_pp_csc2_min_y; /* 0x4294 */ -+ volatile u_v3_ot_pp_csc2_min_c v3_ot_pp_csc2_min_c; /* 0x4298 */ -+ volatile u_v3_ot_pp_csc2_max_y v3_ot_pp_csc2_max_y; /* 0x429c */ -+ volatile u_v3_ot_pp_csc2_max_c v3_ot_pp_csc2_max_c; /* 0x42a0 */ -+ volatile unsigned int reserved_53[19]; /* 19:0x42a4~0x42ec */ -+ volatile u_v3_ot_pp_csc_ink_ctrl v3_ot_pp_csc_ink_ctrl; /* 0x42f0 */ -+ volatile u_v3_ot_pp_csc_ink_pos v3_ot_pp_csc_ink_pos; /* 0x42f4 */ -+ volatile unsigned int v3_ot_pp_csc_ink_data; /* 0x42f8 */ -+ volatile unsigned int v3_ot_pp_csc_ink_data2; /* 0x42fc */ -+ volatile unsigned int reserved_54[128]; /* 128:0x4300~0x44fc */ -+ volatile u_v3_hfir_ctrl v3_hfir_ctrl; /* 0x4500 */ -+ volatile u_v3_hfircoef01 v3_hfircoef01; /* 0x4504 */ -+ volatile u_v3_hfircoef23 v3_hfircoef23; /* 0x4508 */ -+ volatile u_v3_hfircoef45 v3_hfircoef45; /* 0x450c */ -+ volatile u_v3_hfircoef67 v3_hfircoef67; /* 0x4510 */ -+ volatile unsigned int reserved_55[1211]; /* 1211:0x4514~0x57fc */ -+ volatile unsigned int vp0_ctrl; /* 0x5800 */ -+ volatile u_vp0_upd vp0_upd; /* 0x5804 */ -+ volatile u_vp0_ireso vp0_ireso; /* 0x5808 */ -+ volatile unsigned int reserved_56[29]; /* 29:0x580c~0x587c */ -+ volatile u_vp0_lbox_ctrl vp0_lbox_ctrl; /* 0x5880 */ -+ volatile u_vp0_galpha vp0_galpha; /* 0x5884 */ -+ volatile u_vp0_dfpos vp0_dfpos; /* 0x5888 */ -+ volatile u_vp0_dlpos vp0_dlpos; /* 0x588c */ -+ volatile u_vp0_vfpos vp0_vfpos; /* 0x5890 */ -+ volatile u_vp0_vlpos vp0_vlpos; /* 0x5894 */ -+ volatile u_vp0_bk vp0_bk; /* 0x5898 */ -+ volatile u_vp0_alpha vp0_alpha; /* 0x589c */ -+ volatile u_vp0_mute_bk vp0_mute_bk; /* 0x58a0 */ -+ volatile unsigned int reserved_57[1495]; /* 1495:0x58a4~0x6ffc */ -+ volatile u_g0_ctrl g0_ctrl; /* 0x7000 */ -+ volatile u_g0_upd g0_upd; /* 0x7004 */ -+ volatile unsigned int g0_galpha_sum; /* 0x7008 */ -+ volatile u_g0_0reso_read g0_0reso_read; /* 0x700c */ -+ volatile u_g0_ireso g0_ireso; /* 0x7010 */ -+ volatile unsigned int reserved_58[27]; /* 27:0x7014~0x707c */ -+ volatile u_g0_dfpos g0_dfpos; /* 0x7080 */ -+ volatile u_g0_dlpos g0_dlpos; /* 0x7084 */ -+ volatile u_g0_vfpos g0_vfpos; /* 0x7088 */ -+ volatile u_g0_vlpos g0_vlpos; /* 0x708c */ -+ volatile u_g0_bk g0_bk; /* 0x7090 */ -+ volatile u_g0_alpha g0_alpha; /* 0x7094 */ -+ volatile u_g0_mute_bk g0_mute_bk; /* 0x7098 */ -+ volatile u_g0_lbox_ctrl g0_lbox_ctrl; /* 0x709c */ -+ volatile unsigned int reserved_59[24]; /* 24:0x70a0~0x70fc */ -+ volatile u_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; /* 0x7100 */ -+ volatile u_g0_ot_pp_csc_coef00 g0_ot_pp_csc_coef00; /* 0x7104 */ -+ volatile u_g0_ot_pp_csc_coef01 g0_ot_pp_csc_coef01; /* 0x7108 */ -+ volatile u_g0_ot_pp_csc_coef02 g0_ot_pp_csc_coef02; /* 0x710c */ -+ volatile u_g0_ot_pp_csc_coef10 g0_ot_pp_csc_coef10; /* 0x7110 */ -+ volatile u_g0_ot_pp_csc_coef11 g0_ot_pp_csc_coef11; /* 0x7114 */ -+ volatile u_g0_ot_pp_csc_coef12 g0_ot_pp_csc_coef12; /* 0x7118 */ -+ volatile u_g0_ot_pp_csc_coef20 g0_ot_pp_csc_coef20; /* 0x711c */ -+ volatile u_g0_ot_pp_csc_coef21 g0_ot_pp_csc_coef21; /* 0x7120 */ -+ volatile u_g0_ot_pp_csc_coef22 g0_ot_pp_csc_coef22; /* 0x7124 */ -+ volatile u_g0_ot_pp_csc_scale g0_ot_pp_csc_scale; /* 0x7128 */ -+ volatile u_g0_ot_pp_csc_idc0 g0_ot_pp_csc_idc0; /* 0x712c */ -+ volatile u_g0_ot_pp_csc_idc1 g0_ot_pp_csc_idc1; /* 0x7130 */ -+ volatile u_g0_ot_pp_csc_idc2 g0_ot_pp_csc_idc2; /* 0x7134 */ -+ volatile u_g0_ot_pp_csc_odc0 g0_ot_pp_csc_odc0; /* 0x7138 */ -+ volatile u_g0_ot_pp_csc_odc1 g0_ot_pp_csc_odc1; /* 0x713c */ -+ volatile u_g0_ot_pp_csc_odc2 g0_ot_pp_csc_odc2; /* 0x7140 */ -+ volatile u_g0_ot_pp_csc_min_y g0_ot_pp_csc_min_y; /* 0x7144 */ -+ volatile u_g0_ot_pp_csc_min_c g0_ot_pp_csc_min_c; /* 0x7148 */ -+ volatile u_g0_ot_pp_csc_max_y g0_ot_pp_csc_max_y; /* 0x714c */ -+ volatile u_g0_ot_pp_csc_max_c g0_ot_pp_csc_max_c; /* 0x7150 */ -+ volatile u_g0_ot_pp_csc2_coef00 g0_ot_pp_csc2_coef00; /* 0x7154 */ -+ volatile u_g0_ot_pp_csc2_coef01 g0_ot_pp_csc2_coef01; /* 0x7158 */ -+ volatile u_g0_ot_pp_csc2_coef02 g0_ot_pp_csc2_coef02; /* 0x715c */ -+ volatile u_g0_ot_pp_csc2_coef10 g0_ot_pp_csc2_coef10; /* 0x7160 */ -+ volatile u_g0_ot_pp_csc2_coef11 g0_ot_pp_csc2_coef11; /* 0x7164 */ -+ volatile u_g0_ot_pp_csc2_coef12 g0_ot_pp_csc2_coef12; /* 0x7168 */ -+ volatile u_g0_ot_pp_csc2_coef20 g0_ot_pp_csc2_coef20; /* 0x716c */ -+ volatile u_g0_ot_pp_csc2_coef21 g0_ot_pp_csc2_coef21; /* 0x7170 */ -+ volatile u_g0_ot_pp_csc2_coef22 g0_ot_pp_csc2_coef22; /* 0x7174 */ -+ volatile u_g0_ot_pp_csc2_scale g0_ot_pp_csc2_scale; /* 0x7178 */ -+ volatile u_g0_ot_pp_csc2_idc0 g0_ot_pp_csc2_idc0; /* 0x717c */ -+ volatile u_g0_ot_pp_csc2_idc1 g0_ot_pp_csc2_idc1; /* 0x7180 */ -+ volatile u_g0_ot_pp_csc2_idc2 g0_ot_pp_csc2_idc2; /* 0x7184 */ -+ volatile u_g0_ot_pp_csc2_odc0 g0_ot_pp_csc2_odc0; /* 0x7188 */ -+ volatile u_g0_ot_pp_csc2_odc1 g0_ot_pp_csc2_odc1; /* 0x718c */ -+ volatile u_g0_ot_pp_csc2_odc2 g0_ot_pp_csc2_odc2; /* 0x7190 */ -+ volatile u_g0_ot_pp_csc2_min_y g0_ot_pp_csc2_min_y; /* 0x7194 */ -+ volatile u_g0_ot_pp_csc2_min_c g0_ot_pp_csc2_min_c; /* 0x7198 */ -+ volatile u_g0_ot_pp_csc2_max_y g0_ot_pp_csc2_max_y; /* 0x719c */ -+ volatile u_g0_ot_pp_csc2_max_c g0_ot_pp_csc2_max_c; /* 0x71a0 */ -+ volatile unsigned int reserved_60[19]; /* 19:0x71a4~0x71ec */ -+ volatile u_g0_ot_pp_csc_ink_ctrl g0_ot_pp_csc_ink_ctrl; /* 0x71f0 */ -+ volatile u_g0_ot_pp_csc_ink_pos g0_ot_pp_csc_ink_pos; /* 0x71f4 */ -+ volatile unsigned int g0_ot_pp_csc_ink_data; /* 0x71f8 */ -+ volatile unsigned int g0_ot_pp_csc_ink_data2; /* 0x71fc */ -+ volatile u_g0_dof_ctrl g0_dof_ctrl; /* 0x7200 */ -+ volatile u_g0_dof_step g0_dof_step; /* 0x7204 */ -+ volatile u_g0_dof_bkg g0_dof_bkg; /* 0x7208 */ -+ volatile u_g0_dof_alpha g0_dof_alpha; /* 0x720c */ -+ volatile unsigned int reserved_61[60]; /* 60:0x7210~0x72fc */ -+ volatile u_g0_zme_hinfo g0_zme_hinfo; /* 0x7300 */ -+ volatile u_g0_zme_hsp g0_zme_hsp; /* 0x7304 */ -+ volatile u_g0_zme_hloffset g0_zme_hloffset; /* 0x7308 */ -+ volatile u_g0_zme_hcoffset g0_zme_hcoffset; /* 0x730c */ -+ volatile unsigned int reserved_62[5]; /* 5:0x7310~0x7320 */ -+ volatile u_g0_zme_coef_ren g0_zme_coef_ren; /* 0x7324 */ -+ volatile u_g0_zme_coef_rdata g0_zme_coef_rdata; /* 0x7328 */ -+ volatile unsigned int reserved_63[21]; /* 21:0x732c~0x737c */ -+ volatile u_g0_zme_vinfo g0_zme_vinfo; /* 0x7380 */ -+ volatile u_g0_zme_vsp g0_zme_vsp; /* 0x7384 */ -+ volatile u_g0_zme_voffset g0_zme_voffset; /* 0x7388 */ -+ volatile unsigned int reserved_64[285]; /* 285:0x738c~0x77fc */ -+ volatile u_g1_ctrl g1_ctrl; /* 0x7800 */ -+ volatile u_g1_upd g1_upd; /* 0x7804 */ -+ volatile unsigned int g1_galpha_sum; /* 0x7808 */ -+ volatile u_g1_0reso_read g1_0reso_read; /* 0x780c */ -+ volatile u_g1_ireso g1_ireso; /* 0x7810 */ -+ volatile unsigned int reserved_65[27]; /* 27:0x7814~0x787c */ -+ volatile u_g1_dfpos g1_dfpos; /* 0x7880 */ -+ volatile u_g1_dlpos g1_dlpos; /* 0x7884 */ -+ volatile u_g1_vfpos g1_vfpos; /* 0x7888 */ -+ volatile u_g1_vlpos g1_vlpos; /* 0x788c */ -+ volatile u_g1_bk g1_bk; /* 0x7890 */ -+ volatile u_g1_alpha g1_alpha; /* 0x7894 */ -+ volatile u_g1_mute_bk g1_mute_bk; /* 0x7898 */ -+ volatile u_g1_lbox_ctrl g1_lbox_ctrl; /* 0x789c */ -+ volatile unsigned int reserved_66[24]; /* 24:0x78a0~0x78fc */ -+ volatile u_g1_ot_pp_csc_ctrl g1_ot_pp_csc_ctrl; /* 0x7900 */ -+ volatile u_g1_ot_pp_csc_coef00 g1_ot_pp_csc_coef00; /* 0x7904 */ -+ volatile u_g1_ot_pp_csc_coef01 g1_ot_pp_csc_coef01; /* 0x7908 */ -+ volatile u_g1_ot_pp_csc_coef02 g1_ot_pp_csc_coef02; /* 0x790c */ -+ volatile u_g1_ot_pp_csc_coef10 g1_ot_pp_csc_coef10; /* 0x7910 */ -+ volatile u_g1_ot_pp_csc_coef11 g1_ot_pp_csc_coef11; /* 0x7914 */ -+ volatile u_g1_ot_pp_csc_coef12 g1_ot_pp_csc_coef12; /* 0x7918 */ -+ volatile u_g1_ot_pp_csc_coef20 g1_ot_pp_csc_coef20; /* 0x791c */ -+ volatile u_g1_ot_pp_csc_coef21 g1_ot_pp_csc_coef21; /* 0x7920 */ -+ volatile u_g1_ot_pp_csc_coef22 g1_ot_pp_csc_coef22; /* 0x7924 */ -+ volatile u_g1_ot_pp_csc_scale g1_ot_pp_csc_scale; /* 0x7928 */ -+ volatile u_g1_ot_pp_csc_idc0 g1_ot_pp_csc_idc0; /* 0x792c */ -+ volatile u_g1_ot_pp_csc_idc1 g1_ot_pp_csc_idc1; /* 0x7930 */ -+ volatile u_g1_ot_pp_csc_idc2 g1_ot_pp_csc_idc2; /* 0x7934 */ -+ volatile u_g1_ot_pp_csc_odc0 g1_ot_pp_csc_odc0; /* 0x7938 */ -+ volatile u_g1_ot_pp_csc_odc1 g1_ot_pp_csc_odc1; /* 0x793c */ -+ volatile u_g1_ot_pp_csc_odc2 g1_ot_pp_csc_odc2; /* 0x7940 */ -+ volatile u_g1_ot_pp_csc_min_y g1_ot_pp_csc_min_y; /* 0x7944 */ -+ volatile u_g1_ot_pp_csc_min_c g1_ot_pp_csc_min_c; /* 0x7948 */ -+ volatile u_g1_ot_pp_csc_max_y g1_ot_pp_csc_max_y; /* 0x794c */ -+ volatile u_g1_ot_pp_csc_max_c g1_ot_pp_csc_max_c; /* 0x7950 */ -+ volatile u_g1_ot_pp_csc2_coef00 g1_ot_pp_csc2_coef00; /* 0x7954 */ -+ volatile u_g1_ot_pp_csc2_coef01 g1_ot_pp_csc2_coef01; /* 0x7958 */ -+ volatile u_g1_ot_pp_csc2_coef02 g1_ot_pp_csc2_coef02; /* 0x795c */ -+ volatile u_g1_ot_pp_csc2_coef10 g1_ot_pp_csc2_coef10; /* 0x7960 */ -+ volatile u_g1_ot_pp_csc2_coef11 g1_ot_pp_csc2_coef11; /* 0x7964 */ -+ volatile u_g1_ot_pp_csc2_coef12 g1_ot_pp_csc2_coef12; /* 0x7968 */ -+ volatile u_g1_ot_pp_csc2_coef20 g1_ot_pp_csc2_coef20; /* 0x796c */ -+ volatile u_g1_ot_pp_csc2_coef21 g1_ot_pp_csc2_coef21; /* 0x7970 */ -+ volatile u_g1_ot_pp_csc2_coef22 g1_ot_pp_csc2_coef22; /* 0x7974 */ -+ volatile u_g1_ot_pp_csc2_scale g1_ot_pp_csc2_scale; /* 0x7978 */ -+ volatile u_g1_ot_pp_csc2_idc0 g1_ot_pp_csc2_idc0; /* 0x797c */ -+ volatile u_g1_ot_pp_csc2_idc1 g1_ot_pp_csc2_idc1; /* 0x7980 */ -+ volatile u_g1_ot_pp_csc2_idc2 g1_ot_pp_csc2_idc2; /* 0x7984 */ -+ volatile u_g1_ot_pp_csc2_odc0 g1_ot_pp_csc2_odc0; /* 0x7988 */ -+ volatile u_g1_ot_pp_csc2_odc1 g1_ot_pp_csc2_odc1; /* 0x798c */ -+ volatile u_g1_ot_pp_csc2_odc2 g1_ot_pp_csc2_odc2; /* 0x7990 */ -+ volatile u_g1_ot_pp_csc2_min_y g1_ot_pp_csc2_min_y; /* 0x7994 */ -+ volatile u_g1_ot_pp_csc2_min_c g1_ot_pp_csc2_min_c; /* 0x7998 */ -+ volatile u_g1_ot_pp_csc2_max_y g1_ot_pp_csc2_max_y; /* 0x799c */ -+ volatile u_g1_ot_pp_csc2_max_c g1_ot_pp_csc2_max_c; /* 0x79a0 */ -+ volatile unsigned int reserved_67[19]; /* 19:0x79a4~0x79ec */ -+ volatile u_g1_ot_pp_csc_ink_ctrl g1_ot_pp_csc_ink_ctrl; /* 0x79f0 */ -+ volatile u_g1_ot_pp_csc_ink_pos g1_ot_pp_csc_ink_pos; /* 0x79f4 */ -+ volatile unsigned int g1_ot_pp_csc_ink_data; /* 0x79f8 */ -+ volatile unsigned int g1_ot_pp_csc_ink_data2; /* 0x79fc */ -+ volatile unsigned int reserved_68[64]; /* 64:0x7a00~0x7afc */ -+ volatile u_g1_zme_hinfo g1_zme_hinfo; /* 0x7b00 */ -+ volatile u_g1_zme_hsp g1_zme_hsp; /* 0x7b04 */ -+ volatile u_g1_zme_hloffset g1_zme_hloffset; /* 0x7b08 */ -+ volatile u_g1_zme_hcoffset g1_zme_hcoffset; /* 0x7b0c */ -+ volatile unsigned int reserved_69[5]; /* 5:0x7b10~0x7b20 */ -+ volatile u_g1_zme_coef_ren g1_zme_coef_ren; /* 0x7b24 */ -+ volatile u_g1_zme_coef_rdata g1_zme_coef_rdata; /* 0x7b28 */ -+ volatile unsigned int reserved_70[21]; /* 21:0x7b2c~0x7b7c */ -+ volatile u_g1_zme_vinfo g1_zme_vinfo; /* 0x7b80 */ -+ volatile u_g1_zme_vsp g1_zme_vsp; /* 0x7b84 */ -+ volatile u_g1_zme_voffset g1_zme_voffset; /* 0x7b88 */ -+ volatile unsigned int reserved_71[285]; /* 285:0x7b8c~0x7ffc */ -+ volatile u_g2_ctrl g2_ctrl; /* 0x8000 */ -+ volatile u_g2_upd g2_upd; /* 0x8004 */ -+ volatile unsigned int g2_galpha_sum; /* 0x8008 */ -+ volatile u_g2_0reso_read g2_0reso_read; /* 0x800c */ -+ volatile u_g2_ireso g2_ireso; /* 0x8010 */ -+ volatile unsigned int reserved_72[27]; /* 27:0x8014~0x807c */ -+ volatile u_g2_dfpos g2_dfpos; /* 0x8080 */ -+ volatile u_g2_dlpos g2_dlpos; /* 0x8084 */ -+ volatile u_g2_vfpos g2_vfpos; /* 0x8088 */ -+ volatile u_g2_vlpos g2_vlpos; /* 0x808c */ -+ volatile u_g2_bk g2_bk; /* 0x8090 */ -+ volatile u_g2_alpha g2_alpha; /* 0x8094 */ -+ volatile u_g2_mute_bk g2_mute_bk; /* 0x8098 */ -+ volatile u_g2_lbox_ctrl g2_lbox_ctrl; /* 0x809c */ -+ volatile unsigned int reserved_73[24]; /* 24:0x80a0~0x80fc */ -+ volatile u_g2_ot_pp_csc_ctrl g2_ot_pp_csc_ctrl; /* 0x8100 */ -+ volatile u_g2_ot_pp_csc_coef00 g2_ot_pp_csc_coef00; /* 0x8104 */ -+ volatile u_g2_ot_pp_csc_coef01 g2_ot_pp_csc_coef01; /* 0x8108 */ -+ volatile u_g2_ot_pp_csc_coef02 g2_ot_pp_csc_coef02; /* 0x810c */ -+ volatile u_g2_ot_pp_csc_coef10 g2_ot_pp_csc_coef10; /* 0x8110 */ -+ volatile u_g2_ot_pp_csc_coef11 g2_ot_pp_csc_coef11; /* 0x8114 */ -+ volatile u_g2_ot_pp_csc_coef12 g2_ot_pp_csc_coef12; /* 0x8118 */ -+ volatile u_g2_ot_pp_csc_coef20 g2_ot_pp_csc_coef20; /* 0x811c */ -+ volatile u_g2_ot_pp_csc_coef21 g2_ot_pp_csc_coef21; /* 0x8120 */ -+ volatile u_g2_ot_pp_csc_coef22 g2_ot_pp_csc_coef22; /* 0x8124 */ -+ volatile u_g2_ot_pp_csc_scale g2_ot_pp_csc_scale; /* 0x8128 */ -+ volatile u_g2_ot_pp_csc_idc0 g2_ot_pp_csc_idc0; /* 0x812c */ -+ volatile u_g2_ot_pp_csc_idc1 g2_ot_pp_csc_idc1; /* 0x8130 */ -+ volatile u_g2_ot_pp_csc_idc2 g2_ot_pp_csc_idc2; /* 0x8134 */ -+ volatile u_g2_ot_pp_csc_odc0 g2_ot_pp_csc_odc0; /* 0x8138 */ -+ volatile u_g2_ot_pp_csc_odc1 g2_ot_pp_csc_odc1; /* 0x813c */ -+ volatile u_g2_ot_pp_csc_odc2 g2_ot_pp_csc_odc2; /* 0x8140 */ -+ volatile u_g2_ot_pp_csc_min_y g2_ot_pp_csc_min_y; /* 0x8144 */ -+ volatile u_g2_ot_pp_csc_min_c g2_ot_pp_csc_min_c; /* 0x8148 */ -+ volatile u_g2_ot_pp_csc_max_y g2_ot_pp_csc_max_y; /* 0x814c */ -+ volatile u_g2_ot_pp_csc_max_c g2_ot_pp_csc_max_c; /* 0x8150 */ -+ volatile u_g2_ot_pp_csc2_coef00 g2_ot_pp_csc2_coef00; /* 0x8154 */ -+ volatile u_g2_ot_pp_csc2_coef01 g2_ot_pp_csc2_coef01; /* 0x8158 */ -+ volatile u_g2_ot_pp_csc2_coef02 g2_ot_pp_csc2_coef02; /* 0x815c */ -+ volatile u_g2_ot_pp_csc2_coef10 g2_ot_pp_csc2_coef10; /* 0x8160 */ -+ volatile u_g2_ot_pp_csc2_coef11 g2_ot_pp_csc2_coef11; /* 0x8164 */ -+ volatile u_g2_ot_pp_csc2_coef12 g2_ot_pp_csc2_coef12; /* 0x8168 */ -+ volatile u_g2_ot_pp_csc2_coef20 g2_ot_pp_csc2_coef20; /* 0x816c */ -+ volatile u_g2_ot_pp_csc2_coef21 g2_ot_pp_csc2_coef21; /* 0x8170 */ -+ volatile u_g2_ot_pp_csc2_coef22 g2_ot_pp_csc2_coef22; /* 0x8174 */ -+ volatile u_g2_ot_pp_csc2_scale g2_ot_pp_csc2_scale; /* 0x8178 */ -+ volatile u_g2_ot_pp_csc2_idc0 g2_ot_pp_csc2_idc0; /* 0x817c */ -+ volatile u_g2_ot_pp_csc2_idc1 g2_ot_pp_csc2_idc1; /* 0x8180 */ -+ volatile u_g2_ot_pp_csc2_idc2 g2_ot_pp_csc2_idc2; /* 0x8184 */ -+ volatile u_g2_ot_pp_csc2_odc0 g2_ot_pp_csc2_odc0; /* 0x8188 */ -+ volatile u_g2_ot_pp_csc2_odc1 g2_ot_pp_csc2_odc1; /* 0x818c */ -+ volatile u_g2_ot_pp_csc2_odc2 g2_ot_pp_csc2_odc2; /* 0x8190 */ -+ volatile u_g2_ot_pp_csc2_min_y g2_ot_pp_csc2_min_y; /* 0x8194 */ -+ volatile u_g2_ot_pp_csc2_min_c g2_ot_pp_csc2_min_c; /* 0x8198 */ -+ volatile u_g2_ot_pp_csc2_max_y g2_ot_pp_csc2_max_y; /* 0x819c */ -+ volatile u_g2_ot_pp_csc2_max_c g2_ot_pp_csc2_max_c; /* 0x81a0 */ -+ volatile unsigned int reserved_74[19]; /* 19:0x81a4~0x81ec */ -+ volatile u_g2_ot_pp_csc_ink_ctrl g2_ot_pp_csc_ink_ctrl; /* 0x81f0 */ -+ volatile u_g2_ot_pp_csc_ink_pos g2_ot_pp_csc_ink_pos; /* 0x81f4 */ -+ volatile unsigned int g2_ot_pp_csc_ink_data; /* 0x81f8 */ -+ volatile unsigned int g2_ot_pp_csc_ink_data2; /* 0x81fc */ -+ volatile unsigned int reserved_75[384]; /* 384:0x8200~0x87fc */ -+ volatile u_g3_ctrl g3_ctrl; /* 0x8800 */ -+ volatile u_g3_upd g3_upd; /* 0x8804 */ -+ volatile unsigned int g3_galpha_sum; /* 0x8808 */ -+ volatile u_g3_0reso_read g3_0reso_read; /* 0x880c */ -+ volatile u_g3_ireso g3_ireso; /* 0x8810 */ -+ volatile unsigned int reserved_76[27]; /* 27:0x8814~0x887c */ -+ volatile u_g3_dfpos g3_dfpos; /* 0x8880 */ -+ volatile u_g3_dlpos g3_dlpos; /* 0x8884 */ -+ volatile u_g3_vfpos g3_vfpos; /* 0x8888 */ -+ volatile u_g3_vlpos g3_vlpos; /* 0x888c */ -+ volatile u_g3_bk g3_bk; /* 0x8890 */ -+ volatile u_g3_alpha g3_alpha; /* 0x8894 */ -+ volatile u_g3_mute_bk g3_mute_bk; /* 0x8898 */ -+ volatile u_g3_lbox_ctrl g3_lbox_ctrl; /* 0x889c */ -+ volatile unsigned int reserved_77[24]; /* 24:0x88a0~0x88fc */ -+ volatile u_g3_ot_pp_csc_ctrl g3_ot_pp_csc_ctrl; /* 0x8900 */ -+ volatile u_g3_ot_pp_csc_coef00 g3_ot_pp_csc_coef00; /* 0x8904 */ -+ volatile u_g3_ot_pp_csc_coef01 g3_ot_pp_csc_coef01; /* 0x8908 */ -+ volatile u_g3_ot_pp_csc_coef02 g3_ot_pp_csc_coef02; /* 0x890c */ -+ volatile u_g3_ot_pp_csc_coef10 g3_ot_pp_csc_coef10; /* 0x8910 */ -+ volatile u_g3_ot_pp_csc_coef11 g3_ot_pp_csc_coef11; /* 0x8914 */ -+ volatile u_g3_ot_pp_csc_coef12 g3_ot_pp_csc_coef12; /* 0x8918 */ -+ volatile u_g3_ot_pp_csc_coef20 g3_ot_pp_csc_coef20; /* 0x891c */ -+ volatile u_g3_ot_pp_csc_coef21 g3_ot_pp_csc_coef21; /* 0x8920 */ -+ volatile u_g3_ot_pp_csc_coef22 g3_ot_pp_csc_coef22; /* 0x8924 */ -+ volatile u_g3_ot_pp_csc_scale g3_ot_pp_csc_scale; /* 0x8928 */ -+ volatile u_g3_ot_pp_csc_idc0 g3_ot_pp_csc_idc0; /* 0x892c */ -+ volatile u_g3_ot_pp_csc_idc1 g3_ot_pp_csc_idc1; /* 0x8930 */ -+ volatile u_g3_ot_pp_csc_idc2 g3_ot_pp_csc_idc2; /* 0x8934 */ -+ volatile u_g3_ot_pp_csc_odc0 g3_ot_pp_csc_odc0; /* 0x8938 */ -+ volatile u_g3_ot_pp_csc_odc1 g3_ot_pp_csc_odc1; /* 0x893c */ -+ volatile u_g3_ot_pp_csc_odc2 g3_ot_pp_csc_odc2; /* 0x8940 */ -+ volatile u_g3_ot_pp_csc_min_y g3_ot_pp_csc_min_y; /* 0x8944 */ -+ volatile u_g3_ot_pp_csc_min_c g3_ot_pp_csc_min_c; /* 0x8948 */ -+ volatile u_g3_ot_pp_csc_max_y g3_ot_pp_csc_max_y; /* 0x894c */ -+ volatile u_g3_ot_pp_csc_max_c g3_ot_pp_csc_max_c; /* 0x8950 */ -+ volatile u_g3_ot_pp_csc2_coef00 g3_ot_pp_csc2_coef00; /* 0x8954 */ -+ volatile u_g3_ot_pp_csc2_coef01 g3_ot_pp_csc2_coef01; /* 0x8958 */ -+ volatile u_g3_ot_pp_csc2_coef02 g3_ot_pp_csc2_coef02; /* 0x895c */ -+ volatile u_g3_ot_pp_csc2_coef10 g3_ot_pp_csc2_coef10; /* 0x8960 */ -+ volatile u_g3_ot_pp_csc2_coef11 g3_ot_pp_csc2_coef11; /* 0x8964 */ -+ volatile u_g3_ot_pp_csc2_coef12 g3_ot_pp_csc2_coef12; /* 0x8968 */ -+ volatile u_g3_ot_pp_csc2_coef20 g3_ot_pp_csc2_coef20; /* 0x896c */ -+ volatile u_g3_ot_pp_csc2_coef21 g3_ot_pp_csc2_coef21; /* 0x8970 */ -+ volatile u_g3_ot_pp_csc2_coef22 g3_ot_pp_csc2_coef22; /* 0x8974 */ -+ volatile u_g3_ot_pp_csc2_scale g3_ot_pp_csc2_scale; /* 0x8978 */ -+ volatile u_g3_ot_pp_csc2_idc0 g3_ot_pp_csc2_idc0; /* 0x897c */ -+ volatile u_g3_ot_pp_csc2_idc1 g3_ot_pp_csc2_idc1; /* 0x8980 */ -+ volatile u_g3_ot_pp_csc2_idc2 g3_ot_pp_csc2_idc2; /* 0x8984 */ -+ volatile u_g3_ot_pp_csc2_odc0 g3_ot_pp_csc2_odc0; /* 0x8988 */ -+ volatile u_g3_ot_pp_csc2_odc1 g3_ot_pp_csc2_odc1; /* 0x898c */ -+ volatile u_g3_ot_pp_csc2_odc2 g3_ot_pp_csc2_odc2; /* 0x8990 */ -+ volatile u_g3_ot_pp_csc2_min_y g3_ot_pp_csc2_min_y; /* 0x8994 */ -+ volatile u_g3_ot_pp_csc2_min_c g3_ot_pp_csc2_min_c; /* 0x8998 */ -+ volatile u_g3_ot_pp_csc2_max_y g3_ot_pp_csc2_max_y; /* 0x899c */ -+ volatile u_g3_ot_pp_csc2_max_c g3_ot_pp_csc2_max_c; /* 0x89a0 */ -+ volatile unsigned int reserved_78[19]; /* 19:0x89a4~0x89ec */ -+ volatile u_g3_ot_pp_csc_ink_ctrl g3_ot_pp_csc_ink_ctrl; /* 0x89f0 */ -+ volatile u_g3_ot_pp_csc_ink_pos g3_ot_pp_csc_ink_pos; /* 0x89f4 */ -+ volatile unsigned int g3_ot_pp_csc_ink_data; /* 0x89f8 */ -+ volatile unsigned int g3_ot_pp_csc_ink_data2; /* 0x89fc */ -+ volatile u_osb_mute_bk osb_mute_bk; /* 0x8a00 */ -+ volatile u_osb_bk_alpha osb_bk_alpha; /* 0x8a04 */ -+ volatile u_osb_coef_rd_en osb_coef_rd_en; /* 0x8a08 */ -+ volatile unsigned int osb_coef_rd_addr; /* 0x8a0c */ -+ volatile unsigned int reserved_79[892]; /* 892:0x8a10~0x97fc 892 regs */ -+ volatile unsigned int gp0_ctrl; /* 0x9800 */ -+ volatile u_gp0_upd gp0_upd; /* 0x9804 */ -+ volatile u_gp0_ireso gp0_ireso; /* 0x9808 */ -+ volatile unsigned int reserved_80[29]; /* 29:0x980c~0x987c */ -+ volatile u_gp0_lbox_ctrl gp0_lbox_ctrl; /* 0x9880 */ -+ volatile u_gp0_galpha gp0_galpha; /* 0x9884 */ -+ volatile unsigned int gp0_galpha_sum; /* 0x9888 */ -+ volatile u_gp0_dfpos gp0_dfpos; /* 0x988c */ -+ volatile u_gp0_dlpos gp0_dlpos; /* 0x9890 */ -+ volatile u_gp0_vfpos gp0_vfpos; /* 0x9894 */ -+ volatile u_gp0_vlpos gp0_vlpos; /* 0x9898 */ -+ volatile u_gp0_bk gp0_bk; /* 0x989c */ -+ volatile u_gp0_alpha gp0_alpha; /* 0x98a0 */ -+ volatile u_gp0_mute_bk gp0_mute_bk; /* 0x98a4 */ -+ volatile unsigned int reserved_81[22]; /* 22:0x98a8~0x98fc */ -+ volatile u_gp0_csc_idc gp0_csc_idc; /* 0x9900 */ -+ volatile u_gp0_csc_odc gp0_csc_odc; /* 0x9904 */ -+ volatile u_gp0_csc_iodc gp0_csc_iodc; /* 0x9908 */ -+ volatile u_gp0_csc_p0 gp0_csc_p0; /* 0x990c */ -+ volatile u_gp0_csc_p1 gp0_csc_p1; /* 0x9910 */ -+ volatile u_gp0_csc_p2 gp0_csc_p2; /* 0x9914 */ -+ volatile u_gp0_csc_p3 gp0_csc_p3; /* 0x9918 */ -+ volatile u_gp0_csc_p4 gp0_csc_p4; /* 0x991c */ -+ volatile unsigned int reserved_82[1464]; /* 1464:0x9920~0xaffc */ -+ volatile u_wbc_g0_ctrl wbc_g0_ctrl; /* 0xb000 */ -+ volatile u_wbc_g0_upd wbc_g0_upd; /* 0xb004 */ -+ volatile u_wbc_g0_cmp wbc_g0_cmp; /* 0xb008 */ -+ volatile unsigned int reserved_83; /* 0xb00c */ -+ volatile unsigned int wbc_g0_ar_addr; /* 0xb010 */ -+ volatile unsigned int wbc_g0_gb_addr; /* 0xb014 */ -+ volatile u_wbc_g0_stride wbc_g0_stride; /* 0xb018 */ -+ volatile unsigned int wbc_g0_offset; /* 0xb01c */ -+ volatile u_wbc_g0_oreso wbc_g0_oreso; /* 0xb020 */ -+ volatile u_wbc_g0_fcrop wbc_g0_fcrop; /* 0xb024 */ -+ volatile u_wbc_g0_lcrop wbc_g0_lcrop; /* 0xb028 */ -+ volatile unsigned int reserved_84[501]; /* 501:0xb02c~0xb7fc */ -+ volatile u_wbc_gp0_ctrl wbc_gp0_ctrl; /* 0xb800 */ -+ volatile u_wbc_gp0_upd wbc_gp0_upd; /* 0xb804 */ -+ volatile unsigned int reserved_85[2]; /* 2:0xb808~0xb80c */ -+ volatile unsigned int wbc_gp0_yaddr; /* 0xb810 */ -+ volatile unsigned int wbc_gp0_caddr; /* 0xb814 */ -+ volatile u_wbc_gp0_stride wbc_gp0_stride; /* 0xb818 */ -+ volatile unsigned int reserved_86; /* 0xb81c */ -+ volatile u_wbc_gp0_oreso wbc_gp0_oreso; /* 0xb820 */ -+ volatile u_wbc_gp0_fcrop wbc_gp0_fcrop; /* 0xb824 */ -+ volatile u_wbc_gp0_lcrop wbc_gp0_lcrop; /* 0xb828 */ -+ volatile unsigned int reserved_87[53]; /* 53:0xb82c~0xb8fc */ -+ volatile u_wbc_gp0_dither_ctrl wbc_gp0_dither_ctrl; /* 0xb900 */ -+ volatile u_wbc_gp0_dither_coef0 wbc_gp0_dither_coef0; /* 0xb904 */ -+ volatile u_wbc_gp0_dither_coef1 wbc_gp0_dither_coef1; /* 0xb908 */ -+ volatile unsigned int reserved_88[17]; /* 17:0xb90c~0xb94c */ -+ volatile u_wbc_gp0_hpzme wbc_gp0_hpzme; /* 0xb950 */ -+ volatile unsigned int reserved_89[43]; /* 43:0xb954~0xb9fc */ -+ volatile u_wbc_me_ctrl wbc_me_ctrl; /* 0xba00 */ -+ volatile u_wbc_me_upd wbc_me_upd; /* 0xba04 */ -+ volatile u_wbc_me_wlen_sel wbc_me_wlen_sel; /* 0xba08 */ -+ volatile unsigned int reserved_90; /* 0xba0c */ -+ volatile unsigned int wbc_me_yaddr; /* 0xba10 */ -+ volatile unsigned int wbc_me_caddr; /* 0xba14 */ -+ volatile u_wbc_me_stride wbc_me_stride; /* 0xba18 */ -+ volatile unsigned int reserved_91; /* 0xba1c */ -+ volatile u_wbc_me_oreso wbc_me_oreso; /* 0xba20 */ -+ volatile unsigned int reserved_92[2]; /* 2:0xba24~0xba28 */ -+ volatile u_wbc_me_smmu_bypass wbc_me_smmu_bypass; /* 0xba2c */ -+ volatile unsigned int reserved_93[4]; /* 4:0xba30~0xba3c */ -+ volatile u_wbc_me_paraup wbc_me_paraup; /* 0xba40 */ -+ volatile unsigned int reserved_94[3]; /* 3:0xba44~0xba4c */ -+ volatile unsigned int wbc_me_hlcoefad; /* 0xba50 */ -+ volatile unsigned int wbc_me_hccoefad; /* 0xba54 */ -+ volatile unsigned int wbc_me_vlcoefad; /* 0xba58 */ -+ volatile unsigned int wbc_me_vccoefad; /* 0xba5c */ -+ volatile unsigned int reserved_95[36]; /* 36:0xba60~0xbaec */ -+ volatile unsigned int wbc_me_checksum_y; /* 0xbaf0 */ -+ volatile unsigned int wbc_me_checksum_c; /* 0xbaf4 */ -+ volatile unsigned int reserved_96[2]; /* 2:0xbaf8~0xbafc */ -+ volatile u_wbc_me_dither_ctrl wbc_me_dither_ctrl; /* 0xbb00 */ -+ volatile u_wbc_me_dither_coef0 wbc_me_dither_coef0; /* 0xbb04 */ -+ volatile u_wbc_me_dither_coef1 wbc_me_dither_coef1; /* 0xbb08 */ -+ volatile unsigned int reserved_97[109]; /* 109:0xbb0c~0xbcbc */ -+ volatile u_wbc_me_zme_hsp wbc_me_zme_hsp; /* 0xbcc0 */ -+ volatile u_wbc_me_zme_hloffset wbc_me_zme_hloffset; /* 0xbcc4 */ -+ volatile u_wbc_me_zme_hcoffset wbc_me_zme_hcoffset; /* 0xbcc8 */ -+ volatile unsigned int reserved_98[3]; /* 3:0xbccc~0xbcd4 */ -+ volatile u_wbc_me_zme_vsp wbc_me_zme_vsp; /* 0xbcd8 */ -+ volatile u_wbc_me_zme_vsr wbc_me_zme_vsr; /* 0xbcdc */ -+ volatile u_wbc_me_zme_voffset wbc_me_zme_voffset; /* 0xbce0 */ -+ volatile u_wbc_me_zme_vboffset wbc_me_zme_vboffset; /* 0xbce4 */ -+ volatile unsigned int reserved_99[6]; /* 6:0xbce8~0xbcfc */ -+ volatile u_wbc_fi_ctrl wbc_fi_ctrl; /* 0xbd00 */ -+ volatile u_wbc_fi_upd wbc_fi_upd; /* 0xbd04 */ -+ volatile u_wbc_fi_wlen_sel wbc_fi_wlen_sel; /* 0xbd08 */ -+ volatile unsigned int reserved_100; /* 0xbd0c */ -+ volatile unsigned int wbc_fi_yaddr; /* 0xbd10 */ -+ volatile unsigned int wbc_fi_caddr; /* 0xbd14 */ -+ volatile u_wbc_fi_stride wbc_fi_stride; /* 0xbd18 */ -+ volatile unsigned int reserved_101; /* 0xbd1c */ -+ volatile u_wbc_fi_oreso wbc_fi_oreso; /* 0xbd20 */ -+ volatile unsigned int reserved_102[2]; /* 2:0xbd24~0xbd28 */ -+ volatile u_wbc_fi_smmu_bypass wbc_fi_smmu_bypass; /* 0xbd2c */ -+ volatile unsigned int reserved_103[5]; /* 5:0xbd30~0xbd40 */ -+ volatile u_wbc_fi_frame_size wbc_fi_frame_size; /* 0xbd44 */ -+ volatile unsigned int wbc_fi_y_raddr; /* 0xbd48 */ -+ volatile unsigned int wbc_fi_c_raddr; /* 0xbd4c */ -+ volatile unsigned int reserved_104[40]; /* 40:0xbd50~0xbdec */ -+ volatile unsigned int wbc_fi_checksum_y; /* 0xbdf0 */ -+ volatile unsigned int wbc_fi_checksum_c; /* 0xbdf4 */ -+ volatile unsigned int reserved_105[6]; /* 6:0xbdf8~0xbe0c */ -+ volatile u_wbc_fi_hcds wbc_fi_hcds; /* 0xbe10 */ -+ volatile u_wbc_fi_hcds_coef0 wbc_fi_hcds_coef0; /* 0xbe14 */ -+ volatile u_wbc_fi_hcds_coef1 wbc_fi_hcds_coef1; /* 0xbe18 */ -+ volatile unsigned int reserved_106; /* 0xbe1c */ -+ volatile u_wbc_fi_cmp_mb wbc_fi_cmp_mb; /* 0xbe20 */ -+ volatile u_wbc_fi_cmp_max_min wbc_fi_cmp_max_min; /* 0xbe24 */ -+ volatile u_wbc_fi_cmp_adj_thr wbc_fi_cmp_adj_thr; /* 0xbe28 */ -+ volatile u_wbc_fi_cmp_big_grad wbc_fi_cmp_big_grad; /* 0xbe2c */ -+ volatile u_wbc_fi_cmp_blk wbc_fi_cmp_blk; /* 0xbe30 */ -+ volatile u_wbc_fi_cmp_graphic_judge wbc_fi_cmp_graphic_judge; /* 0xbe34 */ -+ volatile u_wbc_fi_cmp_rc wbc_fi_cmp_rc; /* 0xbe38 */ -+ volatile u_wbc_fi_cmp_frame_size wbc_fi_cmp_frame_size; /* 0xbe3c */ -+ volatile unsigned int reserved_107[48]; /* 48:0xbe40~0xbefc */ -+ volatile u_wbc_cmp_glb_info wbc_cmp_glb_info; /* 0xbf00 */ -+ volatile u_wbc_cmp_framesize wbc_cmp_framesize; /* 0xbf04 */ -+ volatile u_wbc_cmp_rc_cfg0 wbc_cmp_rc_cfg0; /* 0xbf08 */ -+ volatile u_wbc_cmp_rc_cfg2 wbc_cmp_rc_cfg2; /* 0xbf0c */ -+ volatile u_wbc_cmp_rc_cfg3 wbc_cmp_rc_cfg3; /* 0xbf10 */ -+ volatile u_wbc_cmp_rc_cfg4 wbc_cmp_rc_cfg4; /* 0xbf14 */ -+ volatile u_wbc_cmp_rc_cfg5 wbc_cmp_rc_cfg5; /* 0xbf18 */ -+ volatile u_wbc_cmp_rc_cfg6 wbc_cmp_rc_cfg6; /* 0xbf1c */ -+ volatile u_wbc_cmp_rc_cfg7 wbc_cmp_rc_cfg7; /* 0xbf20 */ -+ volatile u_wbc_cmp_rc_cfg8 wbc_cmp_rc_cfg8; /* 0xbf24 */ -+ volatile u_wbc_cmp_rc_cfg10 wbc_cmp_rc_cfg10; /* 0xbf28 */ -+ volatile u_wbc_cmp_outsize0 wbc_cmp_outsize0; /* 0xbf2c */ -+ volatile unsigned int wbc_cmp_dbg_reg0; /* 0xbf30 */ -+ volatile u_wbc_cmp_max_row wbc_cmp_max_row; /* 0xbf34 */ -+ volatile u_wbc_bmp_ctrl wbc_bmp_ctrl; /* 0xbf38 */ -+ volatile u_wbc_bmp_upd wbc_bmp_upd; /* 0xbf3c */ -+ volatile unsigned int wbc_bmp_yaddr; /* 0xbf40 */ -+ volatile unsigned int reserved_108[23]; /* 23:0xbf44~0xbf9c */ -+ volatile u_wbc_bmp_oreso wbc_bmp_oreso; /* 0xbfa0 */ -+ volatile u_wbc_bmp_sum wbc_bmp_sum; /* 0xbfa4 */ -+ volatile unsigned int reserved_109[18]; /* 18:0xbfa8~0xbfec */ -+ volatile unsigned int wbc_bmp_checksum_y; /* 0xbff0 */ -+ volatile unsigned int wbc_bmp_checksum_c; /* 0xbff4 */ -+ volatile unsigned int reserved_110[2]; /* 2:0xbff8~0xbffc */ -+ volatile u_wbc_dhd0_ctrl wbc_dhd0_ctrl; /* 0xc000 */ -+ volatile u_wbc_dhd0_upd wbc_dhd0_upd; /* 0xc004 */ -+ volatile u_wbc_dhd0_oreso wbc_dhd0_oreso; /* 0xc008 */ -+ volatile unsigned int reserved_111[29]; /* 29:0xc00c~0xc07c */ -+ volatile u_wd_hpzme_ctrl wd_hpzme_ctrl; /* 0xc080 */ -+ volatile u_wd_hpzmecoef01 wd_hpzmecoef01; /* 0xc084 */ -+ volatile u_wd_hpzmecoef23 wd_hpzmecoef23; /* 0xc088 */ -+ volatile u_wd_hpzmecoef45 wd_hpzmecoef45; /* 0xc08c */ -+ volatile u_wd_hpzmecoef67 wd_hpzmecoef67; /* 0xc090 */ -+ volatile unsigned int reserved_112[91]; /* 91:0xc094~0xc1fc */ -+ volatile u_wd_hcds_ctrl wd_hcds_ctrl; /* 0xc200 */ -+ volatile u_wd_hcdscoef01 wd_hcdscoef01; /* 0xc204 */ -+ volatile u_wd_hcdscoef23 wd_hcdscoef23; /* 0xc208 */ -+ volatile u_wd_hcdscoef45 wd_hcdscoef45; /* 0xc20c */ -+ volatile u_wd_hcdscoef67 wd_hcdscoef67; /* 0xc210 */ -+ volatile unsigned int reserved_113[27]; /* 27:0xc214~0xc27c */ -+ volatile u_dither_ctrl dither_ctrl; /* 0xc280 */ -+ volatile u_dither_sed_y0 dither_sed_y0; /* 0xc284 */ -+ volatile u_dither_sed_u0 dither_sed_u0; /* 0xc288 */ -+ volatile u_dither_sed_v0 dither_sed_v0; /* 0xc28c */ -+ volatile u_dither_sed_w0 dither_sed_w0; /* 0xc290 */ -+ volatile u_dither_sed_y1 dither_sed_y1; /* 0xc294 */ -+ volatile u_dither_sed_u1 dither_sed_u1; /* 0xc298 */ -+ volatile u_dither_sed_v1 dither_sed_v1; /* 0xc29c */ -+ volatile u_dither_sed_w1 dither_sed_w1; /* 0xc2a0 */ -+ volatile u_dither_sed_y2 dither_sed_y2; /* 0xc2a4 */ -+ volatile u_dither_sed_u2 dither_sed_u2; /* 0xc2a8 */ -+ volatile u_dither_sed_v2 dither_sed_v2; /* 0xc2ac */ -+ volatile u_dither_sed_w2 dither_sed_w2; /* 0xc2b0 */ -+ volatile u_dither_sed_y3 dither_sed_y3; /* 0xc2b4 */ -+ volatile u_dither_sed_u3 dither_sed_u3; /* 0xc2b8 */ -+ volatile u_dither_sed_v3 dither_sed_v3; /* 0xc2bc */ -+ volatile u_dither_sed_w3 dither_sed_w3; /* 0xc2c0 */ -+ volatile u_dither_thr dither_thr; /* 0xc2c4 */ -+ volatile unsigned int reserved_114[14]; /* 14:0xc2c8~0xc2fc */ -+ volatile u_wd_zme_hinfo wd_zme_hinfo; /* 0xc300 */ -+ volatile u_wd_zme_hsp wd_zme_hsp; /* 0xc304 */ -+ volatile u_wd_zme_hloffset wd_zme_hloffset; /* 0xc308 */ -+ volatile u_wd_zme_hcoffset wd_zme_hcoffset; /* 0xc30c */ -+ volatile unsigned int reserved_115[5]; /* 5:0xc310~0xc320 */ -+ volatile u_wd_zme_hcoef_ren wd_zme_hcoef_ren; /* 0xc324 */ -+ volatile u_wd_zme_hcoef_rdata wd_zme_hcoef_rdata; /* 0xc328 */ -+ volatile u_wd_zme_hdraw wd_zme_hdraw; /* 0xc32c */ -+ volatile u_wd_zme_hratio wd_zme_hratio; /* 0xc330 */ -+ volatile unsigned int reserved_116[51]; /* 51:0xc334~0xc3fc */ -+ volatile u_wd_zme_vinfo wd_zme_vinfo; /* 0xc400 */ -+ volatile u_wd_zme_vsp wd_zme_vsp; /* 0xc404 */ -+ volatile u_wd_zme_voffset wd_zme_voffset; /* 0xc408 */ -+ volatile u_wd_zme_vboffset wd_zme_vboffset; /* 0xc40c */ -+ volatile unsigned int reserved_117[5]; /* 5:0xc410~0xc420 */ -+ volatile u_wd_zme_vcoef_ren wd_zme_vcoef_ren; /* 0xc424 */ -+ volatile u_wd_zme_vcoef_rdata wd_zme_vcoef_rdata; /* 0xc428 */ -+ volatile u_wd_zme_vdraw wd_zme_vdraw; /* 0xc42c */ -+ volatile u_wd_zme_vratio wd_zme_vratio; /* 0xc430 */ -+ volatile unsigned int reserved_118[755]; /* 755:0xc434~0xcffc */ -+ volatile u_dhd0_ctrl dhd0_ctrl; /* 0xd000 */ -+ volatile u_dhd0_vsync1 dhd0_vsync1; /* 0xd004 */ -+ volatile u_dhd0_vsync2 dhd0_vsync2; /* 0xd008 */ -+ volatile u_dhd0_hsync1 dhd0_hsync1; /* 0xd00c */ -+ volatile u_dhd0_hsync2 dhd0_hsync2; /* 0xd010 */ -+ volatile u_dhd0_vplus1 dhd0_vplus1; /* 0xd014 */ -+ volatile u_dhd0_vplus2 dhd0_vplus2; /* 0xd018 */ -+ volatile u_dhd0_pwr dhd0_pwr; /* 0xd01c */ -+ volatile u_dhd0_vtthd3 dhd0_vtthd3; /* 0xd020 */ -+ volatile u_dhd0_vtthd dhd0_vtthd; /* 0xd024 */ -+ volatile u_dhd0_parathd dhd0_parathd; /* 0xd028 */ -+ volatile u_dhd0_precharge_thd dhd0_precharge_thd; /* 0xd02c */ -+ volatile u_dhd0_start_pos dhd0_start_pos; /* 0xd030 */ -+ volatile u_dhd0_start_pos1 dhd0_start_pos1; /* 0xd034 */ -+ volatile u_dhd0_paraup dhd0_paraup; /* 0xd038 */ -+ volatile u_dhd0_sync_inv dhd0_sync_inv; /* 0xd03c */ -+ volatile u_dhd0_clk_dv_ctrl dhd0_clk_dv_ctrl; /* 0xd040 */ -+ volatile u_dhd0_rgb_fix_ctrl dhd0_rgb_fix_ctrl; /* 0xd044 */ -+ volatile u_dhd0_lockcfg dhd0_lockcfg; /* 0xd048 */ -+ volatile unsigned int dhd0_cap_frm_cnt; /* 0xd04c */ -+ volatile unsigned int dhd0_vdp_frm_cnt; /* 0xd050 */ -+ volatile unsigned int dhd0_vsync_cap_vdp_cnt; /* 0xd054 */ -+ volatile unsigned int dhd0_intf_chksum_y; /* 0xd058 */ -+ volatile unsigned int dhd0_intf_chksum_u; /* 0xd05c */ -+ volatile unsigned int dhd0_intf_chksum_v; /* 0xd060 */ -+ volatile unsigned int dhd0_intf1_chksum_y; /* 0xd064 */ -+ volatile unsigned int dhd0_intf1_chksum_u; /* 0xd068 */ -+ volatile unsigned int dhd0_intf1_chksum_v; /* 0xd06c */ -+ volatile u_dhd0_intf_chksum_high1 dhd0_intf_chksum_high1; /* 0xd070 */ -+ volatile u_dhd0_intf_chksum_high2 dhd0_intf_chksum_high2; /* 0xd074 */ -+ volatile unsigned int reserved_119[3]; /* 3:0xd078~0xd080 */ -+ volatile unsigned int dhd0_afifo_pre_thd; /* 0xd084 */ -+ volatile u_dhd0_state dhd0_state; /* 0xd088 */ -+ volatile u_dhd0_uf_state dhd0_uf_state; /* 0xd08c */ -+ volatile u_vo_mux vo_mux; /* 0xd090 */ -+ volatile u_vo_mux_sync vo_mux_sync; /* 0xd094 */ -+ volatile u_vo_mux_data vo_mux_data; /* 0xd098 */ -+ volatile unsigned int reserved_120; /* 0xd09c */ -+ volatile u_dhd0_vsync_te_state dhd0_vsync_te_state; /* 0xd0a0 */ -+ volatile u_dhd0_vsync_te_state1 dhd0_vsync_te_state1; /* 0xd0a4 */ -+ volatile unsigned int reserved_121[6]; /* 6:0xd0a8~0xd0bc */ -+ volatile u_dhd0_ccdoimgmod dhd0_ccdoimgmod; /* 0xd0c0 */ -+ volatile u_dhd0_ccdoposmskh dhd0_ccdoposmskh; /* 0xd0c4 */ -+ volatile u_dhd0_ccdoposmskl dhd0_ccdoposmskl; /* 0xd0c8 */ -+ volatile unsigned int reserved_122; /* 0xd0cc */ -+ volatile u_dhd0_dacdet1 dhd0_dacdet1; /* 0xd0d0 */ -+ volatile u_dhd0_dacdet2 dhd0_dacdet2; /* 0xd0d4 */ -+ volatile unsigned int reserved_123[2]; /* 2:0xd0d8~0xd0dc */ -+ volatile u_dhd0_ccd_info1 dhd0_ccd_info1; /* 0xd0e0 */ -+ volatile u_dhd0_ccd_info2 dhd0_ccd_info2; /* 0xd0e4 */ -+ volatile u_dhd0_ccd_info3 dhd0_ccd_info3; /* 0xd0e8 */ -+ volatile unsigned int reserved_124[5]; /* 5:0xd0ec~0xd0fc */ -+ volatile u_intf_hdmi_ctrl intf_hdmi_ctrl; /* 0xd100 */ -+ volatile u_intf_hdmi_upd intf_hdmi_upd; /* 0xd104 */ -+ volatile u_intf_hdmi_sync_inv intf_hdmi_sync_inv; /* 0xd108 */ -+ volatile unsigned int reserved_125; /* 0xd10c */ -+ volatile unsigned int hdmi_intf_chksum_y; /* 0xd110 */ -+ volatile unsigned int hdmi_intf_chksum_u; /* 0xd114 */ -+ volatile unsigned int hdmi_intf_chksum_v; /* 0xd118 */ -+ volatile u_hdmi_intf_chksum_high hdmi_intf_chksum_high; /* 0xd11c */ -+ volatile unsigned int hdmi_intf1_chksum_y; /* 0xd120 */ -+ volatile unsigned int hdmi_intf1_chksum_u; /* 0xd124 */ -+ volatile unsigned int hdmi_intf1_chksum_v; /* 0xd128 */ -+ volatile u_hdmi_intf1_chksum_high hdmi_intf1_chksum_high; /* 0xd12c */ -+ volatile unsigned int reserved_126[8]; /* 8:0xd130~0xd14c */ -+ volatile u_hdmi_hfir_coef0 hdmi_hfir_coef0; /* 0xd150 */ -+ volatile u_hdmi_hfir_coef1 hdmi_hfir_coef1; /* 0xd154 */ -+ volatile u_hdmi_hfir_coef2 hdmi_hfir_coef2; /* 0xd158 */ -+ volatile u_hdmi_hfir_coef3 hdmi_hfir_coef3; /* 0xd15c */ -+ volatile u_hdmi_csc_idc hdmi_csc_idc; /* 0xd160 */ -+ volatile u_hdmi_csc_odc hdmi_csc_odc; /* 0xd164 */ -+ volatile u_hdmi_csc_iodc hdmi_csc_iodc; /* 0xd168 */ -+ volatile u_hdmi_csc_p0 hdmi_csc_p0; /* 0xd16c */ -+ volatile u_hdmi_csc_p1 hdmi_csc_p1; /* 0xd170 */ -+ volatile u_hdmi_csc_p2 hdmi_csc_p2; /* 0xd174 */ -+ volatile u_hdmi_csc_p3 hdmi_csc_p3; /* 0xd178 */ -+ volatile u_hdmi_csc_p4 hdmi_csc_p4; /* 0xd17c */ -+ volatile u_intf_mipi_ctrl intf_mipi_ctrl; /* 0xd180 */ -+ volatile u_intf_mipi_upd intf_mipi_upd; /* 0xd184 */ -+ volatile u_intf_mipi_sync_inv intf_mipi_sync_inv; /* 0xd188 */ -+ volatile unsigned int reserved_127; /* 0xd18c */ -+ volatile unsigned int mipi_intf_chksum_y; /* 0xd190 */ -+ volatile unsigned int mipi_intf_chksum_u; /* 0xd194 */ -+ volatile unsigned int mipi_intf_chksum_v; /* 0xd198 */ -+ volatile u_mipi_intf_chksum_high mipi_intf_chksum_high; /* 0xd19c */ -+ volatile unsigned int mipi_intf1_chksum_y; /* 0xd1a0 */ -+ volatile unsigned int mipi_intf1_chksum_u; /* 0xd1a4 */ -+ volatile unsigned int mipi_intf1_chksum_v; /* 0xd1a8 */ -+ volatile u_mipi_intf1_chksum_high mipi_intf1_chksum_high; /* 0xd1ac */ -+ volatile unsigned int reserved_128[8]; /* 8:0xd1b0~0xd1cc */ -+ volatile u_mipi_hfir_coef0 mipi_hfir_coef0; /* 0xd1d0 */ -+ volatile u_mipi_hfir_coef1 mipi_hfir_coef1; /* 0xd1d4 */ -+ volatile u_mipi_hfir_coef2 mipi_hfir_coef2; /* 0xd1d8 */ -+ volatile u_mipi_hfir_coef3 mipi_hfir_coef3; /* 0xd1dc */ -+ volatile unsigned int reserved_129[8]; /* 8:0xd1e0~0xd1fc */ -+ volatile u_intf_bt_ctrl intf_bt_ctrl; /* 0xd200 */ -+ volatile u_intf_bt_upd intf_bt_upd; /* 0xd204 */ -+ volatile u_intf_bt_sync_inv intf_bt_sync_inv; /* 0xd208 */ -+ volatile unsigned int reserved_130; /* 0xd20c */ -+ volatile u_bt_clip0_l bt_clip0_l; /* 0xd210 */ -+ volatile u_bt_clip0_h bt_clip0_h; /* 0xd214 */ -+ volatile unsigned int reserved_131[26]; /* 26:0xd218~0xd27c */ -+ volatile u_bt_dither_ctrl bt_dither_ctrl; /* 0xd280 */ -+ volatile u_bt_dither_sed_y0 bt_dither_sed_y0; /* 0xd284 */ -+ volatile u_bt_dither_sed_u0 bt_dither_sed_u0; /* 0xd288 */ -+ volatile u_bt_dither_sed_v0 bt_dither_sed_v0; /* 0xd28c */ -+ volatile u_bt_dither_sed_w0 bt_dither_sed_w0; /* 0xd290 */ -+ volatile u_bt_dither_sed_y1 bt_dither_sed_y1; /* 0xd294 */ -+ volatile u_bt_dither_sed_u1 bt_dither_sed_u1; /* 0xd298 */ -+ volatile u_bt_dither_sed_v1 bt_dither_sed_v1; /* 0xd29c */ -+ volatile u_bt_dither_sed_w1 bt_dither_sed_w1; /* 0xd2a0 */ -+ volatile u_bt_dither_sed_y2 bt_dither_sed_y2; /* 0xd2a4 */ -+ volatile u_bt_dither_sed_u2 bt_dither_sed_u2; /* 0xd2a8 */ -+ volatile u_bt_dither_sed_v2 bt_dither_sed_v2; /* 0xd2ac */ -+ volatile u_bt_dither_sed_w2 bt_dither_sed_w2; /* 0xd2b0 */ -+ volatile u_bt_dither_sed_y3 bt_dither_sed_y3; /* 0xd2b4 */ -+ volatile u_bt_dither_sed_u3 bt_dither_sed_u3; /* 0xd2b8 */ -+ volatile u_bt_dither_sed_v3 bt_dither_sed_v3; /* 0xd2bc */ -+ volatile u_bt_dither_sed_w3 bt_dither_sed_w3; /* 0xd2c0 */ -+ volatile u_bt_dither_thr bt_dither_thr; /* 0xd2c4 */ -+ volatile unsigned int reserved_132[10]; /* 10:0xd2c8~0xd2ec */ -+ volatile unsigned int bt_intf_chksum_y; /* 0xd2f0 */ -+ volatile unsigned int bt_intf_chksum_u; /* 0xd2f4 */ -+ volatile unsigned int bt_intf_chksum_v; /* 0xd2f8 */ -+ volatile unsigned int reserved_133; /* 0xd2fc */ -+ volatile u_intf_lcd_ctrl intf_lcd_ctrl; /* 0xd300 */ -+ volatile u_intf_lcd_upd intf_lcd_upd; /* 0xd304 */ -+ volatile u_intf_lcd_sync_inv intf_lcd_sync_inv; /* 0xd308 */ -+ volatile unsigned int reserved_134[29]; /* 29:0xd30c~0xd37c */ -+ volatile u_lcd_dither_ctrl lcd_dither_ctrl; /* 0xd380 */ -+ volatile u_lcd_dither_sed_y0 lcd_dither_sed_y0; /* 0xd384 */ -+ volatile u_lcd_dither_sed_u0 lcd_dither_sed_u0; /* 0xd388 */ -+ volatile u_lcd_dither_sed_v0 lcd_dither_sed_v0; /* 0xd38c */ -+ volatile u_lcd_dither_sed_w0 lcd_dither_sed_w0; /* 0xd390 */ -+ volatile u_lcd_dither_sed_y1 lcd_dither_sed_y1; /* 0xd394 */ -+ volatile u_lcd_dither_sed_u1 lcd_dither_sed_u1; /* 0xd398 */ -+ volatile u_lcd_dither_sed_v1 lcd_dither_sed_v1; /* 0xd39c */ -+ volatile u_lcd_dither_sed_w1 lcd_dither_sed_w1; /* 0xd3a0 */ -+ volatile u_lcd_dither_sed_y2 lcd_dither_sed_y2; /* 0xd3a4 */ -+ volatile u_lcd_dither_sed_u2 lcd_dither_sed_u2; /* 0xd3a8 */ -+ volatile u_lcd_dither_sed_v2 lcd_dither_sed_v2; /* 0xd3ac */ -+ volatile u_lcd_dither_sed_w2 lcd_dither_sed_w2; /* 0xd3b0 */ -+ volatile u_lcd_dither_sed_y3 lcd_dither_sed_y3; /* 0xd3b4 */ -+ volatile u_lcd_dither_sed_u3 lcd_dither_sed_u3; /* 0xd3b8 */ -+ volatile u_lcd_dither_sed_v3 lcd_dither_sed_v3; /* 0xd3bc */ -+ volatile u_lcd_dither_sed_w3 lcd_dither_sed_w3; /* 0xd3c0 */ -+ volatile u_lcd_dither_thr lcd_dither_thr; /* 0xd3c4 */ -+ volatile unsigned int reserved_135[10]; /* 10:0xd3c8~0xd3ec */ -+ volatile unsigned int lcd_intf_chksum_y; /* 0xd3f0 */ -+ volatile unsigned int lcd_intf_chksum_u; /* 0xd3f4 */ -+ volatile unsigned int lcd_intf_chksum_v; /* 0xd3f8 */ -+ volatile unsigned int reserved_136; /* 0xd3fc */ -+ volatile u_intf_hdmi1_ctrl intf_hdmi1_ctrl; /* 0xd400 */ -+ volatile u_intf_hdmi1_upd intf_hdmi1_upd; /* 0xd404 */ -+ volatile u_intf_hdmi1_sync_inv intf_hdmi1_sync_inv; /* 0xd408 */ -+ volatile unsigned int reserved_137; /* 0xd40c */ -+ volatile unsigned int hdmi1_intf_chksum_y; /* 0xd410 */ -+ volatile unsigned int hdmi1_intf_chksum_u; /* 0xd414 */ -+ volatile unsigned int hdmi1_intf_chksum_v; /* 0xd418 */ -+ volatile u_hdmi1_intf_chksum_high hdmi1_intf_chksum_high; /* 0xd41c */ -+ volatile unsigned int hdmi1_intf1_chksum_y; /* 0xd420 */ -+ volatile unsigned int hdmi1_intf1_chksum_u; /* 0xd424 */ -+ volatile unsigned int hdmi1_intf1_chksum_v; /* 0xd428 */ -+ volatile u_hdmi1_intf1_chksum_high hdmi1_intf1_chksum_high; /* 0xd42c */ -+ volatile unsigned int reserved_138[8]; /* 8:0xd430~0xd44c */ -+ volatile u_hdmi1_hfir_coef0 hdmi1_hfir_coef0; /* 0xd450 */ -+ volatile u_hdmi1_hfir_coef1 hdmi1_hfir_coef1; /* 0xd454 */ -+ volatile u_hdmi1_hfir_coef2 hdmi1_hfir_coef2; /* 0xd458 */ -+ volatile u_hdmi1_hfir_coef3 hdmi1_hfir_coef3; /* 0xd45c */ -+ volatile unsigned int reserved_139[40]; /* 40:0xd460~0xd4fc */ -+ volatile u_intf_vga_ctrl intf_vga_ctrl; /* 0xd500 */ -+ volatile u_intf_vga_upd intf_vga_upd; /* 0xd504 */ -+ volatile u_intf_vga_sync_inv intf_vga_sync_inv; /* 0xd508 */ -+ volatile unsigned int reserved_140[5]; /* 5:0xd50c~0xd51c */ -+ volatile u_vga_csc_idc vga_csc_idc; /* 0xd520 */ -+ volatile u_vga_csc_odc vga_csc_odc; /* 0xd524 */ -+ volatile u_vga_csc_iodc vga_csc_iodc; /* 0xd528 */ -+ volatile u_vga_csc_p0 vga_csc_p0; /* 0xd52c */ -+ volatile u_vga_csc_p1 vga_csc_p1; /* 0xd530 */ -+ volatile u_vga_csc_p2 vga_csc_p2; /* 0xd534 */ -+ volatile u_vga_csc_p3 vga_csc_p3; /* 0xd538 */ -+ volatile u_vga_csc_p4 vga_csc_p4; /* 0xd53c */ -+ volatile u_vga_hspcfg0 vga_hspcfg0; /* 0xd540 */ -+ volatile u_vga_hspcfg1 vga_hspcfg1; /* 0xd544 */ -+ volatile unsigned int reserved_141[3]; /* 3:0xd548~0xd550 */ -+ volatile u_vga_hspcfg5 vga_hspcfg5; /* 0xd554 */ -+ volatile u_vga_hspcfg6 vga_hspcfg6; /* 0xd558 */ -+ volatile u_vga_hspcfg7 vga_hspcfg7; /* 0xd55c */ -+ volatile u_vga_hspcfg8 vga_hspcfg8; /* 0xd560 */ -+ volatile unsigned int reserved_142[3]; /* 3:0xd564~0xd56c */ -+ volatile u_vga_hspcfg12 vga_hspcfg12; /* 0xd570 */ -+ volatile u_vga_hspcfg13 vga_hspcfg13; /* 0xd574 */ -+ volatile u_vga_hspcfg14 vga_hspcfg14; /* 0xd578 */ -+ volatile u_vga_hspcfg15 vga_hspcfg15; /* 0xd57c */ -+ volatile unsigned int reserved_143[28]; /* 28:0xd580~0xd5ec */ -+ volatile unsigned int vga_intf_chksum_y; /* 0xd5f0 */ -+ volatile unsigned int vga_intf_chksum_u; /* 0xd5f4 */ -+ volatile unsigned int vga_intf_chksum_v; /* 0xd5f8 */ -+ volatile unsigned int reserved_144; /* 0xd5fc */ -+ volatile u_intf_date_ctrl intf_date_ctrl; /* 0xd600 */ -+ volatile u_intf_date_upd intf_date_upd; /* 0xd604 */ -+ volatile u_intf_date_sync_inv intf_date_sync_inv; /* 0xd608 */ -+ volatile unsigned int reserved_145; /* 0xd60c */ -+ volatile u_date_clip0_l date_clip0_l; /* 0xd610 */ -+ volatile u_date_clip0_h date_clip0_h; /* 0xd614 */ -+ volatile unsigned int reserved_146[58]; /* 58:0xd618~0xd6fc */ -+ volatile u_intf0_dither_ctrl intf0_dither_ctrl; /* 0xd700 */ -+ volatile u_intf0_dither_sed_y0 intf0_dither_sed_y0; /* 0xd704 */ -+ volatile u_intf0_dither_sed_u0 intf0_dither_sed_u0; /* 0xd708 */ -+ volatile u_intf0_dither_sed_v0 intf0_dither_sed_v0; /* 0xd70c */ -+ volatile u_intf0_dither_sed_w0 intf0_dither_sed_w0; /* 0xd710 */ -+ volatile u_intf0_dither_sed_y1 intf0_dither_sed_y1; /* 0xd714 */ -+ volatile u_intf0_dither_sed_u1 intf0_dither_sed_u1; /* 0xd718 */ -+ volatile u_intf0_dither_sed_v1 intf0_dither_sed_v1; /* 0xd71c */ -+ volatile u_intf0_dither_sed_w1 intf0_dither_sed_w1; /* 0xd720 */ -+ volatile u_intf0_dither_sed_y2 intf0_dither_sed_y2; /* 0xd724 */ -+ volatile u_intf0_dither_sed_u2 intf0_dither_sed_u2; /* 0xd728 */ -+ volatile u_intf0_dither_sed_v2 intf0_dither_sed_v2; /* 0xd72c */ -+ volatile u_intf0_dither_sed_w2 intf0_dither_sed_w2; /* 0xd730 */ -+ volatile u_intf0_dither_sed_y3 intf0_dither_sed_y3; /* 0xd734 */ -+ volatile u_intf0_dither_sed_u3 intf0_dither_sed_u3; /* 0xd738 */ -+ volatile u_intf0_dither_sed_v3 intf0_dither_sed_v3; /* 0xd73c */ -+ volatile u_intf0_dither_sed_w3 intf0_dither_sed_w3; /* 0xd740 */ -+ volatile u_intf0_dither_thr intf0_dither_thr; /* 0xd744 */ -+ volatile unsigned int reserved_147[558]; /* 558:0xd748~0xdffc */ -+ volatile u_dhd1_ctrl dhd1_ctrl; /* 0xe000 */ -+ volatile u_dhd1_vsync1 dhd1_vsync1; /* 0xe004 */ -+ volatile u_dhd1_vsync2 dhd1_vsync2; /* 0xe008 */ -+ volatile u_dhd1_hsync1 dhd1_hsync1; /* 0xe00c */ -+ volatile u_dhd1_hsync2 dhd1_hsync2; /* 0xe010 */ -+ volatile u_dhd1_vplus1 dhd1_vplus1; /* 0xe014 */ -+ volatile u_dhd1_vplus2 dhd1_vplus2; /* 0xe018 */ -+ volatile u_dhd1_pwr dhd1_pwr; /* 0xe01c */ -+ volatile u_dhd1_vtthd3 dhd1_vtthd3; /* 0xe020 */ -+ volatile u_dhd1_vtthd dhd1_vtthd; /* 0xe024 */ -+ volatile u_dhd1_parathd dhd1_parathd; /* 0xe028 */ -+ volatile u_dhd1_precharge_thd dhd1_precharge_thd; /* 0xe02c */ -+ volatile u_dhd1_start_pos dhd1_start_pos; /* 0xe030 */ -+ volatile u_dhd1_start_pos1 dhd1_start_pos1; /* 0xe034 */ -+ volatile u_dhd1_paraup dhd1_paraup; /* 0xe038 */ -+ volatile u_dhd1_sync_inv dhd1_sync_inv; /* 0xe03c */ -+ volatile u_dhd1_clk_dv_ctrl dhd1_clk_dv_ctrl; /* 0xe040 */ -+ volatile u_dhd1_rgb_fix_ctrl dhd1_rgb_fix_ctrl; /* 0xe044 */ -+ volatile u_dhd1_lockcfg dhd1_lockcfg; /* 0xe048 */ -+ volatile unsigned int dhd1_cap_frm_cnt; /* 0xe04c */ -+ volatile unsigned int dhd1_vdp_frm_cnt; /* 0xe050 */ -+ volatile unsigned int dhd1_vsync_cap_vdp_cnt; /* 0xe054 */ -+ volatile unsigned int dhd1_intf_chksum_y; /* 0xe058 */ -+ volatile unsigned int dhd1_intf_chksum_u; /* 0xe05c */ -+ volatile unsigned int dhd1_intf_chksum_v; /* 0xe060 */ -+ volatile unsigned int dhd1_intf1_chksum_y; /* 0xe064 */ -+ volatile unsigned int dhd1_intf1_chksum_u; /* 0xe068 */ -+ volatile unsigned int dhd1_intf1_chksum_v; /* 0xe06c */ -+ volatile u_dhd1_intf_chksum_high1 dhd1_intf_chksum_high1; /* 0xe070 */ -+ volatile u_dhd1_intf_chksum_high2 dhd1_intf_chksum_high2; /* 0xe074 */ -+ volatile unsigned int reserved_148[3]; /* 3:0xe078~0xe080 */ -+ volatile unsigned int dhd1_afifo_pre_thd; /* 0xe084 */ -+ volatile u_dhd1_state dhd1_state; /* 0xe088 */ -+ volatile u_dhd1_uf_state dhd1_uf_state; /* 0xe08c */ -+ volatile unsigned int reserved_149[4]; /* 4:0xe090~0xe09c */ -+ volatile u_dhd1_vsync_te_state dhd1_vsync_te_state; /* 0xe0a0 */ -+ volatile u_dhd1_vsync_te_state1 dhd1_vsync_te_state1; /* 0xe0a4 */ -+ volatile unsigned int reserved_150[406]; /* 406:0xe0a8~0xe6fc */ -+ volatile u_intf1_dither_ctrl intf1_dither_ctrl; /* 0xe700 */ -+ volatile u_intf1_dither_sed_y0 intf1_dither_sed_y0; /* 0xe704 */ -+ volatile u_intf1_dither_sed_u0 intf1_dither_sed_u0; /* 0xe708 */ -+ volatile u_intf1_dither_sed_v0 intf1_dither_sed_v0; /* 0xe70c */ -+ volatile u_intf1_dither_sed_w0 intf1_dither_sed_w0; /* 0xe710 */ -+ volatile u_intf1_dither_sed_y1 intf1_dither_sed_y1; /* 0xe714 */ -+ volatile u_intf1_dither_sed_u1 intf1_dither_sed_u1; /* 0xe718 */ -+ volatile u_intf1_dither_sed_v1 intf1_dither_sed_v1; /* 0xe71c */ -+ volatile u_intf1_dither_sed_w1 intf1_dither_sed_w1; /* 0xe720 */ -+ volatile u_intf1_dither_sed_y2 intf1_dither_sed_y2; /* 0xe724 */ -+ volatile u_intf1_dither_sed_u2 intf1_dither_sed_u2; /* 0xe728 */ -+ volatile u_intf1_dither_sed_v2 intf1_dither_sed_v2; /* 0xe72c */ -+ volatile u_intf1_dither_sed_w2 intf1_dither_sed_w2; /* 0xe730 */ -+ volatile u_intf1_dither_sed_y3 intf1_dither_sed_y3; /* 0xe734 */ -+ volatile u_intf1_dither_sed_u3 intf1_dither_sed_u3; /* 0xe738 */ -+ volatile u_intf1_dither_sed_v3 intf1_dither_sed_v3; /* 0xe73c */ -+ volatile u_intf1_dither_sed_w3 intf1_dither_sed_w3; /* 0xe740 */ -+ volatile u_intf1_dither_thr intf1_dither_thr; /* 0xe744 */ -+ volatile unsigned int reserved_151[558]; /* 558:0xe748~0xeffc */ -+ volatile u_dhd2_ctrl dhd2_ctrl; /* 0xf000 */ -+ volatile u_dhd2_vsync1 dhd2_vsync1; /* 0xf004 */ -+ volatile u_dhd2_vsync2 dhd2_vsync2; /* 0xf008 */ -+ volatile u_dhd2_hsync1 dhd2_hsync1; /* 0xf00c */ -+ volatile u_dhd2_hsync2 dhd2_hsync2; /* 0xf010 */ -+ volatile u_dhd2_vplus1 dhd2_vplus1; /* 0xf014 */ -+ volatile u_dhd2_vplus2 dhd2_vplus2; /* 0xf018 */ -+ volatile u_dhd2_pwr dhd2_pwr; /* 0xf01c */ -+ volatile u_dhd2_vtthd3 dhd2_vtthd3; /* 0xf020 */ -+ volatile u_dhd2_vtthd dhd2_vtthd; /* 0xf024 */ -+ volatile u_dhd2_parathd dhd2_parathd; /* 0xf028 */ -+ volatile u_dhd2_precharge_thd dhd2_precharge_thd; /* 0xf02c */ -+ volatile u_dhd2_start_pos dhd2_start_pos; /* 0xf030 */ -+ volatile u_dhd2_start_pos1 dhd2_start_pos1; /* 0xf034 */ -+ volatile u_dhd2_paraup dhd2_paraup; /* 0xf038 */ -+ volatile u_dhd2_sync_inv dhd2_sync_inv; /* 0xf03c */ -+ volatile u_dhd2_clk_dv_ctrl dhd2_clk_dv_ctrl; /* 0xf040 */ -+ volatile u_dhd2_rgb_fix_ctrl dhd2_rgb_fix_ctrl; /* 0xf044 */ -+ volatile u_dhd2_lockcfg dhd2_lockcfg; /* 0xf048 */ -+ volatile unsigned int dhd2_cap_frm_cnt; /* 0xf04c */ -+ volatile unsigned int dhd2_vdp_frm_cnt; /* 0xf050 */ -+ volatile unsigned int dhd2_vsync_cap_vdp_cnt; /* 0xf054 */ -+ volatile unsigned int dhd2_intf_chksum_y; /* 0xf058 */ -+ volatile unsigned int dhd2_intf_chksum_u; /* 0xf05c */ -+ volatile unsigned int dhd2_intf_chksum_v; /* 0xf060 */ -+ volatile unsigned int dhd2_intf1_chksum_y; /* 0xf064 */ -+ volatile unsigned int dhd2_intf1_chksum_u; /* 0xf068 */ -+ volatile unsigned int dhd2_intf1_chksum_v; /* 0xf06c */ -+ volatile u_dhd2_intf_chksum_high1 dhd2_intf_chksum_high1; /* 0xf070 */ -+ volatile u_dhd2_intf_chksum_high2 dhd2_intf_chksum_high2; /* 0xf074 */ -+ volatile unsigned int reserved_152[3]; /* 3:0xf078~0xf080 */ -+ volatile unsigned int dhd2_afifo_pre_thd; /* 0xf084 */ -+ volatile u_dhd2_state dhd2_state; /* 0xf088 */ -+ volatile u_dhd2_uf_state dhd2_uf_state; /* 0xf08c */ -+ volatile unsigned int reserved_153[4]; /* 4:0xf090~0xf09c */ -+ volatile u_dhd2_vsync_te_state dhd2_vsync_te_state; /* 0xf0a0 */ -+ volatile u_dhd2_vsync_te_state1 dhd2_vsync_te_state1; /* 0xf0a4 */ -+ volatile unsigned int reserved_154[406]; /* 406:0xf0a8~0xf6fc */ -+ volatile u_intf2_dither_ctrl intf2_dither_ctrl; /* 0xf700 */ -+ volatile u_intf2_dither_sed_y0 intf2_dither_sed_y0; /* 0xf704 */ -+ volatile u_intf2_dither_sed_u0 intf2_dither_sed_u0; /* 0xf708 */ -+ volatile u_intf2_dither_sed_v0 intf2_dither_sed_v0; /* 0xf70c */ -+ volatile u_intf2_dither_sed_w0 intf2_dither_sed_w0; /* 0xf710 */ -+ volatile u_intf2_dither_sed_y1 intf2_dither_sed_y1; /* 0xf714 */ -+ volatile u_intf2_dither_sed_u1 intf2_dither_sed_u1; /* 0xf718 */ -+ volatile u_intf2_dither_sed_v1 intf2_dither_sed_v1; /* 0xf71c */ -+ volatile u_intf2_dither_sed_w1 intf2_dither_sed_w1; /* 0xf720 */ -+ volatile u_intf2_dither_sed_y2 intf2_dither_sed_y2; /* 0xf724 */ -+ volatile u_intf2_dither_sed_u2 intf2_dither_sed_u2; /* 0xf728 */ -+ volatile u_intf2_dither_sed_v2 intf2_dither_sed_v2; /* 0xf72c */ -+ volatile u_intf2_dither_sed_w2 intf2_dither_sed_w2; /* 0xf730 */ -+ volatile u_intf2_dither_sed_y3 intf2_dither_sed_y3; /* 0xf734 */ -+ volatile u_intf2_dither_sed_u3 intf2_dither_sed_u3; /* 0xf738 */ -+ volatile u_intf2_dither_sed_v3 intf2_dither_sed_v3; /* 0xf73c */ -+ volatile u_intf2_dither_sed_w3 intf2_dither_sed_w3; /* 0xf740 */ -+ volatile u_intf2_dither_thr intf2_dither_thr; /* 0xf744 */ -+ volatile unsigned int reserved_155[46]; /* 46:0xf748~0xf7fc */ -+ volatile u_date_coeff0 date_coeff0; /* 0xf800 */ -+ volatile u_date_coeff1 date_coeff1; /* 0xf804 */ -+ volatile unsigned int date_coeff2; /* 0xf808 */ -+ volatile u_date_coeff3 date_coeff3; /* 0xf80c */ -+ volatile u_date_coeff4 date_coeff4; /* 0xf810 */ -+ volatile u_date_coeff5 date_coeff5; /* 0xf814 */ -+ volatile u_date_coeff6 date_coeff6; /* 0xf818 */ -+ volatile u_date_coeff7 date_coeff7; /* 0xf81c */ -+ volatile unsigned int date_coeff8; /* 0xf820 */ -+ volatile unsigned int date_coeff9; /* 0xf824 */ -+ volatile u_date_coeff10 date_coeff10; /* 0xf828 */ -+ volatile u_date_coeff11 date_coeff11; /* 0xf82c */ -+ volatile u_date_coeff12 date_coeff12; /* 0xf830 */ -+ volatile u_date_coeff13 date_coeff13; /* 0xf834 */ -+ volatile u_date_coeff14 date_coeff14; /* 0xf838 */ -+ volatile u_date_coeff15 date_coeff15; /* 0xf83c */ -+ volatile u_date_coeff16 date_coeff16; /* 0xf840 */ -+ volatile unsigned int date_coeff17; /* 0xf844 */ -+ volatile unsigned int date_coeff18; /* 0xf848 */ -+ volatile u_date_coeff19 date_coeff19; /* 0xf84c */ -+ volatile u_date_coeff20 date_coeff20; /* 0xf850 */ -+ volatile u_date_coeff21 date_coeff21; /* 0xf854 */ -+ volatile u_date_coeff22 date_coeff22; /* 0xf858 */ -+ volatile u_date_coeff23 date_coeff23; /* 0xf85c */ -+ volatile unsigned int date_coeff24; /* 0xf860 */ -+ volatile u_date_coeff25 date_coeff25; /* 0xf864 */ -+ volatile u_date_coeff26 date_coeff26; /* 0xf868 */ -+ volatile u_date_coeff27 date_coeff27; /* 0xf86c */ -+ volatile u_date_coeff28 date_coeff28; /* 0xf870 */ -+ volatile u_date_coeff29 date_coeff29; /* 0xf874 */ -+ volatile u_date_coeff30 date_coeff30; /* 0xf878 */ -+ volatile unsigned int reserved_156; /* 0xf87c */ -+ volatile u_date_isrmask date_isrmask; /* 0xf880 */ -+ volatile u_date_isrstate date_isrstate; /* 0xf884 */ -+ volatile u_date_isr date_isr; /* 0xf888 */ -+ volatile unsigned int reserved_157; /* 0xf88c */ -+ volatile unsigned int date_version; /* 0xf890 */ -+ volatile u_date_coeff37 date_coeff37; /* 0xf894 */ -+ volatile u_date_coeff38 date_coeff38; /* 0xf898 */ -+ volatile u_date_coeff39 date_coeff39; /* 0xf89c */ -+ volatile u_date_coeff40 date_coeff40; /* 0xf8a0 */ -+ volatile u_date_coeff41 date_coeff41; /* 0xf8a4 */ -+ volatile u_date_coeff42 date_coeff42; /* 0xf8a8 */ -+ volatile unsigned int reserved_158[5]; /* 5:0xf8ac~0xf8bc */ -+ volatile u_date_dacdet1 date_dacdet1; /* 0xf8c0 */ -+ volatile u_date_dacdet2 date_dacdet2; /* 0xf8c4 */ -+ volatile u_date_coeff50 date_coeff50; /* 0xf8c8 */ -+ volatile u_date_coeff51 date_coeff51; /* 0xf8cc */ -+ volatile u_date_coeff52 date_coeff52; /* 0xf8d0 */ -+ volatile u_date_coeff53 date_coeff53; /* 0xf8d4 */ -+ volatile u_date_coeff54 date_coeff54; /* 0xf8d8 */ -+ volatile u_date_coeff55 date_coeff55; /* 0xf8dc */ -+ volatile unsigned int reserved_159[456]; /* 456:0xf8e0~0xfffc */ -+ volatile u_mac_outstanding mac_outstanding; /* 0x10000 */ -+ volatile u_mac_ctrl mac_ctrl; /* 0x10004 */ -+ volatile unsigned int reserved_160[2]; /* 2:0x10008~0x1000c */ -+ volatile u_mac_rchn_prio mac_rchn_prio; /* 0x10010 */ -+ volatile unsigned int reserved_161; /* 0x10014 */ -+ volatile u_mac_wchn_prio mac_wchn_prio; /* 0x10018 */ -+ volatile unsigned int reserved_162; /* 0x1001c */ -+ volatile u_mac_rchn_sel0 mac_rchn_sel0; /* 0x10020 */ -+ volatile unsigned int mac_rchn_sel1; /* 0x10024 */ -+ volatile unsigned int reserved_163[2]; /* 2:0x10028~0x1002c */ -+ volatile u_mac_wchn_sel0 mac_wchn_sel0; /* 0x10030 */ -+ volatile unsigned int reserved_164[3]; /* 3:0x10034~0x1003c */ -+ volatile u_mac_bus_err_clr mac_bus_err_clr; /* 0x10040 */ -+ volatile u_mac_bus_err mac_bus_err; /* 0x10044 */ -+ volatile unsigned int reserved_165[2]; /* 2:0x10048~0x1004c */ -+ volatile unsigned int mac_src0_status0; /* 0x10050 */ -+ volatile unsigned int mac_src0_status1; /* 0x10054 */ -+ volatile unsigned int mac_src1_status0; /* 0x10058 */ -+ volatile unsigned int mac_src1_status1; /* 0x1005c */ -+ volatile unsigned int mac_src2_status0; /* 0x10060 */ -+ volatile unsigned int mac_src2_status1; /* 0x10064 */ -+ volatile unsigned int reserved_166[2]; /* 2:0x10068~0x1006c */ -+ volatile u_mac_debug_ctrl mac_debug_ctrl; /* 0x10070 */ -+ volatile u_mac_debug_clr mac_debug_clr; /* 0x10074 */ -+ volatile unsigned int reserved_167[2]; /* 2:0x10078~0x1007c */ -+ volatile unsigned int mac0_debug_info; /* 0x10080 */ -+ volatile unsigned int reserved_168[3]; /* 3:0x10084~0x1008c */ -+ volatile unsigned int mac0_rd_info; /* 0x10090 */ -+ volatile unsigned int mac0_wr_info; /* 0x10094 */ -+ volatile unsigned int mac1_rd_info; /* 0x10098 */ -+ volatile unsigned int mac1_wr_info; /* 0x1009c */ -+ volatile unsigned int mac2_rd_info; /* 0x100a0 */ -+ volatile unsigned int mac2_wr_info; /* 0x100a4 */ -+ volatile unsigned int reserved_169[2]; /* 2:0x100a8~0x100ac */ -+ volatile unsigned int mac0_det_latency0; /* 0x100b0 */ -+ volatile unsigned int mac0_det_latency1; /* 0x100b4 */ -+ volatile unsigned int mac0_det_latency2; /* 0x100b8 */ -+ volatile unsigned int mac0_det_latency3; /* 0x100bc */ -+ volatile unsigned int mac0_det_latency4; /* 0x100c0 */ -+ volatile unsigned int mac0_det_latency5; /* 0x100c4 */ -+ volatile unsigned int mac1_det_latency0; /* 0x100c8 */ -+ volatile unsigned int mac1_det_latency1; /* 0x100cc */ -+ volatile unsigned int mac1_det_latency2; /* 0x100d0 */ -+ volatile unsigned int mac1_det_latency3; /* 0x100d4 */ -+ volatile unsigned int mac1_det_latency4; /* 0x100d8 */ -+ volatile unsigned int mac1_det_latency5; /* 0x100dc */ -+ volatile unsigned int reserved_170[72]; /* 72:0x100e0~0x101fc */ -+ volatile u_vid_read_ctrl vid_read_ctrl; /* 0x10200 */ -+ volatile u_vid_mac_ctrl vid_mac_ctrl; /* 0x10204 */ -+ volatile unsigned int reserved_171[2]; /* 2:0x10208~0x1020c */ -+ volatile u_vid_out_ctrl vid_out_ctrl; /* 0x10210 */ -+ volatile u_vid_mute_alpha vid_mute_alpha; /* 0x10214 */ -+ volatile unsigned int reserved_172; /* 0x10218 */ -+ volatile u_vid_mute_bk vid_mute_bk; /* 0x1021c */ -+ volatile unsigned int reserved_173[8]; /* 8:0x10220~0x1023c */ -+ volatile u_vid_src_info vid_src_info; /* 0x10240 */ -+ volatile u_vid_src_reso vid_src_reso; /* 0x10244 */ -+ volatile u_vid_src_crop vid_src_crop; /* 0x10248 */ -+ volatile u_vid_in_reso vid_in_reso; /* 0x1024c */ -+ volatile unsigned int vid_addr_h; /* 0x10250 */ -+ volatile unsigned int vid_addr_l; /* 0x10254 */ -+ volatile unsigned int vid_caddr_h; /* 0x10258 */ -+ volatile unsigned int vid_caddr_l; /* 0x1025c */ -+ volatile unsigned int vid_naddr_h; /* 0x10260 */ -+ volatile unsigned int vid_naddr_l; /* 0x10264 */ -+ volatile unsigned int vid_ncaddr_h; /* 0x10268 */ -+ volatile unsigned int vid_ncaddr_l; /* 0x1026c */ -+ volatile u_vid_stride vid_stride; /* 0x10270 */ -+ volatile u_vid_2bit_stride vid_2bit_stride; /* 0x10274 */ -+ volatile u_vid_head_stride vid_head_stride; /* 0x10278 */ -+ volatile unsigned int reserved_174; /* 0x1027c */ -+ volatile u_vid_smmu_bypass vid_smmu_bypass; /* 0x10280 */ -+ volatile unsigned int reserved_175[3]; /* 3:0x10284~0x1028c */ -+ volatile unsigned int vid_head_addr_h; /* 0x10290 */ -+ volatile unsigned int vid_head_addr_l; /* 0x10294 */ -+ volatile unsigned int vid_head_caddr_h; /* 0x10298 */ -+ volatile unsigned int vid_head_caddr_l; /* 0x1029c */ -+ volatile u_vid_testpat_cfg vid_testpat_cfg; /* 0x102a0 */ -+ volatile u_vid_testpat_seed vid_testpat_seed; /* 0x102a4 */ -+ volatile unsigned int vid_testpat_chksum_y; /* 0x102a8 */ -+ volatile unsigned int vid_testpat_chksum_c; /* 0x102ac */ -+ volatile unsigned int reserved_176[20]; /* 20:0x102b0~0x102fc */ -+ volatile unsigned int vid_l_cur_flow; /* 0x10300 */ -+ volatile unsigned int vid_l_cur_sreq_time; /* 0x10304 */ -+ volatile unsigned int vid_c_cur_flow; /* 0x10308 */ -+ volatile unsigned int vid_c_cur_sreq_time; /* 0x1030c */ -+ volatile unsigned int vid_l_last_flow; /* 0x10310 */ -+ volatile unsigned int vid_l_last_sreq_time; /* 0x10314 */ -+ volatile unsigned int vid_c_last_flow; /* 0x10318 */ -+ volatile unsigned int vid_c_last_sreq_time; /* 0x1031c */ -+ volatile unsigned int vid_l_busy_time; /* 0x10320 */ -+ volatile unsigned int vid_l_neednordy_time; /* 0x10324 */ -+ volatile unsigned int vid_l2_neednordy_time; /* 0x10328 */ -+ volatile unsigned int vid_c_busy_time; /* 0x1032c */ -+ volatile unsigned int vid_c_neednordy_time; /* 0x10330 */ -+ volatile unsigned int vid_c2_neednordy_time; /* 0x10334 */ -+ volatile unsigned int reserved_177[2]; /* 2:0x10338~0x1033c */ -+ volatile u_vid_dcmp_ctrl vid_dcmp_ctrl; /* 0x10340 */ -+ volatile unsigned int vid_dcmp_l_fsize; /* 0x10344 */ -+ volatile unsigned int reserved_178[14]; /* 14:0x10348~0x1037c */ -+ volatile u_vdp_v3r2_lineseg_dcmp_glb_info vdp_v3r2_lineseg_dcmp_glb_info; /* 0x10380 */ -+ volatile u_vdp_v3r2_lineseg_dcmp_frame_size vdp_v3r2_lineseg_dcmp_frame_size; /* 0x10384 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0; /* 0x10388 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1; /* 0x1038c */ -+ volatile u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; /* 0x10390 */ -+ volatile u_vdp_v3r2_lineseg_dcmp_error_sta vdp_v3r2_lineseg_dcmp_error_sta; /* 0x10394 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra; /* 0x10398 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg; /* 0x1039c */ -+ volatile unsigned int reserved_179[8]; /* 8:0x103a0~0x103bc */ -+ volatile u_vdp_v3r2_lineseg_dcmp_glb_info_c vdp_v3r2_lineseg_dcmp_glb_info_c; /* 0x103c0 */ -+ volatile u_vdp_v3r2_lineseg_dcmp_frame_size_c vdp_v3r2_lineseg_dcmp_frame_size_c; /* 0x103c4 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0_c; /* 0x103c8 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1_c; /* 0x103cc */ -+ volatile u_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; /* 0x103d0 */ -+ volatile u_vdp_v3r2_lineseg_dcmp_error_sta_c vdp_v3r2_lineseg_dcmp_error_sta_c; /* 0x103d4 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra_c; /* 0x103d8 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg_c; /* 0x103dc */ -+ volatile unsigned int reserved_180[648]; /* 648:0x103e0~0x10dfc */ -+ volatile u_gfx_read_ctrl gfx_read_ctrl; /* 0x10e00 */ -+ volatile u_gfx_mac_ctrl gfx_mac_ctrl; /* 0x10e04 */ -+ volatile u_gfx_out_ctrl gfx_out_ctrl; /* 0x10e08 */ -+ volatile unsigned int reserved_181; /* 0x10e0c */ -+ volatile u_gfx_mute_alpha gfx_mute_alpha; /* 0x10e10 */ -+ volatile u_gfx_mute_bk gfx_mute_bk; /* 0x10e14 */ -+ volatile unsigned int reserved_182[2]; /* 2:0x10e18~0x10e1c */ -+ volatile u_gfx_smmu_bypass gfx_smmu_bypass; /* 0x10e20 */ -+ volatile unsigned int reserved_183; /* 0x10e24 */ -+ volatile u_gfx_1555_alpha gfx_1555_alpha; /* 0x10e28 */ -+ volatile unsigned int reserved_184[5]; /* 5:0x10e2c~0x10e3c */ -+ volatile u_gfx_src_info gfx_src_info; /* 0x10e40 */ -+ volatile u_gfx_src_reso gfx_src_reso; /* 0x10e44 */ -+ volatile u_gfx_src_crop gfx_src_crop; /* 0x10e48 */ -+ volatile u_gfx_ireso gfx_ireso; /* 0x10e4c */ -+ volatile unsigned int gfx_addr_h; /* 0x10e50 */ -+ volatile unsigned int gfx_addr_l; /* 0x10e54 */ -+ volatile unsigned int gfx_naddr_h; /* 0x10e58 */ -+ volatile unsigned int gfx_naddr_l; /* 0x10e5c */ -+ volatile u_gfx_stride gfx_stride; /* 0x10e60 */ -+ volatile unsigned int reserved_185[3]; /* 3:0x10e64~0x10e6c */ -+ volatile unsigned int gfx_dcmp_addr_h; /* 0x10e70 */ -+ volatile unsigned int gfx_dcmp_addr_l; /* 0x10e74 */ -+ volatile unsigned int gfx_dcmp_naddr_h; /* 0x10e78 */ -+ volatile unsigned int gfx_dcmp_naddr_l; /* 0x10e7c */ -+ volatile unsigned int reserved_186[32]; /* 32:0x10e80~0x10efc */ -+ volatile u_gfx_ckey_max gfx_ckey_max; /* 0x10f00 */ -+ volatile u_gfx_ckey_min gfx_ckey_min; /* 0x10f04 */ -+ volatile u_gfx_ckey_mask gfx_ckey_mask; /* 0x10f08 */ -+ volatile unsigned int reserved_187; /* 0x10f0c */ -+ volatile u_gfx_testpat_cfg gfx_testpat_cfg; /* 0x10f10 */ -+ volatile u_gfx_testpat_seed gfx_testpat_seed; /* 0x10f14 */ -+ volatile unsigned int reserved_188[2]; /* 2:0x10f18~0x10f1c */ -+ volatile unsigned int gfx_dcmp_framesize0; /* 0x10f20 */ -+ volatile unsigned int gfx_dcmp_framesize1; /* 0x10f24 */ -+ volatile unsigned int reserved_189[2]; /* 2:0x10f28~0x10f2c */ -+ volatile unsigned int gfx_cur_flow; /* 0x10f30 */ -+ volatile unsigned int gfx_cur_sreq_time; /* 0x10f34 */ -+ volatile unsigned int gfx_last_flow; /* 0x10f38 */ -+ volatile unsigned int gfx_last_sreq_time; /* 0x10f3c */ -+ volatile unsigned int gfx_busy_time; /* 0x10f40 */ -+ volatile unsigned int gfx_ar_neednordy_time; /* 0x10f44 */ -+ volatile unsigned int gfx_gb_neednordy_time; /* 0x10f48 */ -+ volatile unsigned int reserved_190_1[1]; /* 0x10f4c */ -+ volatile u_gfx_ld_ctrl gfx_ld_ctrl; /* 0x10f50 */ -+ volatile unsigned int gfx_tde_safe_dis; /* 0x10f54 */ -+ volatile u_gfx_ld_smute_ctrl gfx_ld_smute_ctrl; /* 0x10f58 */ -+ volatile u_gfx_ld_err_sta gfx_ld_err_sta; /* 0x10f5c */ -+ volatile unsigned int gfx_ld_debug0; /* 0x10f60 */ -+ volatile unsigned int gfx_ld_debug1; /* 0x10f64 */ -+ volatile unsigned int gfx_ld_debug2; /* 0x10f68 */ -+ volatile unsigned int gfx_ld_debug3; /* 0x10f6c */ -+ volatile unsigned int gfx_ld_debug4; /* 0x10f70 */ -+ volatile unsigned int gfx_ld_debug5; /* 0x10f74 */ -+ volatile unsigned int reserved_190_2[2]; /* 2:0x10f78~0x10f7c */ -+ volatile u_vdp_v3r2_line_osd_dcmp_glb_info vdp_v3r2_line_osd_dcmp_glb_info; /* 0x10f80 */ -+ volatile u_vdp_v3r2_line_osd_dcmp_frame_size vdp_v3r2_line_osd_dcmp_frame_size; /* 0x10f84 */ -+ volatile u_vdp_v3r2_line_osd_dcmp_error_sta vdp_v3r2_line_osd_dcmp_error_sta; /* 0x10f88 */ -+ volatile unsigned int reserved_191[541]; /* 0x10f8c~0x117fc 541 regs */ -+ volatile u_wbc_ctrl wbc_ctrl; /* 0x11800 */ -+ volatile u_wbc_mac_ctrl wbc_mac_ctrl; /* 0x11804 */ -+ volatile unsigned int reserved_193[3]; /* 3:0x11808~0x11810 */ -+ volatile u_wbc_smmu_bypass wbc_smmu_bypass; /* 0x11814 */ -+ volatile unsigned int reserved_194[2]; /* 2:0x11818~0x1181c */ -+ volatile u_wbc_lowdlyctrl wbc_lowdlyctrl; /* 0x11820 */ -+ volatile unsigned int wbc_tunladdr_h; /* 0x11824 */ -+ volatile unsigned int wbc_tunladdr_l; /* 0x11828 */ -+ volatile u_wbc_lowdlysta wbc_lowdlysta; /* 0x1182c */ -+ volatile unsigned int reserved_195[8]; /* 8:0x11830~0x1184c */ -+ volatile unsigned int wbc_yaddr_h; /* 0x11850 */ -+ volatile unsigned int wbc_yaddr_l; /* 0x11854 */ -+ volatile unsigned int wbc_caddr_h; /* 0x11858 */ -+ volatile unsigned int wbc_caddr_l; /* 0x1185c */ -+ volatile u_wbc_ystride wbc_ystride; /* 0x11860 */ -+ volatile u_wbc_cstride wbc_cstride; /* 0x11864 */ -+ volatile unsigned int reserved_196[2]; /* 2:0x11868~0x1186c */ -+ volatile unsigned int wbc_ynaddr_h; /* 0x11870 */ -+ volatile unsigned int wbc_ynaddr_l; /* 0x11874 */ -+ volatile unsigned int wbc_cnaddr_h; /* 0x11878 */ -+ volatile unsigned int wbc_cnaddr_l; /* 0x1187c */ -+ volatile u_wbc_ynstride wbc_ynstride; /* 0x11880 */ -+ volatile u_wbc_cnstride wbc_cnstride; /* 0x11884 */ -+ volatile unsigned int reserved_197[10]; /* 10:0x11888~0x118ac */ -+ volatile u_wbc_sta wbc_sta; /* 0x118b0 */ -+ volatile u_wbc_line_num wbc_line_num; /* 0x118b4 */ -+ volatile u_wbc_cap_reso wbc_cap_reso; /* 0x118b8 */ -+ volatile unsigned int wbc_cap_info; /* 0x118bc */ -+ volatile unsigned int reserved_198[16]; /* 16:0x118c0~0x118fc */ -+ volatile u_vdp_v3r2_lineseg_cmp_glb_info vdp_v3r2_lineseg_cmp_glb_info; /* 0x11900 */ -+ volatile u_vdp_v3r2_lineseg_cmp_frame_size vdp_v3r2_lineseg_cmp_frame_size; /* 0x11904 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg0 vdp_v3r2_lineseg_cmp_rc_cfg0; /* 0x11908 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg1 vdp_v3r2_lineseg_cmp_rc_cfg1; /* 0x1190c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2; /* 0x11910 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3; /* 0x11914 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4; /* 0x11918 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5; /* 0x1191c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6; /* 0x11920 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7; /* 0x11924 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8; /* 0x11928 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9; /* 0x1192c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10; /* 0x11930 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11; /* 0x11934 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg12 vdp_v3r2_lineseg_cmp_rc_cfg12; /* 0x11938 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg13 vdp_v3r2_lineseg_cmp_rc_cfg13; /* 0x1193c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14; /* 0x11940 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15; /* 0x11944 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0; /* 0x11948 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1; /* 0x1194c */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg16 vdp_v3r2_lineseg_cmp_rc_cfg16; /* 0x11950 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg; /* 0x11954 */ -+ volatile u_vdp_v3r2_lineseg_cmp_glb_st vdp_v3r2_lineseg_cmp_glb_st; /* 0x11958 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg; /* 0x1195c */ -+ volatile unsigned int reserved_199[8]; /* 8:0x11960~0x1197c */ -+ volatile u_vdp_v3r2_lineseg_cmp_glb_info_c vdp_v3r2_lineseg_cmp_glb_info_c; /* 0x11980 */ -+ volatile u_vdp_v3r2_lineseg_cmp_frame_size_c vdp_v3r2_lineseg_cmp_frame_size_c; /* 0x11984 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg0_c vdp_v3r2_lineseg_cmp_rc_cfg0_c; /* 0x11988 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg1_c vdp_v3r2_lineseg_cmp_rc_cfg1_c; /* 0x1198c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2_c; /* 0x11990 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3_c; /* 0x11994 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4_c; /* 0x11998 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5_c; /* 0x1199c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6_c; /* 0x119a0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7_c; /* 0x119a4 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8_c; /* 0x119a8 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9_c; /* 0x119ac */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10_c; /* 0x119b0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11_c; /* 0x119b4 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg12_c vdp_v3r2_lineseg_cmp_rc_cfg12_c; /* 0x119b8 */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg13_c vdp_v3r2_lineseg_cmp_rc_cfg13_c; /* 0x119bc */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14_c; /* 0x119c0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15_c; /* 0x119c4 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0_c; /* 0x119c8 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1_c; /* 0x119cc */ -+ volatile u_vdp_v3r2_lineseg_cmp_rc_cfg16_c vdp_v3r2_lineseg_cmp_rc_cfg16_c; /* 0x119d0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg_c; /* 0x119d4 */ -+ volatile u_vdp_v3r2_lineseg_cmp_glb_st_c vdp_v3r2_lineseg_cmp_glb_st_c; /* 0x119d8 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg_c; /* 0x119dc */ -+ volatile unsigned int reserved_200[264]; /* 264:0x119e0~0x11dfc */ -+ volatile u_wbc_cmp_ctrl wbc_cmp_ctrl; /* 0x11e00 */ -+ volatile u_wbc_cmp_upd wbc_cmp_upd; /* 0x11e04 */ -+ volatile u_wbc_cmp_height wbc_cmp_height; /* 0x11e08 */ -+ volatile u_wbc_cmp_oreso wbc_cmp_oreso; /* 0x11e0c */ -+ volatile unsigned int wbc_cmp_yaddr; /* 0x11e10 */ -+ volatile unsigned int wbc_cmp_yaddr1; /* 0x11e14 */ -+ volatile unsigned int wbc_cmp_caddr; /* 0x11e18 */ -+ volatile unsigned int wbc_cmp_caddr1; /* 0x11e1c */ -+ volatile unsigned int wbc_cmp_addr0_t0; /* 0x11e20 */ -+ volatile unsigned int wbc_cmp_addr1_t0; /* 0x11e24 */ -+ volatile unsigned int wbc_cmp_addr0_t1; /* 0x11e28 */ -+ volatile unsigned int wbc_cmp_addr1_t1; /* 0x11e2c */ -+ volatile unsigned int wbc_cmp_l_fsize; /* 0x11e30 */ -+ volatile unsigned int wbc_cmp_c_fsize; /* 0x11e34 */ -+ volatile unsigned int wbc_cmp_t0_fsize; /* 0x11e38 */ -+ volatile unsigned int wbc_cmp_t1_fsize; /* 0x11e3c */ -+ volatile unsigned int wbc_sety_fsize; /* 0x11e40 */ -+ volatile unsigned int wbc_setc_fsize; /* 0x11e44 */ -+ volatile unsigned int wbc_sett0_fsize; /* 0x11e48 */ -+ volatile unsigned int wbc_sett1_fsize; /* 0x11e4c */ -+ volatile u_wbc_od_state wbc_od_state; /* 0x11e50 */ -+ volatile unsigned int reserved_201[43]; /* 43:0x11e54~0x11efc */ -+ volatile u_od_pic_osd_glb_info od_pic_osd_glb_info; /* 0x11f00 */ -+ volatile u_od_pic_osd_frame_size od_pic_osd_frame_size; /* 0x11f04 */ -+ volatile u_od_pic_osd_rc_cfg0 od_pic_osd_rc_cfg0; /* 0x11f08 */ -+ volatile u_od_pic_osd_rc_cfg1 od_pic_osd_rc_cfg1; /* 0x11f0c */ -+ volatile u_od_pic_osd_rc_cfg2 od_pic_osd_rc_cfg2; /* 0x11f10 */ -+ volatile u_od_pic_osd_rc_cfg3 od_pic_osd_rc_cfg3; /* 0x11f14 */ -+ volatile u_od_pic_osd_rc_cfg4 od_pic_osd_rc_cfg4; /* 0x11f18 */ -+ volatile u_od_pic_osd_rc_cfg5 od_pic_osd_rc_cfg5; /* 0x11f1c */ -+ volatile u_od_pic_osd_rc_cfg6 od_pic_osd_rc_cfg6; /* 0x11f20 */ -+ volatile u_od_pic_osd_rc_cfg7 od_pic_osd_rc_cfg7; /* 0x11f24 */ -+ volatile u_od_pic_osd_rc_cfg8 od_pic_osd_rc_cfg8; /* 0x11f28 */ -+ volatile u_od_pic_osd_rc_cfg9 od_pic_osd_rc_cfg9; /* 0x11f2c */ -+ volatile u_od_pic_osd_rc_cfg10 od_pic_osd_rc_cfg10; /* 0x11f30 */ -+ volatile u_od_pic_osd_rc_cfg11 od_pic_osd_rc_cfg11; /* 0x11f34 */ -+ volatile u_od_pic_osd_rc_cfg12 od_pic_osd_rc_cfg12; /* 0x11f38 */ -+ volatile u_od_pic_osd_rc_cfg13 od_pic_osd_rc_cfg13; /* 0x11f3c */ -+ volatile u_od_pic_osd_rc_cfg14 od_pic_osd_rc_cfg14; /* 0x11f40 */ -+ volatile u_od_pic_osd_rc_cfg15 od_pic_osd_rc_cfg15; /* 0x11f44 */ -+ volatile u_od_pic_osd_rc_cfg16 od_pic_osd_rc_cfg16; /* 0x11f48 */ -+ volatile u_od_pic_osd_rc_cfg17 od_pic_osd_rc_cfg17; /* 0x11f4c */ -+ volatile u_od_pic_osd_rc_cfg18 od_pic_osd_rc_cfg18; /* 0x11f50 */ -+ volatile u_od_pic_osd_rc_cfg19 od_pic_osd_rc_cfg19; /* 0x11f54 */ -+ volatile unsigned int reserved_202[2]; /* 2:0x11f58~0x11f5c */ -+ volatile u_od_pic_osd_stat_thr od_pic_osd_stat_thr; /* 0x11f60 */ -+ volatile u_od_pic_osd_pcmp od_pic_osd_pcmp; /* 0x11f64 */ -+ volatile unsigned int reserved_203[6]; /* 6:0x11f68~0x11f7c */ -+ volatile u_od_pic_osd_bs_size od_pic_osd_bs_size; /* 0x11f80 */ -+ volatile u_od_pic_osd_worst_row od_pic_osd_worst_row; /* 0x11f84 */ -+ volatile u_od_pic_osd_best_row od_pic_osd_best_row; /* 0x11f88 */ -+ volatile u_od_pic_osd_stat_info od_pic_osd_stat_info; /* 0x11f8c */ -+ volatile unsigned int od_pic_osd_debug0; /* 0x11f90 */ -+ volatile unsigned int od_pic_osd_debug1; /* 0x11f94 */ -+ volatile unsigned int reserved_204[26]; /* 26:0x11f98~0x11ffc */ -+ volatile u_v0_mrg_ctrl v0_mrg_ctrl; /* 0x12000 */ -+ volatile u_v0_mrg_disp_pos v0_mrg_disp_pos; /* 0x12004 */ -+ volatile u_v0_mrg_disp_reso v0_mrg_disp_reso; /* 0x12008 */ -+ volatile u_v0_mrg_src_reso v0_mrg_src_reso; /* 0x1200c */ -+ volatile u_v0_mrg_src_offset v0_mrg_src_offset; /* 0x12010 */ -+ volatile unsigned int v0_mrg_y_addr; /* 0x12014 */ -+ volatile unsigned int v0_mrg_c_addr; /* 0x12018 */ -+ volatile u_v0_mrg_stride v0_mrg_stride; /* 0x1201c */ -+ volatile unsigned int v0_mrg_yh_addr; /* 0x12020 */ -+ volatile unsigned int v0_mrg_ch_addr; /* 0x12024 */ -+ volatile u_v0_mrg_hstride v0_mrg_hstride; /* 0x12028 */ -+ volatile unsigned int reserved_205[5]; /* 5:0x1202c~0x1203c */ -+ volatile u_v0_mrg_read_ctrl v0_mrg_read_ctrl; /* 0x12040 */ -+ volatile u_v0_mrg_read_en v0_mrg_read_en; /* 0x12044 */ -+ volatile unsigned int reserved_206[750]; /* 750:0x12048~0x12bfc */ -+ volatile u_v1_mrg_ctrl v1_mrg_ctrl; /* 0x12c00 */ -+ volatile u_v1_mrg_disp_pos v1_mrg_disp_pos; /* 0x12c04 */ -+ volatile u_v1_mrg_disp_reso v1_mrg_disp_reso; /* 0x12c08 */ -+ volatile u_v1_mrg_src_reso v1_mrg_src_reso; /* 0x12c0c */ -+ volatile u_v1_mrg_src_offset v1_mrg_src_offset; /* 0x12c10 */ -+ volatile unsigned int v1_mrg_y_addr; /* 0x12c14 */ -+ volatile unsigned int v1_mrg_c_addr; /* 0x12c18 */ -+ volatile u_v1_mrg_stride v1_mrg_stride; /* 0x12c1c */ -+ volatile unsigned int v1_mrg_yh_addr; /* 0x12c20 */ -+ volatile unsigned int v1_mrg_ch_addr; /* 0x12c24 */ -+ volatile u_v1_mrg_hstride v1_mrg_hstride; /* 0x12c28 */ -+ volatile unsigned int reserved_207[5]; /* 5:0x12c2c~0x12c3c */ -+ volatile u_v1_mrg_read_ctrl v1_mrg_read_ctrl; /* 0x12c40 */ -+ volatile u_v1_mrg_read_en v1_mrg_read_en; /* 0x12c44 */ -+ volatile unsigned int reserved_208_1[1262]; /* 1262:0x12c48~0x14ffc */ -+ volatile u_osb_ctrl1_box_0 osb_ctrl1_box_0; /* 0x14000 */ -+ volatile u_osb_ctrl2_box_0 osb_ctrl2_box_0; /* 0x14004 */ -+ volatile u_osb_ctrl3_box_0 osb_ctrl3_box_0; /* 0x14008 */ -+ volatile unsigned int reserved_208_2[1021]; /* 1021:0x1400c~0x14ffc 1021 regs */ -+ volatile u_v1_csc_idc v1_csc_idc; /* 0x15000 */ -+ volatile u_v1_csc_odc v1_csc_odc; /* 0x15004 */ -+ volatile u_v1_csc_iodc v1_csc_iodc; /* 0x15008 */ -+ volatile u_v1_csc_p0 v1_csc_p0; /* 0x1500c */ -+ volatile u_v1_csc_p1 v1_csc_p1; /* 0x15010 */ -+ volatile u_v1_csc_p2 v1_csc_p2; /* 0x15014 */ -+ volatile u_v1_csc_p3 v1_csc_p3; /* 0x15018 */ -+ volatile u_v1_csc_p4 v1_csc_p4; /* 0x1501c */ -+ volatile u_v1_csc1_idc v1_csc1_idc; /* 0x15020 */ -+ volatile u_v1_csc1_odc v1_csc1_odc; /* 0x15024 */ -+ volatile u_v1_csc1_iodc v1_csc1_iodc; /* 0x15028 */ -+ volatile u_v1_csc1_p0 v1_csc1_p0; /* 0x1502c */ -+ volatile u_v1_csc1_p1 v1_csc1_p1; /* 0x15030 */ -+ volatile u_v1_csc1_p2 v1_csc1_p2; /* 0x15034 */ -+ volatile u_v1_csc1_p3 v1_csc1_p3; /* 0x15038 */ -+ volatile u_v1_csc1_p4 v1_csc1_p4; /* 0x1503c */ -+ volatile unsigned int reserved_209[48]; /* 48:0x15040~0x150fc */ -+ volatile u_v2_csc_idc v2_csc_idc; /* 0x15100 */ -+ volatile u_v2_csc_odc v2_csc_odc; /* 0x15104 */ -+ volatile u_v2_csc_iodc v2_csc_iodc; /* 0x15108 */ -+ volatile u_v2_csc_p0 v2_csc_p0; /* 0x1510c */ -+ volatile u_v2_csc_p1 v2_csc_p1; /* 0x15110 */ -+ volatile u_v2_csc_p2 v2_csc_p2; /* 0x15114 */ -+ volatile u_v2_csc_p3 v2_csc_p3; /* 0x15118 */ -+ volatile u_v2_csc_p4 v2_csc_p4; /* 0x1511c */ -+ volatile u_v2_csc1_idc v2_csc1_idc; /* 0x15120 */ -+ volatile u_v2_csc1_odc v2_csc1_odc; /* 0x15124 */ -+ volatile u_v2_csc1_iodc v2_csc1_iodc; /* 0x15128 */ -+ volatile u_v2_csc1_p0 v2_csc1_p0; /* 0x1512c */ -+ volatile u_v2_csc1_p1 v2_csc1_p1; /* 0x15130 */ -+ volatile u_v2_csc1_p2 v2_csc1_p2; /* 0x15134 */ -+ volatile u_v2_csc1_p3 v2_csc1_p3; /* 0x15138 */ -+ volatile u_v2_csc1_p4 v2_csc1_p4; /* 0x1513c */ -+ volatile unsigned int reserved_210[48]; /* 48:0x15140~0x151fc */ -+ volatile u_g1_csc_idc g1_csc_idc; /* 0x15200 */ -+ volatile u_g1_csc_odc g1_csc_odc; /* 0x15204 */ -+ volatile u_g1_csc_iodc g1_csc_iodc; /* 0x15208 */ -+ volatile u_g1_csc_p0 g1_csc_p0; /* 0x1520c */ -+ volatile u_g1_csc_p1 g1_csc_p1; /* 0x15210 */ -+ volatile u_g1_csc_p2 g1_csc_p2; /* 0x15214 */ -+ volatile u_g1_csc_p3 g1_csc_p3; /* 0x15218 */ -+ volatile u_g1_csc_p4 g1_csc_p4; /* 0x1521c */ -+ volatile u_g1_csc1_idc g1_csc1_idc; /* 0x15220 */ -+ volatile u_g1_csc1_odc g1_csc1_odc; /* 0x15224 */ -+ volatile u_g1_csc1_iodc g1_csc1_iodc; /* 0x15228 */ -+ volatile u_g1_csc1_p0 g1_csc1_p0; /* 0x1522c */ -+ volatile u_g1_csc1_p1 g1_csc1_p1; /* 0x15230 */ -+ volatile u_g1_csc1_p2 g1_csc1_p2; /* 0x15234 */ -+ volatile u_g1_csc1_p3 g1_csc1_p3; /* 0x15238 */ -+ volatile u_g1_csc1_p4 g1_csc1_p4; /* 0x1523c */ -+ volatile unsigned int reserved_211[48]; /* 48:0x15240~0x152fc */ -+ volatile u_g3_csc_idc g3_csc_idc; /* 0x15300 */ -+ volatile u_g3_csc_odc g3_csc_odc; /* 0x15304 */ -+ volatile u_g3_csc_iodc g3_csc_iodc; /* 0x15308 */ -+ volatile u_g3_csc_p0 g3_csc_p0; /* 0x1530c */ -+ volatile u_g3_csc_p1 g3_csc_p1; /* 0x15310 */ -+ volatile u_g3_csc_p2 g3_csc_p2; /* 0x15314 */ -+ volatile u_g3_csc_p3 g3_csc_p3; /* 0x15318 */ -+ volatile u_g3_csc_p4 g3_csc_p4; /* 0x1531c */ -+ volatile u_g3_csc1_idc g3_csc1_idc; /* 0x15320 */ -+ volatile u_g3_csc1_odc g3_csc1_odc; /* 0x15324 */ -+ volatile u_g3_csc1_iodc g3_csc1_iodc; /* 0x15328 */ -+ volatile u_g3_csc1_p0 g3_csc1_p0; /* 0x1532c */ -+ volatile u_g3_csc1_p1 g3_csc1_p1; /* 0x15330 */ -+ volatile u_g3_csc1_p2 g3_csc1_p2; /* 0x15334 */ -+ volatile u_g3_csc1_p3 g3_csc1_p3; /* 0x15338 */ -+ volatile u_g3_csc1_p4 g3_csc1_p4; /* 0x1533c */ -+ volatile unsigned int reserved_212[48]; /* 48:0x15340~0x153fc */ -+ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; /* 0x15400 */ -+ volatile u_v0_cvfir_vsp v0_cvfir_vsp; /* 0x15404 */ -+ volatile u_v0_cvfir_voffset v0_cvfir_voffset; /* 0x15408 */ -+ volatile u_v0_cvfir_vboffset v0_cvfir_vboffset; /* 0x1540c */ -+ volatile unsigned int reserved_213[8]; /* 8:0x15410~0x1542c */ -+ volatile u_v0_cvfir_vcoef0 v0_cvfir_vcoef0; /* 0x15430 */ -+ volatile u_v0_cvfir_vcoef1 v0_cvfir_vcoef1; /* 0x15434 */ -+ volatile u_v0_cvfir_vcoef2 v0_cvfir_vcoef2; /* 0x15438 */ -+ volatile unsigned int reserved_214[721]; /* 721:0x1543c~0x15f7c */ -+ volatile u_gfx_osd_glb_info gfx_osd_glb_info; /* 0x15f80 */ -+ volatile u_gfx_osd_frame_size gfx_osd_frame_size; /* 0x15f84 */ -+ volatile unsigned int reserved_215[2]; /* 2:0x15f88~0x15f8c */ -+ volatile u_gfx_osd_dbg_reg gfx_osd_dbg_reg; /* 0x15f90 */ -+ volatile u_gfx_osd_dbg_reg1 gfx_osd_dbg_reg1; /* 0x15f94 */ -+} vdp_regs_type; -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif /* __cplusplus */ -+#endif /* __cplusplus */ -+ -+#endif /* GFBG_REG_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.c b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.c -new file mode 100755 -index 0000000..a7a7a4d ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.c -@@ -0,0 +1,180 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#include "hdmi_product_define.h" -+#include "hdmi_reg_video_path.h" -+ -+#define CRG_RESET_DELAY 2 -+#define HDMI_IO_CFG_HPD_SEL 0x2801 -+#define HDMI_IO_CFG_DDC_SEL 0x6801 -+ -+void hdmi_tx_reg_write(unsigned int *reg_addr, unsigned int value) -+{ -+ *(volatile unsigned int *)reg_addr = value; -+ return; -+} -+ -+unsigned int hdmi_tx_reg_read(const unsigned int *reg_addr) -+{ -+ return *(volatile unsigned int *)(reg_addr); -+} -+ -+void hdmi_reg_write_u32(unsigned int reg_addr, unsigned int value) -+{ -+ volatile unsigned int *addr = NULL; -+ -+ addr = (volatile unsigned int *)ioremap((unsigned long long)reg_addr, HDMI_REGISTER_SIZE); -+ if (addr != NULL) { -+ *addr = value; -+ iounmap((void *)addr); -+ } else { -+ printk("ioremap addr=0x%x err!\n", reg_addr); -+ } -+ -+ return; -+} -+ -+unsigned int hdmi_reg_read_u32(unsigned int reg_addr) -+{ -+ volatile unsigned int *addr = NULL; -+ unsigned int value = 0; -+ -+ -+ addr = (volatile unsigned int *)ioremap((unsigned long long)reg_addr, HDMI_REGISTER_SIZE); -+ if (addr != NULL) { -+ value = *addr; -+ iounmap((void *)addr); -+ } else { -+ printk("ioremap addr=0x%x\n err!\n", reg_addr); -+ } -+ -+ return value; -+} -+ -+void drv_hdmi_prod_io_cfg_set(void) -+{ -+ -+ hdmi_if_fpga_return_void(); -+ -+ hdmi_reg_write_u32(HDMI_ADDR_IO_CFG_HOTPLUG, HDMI_IO_CFG_HPD_SEL); -+ hdmi_reg_write_u32(HDMI_ADDR_IO_CFG_SDA, HDMI_IO_CFG_DDC_SEL); -+ hdmi_reg_write_u32(HDMI_ADDR_IO_CFG_SCL, HDMI_IO_CFG_DDC_SEL); -+ -+ return; -+} -+ -+void drv_hdmi_prod_crg_gate_set(bool enable) -+{ -+ -+ hdmi_if_fpga_return_void(); -+ -+ hdmi_reg_ctrl_osc_24m_cken_set(enable); -+ hdmi_reg_ctrl_cec_cken_set(enable); -+ hdmi_reg_ctrl_os_cken_set(enable); -+ hdmi_reg_ctrl_as_cken_set(enable); -+ hdmi_reg_hdmitx_phy_tmds_cken_set(enable); -+ hdmi_reg_hdmitx_phy_modclk_cken_set(enable); -+ hdmi_reg_ac_ctrl_modclk_cken_set(enable); -+ hdmi_reg_phy_clk_pctrl_set(0); -+ -+ return; -+} -+ -+void drv_hdmi_prod_crg_all_reset_set(bool enable) -+{ -+ -+ hdmi_if_fpga_return_void(); -+ -+ -+ hdmi_reg_ctrl_bus_srst_req_set(enable); -+ hdmi_reg_ctrl_srst_req_set(enable); -+ hdmi_reg_ctrl_cec_srst_req_set(enable); -+ hdmi_reg_phy_srst_req_set(enable); -+ hdmi_reg_phy_bus_srst_req_set(enable); -+ hdmi_reg_ac_ctrl_srst_req_set(enable); -+ hdmi_reg_ac_ctrl_bus_srst_req_set(enable); -+ enable = !enable; -+ /* -+ * 2, 2us. to ensure ctrl reset success. -+ * because internal clock of HDMI is smaller than APB clock. -+ */ -+ udelay(CRG_RESET_DELAY); -+ hdmi_reg_ctrl_bus_srst_req_set(enable); -+ hdmi_reg_ctrl_srst_req_set(enable); -+ hdmi_reg_ctrl_cec_srst_req_set(enable); -+ hdmi_reg_phy_srst_req_set(enable); -+ hdmi_reg_phy_bus_srst_req_set(enable); -+ hdmi_reg_ac_ctrl_srst_req_set(enable); -+ hdmi_reg_ac_ctrl_bus_srst_req_set(enable); -+ -+ return; -+} -+ -+void drv_hdmi_low_power_set(bool enable) -+{ -+ -+ hdmi_if_fpga_return_void(); -+ -+ if ((hdmi_reg_crg_init() != 0) || hdmi_video_path_regs_is_inited() != 0) { -+ -+ return; -+ } -+ -+ enable = !enable; -+ hdmi_reg_ctrl_os_cken_set(enable); -+ hdmi_reg_ctrl_as_cken_set(enable); -+ /* blank data help for low power. */ -+ hdmi_reg_video_blank_en_set(enable); -+ -+ return; -+} -+ -+void drv_hdmi_prod_crg_init(void) -+{ -+ -+ drv_hdmi_prod_io_cfg_set(); -+ drv_hdmi_prod_crg_gate_set(1); -+ drv_hdmi_prod_crg_all_reset_set(1); -+ drv_hdmi_low_power_set(1); -+ -+ return; -+} -+ -+void drv_hdmi_hardware_reset(unsigned int id) -+{ -+ -+ hdmi_if_fpga_return_void(); -+ -+ if (hdmi_reg_crg_init() != 0) { -+ printk("CRG reg io map error!\n"); -+ return; -+ } -+ /* reset all module */ -+ hdmi_reg_ctrl_bus_srst_req_set(1); -+ hdmi_reg_ctrl_srst_req_set(1); -+ hdmi_reg_ctrl_cec_srst_req_set(1); -+ hdmi_reg_phy_srst_req_set(1); -+ hdmi_reg_phy_bus_srst_req_set(1); -+ hdmi_reg_ac_ctrl_srst_req_set(1); -+ hdmi_reg_ac_ctrl_bus_srst_req_set(1); -+ /* close all clk */ -+ drv_hdmi_prod_crg_gate_set(0); -+ hdmi_reg_crg_deinit(); -+ -+ return; -+} -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.h -new file mode 100755 -index 0000000..d7ef6b3 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/hdmi_product_define.h -@@ -0,0 +1,160 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HDMI_PRODUCT_DEFINE_H -+#define HDMI_PRODUCT_DEFINE_H -+ -+#include -+#include -+#include -+#include -+#include "hdmi_reg_crg.h" -+ -+/* -+ * ------------- reg base addr -------- -+ * ctrl | dphy | -+ * hdmi0 : 0x17B40000 | 0x17BC0000 | -+ * -------------------|---------------- -+ */ -+#define CRG_BASE_ADDR 0x11010000 -+#define HDMI_CRG_OFFSET 0x7F40 -+#define HDMI_CRG_ADDR ((CRG_BASE_ADDR) + (HDMI_CRG_OFFSET)) -+/* pin mux */ -+#define HDMI_ADDR_BASE_IO_CFG 0x102F0000 -+#define HDMI_ADDR_IO_CFG_HOTPLUG (HDMI_ADDR_BASE_IO_CFG + 0xE4) -+#define HDMI_ADDR_IO_CFG_SDA (HDMI_ADDR_BASE_IO_CFG + 0xE8) -+#define HDMI_ADDR_IO_CFG_SCL (HDMI_ADDR_BASE_IO_CFG + 0xEC) -+/* color bar */ -+#define HDMI_COLOR_BAR_MASK 0x60000000 -+#define HDMI_COLOR_BAR_UPDATE_MASK 0x00000001 -+#define HDMI_COLOR_BAR_BASE 0x17A0D000 -+/* sub-module offset */ -+#define HDMI_TX_BASE_ADDR_CTRL 0x0000 -+#define HDMI_TX_BASE_ADDR_VIDEO 0x0800 -+#define HDMI_TX_BASE_ADDR_AUDIO 0x1000 -+#define HDMI_TX_BASE_ADDR_HDMITX 0x1800 -+#define HDMI_TX_BASE_ADDR_AON 0x4000 -+/* other macro */ -+#define HDMI_FILE_MODE 0777 -+#ifdef OT_ADVCA_FUNCTION_RELEASE -+#define CONFIG_HDMI_PROC_DISABLE -+#define CONFIG_HDMI_DEBUG_DISABLE -+#endif -+ -+#define VERSION_STRING ("[HDMI] Version: [" OT_MPP_VERSION "], Build Time["__DATE__", "__TIME__"]") -+#define hdmi_get_current_id() (get_current()->tgid) -+ -+#define hdmi_err_trace(fmt, ...) -+ -+#define hdmi_warn_trace(fmt, ...) -+ -+#define hdmi_info_trace(fmt, ...) -+ -+#define hdmi_fatal_trace(fmt, ...) -+ -+ -+ -+ -+#ifdef HDMI_LOG_SUPPORT -+#ifndef OT_ADVCA_FUNCTION_RELEASE -+#define hdmi_printk(fmt, args...) printk(fmt, ##args) -+#else -+#define hdmi_printk(fmt, args...) -+#endif -+#else -+#define hdmi_printk(fmt, args...) -+#endif -+ -+#ifdef CONFIG_HDMI_DEBUG_DISABLE -+#define edid_info(fmt...) -+#define edid_warn(fmt...) -+#define edid_err(fmt...) -+#define edid_faital(fmt...) -+#define hdmi_info(fmt...) -+#define hdmi_warn(fmt...) -+#define hdmi_err(fmt...) -+#define hdmi_fatal(fmt...) -+#elif defined(HDMI_LOG_SUPPORT) -+#define edid_info(fmt...) -+#define edid_warn(fmt...) -+#define edid_err(fmt...) -+#define edid_faital(fmt...) -+#define hdmi_info(fmt...) hdmi_info_trace(fmt) -+#define hdmi_warn(fmt...) hdmi_warn_trace(fmt) -+#define hdmi_err(fmt...) hdmi_err_trace(fmt) -+#define hdmi_fatal(fmt...) hdmi_fatal_trace(fmt) -+#else -+#define edid_info(fmt...) hdmi_info_trace(fmt) -+#define edid_warn(fmt...) hdmi_warn_trace(fmt) -+#define edid_err(fmt...) hdmi_err_trace(fmt) -+#define edid_faital(fmt...) hdmi_fatal_trace(fmt) -+#define hdmi_fatal(fmt...) hdmi_fatal_trace(fmt) -+#define hdmi_err(fmt...) hdmi_err_trace(fmt) -+#define hdmi_warn(fmt...) hdmi_warn_trace(fmt) -+#define hdmi_info(fmt...) hdmi_info_trace(fmt) -+#endif -+ -+typedef struct { -+ unsigned int ssc_bypass_div; -+ unsigned int tmds_clk_div; -+} hdmi_crg_cfg; -+ -+void hdmi_tx_reg_write(unsigned int *reg_addr, unsigned int value); -+ -+unsigned int hdmi_tx_reg_read(const unsigned int *reg_addr); -+ -+void hdmi_reg_write_u32(unsigned int reg_addr, unsigned int value); -+ -+unsigned int hdmi_reg_read_u32(unsigned int reg_addr); -+ -+void drv_hdmi_prod_io_cfg_set(void); -+ -+void drv_hdmi_prod_crg_all_reset_set(bool enable); -+ -+void drv_hdmi_prod_crg_gate_set(bool enable); -+ -+void drv_hdmi_prod_crg_phy_reset_set(bool enable); -+ -+void drv_hdmi_prod_crg_phy_reset_get(bool *enable); -+ -+void drv_hdmi_prod_crg_init(void); -+ -+void drv_hdmi_proc_crg_deinit(void); -+ -+void drv_hdmi_hardware_reset(unsigned int id); -+ -+void drv_hdmi_low_power_set(bool enable); -+ -+ -+#define HDMI_REGISTER_SIZE 4 -+#define hdmi_if_fpga_return(ret) -+#define hdmi_if_fpga_return_void() -+typedef enum { -+ HDMI_DEVICE_ID0, -+ HDMI_DEVICE_ID1, -+ HDMI_DEVICE_ID_BUTT -+} hdmi_device_id; -+ -+#ifdef HDMI_SUPPORT_DUAL_CHANNEL -+#define HDMI_ID_MAX HDMI_DEVICE_ID_BUTT -+#else -+#define HDMI_ID_MAX HDMI_DEVICE_ID1 -+#endif -+ -+#endif /* HDMI_PRODUCT_DEFINE_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/ot_board.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/ot_board.h -new file mode 100755 -index 0000000..729a546 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/ot_board.h -@@ -0,0 +1,424 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef OT_BOARD_H -+#define OT_BOARD_H -+ -+ -+#define DDR_BUS_FR (310000000) /* ddr bus 频率:310M */ -+ -+#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ -+ -+#define DDRC0_REG_ADDR 0x11140000 -+#define DDRC_REGS_SIZE 0x20000 -+ -+#define CRG_REGS_ADDR 0x11010000 -+#define CRG_REGS_ADDR_OFFSET 0x4500 -+#define CRG_REGS_SIZE (0x10000 - CRG_REGS_ADDR_OFFSET) -+ -+#define SYS_REGS_ADDR 0x11020000 -+#define SYS_REGS_SIZE 0x4000 -+ -+#define MISC_REGS_ADDR 0x11024000 -+#define MISC_REGS_SIZE 0x5000 -+ -+#define IOCFG_REGS_ADDR 0x200F0000 -+#define IOCFG_REGS_SIZE 0x10000 -+ -+#define VOU_REGS_ADDR 0x17A00000 -+#define VOU_REGS_SIZE 0x40000 -+ -+#define VGS0_REGS_ADDR 0x17240000 -+#define VGS1_REGS_ADDR 0x17250000 -+#define VGS_REGS_SIZE 0x10000 -+ -+#define GDC0_BASE_ADDR 0x172c0000 -+#define GDC1_BASE_ADDR 0x172c0000 -+#define GDC_REGS_SIZE 0x10000 -+ -+#define VPSS_REGS_ADDR 0x17900000 -+#define VPSS_REGS_SIZE 0x10000 -+ -+#define VI_CAP_REGS_ADDR 0x17400000 -+ -+#define VDAU_REGS_ADDR 0x170c0000 -+ -+#define OTP_USER_REGS_ADDR 0x10122000 -+#define OTP_USER_REGS_SIZE 0x2000 -+ -+#define VI_ANR_MISC_REGS_ADDR 0x17920000 -+#define VI_ANR_MISC_REGS_SIZE 0x200 -+ -+#define GFBG_SOFT_INT_ADDR 0x1202001c -+ -+#define MIPI_CTRL_REGS_ADDR 0x11310000 -+ -+#define VEDU_0_REGS_ADDR 0x17140000 -+#define VEDU_REGS_SIZE 0x10000 -+ -+#define DIS_REGS_ADDR 0x11200000 -+#define DIS_REGS_SIZE 0x10000 -+ -+#define DIS_SOFTRST_REGS_ADDR (0x3C + MISC_REGS_ADDR) -+#define DIS_SOFTRST_REGS_SIZE 0x100 -+ -+#define AVS_BASE_ADDR 0x17930000 -+#define AVS_REG_SIZE 0x10000 -+ -+#define HEVC0_REGS_ADDR 0x11300000 -+#define HEVC_REGS_SIZE 0x10000 -+ -+#define JPEGU_REGS_ADDR 0x171c0000 -+#define JPEGU_REGS_SIZE 0x10000 -+ -+#define JPEGD_REGS_ADDR (0x17180000) -+#define JPEGD_REGS_SIZE 0x6BF -+ -+#define IVE_REGS_ADDR 0x17000000 -+#define IVE_REGS_SIZE 0x10000 -+#define IVE_CRG_RESET_REGS_ADDR 0x110167C0 -+ -+#define FD_BASE_ADDR 0x11E00000 -+#define FD_REGS_SIZE 0x10000 -+#define FD_CRG_RESET_REGS_ADDR 0x12010070 -+ -+#define DSP0_REGS_ADDR 0x16110000 -+#define DSP1_REGS_ADDR 0x16310000 -+ -+#define DPU_REGS_ADDR 0x17030000 -+ -+#define SVP_MAU_0_REGS_ADDR 0x17030000 -+#define SVP_MAU_0_REGS_SIZE 0x10000 -+ -+#define PQP0_REGS_ADDR 0x15000000 -+#define PQP0_REGS_SIZE 0x10000 -+ -+#define SVP_NPU0_REGS_ADDR 0x15000000 -+#define SVP_NPU0_REGS_SIZE 0x10000 -+ -+#define AIAO_REG_ADDR 0x17c00000 -+#define AIAO_REG_SIZE 0x10000 -+ -+#define ACODEC_REG_ADDR 0x17c40000 -+#define ACODEC_REG_SIZE 0x10000 -+ -+/* Interrupt Request Number */ -+#define VOU_IRQ_NR 191 -+#define VOU1_IRQ_NR 192 -+#define MIPI_IRQ_NR 60 -+#define VI_CAP0_IRQ_NR 92 -+#define VI_PROC0_IRQ_NR 93 -+#define VI_PROC1_IRQ_NR 94 -+#define VPSS_IRQ_NR 158 -+#define TDE_IRQ_NR 66 -+#define VGS0_IRQ_NR 170 -+#define VGS1_IRQ_NR 171 -+#define AIO_IRQ_NR 194 -+#define VEDU_0_IRQ_NR 183 -+#define JPEGU_IRQ_NR 181 -+#define JPEGD_IRQ_NR 179 -+#define HEVCU_IRQ_NR 69 -+#define IVE_IRQ_NR 181 -+#define FD_IRQ_NR 89 -+#define GDC0_IRQ_NR 179 -+#define GDC1_IRQ_NR 179 -+#define DIS_IRQ_NR 83 -+#define AVS_IRQ_NR 184 -+#define SVP_MAU_IRQ_NR0 196 -+#define DPU_RECT_IRQ_NR 225 -+#define DPU_MATCH_IRQ_NR 226 -+#define DPU_POSTPROC_IRQ_NR 227 -+#define VDAU_IRQ_NR 183 -+#define PQP0_NS_IRQ_NR 190 -+#define PQP0_S_IRQ_NR 191 -+#define SVP_NPU0_NS_IRQ_NR 190 -+#define SVP_NPU0_S_IRQ_NR 191 -+ -+#define SYS_PERCTL0_ADDR (0x0 + SYS_REGS_ADDR) -+#define SYS_PERCTL1_ADDR (0x4 + SYS_REGS_ADDR) -+#define SYS_PERCTL2_ADDR (0x8 + SYS_REGS_ADDR) -+#define SYS_PERCTL3_ADDR (0xc + SYS_REGS_ADDR) -+#define SYS_PERCTL4_ADDR (0x10 + SYS_REGS_ADDR) -+#define SYS_PERCTL5_ADDR (0x14 + SYS_REGS_ADDR) -+#define SYS_PERCTL6_ADDR (0x18 + SYS_REGS_ADDR) -+#define SYS_PERCTL7_ADDR (0x1c + SYS_REGS_ADDR) -+#define SYS_PERCTL8_ADDR (0x20 + SYS_REGS_ADDR) -+#define SYS_PERCTL9_ADDR (0x24 + SYS_REGS_ADDR) -+#define SYS_PERCTL10_ADDR (0x28 + SYS_REGS_ADDR) -+#define SYS_PERCTL11_ADDR (0x2C + SYS_REGS_ADDR) -+#define SYS_PERCTL12_ADDR (0x30 + SYS_REGS_ADDR) -+#define SYS_PERCTL13_ADDR (0x34 + SYS_REGS_ADDR) -+#define SYS_PERCTL14_ADDR (0x38 + SYS_REGS_ADDR) -+#define SYS_PERCTL15_ADDR (0x3C + SYS_REGS_ADDR) -+#define SYS_PERCTL16_ADDR (0x40 + SYS_REGS_ADDR) -+#define SYS_PERCTL17_ADDR (0x44 + SYS_REGS_ADDR) -+#define SYS_PERCTL18_ADDR (0x48 + SYS_REGS_ADDR) -+#define SYS_PERCTL19_ADDR (0x4c + SYS_REGS_ADDR) -+#define SYS_PERCTL20_ADDR (0x50 + SYS_REGS_ADDR) -+#define SYS_PERCTL21_ADDR (0x54 + SYS_REGS_ADDR) -+#define SYS_PERCTL22_ADDR (0x58 + SYS_REGS_ADDR) -+#define SYS_PERCTL23_ADDR (0x5c + SYS_REGS_ADDR) -+#define SYS_PERCTL24_ADDR (0x60 + SYS_REGS_ADDR) -+#define SYS_PERCTL25_ADDR (0x64 + SYS_REGS_ADDR) -+#define SYS_PERCTL26_ADDR (0x68 + SYS_REGS_ADDR) -+#define SYS_PERCTL27_ADDR (0x6C + SYS_REGS_ADDR) -+#define SYS_PERCTL28_ADDR (0x70 + SYS_REGS_ADDR) -+#define SYS_PERCTL29_ADDR (0x74 + SYS_REGS_ADDR) -+#define SYS_PERCTL30_ADDR (0x78 + SYS_REGS_ADDR) -+#define SYS_PERCTL31_ADDR (0x7C + SYS_REGS_ADDR) -+#define SYS_PERCTL32_ADDR (0x80 + SYS_REGS_ADDR) -+#define SYS_PERCTL33_ADDR (0x84 + SYS_REGS_ADDR) -+#define SYS_PERCTL34_ADDR (0x88 + SYS_REGS_ADDR) -+#define SYS_PERCTL35_ADDR (0x8C + SYS_REGS_ADDR) -+#define SYS_PERCTL36_ADDR (0x90 + SYS_REGS_ADDR) -+#define SYS_PERCTL37_ADDR (0x94 + SYS_REGS_ADDR) -+#define SYS_PERCTL38_ADDR (0x98 + SYS_REGS_ADDR) -+#define SYS_PERCTL39_ADDR (0x9C + SYS_REGS_ADDR) -+#define SYS_PERCTL40_ADDR (0xa0 + SYS_REGS_ADDR) -+#define SYS_PERCTL41_ADDR (0xa4 + SYS_REGS_ADDR) -+#define SYS_PERCTL42_ADDR (0xa8 + SYS_REGS_ADDR) -+#define SYS_PERCTL43_ADDR (0xaC + SYS_REGS_ADDR) -+#define SYS_PERCTL44_ADDR (0xb0 + SYS_REGS_ADDR) -+#define SYS_PERCTL45_ADDR (0xb4 + SYS_REGS_ADDR) -+#define SYS_PERCTL46_ADDR (0xb8 + SYS_REGS_ADDR) -+#define SYS_PERCTL47_ADDR (0xbC + SYS_REGS_ADDR) -+#define SYS_PERCTL48_ADDR (0xc0 + SYS_REGS_ADDR) -+#define SYS_PERCTL49_ADDR (0xc4 + SYS_REGS_ADDR) -+#define SYS_PERCTL50_ADDR (0xc8 + SYS_REGS_ADDR) -+#define SYS_PERCTL51_ADDR (0xcC + SYS_REGS_ADDR) -+#define SYS_PERCTL52_ADDR (0xd0 + SYS_REGS_ADDR) -+#define SYS_PERCTL53_ADDR (0xd4 + SYS_REGS_ADDR) -+#define SYS_PERCTL54_ADDR (0xd8 + SYS_REGS_ADDR) -+#define SYS_PERCTL55_ADDR (0xdC + SYS_REGS_ADDR) -+#define SYS_PERCTL56_ADDR (0xe0 + SYS_REGS_ADDR) -+#define SYS_PERCTL57_ADDR (0xe4 + SYS_REGS_ADDR) -+#define SYS_PERCTL58_ADDR (0xe8 + SYS_REGS_ADDR) -+#define SYS_PERCTL59_ADDR (0xeC + SYS_REGS_ADDR) -+#define SYS_PERCTL60_ADDR (0xf0 + SYS_REGS_ADDR) -+#define SYS_PERCTL61_ADDR (0xf4 + SYS_REGS_ADDR) -+#define SYS_PERCTL62_ADDR (0xf8 + SYS_REGS_ADDR) -+#define SYS_PERCTL63_ADDR (0xfC + SYS_REGS_ADDR) -+#define SYS_PERCTL64_ADDR (0x100 + SYS_REGS_ADDR) -+#define SYS_PERCTL65_ADDR (0x104 + SYS_REGS_ADDR) -+#define SYS_PERCTL66_ADDR (0x108 + SYS_REGS_ADDR) -+#define SYS_PERCTL67_ADDR (0x10c + SYS_REGS_ADDR) -+#define SYS_PERCTL68_ADDR (0x110 + SYS_REGS_ADDR) -+#define SYS_PERCTL69_ADDR (0x114 + SYS_REGS_ADDR) -+#define SYS_PERCTL70_ADDR (0x118 + SYS_REGS_ADDR) -+#define SYS_PERCTL71_ADDR (0x11c + SYS_REGS_ADDR) -+#define SYS_PERCTL72_ADDR (0x120 + SYS_REGS_ADDR) -+#define SYS_PERCTL73_ADDR (0x124 + SYS_REGS_ADDR) -+#define SYS_PERCTL74_ADDR (0x128 + SYS_REGS_ADDR) -+#define SYS_PERCTL75_ADDR (0x12C + SYS_REGS_ADDR) -+#define SYS_PERCTL76_ADDR (0x130 + SYS_REGS_ADDR) -+#define SYS_PERCTL77_ADDR (0x134 + SYS_REGS_ADDR) -+#define SYS_PERCTL78_ADDR (0x138 + SYS_REGS_ADDR) -+#define SYS_PERCTL79_ADDR (0x13C + SYS_REGS_ADDR) -+#define SYS_PERCTL80_ADDR (0x140 + SYS_REGS_ADDR) -+#define SYS_PERCTL81_ADDR (0x144 + SYS_REGS_ADDR) -+#define SYS_PERCTL82_ADDR (0x148 + SYS_REGS_ADDR) -+#define SYS_PERCTL83_ADDR (0x14c + SYS_REGS_ADDR) -+#define SYS_PERCTL84_ADDR (0x150 + SYS_REGS_ADDR) -+#define SYS_PERCTL85_ADDR (0x154 + SYS_REGS_ADDR) -+#define SYS_PERCTL86_ADDR (0x158 + SYS_REGS_ADDR) -+#define SYS_PERCTL87_ADDR (0x15c + SYS_REGS_ADDR) -+#define SYS_PERCTL88_ADDR (0x160 + SYS_REGS_ADDR) -+#define SYS_PERCTL89_ADDR (0x164 + SYS_REGS_ADDR) -+#define SYS_PERCTL90_ADDR (0x168 + SYS_REGS_ADDR) -+#define SYS_PERCTL91_ADDR (0x16C + SYS_REGS_ADDR) -+#define SYS_PERCTL92_ADDR (0x170 + SYS_REGS_ADDR) -+#define SYS_PERCTL93_ADDR (0x174 + SYS_REGS_ADDR) -+#define SYS_PERCTL94_ADDR (0x178 + SYS_REGS_ADDR) -+#define SYS_PERCTL95_ADDR (0x17C + SYS_REGS_ADDR) -+#define SYS_PERCTL96_ADDR (0x180 + SYS_REGS_ADDR) -+#define SYS_PERCTL97_ADDR (0x184 + SYS_REGS_ADDR) -+#define SYS_PERCTL98_ADDR (0x188 + SYS_REGS_ADDR) -+#define SYS_PERCTL99_ADDR (0x18C + SYS_REGS_ADDR) -+#define SYS_PERCTL100_ADDR (0x190 + SYS_REGS_ADDR) -+#define SYS_PERCTL101_ADDR (0x194 + SYS_REGS_ADDR) -+#define SYS_PERCTL102_ADDR (0x198 + SYS_REGS_ADDR) -+#define SYS_PERCTL103_ADDR (0x19C + SYS_REGS_ADDR) -+#define SYS_PERCTL104_ADDR (0x1a0 + SYS_REGS_ADDR) -+#define SYS_PERCTL105_ADDR (0x1a4 + SYS_REGS_ADDR) -+#define SYS_PERCTL106_ADDR (0x1a8 + SYS_REGS_ADDR) -+#define SYS_PERCTL107_ADDR (0x1aC + SYS_REGS_ADDR) -+#define SYS_PERCTL108_ADDR (0x1b0 + SYS_REGS_ADDR) -+#define SYS_PERCTL109_ADDR (0x1b4 + SYS_REGS_ADDR) -+#define SYS_PERCTL110_ADDR (0x1b8 + SYS_REGS_ADDR) -+#define SYS_PERCTL111_ADDR (0x1bC + SYS_REGS_ADDR) -+#define SYS_PERCTL112_ADDR (0x1c0 + SYS_REGS_ADDR) -+#define SYS_PERCTL113_ADDR (0x1c4 + SYS_REGS_ADDR) -+#define SYS_PERCTL114_ADDR (0x1c8 + SYS_REGS_ADDR) -+#define SYS_PERCTL115_ADDR (0x1cC + SYS_REGS_ADDR) -+#define SYS_PERCTL116_ADDR (0x1d0 + SYS_REGS_ADDR) -+#define SYS_PERCTL117_ADDR (0x1d4 + SYS_REGS_ADDR) -+#define SYS_PERCTL118_ADDR (0x1d8 + SYS_REGS_ADDR) -+#define SYS_PERCTL119_ADDR (0x1dC + SYS_REGS_ADDR) -+#define SYS_PERCTL120_ADDR (0x1e0 + SYS_REGS_ADDR) -+#define SYS_PERCTL121_ADDR (0x1e4 + SYS_REGS_ADDR) -+#define SYS_PERCTL122_ADDR (0x1e8 + SYS_REGS_ADDR) -+#define SYS_PERCTL123_ADDR (0x1eC + SYS_REGS_ADDR) -+#define SYS_PERCTL124_ADDR (0x1f0 + SYS_REGS_ADDR) -+#define SYS_PERCTL125_ADDR (0x1f4 + SYS_REGS_ADDR) -+#define SYS_PERCTL126_ADDR (0x1f8 + SYS_REGS_ADDR) -+#define SYS_PERCTL127_ADDR (0x1fC + SYS_REGS_ADDR) -+ -+#define CRG_PERCTL_PLL96_ADDR (0x0180 + CRG_REGS_ADDR) -+#define CRG_PERCTL_PLL97_ADDR (0x0184 + CRG_REGS_ADDR) -+#define CRG_PERCTL_PLL224_ADDR (0x0380 + CRG_REGS_ADDR) -+#define CRG_PERCTL_PLL225_ADDR (0x0384 + CRG_REGS_ADDR) -+ -+#define CRG_PERCTL_PLL0_ADDR (0x0000 + CRG_REGS_ADDR) -+#define CRG_PERCTL_PLL1_ADDR (0x0004 + CRG_REGS_ADDR) -+ -+#define CRG_PERCTL4448_ADDR (0x4580 + CRG_REGS_ADDR) -+#define CRG_PERCTL4496_ADDR (0x4640 + CRG_REGS_ADDR) -+#define CRG_PERCTL4498_ADDR (0x4648 + CRG_REGS_ADDR) -+#define CRG_PERCTL4688_ADDR (0x4940 + CRG_REGS_ADDR) -+#define CRG_PERCTL4768_ADDR (0x4A80 + CRG_REGS_ADDR) -+#define CRG_PERCTL4896_ADDR (0x4C80 + CRG_REGS_ADDR) -+#define CRG_PERCTL4897_ADDR (0x4C84 + CRG_REGS_ADDR) -+#define CRG_PERCTL4898_ADDR (0x4C88 + CRG_REGS_ADDR) -+#define CRG_PERCTL5029_ADDR (0x4E94 + CRG_REGS_ADDR) -+#define CRG_PERCTL6464_ADDR (0x6500 + CRG_REGS_ADDR) -+#define CRG_PERCTL6470_ADDR (0x6518 + CRG_REGS_ADDR) -+#define CRG_PERCTL6560_ADDR (0x6680 + CRG_REGS_ADDR) -+#define CRG_PERCTL6561_ADDR (0x6684 + CRG_REGS_ADDR) -+#define CRG_PERCTL6592_ADDR (0x6700 + CRG_REGS_ADDR) -+#define CRG_PERCTL6624_ADDR (0x6780 + CRG_REGS_ADDR) -+#define CRG_PERCTL6625_ADDR (0x6784 + CRG_REGS_ADDR) -+#define CRG_PERCTL6640_ADDR (0x67C0 + CRG_REGS_ADDR) -+#define CRG_PERCTL6704_ADDR (0x68C0 + CRG_REGS_ADDR) -+#define CRG_PERCTL7248_ADDR (0x7140 + CRG_REGS_ADDR) -+#define CRG_PERCTL7256_ADDR (0x7160 + CRG_REGS_ADDR) -+#define CRG_PERCTL7264_ADDR (0x7180 + CRG_REGS_ADDR) -+#define CRG_PERCTL7376_ADDR (0x7340 + CRG_REGS_ADDR) -+#define CRG_PERCTL7408_ADDR (0x73C0 + CRG_REGS_ADDR) -+#define CRG_PERCTL7568_ADDR (0x7640 + CRG_REGS_ADDR) -+#define CRG_PERCTL8144_ADDR (0x7F40 + CRG_REGS_ADDR) -+#define CRG_PERCTL8152_ADDR (0x7F60 + CRG_REGS_ADDR) -+#define CRG_PERCTL8336_ADDR (0x8240 + CRG_REGS_ADDR) -+#define CRG_PERCTL8338_ADDR (0x8248 + CRG_REGS_ADDR) -+#define CRG_PERCTL8340_ADDR (0x8250 + CRG_REGS_ADDR) -+#define CRG_PERCTL8341_ADDR (0x8254 + CRG_REGS_ADDR) -+#define CRG_PERCTL8342_ADDR (0x8258 + CRG_REGS_ADDR) -+#define CRG_PERCTL8346_ADDR (0x8268 + CRG_REGS_ADDR) -+#define CRG_PERCTL8348_ADDR (0x8270 + CRG_REGS_ADDR) -+#define CRG_PERCTL8349_ADDR (0x8274 + CRG_REGS_ADDR) -+#define CRG_PERCTL8350_ADDR (0x8278 + CRG_REGS_ADDR) -+#define CRG_PERCTL8351_ADDR (0x827C + CRG_REGS_ADDR) -+#define CRG_PERCTL8352_ADDR (0x8280 + CRG_REGS_ADDR) -+#define CRG_PERCTL8528_ADDR (0x8540 + CRG_REGS_ADDR) -+#define CRG_PERCTL8536_ADDR (0x8560 + CRG_REGS_ADDR) -+#define CRG_PERCTL8544_ADDR (0x8580 + CRG_REGS_ADDR) -+#define CRG_PERCTL8552_ADDR (0x85A0 + CRG_REGS_ADDR) -+#define CRG_PERCTL8560_ADDR (0x85C0 + CRG_REGS_ADDR) -+#define CRG_PERCTL8568_ADDR (0x85E0 + CRG_REGS_ADDR) -+#define CRG_PERCTL8576_ADDR (0x8600 + CRG_REGS_ADDR) -+#define CRG_PERCTL8584_ADDR (0x8620 + CRG_REGS_ADDR) -+#define CRG_PERCTL8592_ADDR (0x8640 + CRG_REGS_ADDR) -+#define CRG_PERCTL8784_ADDR (0x8940 + CRG_REGS_ADDR) -+#define CRG_PERCTL8792_ADDR (0x8960 + CRG_REGS_ADDR) -+#define CRG_PERCTL8800_ADDR (0x8980 + CRG_REGS_ADDR) -+#define CRG_PERCTL8808_ADDR (0x89A0 + CRG_REGS_ADDR) -+#define CRG_PERCTL9296_ADDR (0x9140 + CRG_REGS_ADDR) -+#define CRG_PERCTL9297_ADDR (0x9144 + CRG_REGS_ADDR) -+#define CRG_PERCTL9298_ADDR (0x9148 + CRG_REGS_ADDR) -+#define CRG_PERCTL9300_ADDR (0x9150 + CRG_REGS_ADDR) -+#define CRG_PERCTL9301_ADDR (0x9154 + CRG_REGS_ADDR) -+#define CRG_PERCTL9302_ADDR (0x9158 + CRG_REGS_ADDR) -+#define CRG_PERCTL9303_ADDR (0x915C + CRG_REGS_ADDR) -+#define CRG_PERCTL9304_ADDR (0x9160 + CRG_REGS_ADDR) -+#define CRG_PERCTL9305_ADDR (0x9164 + CRG_REGS_ADDR) -+#define CRG_PERCTL9313_ADDR (0x9184 + CRG_REGS_ADDR) -+#define CRG_PERCTL9321_ADDR (0x91A4 + CRG_REGS_ADDR) -+#define CRG_PERCTL9329_ADDR (0x91C4 + CRG_REGS_ADDR) -+#define CRG_PERCTL9680_ADDR (0x9740 + CRG_REGS_ADDR) -+#define CRG_PERCTL9681_ADDR (0x9744 + CRG_REGS_ADDR) -+#define CRG_PERCTL9688_ADDR (0x9760 + CRG_REGS_ADDR) -+#define CRG_PERCTL9689_ADDR (0x9764 + CRG_REGS_ADDR) -+#define CRG_PERCTL9936_ADDR (0x9B40 + CRG_REGS_ADDR) -+#define CRG_PERCTL9937_ADDR (0x9B44 + CRG_REGS_ADDR) -+#define CRG_PERCTL9944_ADDR (0x9B60 + CRG_REGS_ADDR) -+#define CRG_PERCTL9945_ADDR (0x9B64 + CRG_REGS_ADDR) -+#define CRG_PERCTL9952_ADDR (0x9B80 + CRG_REGS_ADDR) -+#define CRG_PERCTL9953_ADDR (0x9B84 + CRG_REGS_ADDR) -+#define CRG_PERCTL10064_ADDR (0x9D40 + CRG_REGS_ADDR) -+#define CRG_PERCTL10065_ADDR (0x9D44 + CRG_REGS_ADDR) -+#define CRG_PERCTL10128_ADDR (0x9E40 + CRG_REGS_ADDR) -+#define CRG_PERCTL10129_ADDR (0x9E44 + CRG_REGS_ADDR) -+#define CRG_PERCTL10160_ADDR (0x9EC0 + CRG_REGS_ADDR) -+#define CRG_PERCTL10161_ADDR (0x9EC4 + CRG_REGS_ADDR) -+#define CRG_PERCTL10168_ADDR (0x9EE0 + CRG_REGS_ADDR) -+#define CRG_PERCTL10169_ADDR (0x9EE4 + CRG_REGS_ADDR) -+#define CRG_PERCTL10256_ADDR (0xA040 + CRG_REGS_ADDR) -+#define CRG_PERCTL10784_ADDR (0xA880 + CRG_REGS_ADDR) -+#define CRG_PERCTL10912_ADDR (0xAA80 + CRG_REGS_ADDR) -+#define CRG_PERCTL12288_ADDR (0xC000 + CRG_REGS_ADDR) -+#define CRG_PERCTL12289_ADDR (0xC004 + CRG_REGS_ADDR) -+#define CRG_PERCTL12290_ADDR (0xC008 + CRG_REGS_ADDR) -+ -+#define VI_PORT_CLK_OFFSET 12 -+#define VI_PORT_CLK_MASK 0x7 -+ -+#define MISC_CTL12C_ADDR (0x12C + MISC_REGS_ADDR) -+#define MISC_CTL98_ADDR (0x98 + MISC_REGS_ADDR) -+#define MISC_CTL9C_ADDR (0x9C + MISC_REGS_ADDR) -+#define MISC_CTLAC_ADDR (0xAC + MISC_REGS_ADDR) -+#define MISC_CTLB0_ADDR (0xB0 + MISC_REGS_ADDR) -+#define MISC_CTL2014_ADDR (0x2014 + MISC_REGS_ADDR) -+ -+#define MISC_VICTRL_ADDR (0x009c + MISC_REGS_ADDR) -+#define MISC_VICTRL1_ADDR (0x1000 + MISC_REGS_ADDR) -+ -+#define SYS_VI_DIV_SEL2 0x00 /* 2 division */ -+#define SYS_VI_DIV_SEL4 0x01 /* 4 division */ -+#define SYS_VI_DIV_SEL1 0x02 /* no division */ -+ -+#define SYS_VO_DIV_SEL1 0x00 /* 1 division */ -+#define SYS_VO_DIV_SEL2 0x01 /* 2 division */ -+#define SYS_VO_DIV_SEL4 0x02 /* 4 division */ -+ -+#define SYS_AIO_SAMPLE_CLK16 0x0 /* 16 division */ -+#define SYS_AIO_SAMPLE_CLK32 0x01 /* 32 division */ -+#define SYS_AIO_SAMPLE_CLK48 0x02 /* 48 division */ -+#define SYS_AIO_SAMPLE_CLK64 0x03 /* 64 division */ -+#define SYS_AIO_SAMPLE_CLK128 0x04 /* 128 division */ -+#define SYS_AIO_SAMPLE_CLK256 0x05 /* 256 division */ -+#define SYS_AIO_SAMPLE_CLK320 0x06 /* 320 division */ -+#define SYS_AIO_SAMPLE_CLK384 0x07 /* 384 division */ -+ -+#define SYS_AIO_BS_CLK1 0x00 /* 1 division */ -+#define SYS_AIO_BS_CLK2 0x02 /* 2 division */ -+#define SYS_AIO_BS_CLK3 0x01 /* 3 division */ -+#define SYS_AIO_BS_CLK4 0x03 /* 4 division */ -+#define SYS_AIO_BS_CLK6 0x04 /* 6 division */ -+#define SYS_AIO_BS_CLK8 0x05 /* 8 division */ -+#define SYS_AIO_BS_CLK12 0x06 /* 12 division */ -+#define SYS_AIO_BS_CLK16 0x07 /* 16 division */ -+#define SYS_AIO_BS_CLK24 0x08 /* 24 division */ -+#define SYS_AIO_BS_CLK32 0x09 /* 32 division */ -+#define SYS_AIO_BS_CLK48 0x0a /* 48 division */ -+#define SYS_AIO_BS_CLK64 0x0b /* 64 division */ -+ -+#define MIPI_RX_CFG_ADDR (0x0 + VI_ANR_MISC_REGS_ADDR) -+ -+#define OTP_USER_LOCKABLE0 (0x58 + OTP_USER_REGS_ADDR) -+ -+#endif /* OT_BOARD_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.c b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.c -new file mode 100755 -index 0000000..b48e6d5 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.c -@@ -0,0 +1,251 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#include "hdmi_reg_crg.h" -+#include "hdmi_product_define.h" -+ -+volatile hdmi_reg_crg *g_crg_regs = NULL; -+ -+int hdmi_reg_crg_init(void) -+{ -+ -+ if (g_crg_regs != NULL) { -+ return 0; -+ } -+ g_crg_regs = (volatile hdmi_reg_crg *)ioremap(HDMI_CRG_ADDR, sizeof(hdmi_reg_crg)); -+ if (g_crg_regs == NULL) { -+ printk("crg addr ioremap failed!\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+int hdmi_reg_crg_deinit(void) -+{ -+ if (g_crg_regs != NULL) { -+ iounmap((void *)g_crg_regs); -+ g_crg_regs = NULL; -+ } -+ return 0; -+} -+ -+void hdmi_reg_ctrl_osc_24m_cken_set(unsigned char hdmitx_ctrl_osc_24m_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_osc_24m_cken = hdmitx_ctrl_osc_24m_cken; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctrl_cec_cken_set(unsigned char hdmitx_ctrl_cec_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_cec_cken = hdmitx_ctrl_cec_cken; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctrl_os_cken_set(unsigned char hdmitx_ctrl_os_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_os_cken = hdmitx_ctrl_os_cken; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctrl_as_cken_set(unsigned char as_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_as_cken = as_cken; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctrl_bus_srst_req_set(unsigned char bus_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_bus_srst_req = bus_srst_req; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctrl_srst_req_set(unsigned char srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_srst_req = srst_req; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctrl_cec_srst_req_set(unsigned char cec_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8144 crg8144; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8144.u32); -+ crg8144.u32 = hdmi_tx_reg_read(reg_addr); -+ crg8144.bits.hdmitx_ctrl_cec_srst_req = cec_srst_req; -+ hdmi_tx_reg_write(reg_addr, crg8144.u32); -+ -+ return; -+} -+ -+void hdmi_reg_hdmitx_phy_tmds_cken_set(unsigned char phy_tmds_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.hdmitx_phy_tmds_cken = phy_tmds_cken; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+void hdmi_reg_hdmitx_phy_modclk_cken_set(unsigned char phy_modclk_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.hdmitx_phy_modclk_cken = phy_modclk_cken; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ac_ctrl_modclk_cken_set(unsigned char ac_ctrl_modclk_cken) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.ac_ctrl_modclk_cken = ac_ctrl_modclk_cken; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+void hdmi_reg_phy_srst_req_set(unsigned char phy_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.hdmitx_phy_srst_req = phy_srst_req; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_phy_srst_req_get(void) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ return crg_8152.bits.hdmitx_phy_srst_req; -+} -+ -+void hdmi_reg_phy_bus_srst_req_set(unsigned char bus_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.hdmitx_phy_bus_srst_req = bus_srst_req; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ac_ctrl_srst_req_set(unsigned char ac_ctrl_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.ac_ctrl_srst_req = ac_ctrl_srst_req; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ac_ctrl_bus_srst_req_set(unsigned char ac_ctrl_bus_srst_req) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.ac_ctrl_bus_srst_req = ac_ctrl_bus_srst_req; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -+ -+void hdmi_reg_phy_clk_pctrl_set(unsigned char clk_pctrl) -+{ -+ unsigned int *reg_addr = NULL; -+ peri_crg8152 crg_8152; -+ -+ reg_addr = (unsigned int *)&(g_crg_regs->crg8152.u32); -+ crg_8152.u32 = hdmi_tx_reg_read(reg_addr); -+ crg_8152.bits.hdmitx_phy_clk_pctrl = clk_pctrl; -+ hdmi_tx_reg_write(reg_addr, crg_8152.u32); -+ -+ return; -+} -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.h b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.h -new file mode 100755 -index 0000000..6f759f8 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/hi3403v100/regs/hdmi_reg_crg.h -@@ -0,0 +1,79 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HDMI_REG_CRG_H -+#define HDMI_REG_CRG_H -+ -+ -+typedef union { -+ struct { -+ unsigned int rsv_0 : 2; /* [1..0] */ -+ unsigned int hdmitx_ctrl_osc_24m_cken : 1; /* [2] */ -+ unsigned int hdmitx_ctrl_cec_cken : 1; /* [3] */ -+ unsigned int hdmitx_ctrl_os_cken : 1; /* [4] */ -+ unsigned int hdmitx_ctrl_as_cken : 1; /* [5] */ -+ unsigned int hdmitx_ctrl_bus_srst_req : 1; /* [6] */ -+ unsigned int hdmitx_ctrl_srst_req : 1; /* [7] */ -+ unsigned int hdmitx_ctrl_cec_srst_req : 1; /* [8] */ -+ unsigned int rsv_1 : 23; /* [31..9] */ -+ } bits; -+ unsigned int u32; -+} peri_crg8144; -+ -+typedef union { -+ struct { -+ unsigned int hdmitx_phy_tmds_cken : 1; /* [0] */ -+ unsigned int hdmitx_phy_modclk_cken : 1; /* [1] */ -+ unsigned int ac_ctrl_modclk_cken : 1; /* [2] */ -+ unsigned int rsv_0 : 1; /* [3] */ -+ unsigned int hdmitx_phy_srst_req : 1; /* [4] */ -+ unsigned int hdmitx_phy_bus_srst_req : 1; /* [5] */ -+ unsigned int ac_ctrl_srst_req : 1; /* [6] */ -+ unsigned int ac_ctrl_bus_srst_req : 1; /* [7] */ -+ unsigned int hdmitx_phy_clk_pctrl : 1; /* [8] */ -+ unsigned int rsv_1 : 23; /* [31..9] */ -+ } bits; -+ unsigned int u32; -+} peri_crg8152; -+ -+typedef struct { -+ volatile peri_crg8144 crg8144; /* 0x7F40 */ -+ volatile unsigned int rsv[7]; /* 0x7F44~0x0x7F5C */ -+ volatile peri_crg8152 crg8152; /* 0x7F60 */ -+} hdmi_reg_crg; -+ -+int hdmi_reg_crg_init(void); -+int hdmi_reg_crg_deinit(void); -+void hdmi_reg_ctrl_osc_24m_cken_set(unsigned char hdmitx_ctrl_osc_24m_cken); -+void hdmi_reg_ctrl_cec_cken_set(unsigned char hdmitx_ctrl_cec_cken); -+void hdmi_reg_ctrl_os_cken_set(unsigned char hdmitx_ctrl_os_cken); -+void hdmi_reg_ctrl_as_cken_set(unsigned char hdmitx_ctrl_as_cken); -+void hdmi_reg_ctrl_bus_srst_req_set(unsigned char hdmitx_ctrl_bus_srst_req); -+void hdmi_reg_ctrl_srst_req_set(unsigned char hdmitx_ctrl_srst_req); -+void hdmi_reg_ctrl_cec_srst_req_set(unsigned char hdmitx_ctrl_cec_srst_req); -+void hdmi_reg_hdmitx_phy_tmds_cken_set(unsigned char phy_tmds_cken); -+void hdmi_reg_hdmitx_phy_modclk_cken_set(unsigned char phy_modclk_cken); -+void hdmi_reg_ac_ctrl_modclk_cken_set(unsigned char ac_ctrl_modclk_cken); -+void hdmi_reg_phy_srst_req_set(unsigned char hdmitx_phy_srst_req); -+unsigned char hdmi_reg_phy_srst_req_get(void); -+void hdmi_reg_phy_bus_srst_req_set(unsigned char hdmitx_phy_bus_srst_req); -+void hdmi_reg_ac_ctrl_srst_req_set(unsigned char ac_ctrl_srst_req); -+void hdmi_reg_ac_ctrl_bus_srst_req_set(unsigned char ac_ctrl_bus_srst_req); -+void hdmi_reg_phy_clk_pctrl_set(unsigned char hdmitx_phy_clk_pctrl); -+#endif -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.c b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.c -new file mode 100755 -index 0000000..736bb02 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.c -@@ -0,0 +1,1056 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#include "hdmi_reg_dphy.h" -+#include "hdmi_product_define.h" -+ -+static volatile hdmitx21_dphy_reg_type *g_hdmitx_dphy_regs[HDMI_ID_MAX] = {NULL}; -+ -+int hdmi_reg_tx_phy_init(unsigned int id, char *addr) -+{ -+ -+ g_hdmitx_dphy_regs[id] = (hdmitx21_dphy_reg_type *)(addr); -+ return 0; -+} -+ -+unsigned int *hdmi_reg_tx_get_phy_addr(unsigned int id) -+{ -+ -+ return (unsigned int *)g_hdmitx_dphy_regs[id]; -+} -+ -+int hdmi_reg_tx_phy_deinit(unsigned int id) -+{ -+ -+ if (g_hdmitx_dphy_regs[id] != NULL) { -+ g_hdmitx_dphy_regs[id] = NULL; -+ } -+ return 0; -+} -+ -+static void hdmi21_tx_reg_write(unsigned int *reg_addr, unsigned int value) -+{ -+ -+ *(volatile unsigned int *)reg_addr = value; -+ return; -+} -+ -+static unsigned int hdmi21_tx_reg_read(const unsigned int *reg_addr) -+{ -+ -+ return *(volatile unsigned int *)(reg_addr); -+} -+ -+void hdmi_reg_stb_cs_en_set(unsigned int id, unsigned short stb_cs_en) -+{ -+ unsigned int *reg_addr = NULL; -+ phy_csen csen; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_cs_en.u32); -+ csen.u32 = hdmi21_tx_reg_read(reg_addr); -+ csen.bits.stb_cs_en = stb_cs_en; -+ hdmi21_tx_reg_write(reg_addr, csen.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_wen_set(unsigned int id, unsigned char stb_wen) -+{ -+ unsigned int *reg_addr = NULL; -+ phy_wr tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_write_en.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.stb_wen = stb_wen; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_resetn_set(unsigned int id, unsigned char reg_resetn) -+{ -+ unsigned int *reg_addr = NULL; -+ resetn tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_reset.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.resetn = reg_resetn; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_resetn_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ resetn tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_reset.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ -+ return tmp.bits.resetn; -+} -+ -+void hdmi_reg_src_enable_set(unsigned int id, unsigned char src_enable) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcparam tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.src_enable = src_enable; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_wdata_set(unsigned int id, unsigned char stb_wdata) -+{ -+ unsigned int *reg_addr = NULL; -+ phy_wdata wdata; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_wdata.u32); -+ wdata.u32 = hdmi21_tx_reg_read(reg_addr); -+ wdata.bits.stb_wdata = stb_wdata; -+ hdmi21_tx_reg_write(reg_addr, wdata.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fcg_lock_en_set(unsigned int id, unsigned char up_fcg_lock_en) -+{ -+ unsigned int *reg_addr = NULL; -+ fcgset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fcg_lock_en = up_fcg_lock_en; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_addr_set(unsigned int id, unsigned char stb_addr) -+{ -+ unsigned int *reg_addr = NULL; -+ phy_addr tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_addr.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.stb_addr = stb_addr; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_stb_rdata_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ phy_rdata rdata; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_rdata.u32); -+ rdata.u32 = hdmi21_tx_reg_read(reg_addr); -+ -+ return rdata.bits.stb_rdata; -+} -+ -+void hdmi_reg_src_lock_cnt_set(unsigned int id, unsigned char src_lock_cnt) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcparam tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.src_lock_cnt = src_lock_cnt; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_src_lock_val_set(unsigned int id, unsigned char src_lock_val) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcparam tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.src_lock_val = src_lock_val; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_src_freq_ext_set(unsigned int id, unsigned short src_freq_ext) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcfreq tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.src_freq_ext = src_freq_ext; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fdsrcfreq_unused2_set(unsigned int id, unsigned char fdsrcfreq_unused_2) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcfreq tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fdsrcfreq_unused_2 = fdsrcfreq_unused_2; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_txfifoset0_unused_set(unsigned int id, unsigned char txfifoset0_unused) -+{ -+ unsigned int *reg_addr = NULL; -+ txfifoset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->tx_fifo_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.txfifoset0_unused = txfifoset0_unused; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_src_freq_opt_set(unsigned int id, unsigned char src_freq_opt) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcfreq tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.src_freq_opt = src_freq_opt; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fdsrcfreq_unused1_set(unsigned int id, unsigned char fdsrcfreq_unused_1) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcfreq tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fdsrcfreq_unused_1 = fdsrcfreq_unused_1; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_src_cnt_opt_set(unsigned int id, unsigned char src_cnt_opt) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcfreq tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_freq.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.src_cnt_opt = src_cnt_opt; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+unsigned int hdmi_reg_src_cnt_out_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcres tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_res.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ -+ return tmp.bits.src_cnt_out; -+} -+ -+unsigned char hdmi_reg_src_det_stat_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcres tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_res.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ -+ return tmp.bits.src_det_stat; -+} -+ -+void hdmi_reg_clkdet_sel_set(unsigned int id, unsigned char i_clkdet_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ fcopt tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_opt.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.i_clkdet_sel = i_clkdet_sel; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_up_sampler_ratio_sel_set(unsigned int id, unsigned char up_sampler_ratio_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ fcdstepsetl tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_dstep_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.up_sampler_ratio_sel = up_sampler_ratio_sel; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fcdstepset_unused_set(unsigned int id, unsigned char fcdstepset_unused) -+{ -+ unsigned int *reg_addr = NULL; -+ fcdstepsetl tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_dstep_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fcdstepset_unused = fcdstepset_unused; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_divn_h20_set(unsigned int id, unsigned char up_divn_h20) -+{ -+ unsigned int *reg_addr = NULL; -+ fcdstepsetl tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fc_dstep_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.divn_h20 = up_divn_h20; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_en_sdm_set(unsigned int id, unsigned char en_sdm) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sdm = en_sdm; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mode_en_set(unsigned int id, unsigned char reg_hdmi_mode_en) -+{ -+ unsigned int *reg_addr = NULL; -+ hdmi_mode mode; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->stb_hdmi_mode.u32); -+ mode.u32 = hdmi21_tx_reg_read(reg_addr); -+ mode.bits.reg_hdmi_mode_en = reg_hdmi_mode_en; -+ hdmi21_tx_reg_write(reg_addr, mode.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_en_sdm_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ -+ return tmp.bits.sdm; -+} -+ -+void hdmi_reg_en_mod_set(unsigned int id, unsigned char en_mod) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.mod = en_mod; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_en_mod_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ return tmp.bits.mod; -+} -+ -+void hdmi_reg_en_ctrl_set(unsigned int id, unsigned char en_ctrl) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.ctrl = en_ctrl; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+unsigned char hdmi_reg_en_ctrl_get(unsigned int id) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ -+ return tmp.bits.ctrl; -+} -+ -+void hdmi_reg_init_set(unsigned int id, unsigned char init) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.init = init; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mod_n_set(unsigned int id, unsigned short mod_n) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset3 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set3.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.mod_n = mod_n; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mod_t_set(unsigned int id, unsigned char mod_t) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset3 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set3.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.mod_t = mod_t; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mod_len_set(unsigned int id, unsigned char mod_len) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset3 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set3.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.mod_len = mod_len; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mod_d_set(unsigned int id, unsigned short mod_d) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivset4 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_set4.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.mod_d = mod_d; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fdsrcparam_unused_set(unsigned int id, unsigned char fdsrcparam_unused) -+{ -+ unsigned int *reg_addr = NULL; -+ fdsrcparam tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fd_src_param.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fdsrcparam_unused = fdsrcparam_unused; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fdiv_in_set(unsigned int id, unsigned int i_fdiv_in) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivs_tat1 fdivstat1; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_stat1.u32); -+ fdivstat1.u32 = hdmi21_tx_reg_read(reg_addr); -+ fdivstat1.bits.i_fdiv_in = i_fdiv_in; -+ hdmi21_tx_reg_write(reg_addr, fdivstat1.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mdiv_set(unsigned int id, unsigned char i_mdiv) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivmanual tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_manual.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.i_mdiv = i_mdiv; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_frl_clock_set(unsigned int id, unsigned char sw_reset_frl_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_frl_clock = sw_reset_frl_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_manual_en_set(unsigned int id, unsigned char i_manual_en) -+{ -+ unsigned int *reg_addr = NULL; -+ fdivmanual tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fdiv_manual.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.i_manual_en = i_manual_en; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_delay1_set(unsigned int id, unsigned char stb_delay1) -+{ -+ unsigned int *reg_addr = NULL; -+ stb_opt stbopt; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); -+ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); -+ stbopt.bits.stb_delay1 = stb_delay1; -+ hdmi21_tx_reg_write(reg_addr, stbopt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ref_clk_sel_set(unsigned int id, unsigned char i_ref_clk_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ refclksel tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->ref_clk_sel.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.i_ref_clk_sel = i_ref_clk_sel; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fcg_dither_en_set(unsigned int id, unsigned char up_fcg_dither_en) -+{ -+ unsigned int *reg_addr = NULL; -+ fcgset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fcg_dither_en = up_fcg_dither_en; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fcg_dlf_en_set(unsigned int id, unsigned char up_fcg_dlf_en) -+{ -+ unsigned int *reg_addr = NULL; -+ fcgset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fcg_dlf_en = up_fcg_dlf_en; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fcg_en_set(unsigned int id, unsigned char up_fcg_en) -+{ -+ unsigned int *reg_addr = NULL; -+ fcgset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->fcg_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.fcg_en = up_fcg_en; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_enable_h20_set(unsigned int id, unsigned char up_enable_h20) -+{ -+ unsigned int *reg_addr = NULL; -+ txfifoset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->tx_fifo_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.enable_h20 = up_enable_h20; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_pr_en_h20_set(unsigned int id, unsigned char up_pr_en_h20) -+{ -+ unsigned int *reg_addr = NULL; -+ txfifoset0 tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->tx_fifo_set0.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.pr_en_h20 = up_pr_en_h20; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ch_out_sel_set(unsigned int id, unsigned char up_ch_out_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ tx_data_out_sel txdataoutsel; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->data_out_sel.u32); -+ txdataoutsel.u32 = hdmi21_tx_reg_read(reg_addr); -+ txdataoutsel.bits.ch_out_sel = up_ch_out_sel; -+ hdmi21_tx_reg_write(reg_addr, txdataoutsel.u32); -+ -+ return; -+} -+ -+void hdmi_reg_hsset_set(unsigned int id, unsigned char up_hsset) -+{ -+ unsigned int *reg_addr = NULL; -+ hsset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->hs_set.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.hsset = up_hsset; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_global_reset_set(unsigned int id, unsigned char global_reset) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.global_reset = global_reset; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_swreset_unused_set(unsigned int id, unsigned short swreset_unused) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.swreset_unused = swreset_unused; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_dac_clock_gat_set(unsigned int id, unsigned char dac_clock_gat) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.dac_clock_gat = dac_clock_gat; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_delay2_set(unsigned int id, unsigned char stb_delay2) -+{ -+ unsigned int *reg_addr = NULL; -+ stb_opt stbopt; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); -+ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); -+ stbopt.bits.stb_delay2 = stb_delay2; -+ hdmi21_tx_reg_write(reg_addr, stbopt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_cs_sel_set(unsigned int id, unsigned char stb_cs_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ stb_opt stbopt; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); -+ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); -+ stbopt.bits.stb_cs_sel = stb_cs_sel; -+ hdmi21_tx_reg_write(reg_addr, stbopt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_acc_sel_set(unsigned int id, unsigned char stb_acc_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ stb_opt stbopt; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); -+ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); -+ stbopt.bits.stb_acc_sel = stb_acc_sel; -+ hdmi21_tx_reg_write(reg_addr, stbopt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_stb_delay0_set(unsigned int id, unsigned char stb_delay0) -+{ -+ unsigned int *reg_addr = NULL; -+ stb_opt stbopt; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); -+ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); -+ stbopt.bits.stb_delay0 = stb_delay0; -+ hdmi21_tx_reg_write(reg_addr, stbopt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fd_clk_sel_set(unsigned int id, unsigned char up_fd_clk_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ clk_set clkset; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); -+ clkset.u32 = hdmi21_tx_reg_read(reg_addr); -+ clkset.bits.fd_clk_sel = up_fd_clk_sel; -+ hdmi21_tx_reg_write(reg_addr, clkset.u32); -+ -+ return; -+} -+ -+void hdmi_reg_refclk_sel_set(unsigned int id, unsigned char up_refclk_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ clk_set clkset; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); -+ clkset.u32 = hdmi21_tx_reg_read(reg_addr); -+ clkset.bits.refclk_sel = up_refclk_sel; -+ hdmi21_tx_reg_write(reg_addr, clkset.u32); -+ -+ return; -+} -+ -+void hdmi_reg_ctman_set(unsigned int id, unsigned char up_ctman) -+{ -+ unsigned int *reg_addr = NULL; -+ clk_set clkset; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); -+ clkset.u32 = hdmi21_tx_reg_read(reg_addr); -+ clkset.bits.ctman = up_ctman; -+ hdmi21_tx_reg_write(reg_addr, clkset.u32); -+ -+ return; -+} -+ -+void hdmi_reg_req_length_set(unsigned int id, unsigned char req_length) -+{ -+ unsigned int *reg_addr = NULL; -+ stb_opt stbopt; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->opt.u32); -+ stbopt.u32 = hdmi21_tx_reg_read(reg_addr); -+ stbopt.bits.req_length = req_length; -+ hdmi21_tx_reg_write(reg_addr, stbopt.u32); -+ -+ return; -+} -+ -+void hdmi_reg_fdivclk_sel_set(unsigned int id, unsigned char up_fdivclk_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ clk_set clkset; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); -+ clkset.u32 = hdmi21_tx_reg_read(reg_addr); -+ clkset.bits.fdivclk_sel = up_fdivclk_sel; -+ hdmi21_tx_reg_write(reg_addr, clkset.u32); -+ -+ return; -+} -+ -+void hdmi_reg_mod_div_val_set(unsigned int id, unsigned char mod_div_val) -+{ -+ unsigned int *reg_addr = NULL; -+ clk_set clkset; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); -+ clkset.u32 = hdmi21_tx_reg_read(reg_addr); -+ clkset.bits.mod_div_val = mod_div_val; -+ hdmi21_tx_reg_write(reg_addr, clkset.u32); -+ -+ return; -+} -+ -+void hdmi_reg_modclk_sel_set(unsigned int id, unsigned char up_modclk_sel) -+{ -+ unsigned int *reg_addr = NULL; -+ clk_set clkset; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->clk_set.u32); -+ clkset.u32 = hdmi21_tx_reg_read(reg_addr); -+ clkset.bits.modclk_sel = up_modclk_sel; -+ hdmi21_tx_reg_write(reg_addr, clkset.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_mod_clock_set(unsigned int id, unsigned char sw_reset_mod_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_mod_clock = sw_reset_mod_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_tmds_clock_set(unsigned int id, unsigned char sw_reset_tmds_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_tmds_clock = sw_reset_tmds_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_mpll_clock_set(unsigned int id, unsigned char sw_reset_mpll_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_mpll_clock = sw_reset_mpll_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_nco_clock_set(unsigned int id, unsigned char sw_reset_nco_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_nco_clock = sw_reset_nco_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_fd_clock_set(unsigned int id, unsigned char sw_reset_fd_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_fd_clock = sw_reset_fd_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_mod_and_mpll_clock_set(unsigned int id, unsigned char sw_reset_mod_and_mpll_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_mod_and_mpll_clock = sw_reset_mod_and_mpll_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_mod_and_nco_clock_set(unsigned int id, unsigned char sw_reset_mod_and_nco_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_mod_and_nco_clock = sw_reset_mod_and_nco_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_mod_and_fd_clock_set(unsigned int id, unsigned char sw_reset_mod_and_fd_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_mod_and_fd_clock = sw_reset_mod_and_fd_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_hsfifo_clock_set(unsigned int id, unsigned char sw_reset_hsfifo_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_hsfifo_clock = sw_reset_hsfifo_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_txfifo_clock_set(unsigned int id, unsigned char sw_reset_txfifo_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_txfifo_clock = sw_reset_txfifo_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_data_clock_set(unsigned int id, unsigned char sw_reset_data_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_data_clock = sw_reset_data_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_hs_clock_set(unsigned int id, unsigned char sw_reset_hs_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_hs_clock = sw_reset_hs_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_pllref_clock_set(unsigned int id, unsigned char sw_reset_pllref_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_pllref_clock = sw_reset_pllref_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_sw_reset_dac_clock_set(unsigned int id, unsigned char sw_reset_dac_clock) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.sw_reset_dac_clock = sw_reset_dac_clock; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -+void hdmi_reg_up_sample_fifo_clock_swrst_set(unsigned int id, unsigned char up_sample_fifo_clock_swrst) -+{ -+ unsigned int *reg_addr = NULL; -+ sw_reset tmp; -+ -+ reg_addr = (unsigned int *)&(g_hdmitx_dphy_regs[id]->sw_rst.u32); -+ tmp.u32 = hdmi21_tx_reg_read(reg_addr); -+ tmp.bits.up_sample_fifo_clock_swrst = up_sample_fifo_clock_swrst; -+ hdmi21_tx_reg_write(reg_addr, tmp.u32); -+ -+ return; -+} -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.h b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.h -new file mode 100755 -index 0000000..dbfe642 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/phy/v200/regs/hdmi_reg_dphy.h -@@ -0,0 +1,1095 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+#ifndef HDMI_REG_DPHY_H -+#define HDMI_REG_DPHY_H -+ -+ -+typedef union { -+ struct { -+ unsigned int gpport0 : 16; /* [15:0] */ -+ unsigned int rsv_0 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} t2gpport0; -+ -+typedef union { -+ struct { -+ unsigned int gpport1 : 16; /* [15:0] */ -+ unsigned int rsv_1 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} t2gpport1; -+ -+typedef union { -+ struct { -+ unsigned int stb_cs_en : 16; /* [15:0] */ -+ unsigned int rsv_2 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} phy_csen; -+ -+typedef union { -+ struct { -+ unsigned int stb_wen : 1; /* [0] */ -+ unsigned int rsv_3 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} phy_wr; -+ -+typedef union { -+ struct { -+ unsigned int resetn : 1; /* [0] */ -+ unsigned int rsv_4 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} resetn; -+ -+typedef union { -+ struct { -+ unsigned int stb_addr : 4; /* [3:0] */ -+ unsigned int rsv_5 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} phy_addr; -+ -+typedef union { -+ struct { -+ unsigned int stb_wdata : 8; /* [7:0] */ -+ unsigned int rsv_6 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} phy_wdata; -+ -+typedef union { -+ struct { -+ unsigned int stb_rdata : 8; /* [7:0] */ -+ unsigned int rsv_7 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} phy_rdata; -+ -+typedef union { -+ struct { -+ unsigned int zcal : 5; /* [4:0] */ -+ unsigned int zcaldone : 1; /* [5] */ -+ unsigned int zcalsub : 2; /* [7:6] */ -+ unsigned int rxsense : 4; /* [11:8] */ -+ unsigned int rsv_8 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} zcalreg; -+ -+typedef union { -+ struct { -+ unsigned int zcalclk : 1; /* [0] */ -+ unsigned int rsv_9 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} zcalclk; -+ -+typedef union { -+ struct { -+ unsigned int c0shortdet : 1; /* [0] */ -+ unsigned int c1shortdet : 1; /* [1] */ -+ unsigned int c2shortdet : 1; /* [2] */ -+ unsigned int clkshortdet : 1; /* [3] */ -+ unsigned int rsv_10 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} shortdet; -+ -+typedef union { -+ struct { -+ unsigned int rsv_11 : 12; /* [11:0] */ -+ unsigned int t2_plllkvdetl : 1; /* [12] */ -+ unsigned int t2_plllkcdet : 1; /* [13] */ -+ unsigned int t2_plllkvdet2 : 1; /* [14] */ -+ unsigned int t2_lkvdetlow : 1; /* [15] */ -+ unsigned int t2_lkvdethigh : 1; /* [16] */ -+ unsigned int rsv_12 : 15; /* [31:17] */ -+ } bits; -+ unsigned int u32; -+} det; -+ -+typedef union { -+ struct { -+ unsigned int src_lock_val : 8; /* [7:0] */ -+ unsigned int src_lock_cnt : 8; /* [15:8] */ -+ unsigned int src_enable : 1; /* [16] */ -+ unsigned int fdsrcparam_unused : 3; /* [19:17] */ -+ unsigned int rsv_13 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} fdsrcparam; -+ -+typedef union { -+ struct { -+ unsigned int src_cnt_opt : 3; /* [2:0] */ -+ unsigned int fdsrcfreq_unused_1 : 1; /* [3] */ -+ unsigned int src_freq_opt : 2; /* [5:4] */ -+ unsigned int fdsrcfreq_unused_2 : 2; /* [7:6] */ -+ unsigned int src_freq_ext : 16; /* [23:8] */ -+ unsigned int rsv_14 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fdsrcfreq; -+ -+typedef union { -+ struct { -+ unsigned int src_det_stat : 4; /* [3:0] */ -+ unsigned int src_cnt_out : 20; /* [23:4] */ -+ unsigned int rsv_15 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fdsrcres; -+ -+typedef union { -+ struct { -+ unsigned int i_enable : 1; /* [0] */ -+ unsigned int i_run : 1; /* [1] */ -+ unsigned int ctset0_unused : 2; /* [3:2] */ -+ unsigned int rsv_16 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} ctset0; -+ -+typedef union { -+ struct { -+ unsigned int i_mpll_fcon : 10; /* [9:0] */ -+ unsigned int i_mpll_divn : 3; /* [12:10] */ -+ unsigned int i_mpll_ctlck : 1; /* [13] */ -+ unsigned int ctset1_unused : 18; /* [31:14] */ -+ } bits; -+ unsigned int u32; -+} ctset1; -+ -+typedef union { -+ struct { -+ unsigned int i_deci_cnt_len : 8; /* [7:0] */ -+ unsigned int i_vco_st_wait_len : 8; /* [15:8] */ -+ unsigned int i_vco_end_wait_len : 8; /* [23:16] */ -+ unsigned int i_ref_cnt_len : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fccntr0; -+ -+typedef union { -+ struct { -+ unsigned int i_ct_sel : 1; /* [0] */ -+ unsigned int i_clkdet_sel : 1; /* [1] */ -+ unsigned int i_ct_mode : 2; /* [3:2] */ -+ unsigned int fcopt_unused_1 : 4; /* [7:4] */ -+ unsigned int i_ct_en : 1; /* [8] */ -+ unsigned int fcopt_unused_2 : 3; /* [11:9] */ -+ unsigned int i_ct_idx_sel : 1; /* [12] */ -+ unsigned int i_deci_try_sel : 1; /* [13] */ -+ unsigned int fcopt_unused : 2; /* [15:14] */ -+ unsigned int rsv_17 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fcopt; -+ -+typedef union { -+ struct { -+ unsigned int clk_ok : 1; /* [0] */ -+ unsigned int busy : 1; /* [1] */ -+ unsigned int done : 1; /* [2] */ -+ unsigned int error : 1; /* [3] */ -+ unsigned int divn : 3; /* [6:4] */ -+ unsigned int fcstat_unused_1 : 1; /* [7] */ -+ unsigned int ref_clk_stat : 1; /* [8] */ -+ unsigned int pllvco_clk_stat : 1; /* [9] */ -+ unsigned int fcstat_unused_2 : 2; /* [11:10] */ -+ unsigned int confin_stat : 6; /* [17:12] */ -+ unsigned int fcstat_unused_3 : 2; /* [19:18] */ -+ unsigned int fcon_init : 10; /* [29:20] */ -+ unsigned int rsv_18 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} fcstat; -+ -+typedef union { -+ struct { -+ unsigned int cnt_ref : 16; /* [15:0] */ -+ unsigned int rsv_19 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fccntval0; -+ -+typedef union { -+ struct { -+ unsigned int cnt_mpll : 16; /* [15:0] */ -+ unsigned int rsv_20 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fccntval1; -+ -+typedef union { -+ struct { -+ unsigned int divn_mpll : 3; /* [2:0] */ -+ unsigned int fcresval_unused : 1; /* [3] */ -+ unsigned int fcon_mpll : 10; /* [13:4] */ -+ unsigned int rsv_21 : 18; /* [31:14] */ -+ } bits; -+ unsigned int u32; -+} fcresval; -+ -+typedef union { -+ struct { -+ unsigned int divn_h20 : 3; /* [2:0] */ -+ unsigned int fcdstepset_unused : 1; /* [3] */ -+ unsigned int up_sampler_ratio_sel : 1; /* [4] */ -+ unsigned int rsv_22 : 27; /* [31:5] */ -+ } bits; -+ unsigned int u32; -+} fcdstepsetl; -+ -+typedef union { -+ struct { -+ unsigned int i_h2_sel : 1; /* [0] */ -+ unsigned int i_deci_sel : 1; /* [1] */ -+ unsigned int rsv_23 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} fcdstepth; -+ -+typedef union { -+ struct { -+ unsigned int i_deci2x_th : 16; /* [15:0] */ -+ unsigned int i_deci4x_th : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fcdstepth0; -+ -+typedef union { -+ struct { -+ unsigned int i_deci8x_th : 16; /* [15:0] */ -+ unsigned int i_deci16x_th : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fcdstepth1; -+ -+typedef union { -+ struct { -+ unsigned int i_ref_cnt : 16; /* [15:0] */ -+ unsigned int rsv_24 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fccntr1; -+ -+typedef union { -+ struct { -+ unsigned int contin_upd_en : 1; /* [0] */ -+ unsigned int contin_upd_opt : 1; /* [1] */ -+ unsigned int contin_upd_pol : 1; /* [2] */ -+ unsigned int fccontinset0_unused : 1; /* [3] */ -+ unsigned int contin_upd_step : 4; /* [7:4] */ -+ unsigned int rsv_25 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} fccontinset0; -+ -+typedef union { -+ struct { -+ unsigned int contin_upd_rate : 28; /* [27:0] */ -+ unsigned int contin_upd_time : 4; /* [31:28] */ -+ } bits; -+ unsigned int u32; -+} fccontinset1; -+ -+typedef union { -+ struct { -+ unsigned int contin_upd_th_dn : 10; /* [9:0] */ -+ unsigned int fccontinset2_unused : 2; /* [11:10] */ -+ unsigned int contin_upd_th_up : 10; /* [21:12] */ -+ unsigned int rsv_26 : 10; /* [31:22] */ -+ } bits; -+ unsigned int u32; -+} fccontinset2; -+ -+typedef union { -+ struct { -+ unsigned int init : 1; /* [0] */ -+ unsigned int ctrl : 1; /* [1] */ -+ unsigned int mod : 1; /* [2] */ -+ unsigned int sdm : 1; /* [3] */ -+ unsigned int rsv_27 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} fdivset0; -+ -+typedef union { -+ struct { -+ unsigned int step_d : 8; /* [7:0] */ -+ unsigned int step_t : 8; /* [15:8] */ -+ unsigned int step_n : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fdivset1; -+ -+typedef union { -+ struct { -+ unsigned int up : 1; /* [0] */ -+ unsigned int dn : 1; /* [1] */ -+ unsigned int rsv_28 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} fdivset2; -+ -+typedef union { -+ struct { -+ unsigned int mod_len : 8; /* [7:0] */ -+ unsigned int mod_t : 8; /* [15:8] */ -+ unsigned int mod_n : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fdivset3; -+ -+typedef union { -+ struct { -+ unsigned int mod_d : 16; /* [15:0] */ -+ unsigned int rsv_29 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fdivset4; -+ -+typedef union { -+ struct { -+ unsigned int mod_up : 1; /* [0] */ -+ unsigned int mod_dn : 1; /* [1] */ -+ unsigned int fdivset5_unused : 2; /* [3:2] */ -+ unsigned int rsv_30 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} fdivset5; -+ -+typedef union { -+ struct { -+ unsigned int stc_run : 1; /* [0] */ -+ unsigned int stc_dir : 1; /* [1] */ -+ unsigned int stc_ov : 1; /* [2] */ -+ unsigned int stc_un : 1; /* [3] */ -+ unsigned int stc_cnt : 16; /* [19:4] */ -+ unsigned int rsv_31 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} fdivs_tat0; -+ -+typedef union { -+ struct { -+ unsigned int i_fdiv_in : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} fdivs_tat1; -+ -+typedef union { -+ struct { -+ unsigned int div_out : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} fdivs_tat2; -+ -+typedef union { -+ struct { -+ unsigned int div_sdm : 16; /* [15:0] */ -+ unsigned int rsv_32 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fdivs_tat3; -+ -+typedef union { -+ struct { -+ unsigned int stm_run : 1; /* [0] */ -+ unsigned int stm_ph : 2; /* [2:1] */ -+ unsigned int stm_ov : 1; /* [3] */ -+ unsigned int stm_un : 1; /* [4] */ -+ unsigned int fdivstat4_unused : 3; /* [7:5] */ -+ unsigned int stm_cnt : 16; /* [23:8] */ -+ unsigned int rsv_33 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fdivs_tat4; -+ -+typedef union { -+ struct { -+ unsigned int i_manual_en : 4; /* [3:0] */ -+ unsigned int i_divn : 3; /* [6:4] */ -+ unsigned int fdivmanual_unused : 1; /* [7] */ -+ unsigned int i_mdiv : 4; /* [11:8] */ -+ unsigned int i_ref_cnt_div : 2; /* [13:12] */ -+ unsigned int i_dc_sel : 2; /* [15:14] */ -+ unsigned int i_vic : 8; /* [23:16] */ -+ unsigned int rsv_34 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fdivmanual; -+ -+typedef union { -+ struct { -+ unsigned int t2_refclksel : 1; /* [0] */ -+ unsigned int t2_refclksel2 : 1; /* [1] */ -+ unsigned int i_ref_clk_sel : 1; /* [2] */ -+ unsigned int refclksel_unused_1 : 1; /* [3] */ -+ unsigned int t2_pixelclksel : 1; /* [4] */ -+ unsigned int refclksel_unused_2 : 1; /* [5] */ -+ unsigned int pr_enc_val : 2; /* [7:6] */ -+ unsigned int rsv_35 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} refclksel; -+ -+typedef union { -+ struct { -+ unsigned int pll_lock_val : 8; /* [7:0] */ -+ unsigned int pll_lock_cnt : 8; /* [15:8] */ -+ unsigned int pll_enable : 1; /* [16] */ -+ unsigned int fdpllparam_unused : 3; /* [19:17] */ -+ unsigned int rsv_36 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} fdpllparam; -+ -+typedef union { -+ struct { -+ unsigned int pll_cnt_opt : 3; /* [2:0] */ -+ unsigned int fdpllfreq_unused_1 : 1; /* [3] */ -+ unsigned int pll_freq_opt : 2; /* [5:4] */ -+ unsigned int fdpllfreq_unused_2 : 2; /* [7:6] */ -+ unsigned int pll_freq_ext : 16; /* [23:8] */ -+ unsigned int rsv_37 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fdpllfreq; -+ -+typedef union { -+ struct { -+ unsigned int pll_det_stat : 4; /* [3:0] */ -+ unsigned int pll_cnt_out : 20; /* [23:4] */ -+ unsigned int rsv_38 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} fdpllres; -+ -+typedef union { -+ struct { -+ unsigned int fcg_en : 1; /* [0] */ -+ unsigned int fcg_dlf_en : 1; /* [1] */ -+ unsigned int fcg_dither_en : 1; /* [2] */ -+ unsigned int fcg_lock_en : 1; /* [3] */ -+ unsigned int rsv_39 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} fcgset; -+ -+typedef union { -+ struct { -+ unsigned int tmds_cnt_val : 16; /* [15:0] */ -+ unsigned int cnt1_target : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} fcgcnt; -+ -+typedef union { -+ struct { -+ unsigned int lock_cnt : 8; /* [7:0] */ -+ unsigned int lock_th : 8; /* [15:8] */ -+ unsigned int ki : 6; /* [21:16] */ -+ unsigned int lock_mode : 1; /* [22] */ -+ unsigned int rsv_40 : 9; /* [31:23] */ -+ } bits; -+ unsigned int u32; -+} fcgparam; -+ -+typedef union { -+ struct { -+ unsigned int dlf_lock : 1; /* [0] */ -+ unsigned int dlf_ov : 1; /* [1] */ -+ unsigned int dlf_un : 1; /* [2] */ -+ unsigned int rsv_41 : 29; /* [31:3] */ -+ } bits; -+ unsigned int u32; -+} fcgstate; -+ -+typedef union { -+ struct { -+ unsigned int ch_en_h20 : 4; /* [3:0] */ -+ unsigned int prbs_clr_h20 : 4; /* [7:4] */ -+ unsigned int ch_en_h21 : 4; /* [11:8] */ -+ unsigned int prbs_clr_h21 : 4; /* [15:12] */ -+ unsigned int test_pat_type : 3; /* [18:16] */ -+ unsigned int ch_test_en : 1; /* [19] */ -+ unsigned int test_4to1_mux_sel0 : 2; /* [21:20] */ -+ unsigned int test_4to1_mux_sel1 : 2; /* [23:22] */ -+ unsigned int test_4to1_mux_sel2 : 2; /* [25:24] */ -+ unsigned int test_4to1_mux_sel3 : 2; /* [27:26] */ -+ unsigned int rsv_42 : 4; /* [31:28] */ -+ } bits; -+ unsigned int u32; -+} txteloset; -+ -+typedef union { -+ struct { -+ unsigned int test_pat_ch0 : 20; /* [19:0] */ -+ unsigned int test_pat_ch1_l : 10; /* [29:20] */ -+ unsigned int rsv_43 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} txtelocont0; -+ -+typedef union { -+ struct { -+ unsigned int test_pat_ch1_h : 10; /* [9:0] */ -+ unsigned int test_pat_ch2 : 20; /* [29:10] */ -+ unsigned int rsv_44 : 2; /* [31:30] */ -+ } bits; -+ unsigned int u32; -+} txtelocont1; -+ -+typedef union { -+ struct { -+ unsigned int test_pat_ch3 : 20; /* [19:0] */ -+ unsigned int rsv_45 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} txtelocont2; -+ -+typedef union { -+ struct { -+ unsigned int pr_en_h20 : 1; /* [0] */ -+ unsigned int enable_h20 : 1; /* [1] */ -+ unsigned int txfifoset0_unused : 6; /* [7:2] */ -+ unsigned int rsv_46 : 24; /* [31:8] */ -+ } bits; -+ unsigned int u32; -+} txfifoset0; -+ -+typedef union { -+ struct { -+ unsigned int pol_inv0_h20 : 4; /* [3:0] */ -+ unsigned int data_swap0_h20 : 4; /* [7:4] */ -+ unsigned int ch_sel0_h20 : 8; /* [15:8] */ -+ unsigned int pol_inv1_h20 : 4; /* [19:16] */ -+ unsigned int data_swap1_h20 : 4; /* [23:20] */ -+ unsigned int ch_sel1_h20 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} txfifoset1; -+ -+typedef union { -+ struct { -+ unsigned int pr_fifo_state_h20 : 12; /* [11:0] */ -+ unsigned int txfifostat0_unused : 12; /* [23:12] */ -+ unsigned int rsv_47 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} tx_fifo_stat0; -+ -+typedef union { -+ struct { -+ unsigned int txfifostat1_unused_0 : 12; /* [11:0] */ -+ unsigned int txfifostat1_unused_1 : 12; /* [23:12] */ -+ unsigned int rsv_48 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} tx_fifo_stat1; -+ -+typedef union { -+ struct { -+ unsigned int tx_fifo_state_h20 : 12; /* [11:0] */ -+ unsigned int txfifostat2_unused : 12; /* [23:12] */ -+ unsigned int rsv_49 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} tx_fifo_stat2; -+ -+typedef union { -+ struct { -+ unsigned int txfifostat3_unused_0 : 12; /* [11:0] */ -+ unsigned int txfifostat3_unused_1 : 12; /* [23:12] */ -+ unsigned int rsv_50 : 8; /* [31:24] */ -+ } bits; -+ unsigned int u32; -+} tx_fifo_stat3; -+ -+typedef union { -+ struct { -+ unsigned int dataclkinv : 1; /* [0] */ -+ unsigned int rsv_51 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} data_clk_inv; -+ -+typedef union { -+ struct { -+ unsigned int ch_out_sel : 2; /* [1:0] */ -+ unsigned int rsv_52 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} tx_data_out_sel; -+ -+typedef union { -+ struct { -+ unsigned int reg_hdmi_mode_en : 1; /* [0] */ -+ unsigned int rsv_53 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} hdmi_mode; -+ -+typedef union { -+ struct { -+ unsigned int reg_clk_data_phase0 : 10; /* [9:0] */ -+ unsigned int reg_clk_data_phase1 : 10; /* [19:10] */ -+ unsigned int reg_sw_clk_en : 1; /* [20] */ -+ unsigned int rsv_54 : 11; /* [31:21] */ -+ } bits; -+ unsigned int u32; -+} clk_data1; -+ -+typedef union { -+ struct { -+ unsigned int reg_clk_data_phase2 : 10; /* [9:0] */ -+ unsigned int reg_clk_data_phase3 : 10; /* [19:10] */ -+ unsigned int rsv_55 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} clk_data2; -+ -+typedef union { -+ struct { -+ unsigned int reg_18to20_fifo_rd_rst : 1; /* [0] */ -+ unsigned int reg_18to20_fifo_wr_rst : 1; /* [1] */ -+ unsigned int reg_rd_bypass : 1; /* [2] */ -+ unsigned int reg_status_rrst : 1; /* [3] */ -+ unsigned int reg_status_wrst : 1; /* [4] */ -+ unsigned int rsv_56 : 27; /* [31:5] */ -+ } bits; -+ unsigned int u32; -+} cfg_18_to_20; -+ -+typedef union { -+ struct { -+ unsigned int empty_status : 1; /* [0] */ -+ unsigned int aempty_status : 1; /* [1] */ -+ unsigned int full_status : 1; /* [2] */ -+ unsigned int afull_status : 1; /* [3] */ -+ unsigned int rsv_57 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} fifo_stat_18_to_20; -+ -+typedef union { -+ struct { -+ unsigned int hsset : 2; /* [1:0] */ -+ unsigned int rsv_58 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} hsset; -+ -+typedef union { -+ struct { -+ unsigned int w_hsrxsense : 2; /* [1:0] */ -+ unsigned int rsv_59 : 30; /* [31:2] */ -+ } bits; -+ unsigned int u32; -+} hsrxsense; -+ -+typedef union { -+ struct { -+ unsigned int fifo_state_hs : 12; /* [11:0] */ -+ unsigned int rsv_60 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} hs_fifo_stat; -+ -+typedef union { -+ struct { -+ unsigned int hs_fifo_empty_intr : 1; /* [0] */ -+ unsigned int hs_fifo_full_intr : 1; /* [1] */ -+ unsigned int up_sample_fifo_empty_intr : 1; /* [2] */ -+ unsigned int up_sample_fifo_full_intr : 1; /* [3] */ -+ unsigned int trinsmitter_fifo_empty_intr : 1; /* [4] */ -+ unsigned int trinsmitter_fifo_full_intr : 1; /* [5] */ -+ unsigned int lkvdethigh_intr : 1; /* [6] */ -+ unsigned int lkvdetlow_intr : 1; /* [7] */ -+ unsigned int ct_fcon_intr : 1; /* [8] */ -+ unsigned int rsv_61 : 23; /* [31:9] */ -+ } bits; -+ unsigned int u32; -+} intr_stat; -+ -+typedef union { -+ struct { -+ unsigned int hs_fifo_empty_intr_mask : 1; /* [0] */ -+ unsigned int hs_fifo_full_intr_mask : 1; /* [1] */ -+ unsigned int up_sample_fifo_empty_intr_mask : 1; /* [2] */ -+ unsigned int up_sample_fifo_full_intr_mask : 1; /* [3] */ -+ unsigned int trinsmitter_fifo_empty_intr_mask : 1; /* [4] */ -+ unsigned int trinsmitter_fifo_full_intr_mask : 1; /* [5] */ -+ unsigned int lkvdethigh_intr_mask : 1; /* [6] */ -+ unsigned int lkvdetlow_intr_mask : 1; /* [7] */ -+ unsigned int ct_fcon_intr_mask : 1; /* [8] */ -+ unsigned int rsv_62 : 23; /* [31:9] */ -+ } bits; -+ unsigned int u32; -+} intr_mask; -+ -+typedef union { -+ struct { -+ unsigned int hs_fifo_empty_triger_type : 3; /* [2:0] */ -+ unsigned int hs_fifo_empty_intr_en : 1; /* [3] */ -+ unsigned int hs_fifo_full_triger_type : 3; /* [6:4] */ -+ unsigned int hs_fifo_full_intr_en : 1; /* [7] */ -+ unsigned int up_sample_fifo_empty_triger_type : 3; /* [10:8] */ -+ unsigned int up_sample_fifo_empty_intr_en : 1; /* [11] */ -+ unsigned int up_sample_fifo_full_triger_type : 3; /* [14:12] */ -+ unsigned int up_sample_fifo_full_intr_en : 1; /* [15] */ -+ unsigned int transmitter_fifo_empty_triger_type : 3; /* [18:16] */ -+ unsigned int transmitter_fifo_empty_intr_en : 1; /* [19] */ -+ unsigned int transmitter_fifo_full_triger_type : 3; /* [22:20] */ -+ unsigned int transmitter_fifo_full_intr_en : 1; /* [23] */ -+ unsigned int lkvdethigh_triger_type : 3; /* [26:24] */ -+ unsigned int lkvdethigh_intr_en : 1; /* [27] */ -+ unsigned int lkvdetlow_triger_type : 3; /* [30:28] */ -+ unsigned int lkvdetlow_intr_en : 1; /* [31] */ -+ } bits; -+ unsigned int u32; -+} intr_set; -+ -+typedef union { -+ struct { -+ unsigned int fd_clk_sel : 2; /* [1:0] */ -+ unsigned int refclk_sel : 2; /* [3:2] */ -+ unsigned int ctman : 2; /* [5:4] */ -+ unsigned int modclk_sel : 1; /* [6] */ -+ unsigned int fdivclk_sel : 1; /* [7] */ -+ unsigned int mod_div_val : 4; /* [11:8] */ -+ unsigned int rsv_63 : 20; /* [31:12] */ -+ } bits; -+ unsigned int u32; -+} clk_set; -+ -+typedef union { -+ struct { -+ unsigned int sw_reset_mod_clock : 1; /* [0] */ -+ unsigned int sw_reset_tmds_clock : 1; /* [1] */ -+ unsigned int sw_reset_mpll_clock : 1; /* [2] */ -+ unsigned int sw_reset_nco_clock : 1; /* [3] */ -+ unsigned int sw_reset_fd_clock : 1; /* [4] */ -+ unsigned int sw_reset_mod_and_mpll_clock : 1; /* [5] */ -+ unsigned int sw_reset_mod_and_nco_clock : 1; /* [6] */ -+ unsigned int sw_reset_mod_and_fd_clock : 1; /* [7] */ -+ unsigned int sw_reset_hsfifo_clock : 1; /* [8] */ -+ unsigned int sw_reset_txfifo_clock : 1; /* [9] */ -+ unsigned int sw_reset_data_clock : 1; /* [10] */ -+ unsigned int sw_reset_hs_clock : 1; /* [11] */ -+ unsigned int sw_reset_pllref_clock : 1; /* [12] */ -+ unsigned int sw_reset_dac_clock : 1; /* [13] */ -+ unsigned int dac_clock_gat : 1; /* [14] */ -+ unsigned int up_sample_fifo_clock_swrst : 1; /* [15] */ -+ unsigned int sw_reset_frl_clock : 1; /* [16] */ -+ unsigned int swreset_unused : 14; /* [30:17] */ -+ unsigned int global_reset : 1; /* [31] */ -+ } bits; -+ unsigned int u32; -+} sw_reset; -+ -+typedef union { -+ struct { -+ unsigned int clk0_div : 4; /* [3:0] */ -+ unsigned int clk1_div : 4; /* [7:4] */ -+ unsigned int clk2_div : 4; /* [11:8] */ -+ unsigned int clk3_div : 4; /* [15:12] */ -+ unsigned int clk4_div : 4; /* [19:16] */ -+ unsigned int clk5_div : 4; /* [23:20] */ -+ unsigned int clk6_div : 4; /* [27:24] */ -+ unsigned int clk7_div : 4; /* [31:28] */ -+ } bits; -+ unsigned int u32; -+} glueset0; -+ -+typedef union { -+ struct { -+ unsigned int clk8_div : 4; /* [3:0] */ -+ unsigned int glueset1_unused_1 : 4; /* [7:4] */ -+ unsigned int clk10_div : 4; /* [11:8] */ -+ unsigned int clk11_div : 4; /* [15:12] */ -+ unsigned int clk_sel : 4; /* [19:16] */ -+ unsigned int glueset1_unused_2 : 12; /* [31:20] */ -+ } bits; -+ unsigned int u32; -+} glueset1; -+ -+typedef union { -+ struct { -+ unsigned int ct_fcon_triger_type : 3; /* [2:0] */ -+ unsigned int ct_fcon_intr_en : 1; /* [3] */ -+ unsigned int rsv_64 : 28; /* [31:4] */ -+ } bits; -+ unsigned int u32; -+} ct_intr_set; -+ -+typedef union { -+ struct { -+ unsigned int hw_info : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} hw_info; -+ -+typedef union { -+ struct { -+ unsigned int hw_vers_unused_1 : 4; /* [3:0] */ -+ unsigned int hdmi20_compliance : 1; /* [4] */ -+ unsigned int hdmi21_compliance : 1; /* [5] */ -+ unsigned int hw_vers_unused_2 : 26; /* [31:6] */ -+ } bits; -+ unsigned int u32; -+} hw_vers; -+ -+typedef union { -+ struct { -+ unsigned int ras_mode : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} hw_ras_mode; -+ -+typedef union { -+ struct { -+ unsigned int rfs_mode : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} hw_rfs_mode; -+ -+typedef union { -+ struct { -+ unsigned int rft_mode : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} hw_rft_mode; -+ -+typedef union { -+ struct { -+ unsigned int req_length : 2; /* [1:0] */ -+ unsigned int stb_delay2 : 4; /* [5:2] */ -+ unsigned int stb_delay1 : 4; /* [9:6] */ -+ unsigned int stb_delay0 : 4; /* [13:10] */ -+ unsigned int stb_acc_sel : 1; /* [14] */ -+ unsigned int stb_cs_sel : 1; /* [15] */ -+ unsigned int rsv_65 : 16; /* [31:16] */ -+ } bits; -+ unsigned int u32; -+} stb_opt; -+ -+typedef union { -+ struct { -+ unsigned int req_done : 1; /* [0] */ -+ unsigned int rsv_66 : 31; /* [31:1] */ -+ } bits; -+ unsigned int u32; -+} stb_req; -+ -+typedef union { -+ struct { -+ unsigned int stb_auto_rdata : 32; /* [31:0] */ -+ } bits; -+ unsigned int u32; -+} stb_data; -+ -+typedef struct { -+ volatile t2gpport0 t2gp_port0; /* 0 */ -+ volatile t2gpport1 t2gp_port1; /* 4 */ -+ volatile phy_csen stb_cs_en; /* 8 */ -+ volatile phy_wr stb_write_en; /* C */ -+ volatile resetn stb_reset; /* 10 */ -+ volatile phy_addr stb_addr; /* 14 */ -+ volatile phy_wdata stb_wdata; /* 18 */ -+ volatile phy_rdata stb_rdata; /* 1C */ -+ volatile zcalreg zcal_reg; /* 20 */ -+ volatile zcalclk zcal_clk; /* 24 */ -+ volatile shortdet short_det; /* 28 */ -+ volatile det stb_det; /* 2C */ -+ volatile fdsrcparam fd_src_param; /* 30 */ -+ volatile fdsrcfreq fd_src_freq; /* 34 */ -+ volatile fdsrcres fd_src_res; /* 38 */ -+ volatile ctset0 ct_set0; /* 3C */ -+ volatile ctset1 ct_set1; /* 40 */ -+ unsigned int reserved_0; /* 44 */ -+ volatile fccntr0 fc_cntr0; /* 48 */ -+ volatile fcopt fc_opt; /* 4C */ -+ volatile fcstat fc_stat; /* 50 */ -+ volatile fccntval0 fc_cnt_val0; /* 54 */ -+ volatile fccntval1 fc_cnt_val1; /* 58 */ -+ volatile fcresval fc_res_sval; /* 5C */ -+ volatile fcdstepsetl fc_dstep_set; /* 60 */ -+ volatile fcdstepth fc_dstep_th; /* 64 */ -+ volatile fcdstepth0 fc_dstep_th0; /* 68 */ -+ volatile fcdstepth1 fc_dstep_th1; /* 6C */ -+ volatile fccntr1 fc_cntr1; /* 70 */ -+ volatile fccontinset0 fc_contin_set0; /* 74 */ -+ volatile fccontinset1 fc_contin_set1; /* 78 */ -+ volatile fccontinset2 fc_contin_set2; /* 7C */ -+ unsigned int reserved_1[4]; /* 80-8C */ -+ volatile fdivset0 fdiv_set0; /* 90 */ -+ volatile fdivset1 fdiv_set1; /* 94 */ -+ volatile fdivset2 fdiv_set2; /* 98 */ -+ volatile fdivset3 fdiv_set3; /* 9C */ -+ volatile fdivset4 fdiv_set4; /* A0 */ -+ volatile fdivset5 fdiv_set5; /* A4 */ -+ volatile fdivs_tat0 fdiv_stat0; /* A8 */ -+ volatile fdivs_tat1 fdiv_stat1; /* AC */ -+ volatile fdivs_tat2 fdiv_stat2; /* B0 */ -+ volatile fdivs_tat3 fdiv_stat3; /* B4 */ -+ volatile fdivs_tat4 fdiv_stat4; /* B8 */ -+ volatile fdivmanual fdiv_manual; /* BC */ -+ volatile refclksel ref_clk_sel; /* C0 */ -+ unsigned int reserved_2[15]; /* C4-FC */ -+ volatile fdpllparam fd_pll_param; /* 100 */ -+ volatile fdpllfreq fd_pll_freq; /* 104 */ -+ volatile fdpllres fd_pll_res; /* 108 */ -+ unsigned int reserved_3[5]; /* 10c-11c */ -+ volatile fcgset fcg_set; /* 120 */ -+ volatile fcgcnt fcg_cnt; /* 124 */ -+ volatile fcgparam fcg_param; /* 128 */ -+ volatile fcgstate fcg_state; /* 12C */ -+ unsigned int reserved_4[52]; /* 130-1FC */ -+ volatile txteloset telo_set; /* 200 */ -+ volatile txtelocont0 telo_cnt0; /* 204 */ -+ volatile txtelocont1 telo_cnt1; /* 208 */ -+ volatile txtelocont2 telo_cnt2; /* 20C */ -+ volatile txfifoset0 tx_fifo_set0; /* 210 */ -+ volatile txfifoset1 tx_fifo_set1; /* 214 */ -+ volatile tx_fifo_stat0 tx_fifo_stat0; /* 218 */ -+ volatile tx_fifo_stat1 tx_fifo_stat1; /* 21C */ -+ volatile tx_fifo_stat2 tx_fifo_stat2; /* 220 */ -+ volatile tx_fifo_stat3 tx_fifo_stat3; /* 224 */ -+ volatile data_clk_inv data_clk_inv; /* 228 */ -+ volatile tx_data_out_sel data_out_sel; /* 22C */ -+ volatile hdmi_mode stb_hdmi_mode; /* 230 */ -+ volatile clk_data1 clk_data1; /* 234 */ -+ volatile clk_data2 clk_data2; /* 238 */ -+ volatile cfg_18_to_20 cfg15_to_20; /* 23C */ -+ volatile fifo_stat_18_to_20 fifo_stat18_to_20; /* 240 */ -+ unsigned int reserved_5[7]; /* 244-25c */ -+ volatile hsset hs_set; /* 260 */ -+ volatile hsrxsense hs_rxsense; /* 264 */ -+ volatile hs_fifo_stat hs_fifo_stat; /* 268 */ -+ unsigned int reserved_6[37]; /* 26C-2FC */ -+ volatile intr_stat intr_stat; /* 300 */ -+ volatile intr_mask intr_mask; /* 304 */ -+ volatile intr_set intr_set; /* 308 */ -+ volatile clk_set clk_set; /* 30C */ -+ volatile sw_reset sw_rst; /* 310 */ -+ volatile glueset0 glue_set0; /* 314 */ -+ volatile glueset1 glue_set1; /* 318 */ -+ volatile ct_intr_set ct_intr_set; /* 31C */ -+ unsigned int reserved_7[56]; /* 320-3FC */ -+ volatile hw_info info_hw; /* 400 */ -+ volatile hw_vers vers_hw; /* 404 */ -+ unsigned int reserved_8[6]; /* 408-41C */ -+ volatile hw_ras_mode ras_mode; /* 420 */ -+ volatile hw_rfs_mode rfs_mode; /* 424 */ -+ volatile hw_rft_mode rft_mode; /* 428 */ -+ unsigned int reserved_9[181]; /* 42C-6FC */ -+ volatile stb_opt opt; /* 700 */ -+ volatile stb_req req; /* 704 */ -+ volatile stb_data rdata; /* 708 */ -+} hdmitx21_dphy_reg_type; -+ -+int hdmi_reg_tx_phy_init(unsigned int id, char *addr); -+unsigned int *hdmi_reg_tx_get_phy_addr(unsigned int id); -+int hdmi_reg_tx_phy_deinit(unsigned int id); -+void hdmi_reg_stb_cs_en_set(unsigned int id, unsigned short stb_cs_en); -+void hdmi_reg_stb_wen_set(unsigned int id, unsigned char stb_wen); -+void hdmi_reg_resetn_set(unsigned int id, unsigned char reg_resetn); -+unsigned char hdmi_reg_resetn_get(unsigned int id); -+void hdmi_reg_stb_addr_set(unsigned int id, unsigned char stb_addr); -+void hdmi_reg_stb_wdata_set(unsigned int id, unsigned char stb_wdata); -+unsigned char hdmi_reg_stb_rdata_get(unsigned int id); -+void hdmi_reg_src_lock_val_set(unsigned int id, unsigned char src_lock_val); -+void hdmi_reg_src_lock_cnt_set(unsigned int id, unsigned char src_lock_cnt); -+void hdmi_reg_src_enable_set(unsigned int id, unsigned char src_enable); -+void hdmi_reg_src_cnt_opt_set(unsigned int id, unsigned char src_cnt_opt); -+void hdmi_reg_fdsrcfreq_unused1_set(unsigned int id, unsigned char fdsrcfreq_unused_1); -+void hdmi_reg_src_freq_opt_set(unsigned int id, unsigned char src_freq_opt); -+void hdmi_reg_fdsrcfreq_unused2_set(unsigned int id, unsigned char fdsrcfreq_unused_2); -+void hdmi_reg_src_freq_ext_set(unsigned int id, unsigned short src_freq_ext); -+unsigned char hdmi_reg_src_det_stat_get(unsigned int id); -+unsigned int hdmi_reg_src_cnt_out_get(unsigned int id); -+void hdmi_reg_clkdet_sel_set(unsigned int id, unsigned char i_clkdet_sel); -+void hdmi_reg_divn_h20_set(unsigned int id, unsigned char up_divn_h20); -+void hdmi_reg_up_sampler_ratio_sel_set(unsigned int id, unsigned char up_sampler_ratio_sel); -+void hdmi_reg_init_set(unsigned int id, unsigned char init); -+void hdmi_reg_en_ctrl_set(unsigned int id, unsigned char en_ctrl); -+unsigned char hdmi_reg_en_ctrl_get(unsigned int id); -+void hdmi_reg_en_mod_set(unsigned int id, unsigned char en_mod); -+unsigned char hdmi_reg_en_mod_get(unsigned int id); -+void hdmi_reg_en_sdm_set(unsigned int id, unsigned char en_sdm); -+unsigned char hdmi_reg_en_sdm_get(unsigned int id); -+void hdmi_reg_mod_len_set(unsigned int id, unsigned char mod_len); -+void hdmi_reg_mod_t_set(unsigned int id, unsigned char mod_t); -+void hdmi_reg_mod_n_set(unsigned int id, unsigned short mod_n); -+void hdmi_reg_mod_d_set(unsigned int id, unsigned short mod_d); -+void hdmi_reg_fdiv_in_set(unsigned int id, unsigned int i_fdiv_in); -+void hdmi_reg_manual_en_set(unsigned int id, unsigned char i_manual_en); -+void hdmi_reg_mdiv_set(unsigned int id, unsigned char i_mdiv); -+void hdmi_reg_ref_clk_sel_set(unsigned int id, unsigned char i_ref_clk_sel); -+void hdmi_reg_pr_en_h20_set(unsigned int id, unsigned char up_pr_en_h20); -+void hdmi_reg_enable_h20_set(unsigned int id, unsigned char up_enable_h20); -+void hdmi_reg_ch_out_sel_set(unsigned int id, unsigned char up_ch_out_sel); -+void hdmi_reg_hsset_set(unsigned int id, unsigned char up_hsset); -+void hdmi_reg_fd_clk_sel_set(unsigned int id, unsigned char up_fd_clk_sel); -+void hdmi_reg_refclk_sel_set(unsigned int id, unsigned char up_refclk_sel); -+void hdmi_reg_ctman_set(unsigned int id, unsigned char up_ctman); -+void hdmi_reg_modclk_sel_set(unsigned int id, unsigned char up_modclk_sel); -+void hdmi_reg_fdivclk_sel_set(unsigned int id, unsigned char up_fdivclk_sel); -+void hdmi_reg_mod_div_val_set(unsigned int id, unsigned char mod_div_val); -+void hdmi_reg_dac_clock_gat_set(unsigned int id, unsigned char dac_clock_gat); -+void hdmi_reg_swreset_unused_set(unsigned int id, unsigned short swreset_unused); -+void hdmi_reg_global_reset_set(unsigned int id, unsigned char global_reset); -+void hdmi_reg_sw_reset_mod_clock_set(unsigned int id, unsigned char sw_reset_mod_clock); -+void hdmi_reg_sw_reset_tmds_clock_set(unsigned int id, unsigned char sw_reset_tmds_clock); -+void hdmi_reg_sw_reset_mpll_clock_set(unsigned int id, unsigned char sw_reset_mpll_clock); -+void hdmi_reg_sw_reset_nco_clock_set(unsigned int id, unsigned char sw_reset_nco_clock); -+void hdmi_reg_sw_reset_fd_clock_set(unsigned int id, unsigned char sw_reset_fd_clock); -+void hdmi_reg_sw_reset_mod_and_mpll_clock_set(unsigned int id, unsigned char sw_reset_mod_and_mpll_clock); -+void hdmi_reg_sw_reset_mod_and_nco_clock_set(unsigned int id, unsigned char sw_reset_mod_and_nco_clock); -+void hdmi_reg_sw_reset_mod_and_fd_clock_set(unsigned int id, unsigned char sw_reset_mod_and_fd_clock); -+void hdmi_reg_sw_reset_hsfifo_clock_set(unsigned int id, unsigned char sw_reset_hsfifo_clock); -+void hdmi_reg_sw_reset_txfifo_clock_set(unsigned int id, unsigned char sw_reset_txfifo_clock); -+void hdmi_reg_sw_reset_data_clock_set(unsigned int id, unsigned char sw_reset_data_clock); -+void hdmi_reg_sw_reset_hs_clock_set(unsigned int id, unsigned char sw_reset_hs_clock); -+void hdmi_reg_sw_reset_pllref_clock_set(unsigned int id, unsigned char sw_reset_pllref_clock); -+void hdmi_reg_sw_reset_dac_clock_set(unsigned int id, unsigned char sw_reset_dac_clock); -+void hdmi_reg_up_sample_fifo_clock_swrst_set(unsigned int id, unsigned char up_sample_fifo_clock_swrst); -+void hdmi_reg_fcdstepset_unused_set(unsigned int id, unsigned char fcdstepset_unused); -+void hdmi_reg_req_length_set(unsigned int id, unsigned char req_length); -+void hdmi_reg_stb_cs_sel_set(unsigned int id, unsigned char stb_cs_sel); -+void hdmi_reg_fdsrcparam_unused_set(unsigned int id, unsigned char fdsrcparam_unused); -+void hdmi_reg_fcg_en_set(unsigned int id, unsigned char up_fcg_en); -+void hdmi_reg_fcg_dlf_en_set(unsigned int id, unsigned char up_fcg_dlf_en); -+void hdmi_reg_fcg_dither_en_set(unsigned int id, unsigned char up_fcg_dither_en); -+void hdmi_reg_fcg_lock_en_set(unsigned int id, unsigned char up_fcg_lock_en); -+void hdmi_reg_lock_th_set(unsigned int id, unsigned char up_lock_th); -+void hdmi_reg_txfifoset0_unused_set(unsigned int id, unsigned char txfifoset0_unused); -+void hdmi_reg_mode_en_set(unsigned int id, unsigned char reg_hdmi_mode_en); -+void hdmi_reg_sw_reset_frl_clock_set(unsigned int id, unsigned char sw_reset_frl_clock); -+void hdmi_reg_stb_delay2_set(unsigned int id, unsigned char stb_delay2); -+void hdmi_reg_stb_delay1_set(unsigned int id, unsigned char stb_delay1); -+void hdmi_reg_stb_delay0_set(unsigned int id, unsigned char stb_delay0); -+void hdmi_reg_stb_acc_sel_set(unsigned int id, unsigned char stb_acc_sel); -+#endif /* HDMI_REG_DPHY_H */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c -new file mode 100755 -index 0000000..6d5c6b7 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c -@@ -0,0 +1,406 @@ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "smart_drm_drv.h" -+#include "smart_vo.h" -+ -+#define DRIVER_NAME "smart" -+#define DRIVER_DESC "SMART VISION Soc DRM" -+#define DRIVER_DATE "20250922" -+#define DRIVER_MAJOR 1 -+#define DRIVER_MINOR 0 -+ -+static const struct drm_driver smart_drm_driver; -+ -+ -+ -+static int smart_drm_init_iommu(struct drm_device *drm_dev) -+{ -+ struct smart_drm_private *private = drm_dev->dev_private; -+ struct iommu_domain_geometry *geometry; -+ u64 start, end; -+ -+ if (IS_ERR_OR_NULL(private->iommu_dev)) -+ return 0; -+ -+ private->domain = iommu_domain_alloc(private->iommu_dev->bus); -+ if (!private->domain) -+ return -ENOMEM; -+ -+ geometry = &private->domain->geometry; -+ start = geometry->aperture_start; -+ end = geometry->aperture_end; -+ -+ printk("IOMMU context initialized (aperture: %#llx-%#llx)\n", -+ start, end); -+ drm_mm_init(&private->mm, start, end - start + 1); -+ mutex_init(&private->mm_lock); -+ -+ return 0; -+} -+ -+static void smart_iommu_cleanup(struct drm_device *drm_dev) -+{ -+ struct smart_drm_private *private = drm_dev->dev_private; -+ -+ if (!private->domain) -+ return; -+ -+ drm_mm_takedown(&private->mm); -+ iommu_domain_free(private->domain); -+} -+ -+static const struct drm_mode_config_helper_funcs smart_drm_mode_config_helper = { -+ .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, -+}; -+ -+static const struct drm_mode_config_funcs smart_drm_mode_config_funcs = { -+ .fb_create = drm_gem_fb_create, -+ .output_poll_changed = drm_fb_helper_output_poll_changed, -+ .atomic_check = drm_atomic_helper_check, -+ .atomic_commit = drm_atomic_helper_commit, -+}; -+ -+void smart_drm_mode_config_init(struct drm_device *dev) -+{ -+ -+ dev->mode_config.min_width = 0; -+ dev->mode_config.min_height = 0; -+ -+ /* -+ * set max width and height as default value(4096x4096). -+ * this value would be used to check framebuffer size limitation -+ * at drm_mode_addfb(). -+ */ -+ dev->mode_config.max_width = 4096; -+ dev->mode_config.max_height = 4096; -+ -+ dev->mode_config.funcs = &smart_drm_mode_config_funcs; -+ dev->mode_config.helper_private = &smart_drm_mode_config_helper; -+} -+ -+ -+static int smart_drm_bind(struct device *dev) -+{ -+ struct drm_device *drm_dev; -+ struct smart_drm_private *private; -+ int ret; -+ //struct drm_crtc *crtc; -+ -+ /* Remove existing drivers that may own the framebuffer memory. */ -+ ret = drm_aperture_remove_framebuffers(&smart_drm_driver); -+ if (ret) { -+ DRM_DEV_ERROR(dev, -+ "Failed to remove existing framebuffers - %d.\n", -+ ret); -+ return ret; -+ } -+ -+ drm_dev = drm_dev_alloc(&smart_drm_driver, dev); -+ if (IS_ERR(drm_dev)) -+ return PTR_ERR(drm_dev); -+ -+ dev_set_drvdata(dev, drm_dev); -+ -+ private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL); -+ if (!private) { -+ ret = -ENOMEM; -+ goto err_free; -+ } -+ -+ drm_dev->dev_private = private; -+ -+ ret = drmm_mode_config_init(drm_dev); -+ if (ret) -+ goto err_free; -+ -+ smart_drm_mode_config_init(drm_dev); -+ -+ -+ /* Try to bind all sub drivers. */ -+ ret = component_bind_all(dev, drm_dev); -+ if (ret) -+ goto err_free; -+ -+ ret = smart_drm_init_iommu(drm_dev); -+ if (ret) -+ goto err_unbind_all; -+ -+ ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc); -+ if (ret) -+ goto err_iommu_cleanup; -+ -+ drm_mode_config_reset(drm_dev); -+ -+ /* init kms poll for handling hpd */ -+ drm_kms_helper_poll_init(drm_dev); -+ -+ ret = drm_dev_register(drm_dev, 0); -+ if (ret) -+ goto err_kms_helper_poll_fini; -+ -+ drm_fbdev_generic_setup(drm_dev, 0); -+ return 0; -+err_kms_helper_poll_fini: -+ drm_kms_helper_poll_fini(drm_dev); -+err_iommu_cleanup: -+ smart_iommu_cleanup(drm_dev); -+err_unbind_all: -+ component_unbind_all(dev, drm_dev); -+err_free: -+ drm_dev_put(drm_dev); -+ return ret; -+} -+ -+static void smart_drm_unbind(struct device *dev) -+{ -+ struct drm_device *drm_dev = dev_get_drvdata(dev); -+ -+ drm_dev_unregister(drm_dev); -+ -+ drm_kms_helper_poll_fini(drm_dev); -+ -+ drm_atomic_helper_shutdown(drm_dev); -+ component_unbind_all(dev, drm_dev); -+ smart_iommu_cleanup(drm_dev); -+ -+ drm_dev_put(drm_dev); -+} -+ -+// 私有ioctl命令定义 -+#define DRM_HI3403V100_OVERLAY_FLUSH 1 -+#define DRM_IOCTL_HI3403V100_OVERLAY_FLUSH DRM_IOWR(DRM_COMMAND_BASE + DRM_HI3403V100_OVERLAY_FLUSH, ot_video_frame_info) -+ -+static int smart_drm_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) -+{ -+ ot_video_frame_info video_frame_info = {0}; -+ -+ // 复制用户数据到内核空间 -+ if(data == NULL) { -+ printk("%s,%d data == NULL\n",__func__,__LINE__); -+ return -EINVAL; -+ } -+ memcpy(&video_frame_info, data, sizeof(video_frame_info)); -+ drm_overlay_update(&video_frame_info); -+ return 0; -+} -+ -+static const struct drm_ioctl_desc smart_ioctls[] = { -+ DRM_IOCTL_DEF_DRV(HI3403V100_OVERLAY_FLUSH, smart_drm_flush_ioctl, DRM_AUTH), -+}; -+ -+ -+DEFINE_DRM_GEM_FOPS(smart_drm_driver_fops); -+ -+static const struct drm_driver smart_drm_driver = { -+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, -+ .dumb_create = drm_gem_dma_dumb_create, -+ .gem_prime_import_sg_table = drm_gem_dma_prime_import_sg_table, -+ .ioctls = smart_ioctls, -+ .num_ioctls = ARRAY_SIZE(smart_ioctls), -+ .fops = &smart_drm_driver_fops, -+ .name = DRIVER_NAME, -+ .desc = DRIVER_DESC, -+ .date = DRIVER_DATE, -+ .major = DRIVER_MAJOR, -+ .minor = DRIVER_MINOR, -+}; -+ -+#ifdef CONFIG_PM_SLEEP -+static int smart_drm_sys_suspend(struct device *dev) -+{ -+ struct drm_device *drm = dev_get_drvdata(dev); -+ -+ return drm_mode_config_helper_suspend(drm); -+} -+ -+static int smart_drm_sys_resume(struct device *dev) -+{ -+ struct drm_device *drm = dev_get_drvdata(dev); -+ -+ return drm_mode_config_helper_resume(drm); -+} -+#endif -+ -+static const struct dev_pm_ops smart_drm_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(smart_drm_sys_suspend, -+ smart_drm_sys_resume) -+}; -+ -+#define MAX_SMART_SUB_DRIVERS 16 -+static struct platform_driver *smart_sub_drivers[MAX_SMART_SUB_DRIVERS]; -+static int num_smart_sub_drivers; -+ -+ -+static void smart_drm_match_remove(struct device *dev) -+{ -+ struct device_link *link; -+ -+ list_for_each_entry(link, &dev->links.consumers, s_node) -+ device_link_del(link); -+} -+ -+static struct component_match *smart_drm_match_add(struct device *dev) -+{ -+ struct component_match *match = NULL; -+ int i; -+ for (i = 0; i < num_smart_sub_drivers; i++) { -+ struct platform_driver *drv = smart_sub_drivers[i]; -+ struct device *p = NULL, *d; -+ -+ do { -+ d = platform_find_device_by_driver(p, &drv->driver); -+ put_device(p); -+ p = d; -+ -+ if (!d) -+ break; -+ -+ device_link_add(dev, d, DL_FLAG_STATELESS); -+ component_match_add(dev, &match, component_compare_dev, d); -+ } while (true); -+ } -+ -+ if (IS_ERR(match)) -+ smart_drm_match_remove(dev); -+ return match ?: ERR_PTR(-ENODEV); -+} -+ -+static const struct component_master_ops smart_drm_ops = { -+ .bind = smart_drm_bind, -+ .unbind = smart_drm_unbind, -+}; -+ -+static int smart_drm_platform_of_probe(struct device *dev) -+{ -+ -+ return 0; -+} -+ -+static int smart_drm_platform_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct component_match *match = NULL; -+ int ret; -+ -+ ret = smart_drm_platform_of_probe(dev); -+ if (ret) -+ return ret; -+ -+ match = smart_drm_match_add(dev); -+ if (IS_ERR(match)) -+ return PTR_ERR(match); -+ -+ ret = component_master_add_with_match(dev, &smart_drm_ops, match); -+ if (ret < 0) { -+ smart_drm_match_remove(dev); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void smart_drm_platform_remove(struct platform_device *pdev) -+{ -+ -+ component_master_del(&pdev->dev, &smart_drm_ops); -+ -+ smart_drm_match_remove(&pdev->dev); -+} -+ -+static void smart_drm_platform_shutdown(struct platform_device *pdev) -+{ -+ struct drm_device *drm = platform_get_drvdata(pdev); -+ -+ if (drm) -+ drm_atomic_helper_shutdown(drm); -+} -+ -+static const struct of_device_id smart_drm_dt_ids[] = { -+ { .compatible = "vendor,drm", }, -+ { /* sentinel */ }, -+}; -+MODULE_DEVICE_TABLE(of, smart_drm_dt_ids); -+ -+static struct platform_driver smart_drm_platform_driver = { -+ .probe = smart_drm_platform_probe, -+ .remove_new = smart_drm_platform_remove, -+ .shutdown = smart_drm_platform_shutdown, -+ .driver = { -+ .name = "smart-drm", -+ .of_match_table = smart_drm_dt_ids, -+ .pm = &smart_drm_pm_ops, -+ }, -+}; -+ -+#define ADD_SMART_SUB_DRIVER(drv, cond) { \ -+ if (IS_ENABLED(cond) && \ -+ !WARN_ON(num_smart_sub_drivers >= MAX_SMART_SUB_DRIVERS)) \ -+ smart_sub_drivers[num_smart_sub_drivers++] = &drv; \ -+} -+ -+static int __init smart_drm_init(void) -+{ -+ int ret; -+ -+ -+ num_smart_sub_drivers = 0; -+ ADD_SMART_SUB_DRIVER(smart_vop_driver, -+ CONFIG_DRM_HISI_SMART_VISION); -+ -+ ADD_SMART_SUB_DRIVER(smart_hdmi_driver, -+ CONFIG_DRM_HISI_SMART_VISION); -+ -+ ret = platform_register_drivers(smart_sub_drivers, -+ num_smart_sub_drivers); -+ -+ -+ if (ret) -+ return ret; -+ -+ ret = platform_driver_register(&smart_drm_platform_driver); -+ if (ret) -+ goto err_unreg_drivers; -+ -+ return 0; -+ -+err_unreg_drivers: -+ platform_unregister_drivers(smart_sub_drivers, -+ num_smart_sub_drivers); -+ -+ return ret; -+} -+ -+static void __exit smart_drm_fini(void) -+{ -+ platform_driver_unregister(&smart_drm_platform_driver); -+ -+ platform_unregister_drivers(smart_sub_drivers, -+ num_smart_sub_drivers); -+} -+ -+module_init(smart_drm_init); -+module_exit(smart_drm_fini); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("runkaihong"); -+MODULE_DESCRIPTION("SMART DRM for platform/SoC device"); -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.h b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.h -new file mode 100755 -index 0000000..bff908d ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.h -@@ -0,0 +1,104 @@ -+#ifndef _HI3403V100_DRM_DRV_H -+#define _HI3403V100_DRM_DRV_H -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define HI3403V100_MAX_FB_BUFFER 3 -+#define HI3403V100_MAX_CONNECTOR 2 -+#define HI3403V100_MAX_CRTC 4 -+ -+ -+#define HI3403V100_OUT_MODE_P888 0 -+#define HI3403V100_OUT_MODE_BT1120 0 -+#define HI3403V100_OUT_MODE_P666 1 -+#define HI3403V100_OUT_MODE_P565 2 -+#define HI3403V100_OUT_MODE_BT656 5 -+#define HI3403V100_OUT_MODE_S888 8 -+#define HI3403V100_OUT_MODE_S888_DUMMY 12 -+#define HI3403V100_OUT_MODE_YUV420 14 -+/* for use special outface */ -+#define HI3403V100_OUT_MODE_AAAA 15 -+ -+/* output flags */ -+#define HI3403V100_OUTPUT_DSI_DUAL BIT(0) -+ -+struct drm_device; -+struct drm_connector; -+struct iommu_domain; -+ -+ -+typedef struct { -+ bool syncm; /* RW; sync mode(0:timing,as BT.656; 1:signal,as LCD) */ -+ bool iop; /* RW; interlaced or progressive display(0:i; 1:p) */ -+ unsigned char intfb; /* RW; interlaced bit width while output */ -+ -+ unsigned short vact; /* RW; vertical active area */ -+ unsigned short vbb; /* RW; vertical back blank porch */ -+ unsigned short vfb; /* RW; vertical front blank porch */ -+ -+ unsigned short hact; /* RW; horizontal active area */ -+ unsigned short hbb; /* RW; horizontal back blank porch */ -+ unsigned short hfb; /* RW; horizontal front blank porch */ -+ unsigned short hmid; /* RW; bottom horizontal active area */ -+ -+ unsigned short bvact; /* RW; bottom vertical active area */ -+ unsigned short bvbb; /* RW; bottom vertical back blank porch */ -+ unsigned short bvfb; /* RW; bottom vertical front blank porch */ -+ -+ unsigned short hpw; /* RW; horizontal pulse width */ -+ unsigned short vpw; /* RW; vertical pulse width */ -+ -+ bool idv; /* RW; inverse data valid of output */ -+ bool ihs; /* RW; inverse horizontal synchronization signal */ -+ bool ivs; /* RW; inverse vertical synchronization signal */ -+} ot_vo_sync_info; -+ -+struct smart_crtc_state { -+ struct drm_crtc_state base; -+ u8 encoder_type; -+ unsigned int bg_color; /* RW; background color of a device, in RGB format. */ -+ unsigned int intf_type; /* RW; type of a VO interface */ -+ unsigned int intf_sync; /* RW; type of a VO interface timing */ -+ ot_vo_sync_info sync_info; /* RW; information about VO interface timing */ -+}; -+#define to_smart_crtc_state(s) \ -+ container_of(s, struct smart_crtc_state, base) -+ -+ -+struct smart_drm_private { -+ struct iommu_domain *domain; -+ struct device *iommu_dev; -+ struct mutex mm_lock; -+ struct drm_mm mm; -+}; -+ -+struct smart_encoder { -+ int crtc_endpoint_id; -+ struct drm_encoder encoder; -+}; -+ -+int smart_drm_dma_attach_device(struct drm_device *drm_dev, -+ struct device *dev); -+void smart_drm_dma_detach_device(struct drm_device *drm_dev, -+ struct device *dev); -+void smart_drm_dma_init_device(struct drm_device *drm_dev, -+ struct device *dev); -+int smart_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); -+int smart_drm_encoder_set_crtc_endpoint_id(struct smart_encoder *rencoder, -+ struct device_node *np, int port, int reg); -+int smart_drm_endpoint_is_subdriver(struct device_node *ep); -+extern struct platform_driver smart_hdmi_driver; -+extern struct platform_driver smart_vop_driver; -+static inline struct smart_encoder *to_smart_encoder(struct drm_encoder *encoder) -+{ -+ return container_of(encoder, struct smart_encoder, encoder); -+} -+ -+#endif /* _HI3403V100_DRM_DRV_H_ */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.c b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.c -new file mode 100755 -index 0000000..9f113ec ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.c -@@ -0,0 +1,2122 @@ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "smart_hdmi.h" -+#include "smart_vo.h" -+#include "smart_drm_drv.h" -+ -+ -+struct hdmi_data_info { -+ int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ -+ bool sink_is_hdmi; -+ bool sink_has_audio; -+ -+ unsigned int enc_out_format; -+ unsigned int colorimetry; -+ unsigned int quant_range; -+}; -+ -+struct smart_hdmi { -+ struct device *dev; -+ struct drm_device *drm_dev; -+ -+ struct drm_connector connector; -+ struct smart_encoder encoder; -+ -+ unsigned int tmdsclk; -+ spinlock_t reg_lock; -+ -+ struct hdmi_data_info hdmi_data; -+ struct drm_display_mode previous_mode; -+ -+}; -+ -+struct hdmi_video_def g_cea_video_codes_des[CEA_VIDEO_CODE_MAX] = { -+// { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+// HDMI_PICTURE_ASPECT_NONE, HDMI_VIDEO_TIMING_UNKNOWN, HDMI_VIDEO_UNKNOWN, "NONE" }, -+ { HDMI_640X480P60_4_3, 25175, 59940, 640, 480, 160, 45, 16, 96, 48, 10, 2, 33, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_640X480P_60000, HDMI_VIDEO_PROGRESSIVE, "640*480p60 4:3" }, -+ { HDMI_720X480P60_4_3, 27000, 59940, 720, 480, 138, 45, 16, 62, 60, 9, 6, 30, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_720X480P_60000, HDMI_VIDEO_PROGRESSIVE, "720*480p60 4:3" }, -+ { HDMI_720X480P60_16_9, 27000, 59940, 720, 480, 138, 45, 16, 62, 60, 9, 6, 30, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_720X480P_60000, HDMI_VIDEO_PROGRESSIVE, "720*480p60 16:9" }, -+ { HDMI_1280X720P60_16_9, 74250, 60000, 1280, 720, 370, 30, 110, 40, 220, 5, 5, 20, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1280X720P_60000, HDMI_VIDEO_PROGRESSIVE, "1280*720p60 16:9" }, -+ { HDMI_1920X1080I60_16_9, 74250, 60000, 1920, 1080, 280, 22, 88, 44, 148, 2, 5, 15, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080I_60000, HDMI_VIDEO_INTERLACE, "1920*1080i60 16:9" }, -+ { HDMI_1440X480I60_4_3, 27000, 59940, 1440, 480, 276, 22, 38, 124, 114, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X480I_60000, HDMI_VIDEO_INTERLACE, "1440*480i60 4:3" }, -+ { HDMI_1440X480I60_16_9, 27000, 59940, 1440, 480, 276, 22, 38, 124, 114, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X480I_60000, HDMI_VIDEO_INTERLACE, "1440*480i60 16:9" }, -+ { HDMI_1440X240P60_4_3, 27000, 60054, 1440, 240, 276, 22, 38, 124, 114, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X240P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*240p60 4:3" }, -+ { HDMI_1440X240P60_16_9, 27000, 60054, 1440, 240, 276, 22, 38, 124, 114, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X240P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*240p60 16:9" }, -+ { HDMI_2880X480I60_4_3, 54000, 59940, 2880, 480, 552, 22, 76, 248, 228, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_2880X480I_60000, HDMI_VIDEO_INTERLACE, "2880*480i60 4:3" }, -+ { HDMI_2880X480I60_16_9, 54000, 59940, 2880, 480, 552, 22, 76, 248, 228, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_2880X480I_60000, HDMI_VIDEO_INTERLACE, "2880*480i60 16:9" }, -+ { HDMI_2880X240P60_4_3, 54000, 60054, 2880, 240, 552, 22, 76, 248, 228, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_2880X240I_60000, HDMI_VIDEO_PROGRESSIVE, "2880*240i60 4:3" }, -+ { HDMI_2880X240P60_16_9, 54000, 60054, 2880, 240, 552, 23, 76, 248, 228, 4, 3, 15, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_2880X240I_60000, HDMI_VIDEO_PROGRESSIVE, "2880*240i60 16:9" }, -+ { HDMI_1440X480P60_4_3, 54000, 59940, 1440, 480, 276, 45, 32, 124, 120, 9, 6, 30, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X480P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*480p60 4:3" }, -+ { HDMI_1440X480P60_16_9, 54000, 59940, 1440, 480, 276, 45, 32, 124, 120, 9, 6, 30, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X480P_60000, HDMI_VIDEO_PROGRESSIVE, "1440*480p60 16:9" }, -+ { HDMI_1920X1080P60_16_9, 148500, 60000, 1920, 1080, 280, 45, 88, 44, 148, 4, 5, 36, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_60000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p60 16:9" }, -+ { HDMI_720X576P50_4_3, 27000, 50000, 720, 576, 144, 49, 12, 64, 68, 5, 5, 39, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_720X576P_50000, HDMI_VIDEO_PROGRESSIVE, "720*576p50 4:3" }, -+ { HDMI_720X576P50_16_9, 27000, 50000, 720, 576, 144, 49, 12, 64, 68, 5, 5, 39, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_720X576P_50000, HDMI_VIDEO_PROGRESSIVE, "720*576p50 16:9" }, -+ { HDMI_1280X720P50_16_9, 74250, 50000, 1280, 720, 700, 30, 440, 40, 220, 5, 5, 20, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1280X720P_50000, HDMI_VIDEO_PROGRESSIVE, "1280*720p50 16:9" }, -+ { HDMI_1920X1080I50_16_9, 74250, 50000, 1920, 1080, 720, 24, 528, 44, 148, 2, 5, 15, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080I_50000, HDMI_VIDEO_INTERLACE, "1920*1080i50 16:9" }, -+ { HDMI_1440X576I50_4_3, 27000, 50000, 1440, 576, 288, 24, 24, 126, 138, 2, 3, 19, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X576I_50000, HDMI_VIDEO_INTERLACE, "1440*576i50 4:3" }, -+ { HDMI_1440X576I50_16_9, 27000, 50000, 1440, 576, 288, 24, 24, 126, 138, 2, 3, 19, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X576I_50000, HDMI_VIDEO_INTERLACE, "1440*576i50 16:9" }, -+ { HDMI_1440X576P50_4_3, 54000, 50000, 1440, 576, 288, 49, 24, 128, 136, 5, 5, 39, -+ HDMI_PICTURE_ASPECT_4_3, HDMI_VIDEO_TIMING_1440X576P_50000, HDMI_VIDEO_PROGRESSIVE, "1440*576p50 4:3" }, -+ { HDMI_1440X576P50_16_9, 54000, 50000, 1440, 576, 288, 49, 24, 128, 136, 5, 5, 39, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1440X576P_50000, HDMI_VIDEO_PROGRESSIVE, "1440*576p50 16:9" }, -+ { HDMI_1920X1080P50_16_9, 148500, 50000, 1920, 1080, 720, 45, 528, 44, 148, 4, 5, 36, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_50000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p50 16:9" }, -+ { HDMI_1920X1080P24_16_9, 742500, 24000, 1920, 1080, 830, 45, 638, 44, 148, 4, 5, 36, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_24000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p24 16:9" }, -+ { HDMI_1920X1080P25_16_9, 742500, 25000, 1920, 1080, 720, 45, 528, 44, 148, 4, 5, 36, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_25000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p25 16:9" }, -+ { HDMI_1920X1080P30_16_9, 742500, 30000, 1920, 1080, 280, 45, 88, 44, 148, 4, 5, 36, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_1920X1080P_30000, HDMI_VIDEO_PROGRESSIVE, "1920*1080p30 16:9" }, -+ { HDMI_3840X2160P24_16_9, 297000, 24000, 3840, 2160, 1660, 90, 1276, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_24000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p24 16:9" }, -+ { HDMI_3840X2160P25_16_9, 297000, 25000, 3840, 2160, 1440, 90, 1056, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_25000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p25 16:9" }, -+ { HDMI_3840X2160P30_16_9, 297000, 30000, 3840, 2160, 560, 90, 176, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_30000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p30 16:9" }, -+ { HDMI_3840X2160P50_16_9, 594000, 50000, 3840, 2160, 1440, 90, 1056, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_50000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p50 16:9" }, -+ { HDMI_3840X2160P60_16_9, 594000, 60000, 3840, 2160, 560, 90, 176, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_60000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p60 16:9" }, -+ { HDMI_4096X2160P24_256_135, 297000, 24000, 4096, 2160, 1404, 90, 1020, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_24000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p24 256:135" }, -+ { HDMI_4096X2160P25_256_135, 297000, 25000, 4096, 2160, 1184, 90, 968, 88, 128, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_25000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p25 256:135" }, -+ { HDMI_4096X2160P30_256_135, 297000, 30000, 4096, 2160, 304, 90, 88, 88, 128, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_30000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p30 256:135" }, -+ { HDMI_4096X2160P50_256_135, 594000, 50000, 4096, 2160, 1184, 90, 968, 88, 128, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_50000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p50 256:135" }, -+ { HDMI_4096X2160P60_256_135, 594000, 60000, 4096, 2160, 304, 90, 88, 88, 128, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_60000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p60 256:135" }, -+ { HDMI_3840X2160P120_16_9, 1188000, 120000, 3840, 2160, 560, 90, 176, 88, 296, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_3840X2160P_120000, HDMI_VIDEO_PROGRESSIVE, "3840*2160p120 16:9" }, -+ { HDMI_7680X4320P24_16_9, 1188000, 24000, 7680, 4320, 3320, 180, 2552, 176, 592, 16, 20, 144, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_7680X4320P_24000, HDMI_VIDEO_PROGRESSIVE, "7680*4320p24 16:9" }, -+ { HDMI_7680X4320P25_16_9, 1188000, 25000, 7680, 4320, 3120, 80, 2352, 176, 592, 16, 20, 44, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_7680X4320P_25000, HDMI_VIDEO_PROGRESSIVE, "7680*4320p25 16:9" }, -+ { HDMI_7680X4320P30_16_9, 1188000, 30000, 7680, 4320, 1320, 80, 552, 176, 592, 16, 20, 44, -+ HDMI_PICTURE_ASPECT_16_9, HDMI_VIDEO_TIMING_7680X4320P_30000, HDMI_VIDEO_PROGRESSIVE, "7680*4320p30 16:9" }, -+ { HDMI_4096X2160P120_256_135, 1188000, 120000, 4096, 2160, 304, 90, 88, 88, 128, 8, 10, 72, -+ HDMI_PICTURE_ASPECT_256_135, HDMI_VIDEO_TIMING_4096X2160P_120000, HDMI_VIDEO_PROGRESSIVE, "4096*2160p120 16:9" } -+}; -+ -+static struct smart_hdmi *encoder_to_smart_hdmi(struct drm_encoder *encoder) -+{ -+ struct smart_encoder *rkencoder = to_smart_encoder(encoder); -+ return container_of(rkencoder, struct smart_hdmi, encoder); -+} -+ -+static struct smart_hdmi *connector_to_smart_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct smart_hdmi, connector); -+} -+ -+static inline u8 smart_hdmi_get_power_mode(struct smart_hdmi *hdmi) -+{ -+ -+ return 0; -+} -+ -+static void smart_hdmi_set_power_mode(struct smart_hdmi *hdmi, int mode) -+{ -+ -+} -+ -+static int ctrl_avi_infoframe_data_set(const unsigned char *data) -+{ -+ hdmi_reg_avi_pkt_header_hb_set(data[AVI_OFFSET_TYPE], data[AVI_OFFSET_VERSION], data[AVI_OFFSET_LENGTH]); -+ hdmi_reg_avi_pkt0_low_set(data[AVI_OFFSET_CHECKSUM], -+ data[AVI_OFFSET_PB1], data[AVI_OFFSET_PB2], data[AVI_OFFSET_PB3]); -+ hdmi_reg_avi_pkt0_high_set(data[AVI_OFFSET_VIC], data[AVI_OFFSET_PB5], data[AVI_OFFSET_TOP_BAR_LOWER]); -+ hdmi_reg_avi_pkt1_low_set(data[AVI_OFFSET_TOP_BAR_UPPER], -+ data[AVI_OFFSET_BOTTOM_BAR_LOWER], data[AVI_OFFSET_BOTTOM_BAR_UPPER], data[AVI_OFFSET_LEFT_BAR_LOWER]); -+ hdmi_reg_avi_pkt1_high_set(data[AVI_OFFSET_LEFT_BAR_UPPER], -+ data[AVI_OFFSET_RIGHT_BAR_LOWER], data[AVI_OFFSET_RIGHT_BAR_UPPER]); -+ hdmi_reg_avi_pkt2_low_set(data[AVI_OFFSET_PB14], -+ data[AVI_OFFSET_PB15], data[AVI_OFFSET_PB16], data[AVI_OFFSET_PB17]); -+ hdmi_reg_avi_pkt2_high_set(data[AVI_OFFSET_PB18], data[AVI_OFFSET_PB19], data[AVI_OFFSET_PB20]); -+ hdmi_reg_avi_pkt3_low_set(data[AVI_OFFSET_PB21], -+ data[AVI_OFFSET_PB22], data[AVI_OFFSET_PB23], data[AVI_OFFSET_PB24]); -+ hdmi_reg_avi_pkt3_high_set(data[AVI_OFFSET_PB25], data[AVI_OFFSET_PB26], data[AVI_OFFSET_PB27]); -+ -+ return 0; -+} -+ -+static int ctrl_avi_infoframe_en_set(bool enable) -+{ -+ /* repeat enable */ -+ hdmi_reg_cea_avi_rpt_en_set(enable); -+ /* info_frame enable */ -+ hdmi_reg_cea_avi_en_set(enable); -+ -+ return 0; -+} -+ -+static int -+smart_hdmi_upload_frame(struct smart_hdmi *hdmi, int setup_rc, -+ union hdmi_infoframe *frame, u32 frame_index, -+ u32 mask, u32 disable, u32 enable) -+{ -+ if (setup_rc >= 0) { -+ u8 packed_frame[HDMI_INFOFRAME_BUFFER_SIZE]; // HDMI_INFOFRAME_BUFFER_SIZE 32 -+ ssize_t rc, i; -+ -+ rc = hdmi_infoframe_pack(frame, packed_frame, -+ sizeof(packed_frame)); -+ -+ if (rc < 0) -+ return rc; -+ -+ -+ //ctrl_avi_infoframe_data_set(packed_frame); -+ ctrl_avi_infoframe_en_set(0); -+ ctrl_avi_infoframe_data_set(packed_frame); -+ ctrl_avi_infoframe_en_set(1); -+ } -+ -+ return setup_rc; -+} -+ -+static int smart_hdmi_config_avi(struct smart_hdmi *hdmi, -+ struct drm_display_mode *mode) -+{ -+ union hdmi_infoframe frame; -+ int rc; -+ rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, -+ &hdmi->connector, mode); -+ -+ -+ if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444) -+ frame.avi.colorspace = HDMI_COLORSPACE_YUV444;//2 -+ else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422) -+ frame.avi.colorspace = HDMI_COLORSPACE_YUV422;//1 -+ else -+ frame.avi.colorspace = HDMI_COLORSPACE_RGB;//0 -+ -+ -+ -+ frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;//1 HDMI_COLORIMETRY_ITU_601 -+ frame.avi.scan_mode = HDMI_SCAN_MODE_NONE; -+ frame.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;//8 -+ frame.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9;//2 -+ frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;//2 -+ frame.avi.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;//0 -+ frame.avi.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;//1 -+ frame.avi.content_type = HDMI_CONTENT_TYPE_GRAPHICS;//0 -+ -+ -+ return smart_hdmi_upload_frame(hdmi, rc, &frame, -+ HDMI_INFOFRAME_TYPE_AVI, 0, 0, 0); -+} -+ -+void drm_mode_to_hal_syncinfo(struct drm_display_mode *mode, hal_disp_syncinfo *syncinfo) { -+ syncinfo->vact = mode->vdisplay; -+ syncinfo->vbb = mode->vtotal - mode->vsync_end; -+ syncinfo->vfb = mode->vsync_start - mode->vdisplay; -+ syncinfo->hact = mode->hdisplay; -+ syncinfo->hbb = mode->htotal - mode->hsync_end; -+ syncinfo->hfb = mode->hsync_start - mode->hdisplay; -+ syncinfo->hmid = 0; // 可�?�字�? -+ syncinfo->hpw = mode->hsync_end - mode->hsync_start; -+ syncinfo->vpw = mode->vsync_end - mode->vsync_start; -+ syncinfo->idv = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; -+ syncinfo->ihs = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; -+ syncinfo->ivs = (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1 : 0; -+} -+ -+extern void vo_hal_intf_set_sync_info_other(ot_vo_dev dev, -+ const hal_disp_syncinfo *sync_info); -+extern void vo_hal_intf_set_sync_info_hvsync(ot_vo_dev dev, -+ const hal_disp_syncinfo *sync_info); -+extern void vo_hal_intf_set_hdmi_sync_inv(const hal_disp_syncinv *inv); -+ -+static int smart_hdmi_config_video_timing(struct smart_hdmi *hdmi, -+ struct drm_display_mode *mode) -+{ -+ unsigned int sync_pol_cfg = 0; -+ -+ hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_H_BIT); -+ hdmi_set_bit(sync_pol_cfg, CTRL_SYCN_POL_V_BIT); -+ hdmi_clr_bit(sync_pol_cfg, CTRL_SYCN_POL_DE_BIT); -+ -+ hdmi_reg_inver_sync_set((unsigned char )sync_pol_cfg); -+ hdmi_reg_syncmask_en_set(0); -+ return 0; -+} -+ -+static int smart_hdmi_config_video_csc(struct smart_hdmi *hdmi) -+{ -+ unsigned int csc_mode = 0; -+ struct hdmi_data_info *data = &hdmi->hdmi_data; -+ unsigned int out_colormetry = data->colorimetry; -+ unsigned int in_colormetry = data->colorimetry; -+ unsigned int in_rgb = 0; -+ unsigned int dwsm_hori_enable = 0; -+ unsigned int y422_enable = 0; -+ unsigned int dwsm_vert_enable = 0; -+ unsigned int y420_enable = 0; -+ unsigned int csc_enable = 0; -+ unsigned int out_rgb = 0; -+ -+ //ctrl_video_dither_set -+ hdmi_reg_dither_rnd_bypass_set((unsigned char)(!1)); -+ hdmi_reg_dither_mode_set((unsigned char)HDMI_VIDEO_DITHER_10_8);//hdmi_reg_dither_mode_set((unsigned char)HDMI_VIDEO_DITHER_DISALBE); -+ //ctrl_video_path_deep_clr_set -+ hdmi_reg_tmds_pack_mode_set((unsigned char)HDMI_DEEP_COLOR_24BIT); -+ hdmi_reg_dc_pkt_en_set(0); -+ -+ //ctrl_video_path_colorimetry_set -+ csc_mode = hdmi_reg_csc_mode_get(); -+ out_colormetry = (unsigned int )out_colormetry & CTRL_COLORMETRY_MASK; -+ csc_mode &= CTRL_COLORMETRY_OUT_MASK; -+ csc_mode |= (unsigned int )out_colormetry << CTRL_COLORMETRY_OUT_BIT; -+ -+ in_colormetry = (unsigned int )in_colormetry & CTRL_COLORMETRY_MASK; -+ csc_mode &= CTRL_COLORMETRY_IN_MASK; -+ csc_mode |= (unsigned int )in_colormetry << CTRL_COLORMETRY_IN_BIT; -+ -+ //hdmi_reg_csc_mode_set((unsigned char )csc_mode); -+ -+ //ctrl_video_path_quantization_set -+ //csc_mode = hdmi_reg_csc_mode_get(); -+ -+ if (data->quant_range != HDMI_QUANTIZATION_RANGE_LIMITED) { -+ hdmi_set_bit(csc_mode, CTRL_QUANTIZAION_IN_BIT); -+ } else { -+ hdmi_clr_bit(csc_mode, CTRL_QUANTIZAION_IN_BIT); -+ } -+ -+ if (data->quant_range != HDMI_QUANTIZATION_RANGE_LIMITED) { -+ hdmi_set_bit(csc_mode, CTRL_QUANTIZAION_OUT_BIT); -+ } else { -+ hdmi_clr_bit(csc_mode, CTRL_QUANTIZAION_OUT_BIT); -+ } -+ -+ // hdmi_reg_csc_mode_set((unsigned char )csc_mode); -+ hdmi_reg_csc_saturate_en_set(1); -+ -+ //ctrl_video_color_rgb_set -+ //csc_mode = hdmi_reg_csc_mode_get(); -+ if (in_rgb) { -+ hdmi_set_bit(csc_mode, CTRL_RGB_IN_BIT); -+ } else { -+ hdmi_clr_bit(csc_mode, CTRL_RGB_IN_BIT); -+ } -+ -+ if (out_rgb) { -+ hdmi_set_bit(csc_mode, CTRL_RGB_OUT_BIT); -+ } else { -+ hdmi_clr_bit(csc_mode, CTRL_RGB_OUT_BIT); -+ } -+ hdmi_reg_csc_mode_set((unsigned char )csc_mode); -+ //ctrl_video_color_ycbcr422_set -+ if (y422_enable) { -+ hdmi_reg_vmux_y_sel_set(CTRL_CHANNEL0_Y422); -+ hdmi_reg_vmux_cb_sel_set(CTRL_CHANNEL1_Y422); -+ hdmi_reg_vmux_cr_sel_set(CTRL_CHANNEL2_Y422); -+ } else { -+ hdmi_reg_vmux_y_sel_set(CTRL_CHANNEL0_Y); -+ hdmi_reg_vmux_cb_sel_set(CTRL_CHANNEL1_CB); -+ hdmi_reg_vmux_cr_sel_set(CTRL_CHANNEL2_CR); -+ } -+ //ctrl_video_color_dwsm_hori_set -+ hdmi_reg_hori_filter_en_set((unsigned char)dwsm_hori_enable); -+ hdmi_reg_dwsm_hori_en_set((unsigned char)dwsm_hori_enable); -+ -+ //ctrl_video_color_ycbcr420_set -+ hdmi_reg_demux_420_en_set((unsigned char)y420_enable); -+ hdmi_reg_pxl_div_en_set((unsigned char)y420_enable); -+ -+ //ctrl_video_color_dwsm_vert_set -+ hdmi_reg_dwsm_vert_bypass_set((unsigned char)(!dwsm_vert_enable)); -+ hdmi_reg_dwsm_vert_en_set((unsigned char)dwsm_vert_enable); -+ -+ //ctrl_video_color_csc_set -+ hdmi_reg_csc_en_set((unsigned char)csc_enable); -+ return 0; -+} -+ -+static int ctrl_tmds_mode_get(hdmi_tmds_mode *tmds_mode) -+{ -+ bool hdmi_mode, hdmi2x_enable; -+ hdmi_mode = hdmi_reg_hdmi_mode_get(); -+ hdmi2x_enable = hdmi_reg_enc_hdmi2_on_get(); -+ if (!hdmi_mode) { -+ *tmds_mode = HDMI_TMDS_MODE_DVI; -+ } else if (hdmi_mode && (!hdmi2x_enable)) { -+ *tmds_mode = HDMI_TMDS_MODE_HDMI_1_4; -+ } else if (hdmi_mode && hdmi2x_enable) { -+ *tmds_mode = HDMI_TMDS_MODE_HDMI_2_0; -+ } else { -+ printk("un-config tmds mode!\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static int ctrl_tmds_mode_set(hdmi_tmds_mode tmds_mode) -+{ -+ switch (tmds_mode) { -+ case HDMI_TMDS_MODE_DVI: -+ hdmi_reg_hdmi_mode_set(0); -+ break; -+ case HDMI_TMDS_MODE_HDMI_1_4: -+ hdmi_reg_hdmi_mode_set(1); -+ hdmi_reg_enc_hdmi2_on_set(0); -+ break; -+ case HDMI_TMDS_MODE_HDMI_2_0: -+ hdmi_reg_hdmi_mode_set(1); -+ hdmi_reg_enc_hdmi2_on_set(1); -+ hdmi_reg_enc_bypass_set(0); -+ break; -+ default: -+ printk("un-known tmds mode:%u\n", tmds_mode); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static void phy_hw_reset_release(unsigned int id) -+{ -+ hdmi_reg_phy_bus_srst_req_set(1); -+ msleep(1); -+ hdmi_reg_phy_bus_srst_req_set(0); -+ -+ msleep(1); -+ hdmi_reg_resetn_set(id, 0); -+ hdmi_reg_sw_reset_mod_clock_set(id, 0); -+ hdmi_reg_sw_reset_tmds_clock_set(id, 0); -+ hdmi_reg_sw_reset_mpll_clock_set(id, 0); -+ hdmi_reg_sw_reset_nco_clock_set(id, 0); -+ hdmi_reg_sw_reset_fd_clock_set(id, 0); -+ hdmi_reg_sw_reset_mod_and_mpll_clock_set(id, 0); -+ hdmi_reg_sw_reset_mod_and_nco_clock_set(id, 0); -+ hdmi_reg_sw_reset_mod_and_fd_clock_set(id, 0); -+ hdmi_reg_sw_reset_hsfifo_clock_set(id, 0); -+ hdmi_reg_sw_reset_txfifo_clock_set(id, 0); -+ hdmi_reg_sw_reset_data_clock_set(id, 0); -+ hdmi_reg_sw_reset_hs_clock_set(id, 0); -+ hdmi_reg_sw_reset_pllref_clock_set(id, 0); -+ hdmi_reg_sw_reset_dac_clock_set(id, 0); -+ hdmi_reg_dac_clock_gat_set(id, 0); -+ hdmi_reg_sw_reset_frl_clock_set(id, 0); -+ hdmi_reg_up_sample_fifo_clock_swrst_set(id, 0); -+ hdmi_reg_swreset_unused_set(id, 0); -+ hdmi_reg_global_reset_set(id, 1); -+ hdmi_reg_resetn_set(id, 1); -+ hdmi_reg_global_reset_set(id, 0); -+ hdmi_reg_dac_clock_gat_set(id, 1); -+ hdmi_reg_fd_clk_sel_set(id, 0); -+ hdmi_reg_refclk_sel_set(id, 0); -+ hdmi_reg_ctman_set(id, 0); -+ hdmi_reg_modclk_sel_set(id, 1); -+ hdmi_reg_fdivclk_sel_set(id, 0); -+ hdmi_reg_mod_div_val_set(id, 0); -+ hdmi_reg_ref_clk_sel_set(id, 1); -+ hdmi_reg_req_length_set(id, 0x0); -+ hdmi_reg_stb_delay2_set(id, 0x2); -+ hdmi_reg_stb_delay1_set(id, 0x2); -+ hdmi_reg_stb_delay0_set(id, 0x2); -+ hdmi_reg_stb_acc_sel_set(id, 0); -+ hdmi_reg_stb_cs_sel_set(id, 0); -+ return; -+} -+ -+static int phy_hw_input_clock_check(unsigned int id, unsigned int *pixel_clk) -+{ -+ unsigned int reg_ret_value, input_clk; -+ /* select pixel clock */ -+ hdmi_reg_fd_clk_sel_set(id, 0x0); -+ hdmi_reg_refclk_sel_set(id, 0x0); -+ hdmi_reg_ctman_set(id, 0x0); -+ hdmi_reg_modclk_sel_set(id, 0x1); -+ hdmi_reg_fdivclk_sel_set(id, 0x0); -+ hdmi_reg_mod_div_val_set(id, 0x0); -+ /* set lock_val and lock_cnt */ -+ hdmi_reg_src_lock_val_set(id, 0x04); -+ hdmi_reg_src_lock_cnt_set(id, 0x02); -+ hdmi_reg_src_enable_set(id, 0x0); -+ hdmi_reg_fdsrcparam_unused_set(id, 0x0); -+ /* set frequency options */ -+ hdmi_reg_src_cnt_opt_set(id, 0x1); -+ hdmi_reg_fdsrcfreq_unused1_set(id, 0); -+ hdmi_reg_src_freq_opt_set(id, 0); -+ hdmi_reg_fdsrcfreq_unused2_set(id, 0); -+ hdmi_reg_src_freq_ext_set(id, 0); -+ /* FD enable */ -+ hdmi_reg_src_lock_val_set(id, 0x4); -+ hdmi_reg_src_lock_cnt_set(id, 0x2); -+ hdmi_reg_src_enable_set(id, 0x1); -+ hdmi_reg_fdsrcparam_unused_set(id, 0x0); -+ /* delay time */ -+ msleep(1); -+ /* read status and result */ -+ reg_ret_value = hdmi_reg_src_det_stat_get(id); -+ input_clk = hdmi_reg_src_cnt_out_get(id); -+ printk("input clock = : %u khz\n", input_clk); -+ if ((reg_ret_value & 0xF) == 0xF) { -+ printk("input clock quality : stable\n"); -+ *pixel_clk = input_clk; -+ } else { -+ printk("warning! input clock is unstable!\n"); -+ *pixel_clk = input_clk; -+ return -1; -+ } -+ -+ return 0; -+} -+static void phy_hw_write_stb1_byte(unsigned int id, unsigned int cs, aphy_offset_addr aphy_offset, unsigned int wdata) -+{ -+ /* CS reset */ -+ hdmi_reg_stb_cs_en_set(id, 0x00); -+ /* WR reset */ -+ hdmi_reg_stb_wen_set(id, 0); -+ /* WDATA set */ -+ hdmi_reg_stb_wdata_set(id, wdata); -+ /* ADDR set */ -+ hdmi_reg_stb_addr_set(id, aphy_offset); -+ udelay(1); -+ /* WR set */ -+ hdmi_reg_stb_wen_set(id, 1); -+ /* CS set */ -+ hdmi_reg_stb_cs_en_set(id, cs); -+ udelay(1); -+ /* CS reset */ -+ hdmi_reg_stb_cs_en_set(id, 0x00); -+ /* WR reset */ -+ hdmi_reg_stb_wen_set(id, 0); -+ -+ return; -+} -+ -+static void phy_hw_ref_clk_div_set(unsigned int id, unsigned int pixel_clk) -+{ -+ unsigned int ref_clk_div = 0; -+ if (pixel_clk < g_phy_hw_def_clk_div[0].clk_range.clk_max) { -+ ref_clk_div = g_phy_hw_def_clk_div[0].seek_value; -+ } else if (pixel_clk >= g_phy_hw_def_clk_div[1].clk_range.clk_min && -+ pixel_clk < g_phy_hw_def_clk_div[1].clk_range.clk_max) { -+ ref_clk_div = g_phy_hw_def_clk_div[1].seek_value; -+ } else if (pixel_clk >= g_phy_hw_def_clk_div[2].clk_range.clk_min && -+ pixel_clk < g_phy_hw_def_clk_div[2].clk_range.clk_max) { -+ ref_clk_div = g_phy_hw_def_clk_div[2].seek_value; -+ } else if (pixel_clk >= g_phy_hw_def_clk_div[3].clk_range.clk_min && -+ pixel_clk < g_phy_hw_def_clk_div[3].clk_range.clk_max) { -+ ref_clk_div = g_phy_hw_def_clk_div[3].seek_value; -+ } else if (pixel_clk >= g_phy_hw_def_clk_div[4].clk_range.clk_min && -+ pixel_clk < g_phy_hw_def_clk_div[4].clk_range.clk_max) { -+ ref_clk_div = g_phy_hw_def_clk_div[4].seek_value; -+ } -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_2, ref_clk_div); -+ -+ return; -+} -+ -+static int phy_hw_divn_sel_get(unsigned int tmds_clk, unsigned char *tmds_divn) -+{ -+ unsigned int i; -+ const phy_clk_range_value *phy_tmds_divnsel = NULL; -+ -+ for (i = 0, phy_tmds_divnsel = &g_phy_hw_tmds_divn_sel[0]; -+ (i < hdmi_array_size(g_phy_hw_tmds_divn_sel)); phy_tmds_divnsel++, i++) { -+ if ((tmds_clk >= phy_tmds_divnsel->clk_range.clk_min) && (tmds_clk < phy_tmds_divnsel->clk_range.clk_max)) { -+ *tmds_divn = phy_tmds_divnsel->seek_value; -+ return 0; -+ } -+ } -+ printk("can't find param, tmds_clk:%u\n", tmds_clk); -+ return -1; -+} -+ -+static void phy_hw_tmds_clk_div_set(unsigned int id, unsigned int tmds_clk) -+{ -+ int ret; -+ unsigned char tmds_clk_div = 0; -+ -+ ret = phy_hw_divn_sel_get(tmds_clk, &tmds_clk_div); -+ if (ret != 0) { -+ return; -+ } -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_3, ((0x14 << 0x3) | (tmds_clk_div & 0x7))); -+} -+ -+static void phy_hw_init_tmds(unsigned int id, const hdmi_phy_tmds_cfg *hdmi_spec_cfg) -+{ -+ /* PLL settings */ -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_E, 0x11); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_0, 0xFF); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_1, 0x11); -+ -+ /* aphy refclk select */ -+ phy_hw_ref_clk_div_set(id, hdmi_spec_cfg->pixel_clk); -+ phy_hw_tmds_clk_div_set(id, hdmi_spec_cfg->tmds_clk); -+ -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_4, 0x00); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_9, 0x00); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_A, 0x03); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_B, 0xE0); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_C, 0x14); -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_D, 0xF0); -+ -+ return; -+} -+ -+static const phy_ssc g_phy_ssc_cfg[] = { -+ {{ 25000, 70000 }, { 0, 0 }}, // 0ppm -+ {{ 70001, 90000 }, { 150, 45000 }}, // 0.15 -+ {{ 90001, 110000 }, { 70, 45000 }}, // 0.07% -+ {{ 110001, 145000 }, { 50, 45000 }}, // 0.05% -+ {{ 145001, 180000 }, { 100, 45000 }}, // 0.10% -+ {{ 180001, 220000 }, { 40, 45000 }}, // 0.04% -+ {{ 220001, 250000 }, { 40, 45000 }}, // 0.04% -+ {{ 250001, 300000 }, { 40, 45000 }}, // 0.04% -+ {{ 300001, 600000 }, { 0, 0 }}, // 0 -+}; -+ -+static const phy_ssc_cfg *phy_ssc_data_get(unsigned int tmds_clk) -+{ -+ unsigned int i; -+ const phy_ssc *ssc_cfg = NULL; -+ -+ for (i = 0, ssc_cfg = &g_phy_ssc_cfg[0]; (ssc_cfg && (i < hdmi_array_size(g_phy_ssc_cfg))); ssc_cfg++, i++) { -+ if ((tmds_clk >= ssc_cfg->phy_tmds_clk_range.clk_min) && (tmds_clk <= ssc_cfg->phy_tmds_clk_range.clk_max)) { -+ return (&ssc_cfg->ssc_cfg); -+ } -+ } -+ -+ return NULL; -+} -+ -+unsigned long long hi_div_u64_rem(unsigned long long dividend, unsigned int divisor) -+{ -+ unsigned int remainder; -+ -+ div_u64_rem(dividend, divisor, &remainder); -+ -+ return remainder; -+} -+ -+static void hal_hdmi_phy_ssc_init(unsigned int id, unsigned short mod_d, unsigned short mod_n) -+{ -+ -+ /* MOD_N MOD_T */ -+ hdmi_reg_mod_len_set(id, 0); -+ hdmi_reg_mod_t_set(id, 1); -+ hdmi_reg_mod_n_set(id, mod_n); -+ /* MOD_D */ -+ hdmi_reg_mod_d_set(id, mod_d); -+ /* FDIV init */ -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 0); -+ hdmi_reg_en_mod_set(id, 0); -+ hdmi_reg_en_sdm_set(id, 0); -+ /* FDIV init */ -+ hdmi_reg_init_set(id, 1); -+ udelay(1); /* 150 nsec */ -+ /* FDIV control */ -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 0); -+ hdmi_reg_en_mod_set(id, 0); -+ hdmi_reg_en_sdm_set(id, 0); -+ udelay(1); /* 150 nsec */ -+ /* FDIV control */ -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 1); -+ hdmi_reg_en_mod_set(id, 0); -+ hdmi_reg_en_sdm_set(id, 0); -+ /* FDIV control */ -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 1); -+ hdmi_reg_en_mod_set(id, 1); -+ hdmi_reg_en_sdm_set(id, 0); -+ /* FDIV control */ -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 1); -+ hdmi_reg_en_mod_set(id, 1); -+ hdmi_reg_en_sdm_set(id, 1); -+ -+ return; -+} -+ -+static int phy_hw_clk_rang_value_get(unsigned int tmds_clk, unsigned char size, -+ const phy_clk_range_value *phy_rang_sel, unsigned char *seek_value) -+{ -+ unsigned int i; -+ const phy_clk_range_value *phy_rang = NULL; -+ -+ for (i = 0, phy_rang = &phy_rang_sel[0]; (i < size); phy_rang++, i++) { -+ if ((tmds_clk >= phy_rang->clk_range.clk_min) && (tmds_clk < phy_rang->clk_range.clk_max)) { -+ *seek_value = phy_rang->seek_value; -+ return 0; -+ } -+ } -+ printk("can't find param,tmds_clk:%u,i=%u\n", tmds_clk, i); -+ -+ return -1; -+} -+ -+static unsigned int phy_hw_pow(unsigned int base_num, unsigned int index_num) -+{ -+ unsigned int i; -+ unsigned int ret_val = 1; -+ -+ for (i = 0; i < index_num; i++) { -+ ret_val = ret_val * base_num; -+ } -+ -+ return ret_val; -+} -+ -+static int phy_hw_fractional_mnx_get(unsigned int tmds_clk, unsigned int pixel_clk, hdmi_deep_color deep_color) -+{ -+ unsigned char k, m_value, size; -+ unsigned int mn_value, pll_ref_clk; -+ unsigned char seek_value = 0; -+ unsigned char tmds_divnsel = 0; -+ -+ /* HDMI 2.0 configure pll feedback coefficient M, N, X */ -+ size = (unsigned char)hdmi_array_size(g_phy_hw_def_clk_div); -+ /* determine the reference clock division factor */ -+ if (phy_hw_clk_rang_value_get(pixel_clk, size, &g_phy_hw_def_clk_div[0], &seek_value) != 0) { -+ return -1; -+ } -+ -+ /* obtain TMDS_DIVNSEL */ -+ if (phy_hw_divn_sel_get(tmds_clk, &tmds_divnsel) != 0) { -+ return -1; -+ } -+ -+ printk("pixel_clk: %u, seek_value: %u-%u\n", pixel_clk, seek_value, phy_hw_pow(PHY_POW_BASE_NUM, seek_value)); -+ pll_ref_clk = pixel_clk / phy_hw_pow(PHY_POW_BASE_NUM, seek_value); -+ g_mnx_get.pll_ref_clk = pll_ref_clk; -+ printk("pll_ref_clk(%u), tmds_divnsel(%u), deep_color(%u) \n", g_mnx_get.pll_ref_clk, tmds_divnsel, deep_color); -+ switch (deep_color) { -+ case HDMI_DEEP_COLOR_30BIT: -+ mn_value = TMDS_CLK_FREQ_MUITIPLE * phy_hw_pow(PHY_POW_BASE_NUM, tmds_divnsel) * -+ phy_hw_pow(PHY_POW_BASE_NUM, seek_value) * 5 / 4; /* 5 and 4 means 10bit is std 5/4 multiple */ -+ break; -+ case HDMI_DEEP_COLOR_36BIT: -+ mn_value = TMDS_CLK_FREQ_MUITIPLE * phy_hw_pow(PHY_POW_BASE_NUM, tmds_divnsel) * -+ phy_hw_pow(PHY_POW_BASE_NUM, seek_value) * 3 / 2; /* 3 and 2 means 12bit is std 3/2 multiple */ -+ break; -+ default: -+ mn_value = TMDS_CLK_FREQ_MUITIPLE * phy_hw_pow(PHY_POW_BASE_NUM, tmds_divnsel) * -+ phy_hw_pow(PHY_POW_BASE_NUM, seek_value); -+ break; -+ } -+ printk("mn_value = %u \n", mn_value); -+ g_mnx_get.mn_value = mn_value; -+ -+ /* calculate N value */ -+ g_mnx_get.n_val = (unsigned char)(mn_value % 10); /* 10, about pll coefficient N calculate protocol */ -+ if (g_mnx_get.n_val == 0) { -+ k = 2; /* 2, means 1 + 1, about pll coefficient N real value calculate */ -+ g_mnx_get.n_val = 10; /* calculate result n_val is 0, get real n_val 10 */ -+ } else { -+ k = 1; -+ } -+ -+ /* calculate M value */ -+ m_value = (unsigned char)(mn_value / 10); /* 10, about pll coefficient M calculate protocol */ -+ g_mnx_get.m_val = m_value - k; -+ printk("get mnx M:%x, N:%u\n", g_mnx_get.m_val, g_mnx_get.n_val); -+ -+ return 0; -+} -+ -+int hal_hdmi_phy_ssc_set(unsigned int id, hdmi_phy_ssc_cfg *hdmi_ssc_cfg) -+{ -+ unsigned short mod_d, mod_n; -+ unsigned int mod_dn, ssc_freq; -+ unsigned int rem, ssc_amptd; -+ unsigned long long mod_dl; -+ const phy_ssc_cfg *phy_ssc_cfg_tmp = NULL; -+ -+ phy_ssc_cfg_tmp = phy_ssc_data_get(hdmi_ssc_cfg->tmds_clk); -+ if (hdmi_ssc_cfg->phy_ssc.ssc_enable == 1 && phy_ssc_cfg_tmp != NULL) { -+ hdmi_ssc_cfg->phy_ssc.ssc_cfg = *phy_ssc_cfg_tmp; -+ } else { -+ return -1; -+ } -+ -+ ssc_amptd = hdmi_ssc_cfg->phy_ssc.ssc_cfg.ssc_amptd; -+ ssc_freq = hdmi_ssc_cfg->phy_ssc.ssc_cfg.ssc_freq / HDMI_THOUSAND; /* k_hz/1000, unit is hz */ -+ if (ssc_freq == 0) { -+ return -1; -+ } -+ if (phy_hw_fractional_mnx_get(hdmi_ssc_cfg->tmds_clk, -+ hdmi_ssc_cfg->pix_clk, hdmi_ssc_cfg->deep_color) != 0) { -+ printk("MNX get fail\n"); -+ } -+ /* g_mnx_get.pll_ref_clk * 10000 / (ssc_freq * 4) */ -+ mod_dn = (unsigned int )div64_u64(((unsigned long long)g_mnx_get.pll_ref_clk * 2500), ssc_freq); /* 2500, means 10000/4 */ -+ /* 10000 eq 1000*10. 1000 get to unit k_hz; 10 is get 1 significant digits. 5000 means rounding off mod_n */ -+ mod_n = (mod_dn % MOD_N_MULTI_COEFFICIENT) >= 5000 ? (unsigned short )(mod_dn / MOD_N_MULTI_COEFFICIENT + 1) : -+ (unsigned short )(mod_dn / MOD_N_MULTI_COEFFICIENT); -+ /* relative deviation = (MOD_D(0x80A0[15:0])*MOD_N(0x809C[31:16])) / (65536*(((M+1)*10)+(N+X))) */ -+ if (mod_n == 0) { -+ return -1; -+ } -+ mod_dl = (unsigned long long)div64_u64(((unsigned long long)phy_hw_pow(PHY_POW_BASE_NUM, PHY_POW_INDEX_NUM) * -+ g_mnx_get.mn_value * ssc_amptd), mod_n); -+ /* 100000 eq 1000*100. 1000 get to unit k_hz; 100 is get 2 significant digits. */ -+ rem = (unsigned int )hi_div_u64_rem(mod_dl, MOD_D_MULTI_COEFFICIENT); -+ if (rem >= 50000) { /* 50000 means rounding off mod_n */ -+ mod_d = (unsigned short )(div64_u64(mod_dl, MOD_D_MULTI_COEFFICIENT) + 1); -+ } else { -+ mod_d = (unsigned short )div64_u64(mod_dl, MOD_D_MULTI_COEFFICIENT); -+ } -+ printk("mod_n = %x, mod_d = %x \n", mod_n, mod_d); -+ -+ if (hdmi_ssc_cfg->phy_ssc.ssc_enable) { -+ phy_hw_write_stb1_byte(id, APHY_CS_8, APHY_OFFSET_D, 0xFD); -+ hal_hdmi_phy_ssc_init(id, mod_d, mod_n); -+ } else { -+ /* FDIV init */ -+ hdmi_reg_init_set(id, 1); -+ udelay(1); -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 0); -+ hdmi_reg_en_mod_set(id, 0); -+ } -+ return 0; -+} -+ -+static void phy_hw_tmds_aphy_spec_set(unsigned int id, const struct tmds_spec_params *tmds) -+{ -+ const struct aphy_spec_params *data = &tmds->data.aphy; -+ const struct aphy_spec_params *clk = &tmds->clock.aphy; -+ /* data drv set */ -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_0, data->offset_0); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_1, data->offset_1); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_2, data->offset_2); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_3, data->offset_3); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_4, data->offset_4); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_5, data->offset_5); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_8, data->offset_8); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_9, data->offset_9); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_A, data->offset_a); -+ phy_hw_write_stb1_byte(id, APHY_CS_012, APHY_OFFSET_B, data->offset_b); -+ /* clk drv set */ -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_0, clk->offset_0); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_1, clk->offset_1); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_2, clk->offset_2); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_3, clk->offset_3); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_4, clk->offset_4); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_5, clk->offset_5); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_8, clk->offset_8); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_9, clk->offset_9); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_A, clk->offset_a); -+ phy_hw_write_stb1_byte(id, APHY_CS_3, APHY_OFFSET_B, clk->offset_b); -+} -+ -+static void hdmi_write_mask(unsigned int id, unsigned int offset, unsigned int val, unsigned int mask) -+{ -+ unsigned int tmp; -+ char *reg = NULL; -+ -+ reg = (char *)hdmi_reg_tx_get_phy_addr(id); -+ if (reg == NULL) { -+ hdmi_warn("phy addr is null!\n"); -+ return; -+ } -+ reg += offset; -+ tmp = *(volatile unsigned int *)(reg); -+ tmp = (tmp & ~mask) | (val & mask); -+ *(volatile unsigned int *)reg = tmp; -+} -+ -+static void phy_hw_tmds_dphy_spec_set(unsigned int id, const struct tmds_spec_params *tmds) -+{ -+ const struct dphy_spec_params *data = &tmds->data.dphy; -+ const struct dphy_spec_params *clk = &tmds->clock.dphy; -+ const struct dphy_spec_en *data_en = &tmds->data.en; -+ const struct dphy_spec_en *clk_en = &tmds->clock.en; -+ /* select dphy drv set mode */ -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_hdmi_ffe_sel(0x1), CFG_HDMI_FFE_SEL_M); -+ /* dphy data drv set */ -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_post2_ch0(data->drv_post2), CFG_DRV_POST2_CH0_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_post1_ch0(data->drv_post1), CFG_DRV_POST1_CH0_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_m_ch0(data->drv_main), CFG_DRV_M_CH0_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH0, cfg_drv_pre_ch0(data->drv_pre), CFG_DRV_PRE_CH0_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_post2_ch1(data->drv_post2), CFG_DRV_POST2_CH1_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_post1_ch1(data->drv_post1), CFG_DRV_POST1_CH1_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_m_ch1(data->drv_main), CFG_DRV_M_CH1_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH1, cfg_drv_pre_ch1(data->drv_pre), CFG_DRV_PRE_CH1_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_post2_ch2(data->drv_post2), CFG_DRV_POST2_CH2_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_post1_ch2(data->drv_post1), CFG_DRV_POST1_CH2_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_m_ch2(data->drv_main), CFG_DRV_M_CH2_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH2, cfg_drv_pre_ch2(data->drv_pre), CFG_DRV_PRE_CH2_M); -+ /* dphy clk drv set */ -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_post2_ch3(clk->drv_post2), CFG_DRV_POST2_CH3_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_post1_ch3(clk->drv_post1), CFG_DRV_POST1_CH3_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_m_ch3(clk->drv_main), CFG_DRV_M_CH3_M); -+ hdmi_write_mask(id, TMDS_DRV_CFG_CH3, cfg_drv_pre_ch3(clk->drv_pre), CFG_DRV_PRE_CH3_M); -+ /* dphy data drv enable */ -+ hdmi_write_mask(id, FFE_EN_CFG, cfg_c2_pre_en((unsigned int)data_en->drv_pre_en) | -+ cfg_c2_post1_en((unsigned int)data_en->drv_post1_en) | cfg_c2_post2_en((unsigned int)data_en->drv_post2_en) | -+ cfg_c1_pre_en((unsigned int)data_en->drv_pre_en) | cfg_c1_post1_en((unsigned int)data_en->drv_post1_en) | -+ cfg_c1_post2_en((unsigned int)data_en->drv_post2_en) | cfg_c0_pre_en((unsigned int)data_en->drv_pre_en) | -+ cfg_c0_post1_en((unsigned int)data_en->drv_post1_en) | cfg_c0_post2_en((unsigned int)data_en->drv_post2_en), -+ CFG_C2_PRE_EN_M | CFG_C2_POST1_EN_M | CFG_C2_POST2_EN_M | CFG_C1_PRE_EN_M | -+ CFG_C1_POST1_EN_M | CFG_C1_POST2_EN_M | CFG_C0_PRE_EN_M | CFG_C0_POST1_EN_M | CFG_C0_POST2_EN_M); -+ /* dphy clock drv enable */ -+ hdmi_write_mask(id, FFE_EN_CFG, cfg_c3_pre_en((unsigned int)clk_en->drv_pre_en) | -+ cfg_c3_post1_en((unsigned int)clk_en->drv_post1_en) | cfg_c3_post2_en((unsigned int)clk_en->drv_post2_en), -+ CFG_C3_PRE_EN_M | CFG_C3_POST1_EN_M | CFG_C3_POST2_EN_M); -+} -+ -+static int phy_user_spec_param_set(unsigned int id, int tmds_clk, hdmi_trace_len len, struct tmds_spec_params *spec) -+{ -+ unsigned int i; -+ const struct tmds_spec_params *tmp = NULL; -+ tmp = &g_tmds_spec[0]; -+ -+ /* User's four frequency hw spec settings corresponding to four frequency are configured by default(g_tmds_spec). */ -+ for (i = 0; tmp != NULL && (i < hdmi_array_size(g_tmds_spec)); i++, tmp++) { -+ /* Confirm the current frequency band. */ -+ if (tmds_clk >= tmp->min_tmds_clk && tmds_clk <= tmp->max_tmds_clk) { -+ if (spec->data.dphy.drv_post1 != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_data) { -+ spec->data.dphy.drv_post1 = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_data; -+ } -+ if (spec->clock.dphy.drv_post1 != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_clk) { -+ spec->clock.dphy.drv_post1 = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_de_main_clk; -+ } -+ if (spec->data.dphy.drv_main != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_data) { -+ spec->data.dphy.drv_main = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_data; -+ } -+ if (spec->clock.dphy.drv_main != g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_clk) { -+ spec->clock.dphy.drv_main = g_hdmi_phy_info[id].hw_spec[len].hw_param[i].i_main_clk; -+ } -+ break; -+ } -+ } -+ return 0; -+} -+ -+static void phy_hw_tmds_spec_trace_len_get(const struct tmds_spec_params **hwspec_enhance, hdmi_trace_len trace_len) -+{ -+ const struct tmds_spec_params *hwspec = NULL; -+ switch (trace_len) { -+ case HDMI_TRACE_LEN_0: -+ hwspec = &g_tmds_spec_1inch[0]; -+ break; -+ case HDMI_TRACE_LEN_1: -+ hwspec = &g_tmds_spec_1p5inch[0]; -+ break; -+ case HDMI_TRACE_LEN_2: -+ hwspec = &g_tmds_spec_2inch[0]; -+ break; -+ case HDMI_TRACE_LEN_3: -+ hwspec = &g_tmds_spec_2p5inch[0]; -+ break; -+ case HDMI_TRACE_LEN_4: -+ hwspec = &g_tmds_spec_3inch[0]; -+ break; -+ case HDMI_TRACE_LEN_5: -+ hwspec = &g_tmds_spec_3p5inch[0]; -+ break; -+ case HDMI_TRACE_LEN_6: -+ hwspec = &g_tmds_spec_4inch[0]; -+ break; -+ case HDMI_TRACE_LEN_7: -+ hwspec = &g_tmds_spec_4p5inch[0]; -+ break; -+ case HDMI_TRACE_LEN_8: -+ hwspec = &g_tmds_spec_5inch[0]; -+ break; -+ default: -+ hwspec = &g_tmds_spec[0]; -+ break; -+ } -+ -+ *hwspec_enhance = hwspec; -+ -+ return; -+} -+ -+static const struct tmds_spec_params *get_tmds_spec_params(const hdmi_phy_tmds_cfg *tmds_cfg) -+{ -+ unsigned int i; -+ unsigned int len; -+ const struct tmds_spec_params *tmp = NULL; -+ if (tmds_cfg->trace_len == HDMI_TRACE_DEFAULT) { -+ tmp = &g_tmds_spec[0]; -+ } else { -+ phy_hw_tmds_spec_trace_len_get(&tmp, tmds_cfg->trace_len); -+ } -+ len = (unsigned int)hdmi_array_size(g_tmds_spec); -+ for (i = 0; i < len; i++) { -+ if (tmds_cfg->tmds_clk >= tmp[i].min_tmds_clk && tmds_cfg->tmds_clk < tmp[i].max_tmds_clk) { -+ return &tmp[i]; -+ } -+ } -+ return NULL; -+} -+ -+static int phy_tmds_spec_set(unsigned int id, const hdmi_phy_tmds_cfg *tmds_cfg) -+{ -+ int ret; -+ const struct tmds_spec_params *tmds = NULL; -+ struct tmds_spec_params tmds_spec = {0}; -+ -+ tmds = get_tmds_spec_params(tmds_cfg); -+ if(!tmds) { -+ return -1; -+ } -+ memcpy(&tmds_spec, tmds, sizeof(*tmds)); -+ -+ phy_user_spec_param_set(id, tmds_cfg->tmds_clk, tmds_cfg->trace_len, &tmds_spec); -+ -+ phy_hw_tmds_aphy_spec_set(id, &tmds_spec); -+ phy_hw_tmds_dphy_spec_set(id, &tmds_spec); -+ -+ return 0; -+} -+ -+static int hal_hdmi_clk_set_para_get(unsigned int id, phy_clk_set *phy_clk) -+{ -+ unsigned char size; -+ -+ size = (unsigned char)hdmi_array_size(g_phy_hw_fcd_step_set); -+ if (phy_hw_clk_rang_value_get(phy_clk->tmds_cfg.tmds_clk, size, -+ &g_phy_hw_fcd_step_set[0], &phy_clk->fcd_step) != 0) { -+ return -1; -+ } -+ printk("get fcd_step = %x\n", phy_clk->fcd_step); -+ -+ size = (unsigned int)hdmi_array_size(g_phy_hw_def_clk_div); -+ if (phy_hw_clk_rang_value_get(phy_clk->tmds_cfg.pixel_clk, size, -+ &g_phy_hw_def_clk_div[0], &phy_clk->ref_clk_div) != 0) { -+ return -1; -+ } -+ printk("get ref_clk_div = %x\n", phy_clk->ref_clk_div); -+ -+ size = (unsigned char)hdmi_array_size(g_phy_hw_tmds_divn_sel); -+ if (phy_hw_clk_rang_value_get(phy_clk->tmds_cfg.tmds_clk, size, -+ &g_phy_hw_tmds_divn_sel[0], &phy_clk->tmds_divnsel) != 0) { -+ return -1; -+ } -+ -+ /* shut down FCG */ -+ phy_hw_write_stb1_byte(id, 0x100, 0xB, 0x00); -+ hdmi_reg_fcg_en_set(id, 0); -+ hdmi_reg_fcg_dlf_en_set(id, 0); -+ hdmi_reg_fcg_dither_en_set(id, 0); -+ hdmi_reg_fcg_lock_en_set(id, 0); -+ printk("get tmds_divnsel = %x\n", phy_clk->tmds_divnsel); -+ -+ return 0; -+} -+ -+static void phy_hw_clock_tmds_set(unsigned int id, const phy_clk_set *phy_clk) -+{ -+ hdmi_reg_divn_h20_set(id, (phy_clk->fcd_step & 0x07)); -+ hdmi_reg_fcdstepset_unused_set(id, 0); -+ hdmi_reg_up_sampler_ratio_sel_set(id, 0); -+ hdmi_reg_manual_en_set(id, 0xe); -+ printk("g_mnx_get: M:%u, N:%u\n", g_mnx_get.m_val, g_mnx_get.n_val); -+ hdmi_reg_mdiv_set(id, g_mnx_get.m_val); -+ hdmi_reg_fdiv_in_set(id, ((unsigned int)g_mnx_get.n_val) << 24); /* 24'b, BIT[32:25] */ -+ hdmi_reg_mode_en_set(id, (phy_clk->tmds_cfg.tmds_clk > TMDS_CLOCK_340M) ? 0x1 : 0x0); -+ printk("tmds_clk: %u\n", phy_clk->tmds_cfg.tmds_clk); -+ /* FDIV init */ -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 0); -+ hdmi_reg_en_mod_set(id, 0); -+ hdmi_reg_en_sdm_set(id, 0); -+ hdmi_reg_init_set(id, 1); -+ /* delay 1us */ -+ udelay(1); -+ hdmi_reg_init_set(id, 0); -+ hdmi_reg_en_ctrl_set(id, 0); -+ hdmi_reg_en_mod_set(id, 0); -+ hdmi_reg_en_sdm_set(id, 0); -+ -+ return; -+} -+ -+static void phy_hw_clock_set(unsigned int id, const phy_clk_set *phy_clk) -+{ -+ if (phy_clk->tmds_cfg.mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { -+ phy_hw_clock_tmds_set(id, phy_clk); -+ } else { -+ printk("mode err.\n"); -+ } -+ -+ return; -+} -+ -+static int phy_tmds_clk_set(unsigned int id, const hdmi_phy_tmds_cfg *tmds_cfg, phy_clk_set *phy_clk) -+{ -+ int ret; -+ phy_clk->tmds_cfg.mode_cfg = tmds_cfg->mode_cfg; -+ phy_clk->tmds_cfg.deep_color = tmds_cfg->deep_color; -+ phy_clk->tmds_cfg.pixel_clk = tmds_cfg->pixel_clk; -+ phy_clk->tmds_cfg.tmds_clk = tmds_cfg->tmds_clk; -+ -+ if (tmds_cfg->mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { -+ /* calculate ll parameter */ -+ ret = hal_hdmi_clk_set_para_get(id, phy_clk); -+ if (ret != 0) { -+ printk("hal_hdmi_clk_set_para_get.\n"); -+ return -1; -+ } -+ /* pll feedback clock divider */ -+ ret = phy_hw_fractional_mnx_get(phy_clk->tmds_cfg.tmds_clk, phy_clk->tmds_cfg.pixel_clk, phy_clk->tmds_cfg.deep_color); -+ if (ret != 0) { -+ printk("phy_hw_fractional_mnx_get.\n"); -+ return -1; -+ } -+ } -+ phy_hw_clock_set(id, phy_clk); -+ -+ return 0; -+} -+ -+static void phy_hw_read_stb1_byte(unsigned int id, unsigned int cs, aphy_offset_addr aphy_offset, unsigned char *rdata) -+{ -+ /* CS reset */ -+ hdmi_reg_stb_cs_en_set(id, 0x00); -+ /* WR reset */ -+ hdmi_reg_stb_wen_set(id, 0); -+ /* ADDR set */ -+ hdmi_reg_stb_addr_set(id, aphy_offset); -+ udelay(1); -+ /* CS set */ -+ hdmi_reg_stb_cs_en_set(id, cs); -+ udelay(1); -+ /* RDATA read */ -+ *rdata = (unsigned char)hdmi_reg_stb_rdata_get(id); -+ /* CS reset */ -+ hdmi_reg_stb_cs_en_set(id, 0x00); -+ -+ return; -+} -+ -+static void phy_hw_write_stb(unsigned int id, write_param param) -+{ -+ unsigned char rdata = 0; -+ unsigned int mask_value, write_value; -+ if ((param.msb == 0x7) && (param.lsb == 0x0)) { -+ phy_hw_write_stb1_byte(id, param.cs, param.aphy_offset, param.wdata); -+ } else { -+ if (param.cs == (APHY_CS_012 | APHY_CS_3)) { -+ phy_hw_read_stb1_byte(id, APHY_CS_0, param.aphy_offset, &rdata); -+ } else if (param.cs == APHY_CS_4567) { -+ phy_hw_read_stb1_byte(id, APHY_CS_4, param.aphy_offset, &rdata); -+ } else { -+ phy_hw_read_stb1_byte(id, param.cs, param.aphy_offset, &rdata); -+ } -+ -+ mask_value = (0xff >> (0x7 - param.msb)) & (0xff << param.lsb); -+ write_value = (~mask_value & rdata) + (mask_value & (param.wdata << param.lsb)); -+ phy_hw_write_stb1_byte(id, param.cs, param.aphy_offset, write_value); -+ } -+ -+ return; -+} -+ -+static int phy_hw_post_set_up(unsigned int id, const hdmi_phy_tmds_cfg *tmds_cfg) -+{ -+ write_param param = {0}; -+ (void*)tmds_cfg; -+ hdmi_reg_hsset_set(id, 3); /* 3, HS FIFO enable & HS data selection: External(HS Link) */ -+ hdmi_reg_pr_en_h20_set(id, 1); -+ hdmi_reg_enable_h20_set(id, 1); -+ hdmi_reg_txfifoset0_unused_set(id, 0); -+ -+ hdmi_reg_ch_out_sel_set(id, 0x0); -+ param.cs = APHY_CS_0; -+ param.aphy_offset = APHY_OFFSET_0; -+ param.msb = 1; -+ param.lsb = 1; -+ param.wdata = 0x0; -+ phy_hw_write_stb(id, param); -+ param.cs = APHY_CS_1; -+ phy_hw_write_stb(id, param); -+ param.cs = APHY_CS_2; -+ phy_hw_write_stb(id, param); -+ param.cs = APHY_CS_3; -+ phy_hw_write_stb(id, param); -+ msleep(1); -+ param.cs = APHY_CS_0; -+ param.wdata = 0x1; -+ phy_hw_write_stb(id, param); -+ param.cs = APHY_CS_1; -+ phy_hw_write_stb(id, param); -+ param.cs = APHY_CS_2; -+ phy_hw_write_stb(id, param); -+ param.cs = APHY_CS_3; -+ phy_hw_write_stb(id, param); -+ -+ return 0; -+} -+ -+int hal_hdmi_phy_oe_set(unsigned int id, bool enable) -+{ -+ bool oe_en; -+ unsigned int oe_cfg, mask; -+ oe_en = enable; -+ g_hdmi_phy_info[id].oe_enable = oe_en; -+ -+ mask = CFG_HDMI_OE_CH3_M | CFG_HDMI_OE_CH2_M | CFG_HDMI_OE_CH1_M | CFG_HDMI_OE_CH0_M; -+ oe_cfg = cfg_hdmi_oe_ch3((unsigned int)oe_en) | cfg_hdmi_oe_ch2((unsigned int)oe_en) | -+ cfg_hdmi_oe_ch1((unsigned int)oe_en) | cfg_hdmi_oe_ch0((unsigned int)oe_en); -+ hdmi_write_mask(id, HDMI_OE_CFG, oe_cfg, mask); -+ -+ return 0; -+} -+ -+static unsigned int hdmi_read_mask(unsigned int id, unsigned int offset, unsigned int mask) -+{ -+ unsigned int tmp; -+ char *reg = NULL; -+ -+ reg = (char *)hdmi_reg_tx_get_phy_addr(id); -+ if (reg == NULL) { -+ hdmi_warn("phy addr is null!\n"); -+ return -1; -+ } -+ reg += offset; -+ tmp = *(volatile unsigned int *)(reg); -+ tmp = (tmp & mask); -+ -+ return tmp; -+} -+ -+int hdmi_phy_oe_get(unsigned int id) -+{ -+ unsigned int oe_status; -+ int enable = 0; -+ -+ -+ if (hdmi_reg_resetn_get(id) == 0) { -+ printk("phy is reset now, OE disable.\n"); -+ enable = 0; -+ return enable; -+ } -+ -+ oe_status = hdmi_read_mask(id, HDMI_OE_CFG, -+ CFG_HDMI_OE_CH0_M | CFG_HDMI_OE_CH1_M | CFG_HDMI_OE_CH2_M | CFG_HDMI_OE_CH3_M); -+ if (oe_status == 0xF) { -+ enable = 1; -+ } else { -+ enable = 0; -+ } -+ printk("%s,enable:%d OK\n",__func__,enable); -+ return enable; -+} -+ -+static void smart_hdmi_config_phy(struct smart_hdmi *hdmi) -+{ -+ hdmi_tmds_mode tmds_mode; -+ hdmi_phy_tmds_cfg cfg = {0}; -+ hdmi_phy_ssc_cfg hdmi_ssc_cfg = {0}; -+ int ret; -+ unsigned int pixel_clk = 0; -+ phy_clk_set phy_clk = {0}; -+ -+ /* reset: clear all the aphy register */ -+ phy_hw_reset_release(0); -+ /* input clock check: to configurate dphy source clock detection module */ -+ if (phy_hw_input_clock_check(0, &pixel_clk) != 0) { -+ printk("input clock unstable\n"); -+ } -+ -+ cfg.deep_color = HDMI_DEEP_COLOR_24BIT;//HI_HDMI_DEEP_COLOR_24BIT -+ cfg.emi_enable = 0; -+ cfg.mode_cfg = HDMI_PHY_MODE_CFG_TMDS; -+ cfg.pixel_clk = hdmi->tmdsclk ; -+ cfg.tmds_clk = hdmi->tmdsclk ; -+ cfg.trace_len = HDMI_TRACE_DEFAULT; -+ printk("TMDS mode: %u, pixel_clk: %u, tmds_clk: %u, deep_color: %u, trace_len: %u\n", cfg.mode_cfg, -+ cfg.pixel_clk, cfg.tmds_clk, cfg.deep_color, cfg.trace_len); -+ /* initial: finish aphy, dphy configuration, configurate the register no change with standard */ -+ if (cfg.mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { -+ phy_hw_init_tmds(0, &cfg); -+ } -+ ret = phy_tmds_clk_set(0, &cfg, &phy_clk); -+ if (ret != 0) { -+ printk("phy tmds clk set fail.\n"); -+ return; -+ } -+ hdmi_ssc_cfg.phy_ssc.ssc_enable = cfg.emi_enable; -+ hdmi_ssc_cfg.pix_clk = cfg.pixel_clk; -+ hdmi_ssc_cfg.tmds_clk = cfg.tmds_clk; -+ hdmi_ssc_cfg.deep_color = cfg.deep_color; -+ /* calculate spread spectrum */ -+ if (cfg.mode_cfg == HDMI_PHY_MODE_CFG_TMDS) { -+ hal_hdmi_phy_ssc_set(0, &hdmi_ssc_cfg); -+ } -+ -+ /* initial: index */ -+ ret = phy_tmds_spec_set(0, &cfg); -+ if (ret != 0) { -+ printk("phy tmds spec set fail.\n"); -+ return; -+ } -+ -+ /* data path enable */ -+ phy_hw_post_set_up(0, &cfg); -+ hdmi_phy_oe_get(0); -+ memcpy(&g_hdmi_phy_info[0].tmds_cfg, &cfg, sizeof(hdmi_phy_tmds_cfg)); -+} -+ -+void hdmi_reg_write(volatile unsigned int *reg_addr, unsigned int value) -+{ -+ if (reg_addr != NULL) { -+ *(volatile unsigned int *)reg_addr = value; -+ } -+} -+ -+unsigned int hdmi_reg_read(volatile unsigned int *reg_addr) -+{ -+ if (reg_addr == NULL) { -+ return 0; -+ } -+ return *(volatile unsigned int *)reg_addr; -+} -+ -+ -+static void hdmi_cbar_enable(bool enable) -+{ -+ unsigned int *reg_addr = NULL; -+ unsigned int reg_value; -+ reg_addr = (unsigned int *)ioremap(HDMI_COLOR_BAR_BASE, 4); /* 4: register size */ -+ if (*reg_addr == NULL) { -+ return; -+ } -+ reg_value = hdmi_reg_read(reg_addr); -+ -+ if (enable) { -+ reg_value |= HDMI_COLOR_BAR_MASK; -+ reg_value |= HDMI_COLOR_BAR_UPDATE_MASK; -+ } else { -+ reg_value &= ~HDMI_COLOR_BAR_MASK; -+ reg_value |= HDMI_COLOR_BAR_UPDATE_MASK; -+ } -+ hdmi_reg_write(reg_addr, reg_value); -+ iounmap((void *)reg_addr); /* 4: register size */ -+} -+ -+int hal_hdmi_ctrl_data_reset(hdmi_device_id hdmi, bool debug_mode, unsigned int delay_ms) -+{ -+ static unsigned int delay; -+ -+ hdmi_reg_tx_acr_srst_req_set(1); -+ hdmi_reg_tx_afifo_srst_req_set(1); -+ hdmi_reg_tx_aud_srst_req_set(1); -+ hdmi_reg_tx_hdmi_srst_req_set(1); -+ udelay(CTRL_REAET_WAIT_TIME); -+ hdmi_reg_tx_acr_srst_req_set(0); -+ hdmi_reg_tx_afifo_srst_req_set(0); -+ hdmi_reg_tx_aud_srst_req_set(0); -+ /* TOP rst: will also pack_fifo_ctrl reg_fifo_manu_rst */ -+ hdmi_reg_tx_hdmi_srst_req_set(0); -+ -+ if (debug_mode) { -+ delay = delay_ms; -+ } -+ -+ if (delay) { -+ msleep(delay); -+ printk("data_rst %u ms\n", delay); -+ } -+ -+ return 0; -+} -+ -+int hal_hdmi_ctrl_tmds_stable_get(hdmi_device_id hdmi, bool *stable) -+{ -+ *stable = hdmi_reg_pclk2tclk_stable_get() ? 1 : 0; -+ return 0; -+} -+ -+static void hal_hdmi_ctrl_reset(void) -+{ -+ unsigned int i; -+ bool tmds_stable = 0; -+ bool output = 0; -+ -+ output = hdmi_phy_oe_get(0); -+ if (output == 1) { -+ printk("oe enable, do not reset!\n"); -+ return; -+ } -+ -+ -+ hal_hdmi_ctrl_data_reset(0, 0, 0); -+ -+ for (i = 0; (!tmds_stable) && (i < CTRL_RESET_WAIT); i++) { -+ msleep(1); -+ hal_hdmi_ctrl_tmds_stable_get(0, &tmds_stable); -+ } -+ -+ printk("wait %ums, tmds_stable=%u\n", i, tmds_stable); -+ -+ return; -+} -+ -+static void ctrl_video_mute_set(bool enable) -+{ -+ unsigned int data_value; -+ enum hdmi_colorspace in_color_space = HDMI_COLORSPACE_RGB; -+ enum hdmi_colorspace out_color_space = HDMI_COLORSPACE_RGB; -+ -+ -+ data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_R : CTRL_BLACK_DATA_YUV_CR; -+ hdmi_reg_solid_pattern_cr_set((unsigned short)data_value); -+ -+ data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_G : CTRL_BLACK_DATA_YUV_Y; -+ hdmi_reg_solid_pattern_y_set((unsigned short)data_value); -+ -+ data_value = (in_color_space == HDMI_COLORSPACE_RGB) ? CTRL_BLACK_DATA_RGB_B : CTRL_BLACK_DATA_YUV_CB; -+ hdmi_reg_solid_pattern_cb_set((unsigned short)data_value); -+ -+ hdmi_reg_video_blank_en_set((unsigned char )enable); -+ hdmi_reg_solid_pattern_en_set((unsigned char )enable); -+ -+ return; -+} -+ -+static int smart_hdmi_setup(struct smart_hdmi *hdmi, -+ struct drm_display_mode *mode) -+{ -+ struct drm_display_info *display = &hdmi->connector.display_info; -+ hdmi_tmds_mode tmds_mode; -+ unsigned int pixel_clk = 0; -+ hdmi->hdmi_data.vic = drm_match_cea_mode(mode); -+ -+ -+ if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || -+ hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || -+ hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || -+ hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) -+ hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; -+ else -+ hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; -+ -+ hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; -+ -+ -+ hdmi->tmdsclk = mode->clock; -+ -+ /* Input video mode is RGB 24 bit. Use external data enable signal. */ -+ smart_hdmi_config_video_timing(hdmi, mode); -+ if (display->is_hdmi) { -+ smart_hdmi_config_avi(hdmi, mode); -+ } -+ -+ smart_hdmi_config_video_csc(hdmi); -+ -+ smart_hdmi_config_phy(hdmi); -+ //drv_hdmi_start -+ drv_hdmi_low_power_set(0); -+ //hal_hdmi_tmds_mode_set -+ if (hdmi->tmdsclk > HDMI_EDID_MAX_HDMI14_TMDS_RATE) { -+ tmds_mode = HDMI_TMDS_MODE_HDMI_2_0; -+ } else { -+ tmds_mode = HDMI_TMDS_MODE_HDMI_1_4; -+ } -+ ctrl_tmds_mode_set(tmds_mode); -+ //hal_hdmi_ctrl_reset -+ hal_hdmi_ctrl_reset(); -+ -+ //hdmi_phy_output_enable(hdmi_dev, 1); -+ hal_hdmi_phy_oe_set(0,1); -+ hdmi_phy_oe_get(0); -+ ctrl_video_mute_set(0); -+ -+ -+ //hdmi_cbar_enable(1); -+ return 0; -+} -+ -+static void -+smart_hdmi_encoder_mode_set(struct drm_encoder *encoder, -+ struct drm_display_mode *mode, -+ struct drm_display_mode *adj_mode) -+{ -+ struct smart_hdmi *hdmi = encoder_to_smart_hdmi(encoder); -+ -+ /* Store the display mode for plugin/DPMS poweron events. */ -+ drm_mode_copy(&hdmi->previous_mode, adj_mode); -+} -+ -+static void smart_hdmi_encoder_enable(struct drm_encoder *encoder) -+{ -+ struct smart_hdmi *hdmi = encoder_to_smart_hdmi(encoder); -+ -+ smart_hdmi_setup(hdmi, &hdmi->previous_mode); -+} -+ -+static void smart_hdmi_encoder_disable(struct drm_encoder *encoder) -+{ -+ struct smart_hdmi *hdmi = encoder_to_smart_hdmi(encoder); -+ -+ -+} -+ -+static bool -+smart_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, -+ const struct drm_display_mode *mode, -+ struct drm_display_mode *adj_mode) -+{ -+ -+ return true; -+} -+ -+static int -+smart_hdmi_encoder_atomic_check(struct drm_encoder *encoder, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct smart_crtc_state *s = to_smart_crtc_state(crtc_state); -+ -+ return 0; -+} -+ -+static const -+struct drm_encoder_helper_funcs smart_hdmi_encoder_helper_funcs = { -+ .enable = smart_hdmi_encoder_enable, -+ .disable = smart_hdmi_encoder_disable, -+ .mode_fixup = smart_hdmi_encoder_mode_fixup, -+ .mode_set = smart_hdmi_encoder_mode_set, -+ .atomic_check = smart_hdmi_encoder_atomic_check, -+}; -+ -+static enum drm_connector_status -+smart_hdmi_connector_detect(struct drm_connector *connector, bool force) -+{ -+ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); -+ if(ctrl_hpd_get()) { -+ return connector_status_connected; -+ } -+ return connector_status_disconnected; -+} -+ -+static int ddc_access_enable_wait(unsigned int timeout) -+{ -+ int ret = 0; -+ unsigned int tmp_time = 0; -+ -+ hdmi_reg_cpu_ddc_req_set(1); -+ -+ while (!hdmi_reg_cpu_ddc_req_ack_get()) { -+ msleep(1); -+ tmp_time++; -+ if (tmp_time > timeout) { -+ ret = -1; -+ break; -+ } -+ } -+ return ret; -+} -+static int ddc_scl_wait(unsigned int timeout) -+{ -+ int ret = 0; -+ unsigned int tmp_time = 0; -+ -+ while (!hdmi_reg_ddc_scl_st_get()) { -+ msleep(1); -+ tmp_time += 1; -+ if (tmp_time > timeout) { -+ ret = -1; -+ break; -+ } -+ } -+ return ret; -+} -+ -+static int ddc_sda_wait(unsigned int timeout) -+{ -+ unsigned int tmp_timeout = 0; -+ int ret = 0; -+ if (!hdmi_reg_ddc_sda_st_get()) { -+ hdmi_reg_dcc_man_en_set(1); -+ while ((!hdmi_reg_ddc_sda_st_get()) && tmp_timeout < timeout) { -+ tmp_timeout++; -+ -+ /* pull scl high */ -+ hdmi_reg_ddc_scl_oen_set(1); -+ udelay(DDC_DEFAULT_DELAY); -+ /* pull scl low */ -+ hdmi_reg_ddc_scl_oen_set(0); -+ udelay(DDC_DEFAULT_DELAY); -+ } -+ -+ /* STOP contition */ -+ if (tmp_timeout < timeout && (hdmi_reg_ddc_sda_st_get())) { -+ /* pull sda low */ -+ hdmi_reg_ddc_sda_oen_set(0); -+ udelay(DDC_DEFAULT_DELAY); -+ /* pull scl high */ -+ hdmi_reg_ddc_scl_oen_set(1); -+ udelay(DDC_DEFAULT_DELAY); -+ /* pull sda high */ -+ hdmi_reg_ddc_sda_oen_set(1); -+ udelay(DDC_DEFAULT_DELAY); -+ printk("deadlock clear success\n"); -+ ret = 0; -+ } else { -+ printk("deadlock clear fail\n"); -+ ret = -1; -+ } -+ hdmi_reg_dcc_man_en_set(0); -+ } -+ -+ return ret; -+} -+ -+static int ddc_cmd_issue(unsigned char offset_data) -+{ -+ unsigned short data_size; -+ unsigned char slave_addr, segment, offset; -+ segment = 0; -+ offset = offset_data; -+ slave_addr = DDC_EDID_SALVE_ADDR; -+ data_size = HDMI_EDID_BLOCK_SIZE; -+ hdmi_reg_pwd_mst_cmd_set(DDC_CMD_FIFO_CLR); -+ hdmi_reg_pwd_slave_addr_set(slave_addr); -+ hdmi_reg_pwd_slave_seg_set(segment); -+ hdmi_reg_pwd_slave_offset_set(offset); -+ hdmi_reg_pwd_data_out_cnt_set(data_size); -+ udelay(DDC_DEFAULT_DELAY); -+ hdmi_reg_pwd_mst_cmd_set(DDC_MODE_READ_MUTIL_NO_ACK); -+ return 0; -+} -+ -+static int ddc_read(unsigned char *pdata) -+{ -+ unsigned int len; -+ ddc_func_type type; -+ unsigned char *data = NULL; -+ unsigned int i, retry, data_size; -+ ktime_t start_time, end_time; -+ unsigned int elapsed_ms = 0; -+ data = pdata; -+ type = DDC_FUNC_TYPE_EDID; -+ len = HDMI_EDID_BLOCK_SIZE; -+ retry = DDC_DEFAULT_TIMEOUT_SDA; -+ -+ for (data_size = 0; data_size < len; data_size++, data++) { -+ -+ start_time = ktime_get(); -+ end_time = start_time; -+ elapsed_ms = ktime_to_ns(ktime_sub(end_time, start_time)); -+ elapsed_ms = elapsed_ms / NSEC_PER_MSEC; -+ /* when read-fifo empty, every byte wait a max timeout */ -+ for (i = 0; -+ ((i < retry) && (hdmi_reg_pwd_fifo_empty_get() || (hdmi_reg_pwd_fifo_data_out_get() == 0))) && -+ (elapsed_ms <= DDC_DEFAULT_RETRY_TIMEOUT_ISSUE); -+ i++) { -+ /* wait ddc status update after DDC cmd set. */ -+ msleep(1); -+ if (hdmi_reg_ddc_i2c_no_ack_get() || hdmi_reg_ddc_i2c_bus_low_get()) { -+ hdmi_reg_pwd_mst_cmd_set(DDC_CMD_MASTER_ABORT); -+ printk("DDC status error!\n"); -+ return -1; -+ } -+ -+ end_time = ktime_get(); -+ } -+ -+ elapsed_ms = ktime_to_ns(ktime_sub(end_time, start_time)); -+ elapsed_ms = elapsed_ms / NSEC_PER_MSEC; -+ if ((i >= retry) || (elapsed_ms > DDC_DEFAULT_RETRY_TIMEOUT_ISSUE)) { -+ if (type != DDC_FUNC_TYPE_SCDC) { -+ printk("read fifo retry=%u ms, size=%u, timeout:%u!\n", -+ retry, len, elapsed_ms); -+ } else { -+ printk("read fifo retry=%u ms, size=%u, timeout:%u!\n", -+ retry, len, elapsed_ms); -+ } -+ return -1; -+ } -+ if (data != NULL) { -+ *data = hdmi_reg_rdata_pwd_fifo_data_out_get(); -+ /* -+ * the fifo status is not refresh promptly, -+ * so re-read the fifo status and delay 1us if the fifo is empty, -+ * wait the data ready. it must delay 1us after read fifo data. -+ */ -+ udelay(1); -+ } else { -+ printk("edid &data[%u]=null\n", data_size); -+ return -1; -+ } -+ } -+ -+ return data_size; -+} -+ -+static int ddc_in_prog_wait(unsigned int timeout) -+{ -+ int ret = 0; -+ unsigned int tmp_time = 0; -+ while (hdmi_reg_pwd_i2c_in_prog_get()) { -+ msleep(1); -+ tmp_time += 1; -+ if (tmp_time > timeout) { -+ ret = -1; -+ break; -+ } -+ } -+ -+ return ret; -+} -+ -+static int ddc_access_disable_wait(unsigned int timeout) -+{ -+ int ret = 0; -+ unsigned int tmp_time = 0; -+ hdmi_reg_cpu_ddc_req_set(0); -+ while (hdmi_reg_cpu_ddc_req_ack_get()) { -+ msleep(1); -+ tmp_time += 1; -+ if (tmp_time > timeout) { -+ ret = -1; -+ break; -+ } -+ } -+ return ret; -+} -+ -+static int smart_hdmi_connector_get_modes(struct drm_connector *connector) -+{ -+ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); -+ struct edid *edid; -+ int ret = 0; -+ int data_size = 0; -+ unsigned char edid_data[HDMI_EDID_BLOCK_SIZE*2] = {0}; -+ -+ spin_lock(&hdmi->reg_lock); -+ if (ddc_access_enable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { -+ printk("wait access bus timeout!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ /* scl check */ -+ if (ddc_scl_wait(DDC_DEFAULT_TIMEOUT_SCL) != 0) { -+ printk("wait scl timeout!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ /* sda check */ -+ if (ddc_sda_wait(DDC_DEFAULT_TIMEOUT_SDA) != 0) { -+ printk("wait sda timeout!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ /* issue command */ -+ if (ddc_cmd_issue(0) != 0) { -+ printk("command issue fail!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ data_size = ddc_read(&edid_data[0]); -+ -+ if (ddc_in_prog_wait(DDC_DEFAULT_TIMEOUT_IN_PROG) != 0) { -+ printk("wait in prog timeout!\n"); -+ } -+ -+ if (ddc_access_disable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { -+ printk("wait access disable timeout!\n"); -+ } -+ -+ // BLOCK 1 -+ -+ if (ddc_access_enable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { -+ printk("wait access bus timeout!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ /* scl check */ -+ if (ddc_scl_wait(DDC_DEFAULT_TIMEOUT_SCL) != 0) { -+ printk("wait scl timeout!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ /* sda check */ -+ if (ddc_sda_wait(DDC_DEFAULT_TIMEOUT_SDA) != 0) { -+ printk("wait sda timeout!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ /* issue command */ -+ if (ddc_cmd_issue(HDMI_EDID_BLOCK_SIZE) != 0) { -+ printk("command issue fail!\n"); -+ spin_unlock(&hdmi->reg_lock); -+ return ret; -+ } -+ -+ data_size = ddc_read(&edid_data[HDMI_EDID_BLOCK_SIZE]); -+ if (ddc_in_prog_wait(DDC_DEFAULT_TIMEOUT_IN_PROG) != 0) { -+ printk("wait in prog timeout!\n"); -+ } -+ if (ddc_access_disable_wait(DDC_DEFAULT_TIMEOUT_ACCESS) != 0) { -+ printk("wait access disable timeout!\n"); -+ } -+ spin_unlock(&hdmi->reg_lock); -+ -+ edid = kmalloc(HDMI_EDID_BLOCK_SIZE * 2, GFP_KERNEL); -+ memcpy(edid, (struct edid *)edid_data, HDMI_EDID_BLOCK_SIZE * 2); -+ if (!drm_edid_is_valid(edid)) { -+ printk("Invalid EDID data read from registers\n"); -+ } else { -+ printk("EDID data read from registers\n"); -+ } -+ -+ if (edid) { -+ hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid); -+ hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid); -+ drm_connector_update_edid_property(connector, edid); -+ ret = drm_add_edid_modes(connector, edid); -+ kfree(edid); -+ } -+ return ret; -+} -+ -+static enum drm_mode_status -+smart_hdmi_connector_mode_valid(struct drm_connector *connector, -+ struct drm_display_mode *mode) -+{ -+ struct hdmi_video_def *cfg = &g_cea_video_codes_des[0]; -+ int pclk = mode->clock; -+ bool valid = false; -+ int i; -+ -+ for (i = 0; cfg[i].pixclk != 0; i++) { -+ if (pclk == cfg[i].pixclk) { -+ valid = true; -+ break; -+ } -+ } -+ return (valid) ? MODE_OK : MODE_BAD; -+} -+ -+static struct drm_encoder * -+smart_hdmi_connector_best_encoder(struct drm_connector *connector) -+{ -+ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); -+ return &hdmi->encoder.encoder; -+} -+ -+static int -+smart_hdmi_probe_single_connector_modes(struct drm_connector *connector, -+ uint32_t maxX, uint32_t maxY) -+{ -+ struct smart_hdmi *hdmi = connector_to_smart_hdmi(connector); -+ int ret; -+ -+ ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY); -+ return ret; -+} -+ -+static void smart_hdmi_connector_destroy(struct drm_connector *connector) -+{ -+ -+ drm_connector_unregister(connector); -+ drm_connector_cleanup(connector); -+} -+ -+static const struct drm_connector_funcs smart_hdmi_connector_funcs = { -+ .fill_modes = smart_hdmi_probe_single_connector_modes, -+ .detect = smart_hdmi_connector_detect, -+ .destroy = smart_hdmi_connector_destroy, -+ .reset = drm_atomic_helper_connector_reset, -+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -+}; -+ -+static const -+struct drm_connector_helper_funcs smart_hdmi_connector_helper_funcs = { -+ .get_modes = smart_hdmi_connector_get_modes, -+ .mode_valid = smart_hdmi_connector_mode_valid, -+ .best_encoder = smart_hdmi_connector_best_encoder, -+}; -+ -+static int -+smart_hdmi_register(struct drm_device *drm, struct smart_hdmi *hdmi) -+{ -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; -+ struct device *dev = hdmi->dev; -+ int ret; -+ -+ if (!drm || !hdmi) -+ return -EINVAL; -+ -+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ if (ret) { -+ dev_err(dev, "failed to init simple encoder: %d\n", ret); -+ return ret; -+ } -+ -+ drm_encoder_helper_add(encoder, &smart_hdmi_encoder_helper_funcs); -+ -+ -+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ -+ if (!encoder->possible_crtcs) { -+ dev_warn(dev, "No CRTCs found for HDMI encoder via DT, using fallback\n"); -+ if (drm->mode_config.num_crtc > 0) { -+ encoder->possible_crtcs = 1; // 绑定到crtc0 -+ } else { -+ dev_err(dev, "No fallback CRTC available\n"); -+ return -ENODEV; -+ } -+ } -+ -+ -+ /* 4. 配置连接器并初始�? */ -+ hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; -+ drm_connector_helper_add(&hdmi->connector, -+ &smart_hdmi_connector_helper_funcs); -+ -+ ret = drm_connector_init(drm, &hdmi->connector, -+ &smart_hdmi_connector_funcs, -+ DRM_MODE_CONNECTOR_HDMIA); -+ if (ret) { -+ dev_err(dev, "failed to init connector: %d\n", ret); -+ return ret; -+ } -+ -+ /* 5. 将连接器附加到编码器 */ -+ ret = drm_connector_attach_encoder(&hdmi->connector, encoder); -+ if (ret) { -+ dev_err(dev, "failed to attach connector to encoder: %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static bool ctrl_hpd_get(void) -+{ -+ int hot_plug; -+ bool hpd; -+ -+ hot_plug = hdmi_reg_hotplug_state_get(); -+ if (hdmi_reg_hpd_polarity_ctl_get() > 0) { -+ hpd = (hot_plug > 0) ? 0 : 1; -+ } else { -+ hpd = (hot_plug > 0) ? 1 : 0; -+ } -+ return hpd; -+} -+ -+ -+static bool ctrl_rsen_get(void) -+{ -+ if (hdmi_reg_phy_rx_sense_get()) { -+ return 1; -+ } -+ return 0; -+} -+ -+static void ctrl_hpd_intr_enable(bool enable) -+{ -+ hdmi_reg_aon_intr_stat0_set(1); -+ hdmi_reg_aon_intr_mask0_set(enable); -+ return; -+} -+static void phy_default_spec_set(void) -+{ -+ unsigned char i; -+ hdmi_hw_spec *spec = NULL; -+ const struct tmds_spec_params *tmp = NULL; -+ hdmi_trace_len tmp_trace; -+ -+ for (tmp_trace = HDMI_TRACE_LEN_0; tmp_trace <= HDMI_TRACE_DEFAULT; tmp_trace++) { -+ spec = &g_hdmi_phy_info[0].hw_spec[tmp_trace]; -+ phy_hw_tmds_spec_trace_len_get(&tmp, tmp_trace); -+ for (i = 0; i < HDMI_HW_PARAM_NUM; i++) { -+ spec->hw_param[i].i_de_main_clk = tmp[i].clock.dphy.drv_post1; -+ spec->hw_param[i].i_de_main_data = tmp[i].data.dphy.drv_post1; -+ spec->hw_param[i].i_main_clk = tmp[i].clock.dphy.drv_main; -+ spec->hw_param[i].i_main_data = tmp[i].data.dphy.drv_main; -+ } -+ } -+ -+ return; -+} -+ -+static int smart_hdmi_bind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct drm_device *drm = data; -+ struct smart_hdmi *hdmi; -+ int ret = 0; -+ static char *hdmi0_base; -+ static char *phy_base; -+ struct resource *res; -+ -+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return -ENOMEM; -+ -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,"hdmi0"); -+ if (!res) -+ return -ENODEV; -+ -+ hdmi0_base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(hdmi0_base)) { -+ dev_err(&pdev->dev, "Failed to map HDMI controller registers\n"); -+ return PTR_ERR(hdmi0_base); -+ } -+ -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); -+ if (!res) { -+ dev_err(&pdev->dev, "Failed to get HDMI PHY resource\n"); -+ return -ENODEV; -+ } -+ -+ phy_base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(phy_base)) { -+ dev_err(&pdev->dev, "Failed to map HDMI PHY registers\n"); -+ return PTR_ERR(phy_base); -+ } -+ -+ //hal_hdmi_phy_init -+ hdmi_reg_tx_phy_init(0,phy_base); -+ phy_default_spec_set(); -+ -+ ret += hdmi_reg_crg_init(); -+ ret += hdmi_reg_aon_regs_init(hdmi0_base); -+ ret += hdmi_reg_audio_path_regs_init(hdmi0_base); -+ /* this functions will not be used at BVT */ -+ ret += hdmi_reg_tx_ctrl_regs_init(hdmi0_base); -+ ret += hdmi_reg_tx_hdmi_regs_init(hdmi0_base); -+ ret += hdmi_reg_video_path_regs_init(hdmi0_base); -+ -+ -+ //drv_hdmi_prod_crg_gate_set -+ drv_hdmi_prod_crg_gate_set(1); -+ //hal_hdmi_mach_start --> ctrl_hpd_intr_enable -+ ctrl_hpd_intr_enable(1); -+ -+ // hdmi_reg_video_blank_en_set(1); -+ -+ //hal_hdmi_phy_oe_get -+ hdmi_phy_oe_get(0); -+ -+ //drv_hdmi_prod_io_cfg_set -+ drv_hdmi_prod_crg_init(); -+ -+ //hal_hdmi_hot_plug_status_get -+ ctrl_hpd_get(); -+ ctrl_rsen_get(); -+ -+ ctrl_hpd_get(); -+ ctrl_rsen_get(); -+ -+ if(hdmi_reg_aon_intr_stat0_get()) { -+ hdmi_reg_aon_intr_stat0_set(1); -+ ctrl_hpd_get(); -+ } -+ -+ if(hdmi_reg_aon_intr_stat1_get()) { -+ hdmi_reg_aon_intr_stat1_set(1); -+ ctrl_rsen_get(); -+ } -+ hdmi->dev = dev; -+ hdmi->drm_dev = drm; -+ -+ ret = smart_hdmi_register(drm, hdmi); -+ if (ret) -+ goto err_cleanup_hdmi; -+ -+ dev_set_drvdata(dev, hdmi); -+ return 0; -+ -+err_cleanup_hdmi: -+ hdmi->connector.funcs->destroy(&hdmi->connector); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); -+ return ret; -+} -+ -+static void smart_hdmi_unbind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct smart_hdmi *hdmi = dev_get_drvdata(dev); -+ hdmi->connector.funcs->destroy(&hdmi->connector); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); -+} -+ -+static const struct component_ops smart_hdmi_ops = { -+ .bind = smart_hdmi_bind, -+ .unbind = smart_hdmi_unbind, -+}; -+ -+static int smart_hdmi_probe(struct platform_device *pdev) -+{ -+ return component_add(&pdev->dev, &smart_hdmi_ops); -+} -+ -+static void smart_hdmi_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &smart_hdmi_ops); -+} -+ -+static const struct of_device_id smart_hdmi_dt_ids[] = { -+ { .compatible = "vendor,hdmi" }, -+ { /* sentinel */ }, -+}; -+MODULE_DEVICE_TABLE(of, smart_hdmi_dt_ids); -+ -+struct platform_driver smart_hdmi_driver = { -+ .probe = smart_hdmi_probe, -+ .remove_new = smart_hdmi_remove, -+ .driver = { -+ .name = "hi3403v100-hdmi", -+ .of_match_table = smart_hdmi_dt_ids, -+ }, -+}; -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("runkaihong"); -+MODULE_DESCRIPTION("HI3403V100 HDMI for platform/SoC device"); -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.h b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.h -new file mode 100755 -index 0000000..39587fc ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_hdmi.h -@@ -0,0 +1,1329 @@ -+#ifndef __HI3403V100_HDMI_H__ -+#define __HI3403V100_HDMI_H__ -+ -+#include "hdmi_reg_aon.h" -+#include "hdmi_reg_audio_path.h" -+#include "hdmi_reg_ctrl.h" -+#include "hdmi_reg_tx.h" -+#include "hdmi_reg_video_path.h" -+#include "hdmi_reg_crg.h" -+#include "hdmi_product_define.h" -+#include "hdmi_reg_dphy.h" -+ -+#define DDC_SEGMENT_ADDR 0x30 -+#define HDMI_SCL_RATE (50 * 1000) -+#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x1F -+ -+#define HDMI_OE_CFG 0x520 -+#define cfg_oe_sync_en(x) (((x) & 0x1) << 4) -+#define CFG_OE_SYNC_EN_M (1 << 4) -+#define cfg_hdmi_oe_ch3(x) (((x) & 0x1) << 3) -+#define CFG_HDMI_OE_CH3_M (1 << 3) -+#define cfg_hdmi_oe_ch2(x) (((x) & 0x1) << 2) -+#define CFG_HDMI_OE_CH2_M (1 << 2) -+#define cfg_hdmi_oe_ch1(x) (((x) & 0x1) << 1) -+#define CFG_HDMI_OE_CH1_M (1 << 1) -+#define cfg_hdmi_oe_ch0(x) (((x) & 0x1) << 0) -+#define CFG_HDMI_OE_CH0_M (1 << 0) -+ -+/* AVI InfoFrame Packet byte offset define */ -+#define AVI_OFFSET_TYPE 0 -+#define AVI_OFFSET_VERSION 1 -+#define AVI_OFFSET_LENGTH 2 -+#define AVI_OFFSET_CHECKSUM 3 -+/* -+ * include : -+ * color space -+ * active information present -+ * bar Info data valid -+ * scan Information -+ */ -+#define AVI_OFFSET_PB1 4 -+/* -+ * include : -+ * colorimetry -+ * picture aspect ratio -+ * active format aspect ratio -+ */ -+#define AVI_OFFSET_PB2 5 -+/* -+ * include : -+ * IT content -+ * extended colorimetry -+ * quantization range -+ * non-uniform picture scaling -+ */ -+#define AVI_OFFSET_PB3 6 -+#define AVI_OFFSET_VIC 7 -+/* -+ * include : -+ * YCC quantization range -+ * content type -+ * pixel repetition factor -+ */ -+#define AVI_OFFSET_PB5 8 -+#define AVI_OFFSET_TOP_BAR_LOWER 9 -+#define AVI_OFFSET_TOP_BAR_UPPER 10 -+#define AVI_OFFSET_BOTTOM_BAR_LOWER 11 -+#define AVI_OFFSET_BOTTOM_BAR_UPPER 12 -+#define AVI_OFFSET_LEFT_BAR_LOWER 13 -+#define AVI_OFFSET_LEFT_BAR_UPPER 14 -+#define AVI_OFFSET_RIGHT_BAR_LOWER 15 -+#define AVI_OFFSET_RIGHT_BAR_UPPER 16 -+#define AVI_OFFSET_PB14 17 -+#define AVI_OFFSET_PB15 18 -+#define AVI_OFFSET_PB16 19 -+#define AVI_OFFSET_PB17 20 -+#define AVI_OFFSET_PB18 21 -+#define AVI_OFFSET_PB19 22 -+#define AVI_OFFSET_PB20 23 -+#define AVI_OFFSET_PB21 24 -+#define AVI_OFFSET_PB22 25 -+#define AVI_OFFSET_PB23 26 -+#define AVI_OFFSET_PB24 27 -+#define AVI_OFFSET_PB25 28 -+#define AVI_OFFSET_PB26 29 -+#define AVI_OFFSET_PB27 30 -+#define AVI_FRAME_COLORIMETRY_MASK 0x3 -+#define AVI_FRAME_PIC_ASPECT_MASK 0x3 -+#define AVI_FRAME_ACTIVE_ASPECT_MASK 0xF -+#define AVI_FRAME_EXT_COLORIMETRY_MASK 0x7 -+#define AVI_FRAME_QUANT_RANGE_MASK 0x3 -+#define AVI_FRAME_YCC_QUANT_RANGE_MASK 0x3 -+#define AVI_FRAME_PIXEL_REPET_MASK 0xF -+ -+//hdmi_hal_ddc.h -+#define DDC_MAX_RECORD_NUM 30 -+#define DDC_DEFAULT_TIMEOUT_ACCESS 100 -+#define DDC_DEFAULT_TIMEOUT_HPD 100 -+#define DDC_DEFAULT_TIMEOUT_IN_PROG 20 -+#define DDC_DEFAULT_TIMEOUT_SCL 1 -+#define DDC_DEFAULT_TIMEOUT_SDA 30 -+#define DDC_DEFAULT_TIMEOUT_ISSUE 20 -+#define DDC_DEFAULT_RETRY_TIMEOUT_ISSUE 60 -+ -+#define DDC_EDID_SALVE_ADDR 0xa0 -+#define DDC_HDCP_SALVE_ADDR 0x74 -+#define DDC_SCDC_SALVE_ADDR 0xa8 -+#define DDC_MAX_FIFO_SIZE 16 -+#define DDC_EXT_BLOCK_OFFSET 0x7e -+#define DDC_MAX_EDID_EXT_NUM 3 /* 3: 4(max block num) - 1(base block) */ -+#define DDC_DEFAULT_DELAY 8 /* 8us */ -+ -+static bool ctrl_hpd_get(void); -+ -+#define HDMI_EDID_BLOCK_SIZE 128 -+#define HDMI_EDID_TOTAL_BLOCKS 4 -+#define HDMI_EDID_SIZE (HDMI_EDID_BLOCK_SIZE * HDMI_EDID_TOTAL_BLOCKS) -+#define HDMI_REGISTER_SIZE 4 -+#define HDMI_EDID_MAX_BLOCK_NUM 4 -+#define HDMI_HW_PARAM_LEN 4 -+#define HDMI_EDID_TOTAL_SIZE ((HDMI_EDID_BLOCK_SIZE) * (HDMI_EDID_MAX_BLOCK_NUM)) -+ -+typedef enum { -+ DDC_CMD_READ_SINGLE_NO_ACK, -+ DDC_CMD_READ_SINGLE_ACK, -+ DDC_CMD_READ_MUTI_NO_ACK, -+ DDC_CMD_READ_MUTI_ACK, -+ DDC_CMD_READ_SEGMENT_NO_ACK, -+ DDC_CMD_READ_SEGMENT_ACK, -+ DDC_CMD_WRITE_MUTI_NO_ACK, -+ DDC_CMD_WRITE_MUTI_ACK, -+ DDC_CMD_FIFO_CLR = 0x09, -+ DDC_CMD_SCL_DRV, -+ DDC_CMD_MASTER_ABORT = 0x0f -+} ddc_issue_cmd; -+ -+typedef enum { -+ DDC_MODE_READ_SINGLE_NO_ACK, -+ DDC_MODE_READ_SINGLE_ACK, -+ DDC_MODE_READ_MUTIL_NO_ACK, -+ DDC_MODE_READ_MUTIL_ACK, -+ DDC_MODE_READ_SEGMENT_NO_ACK, -+ DDC_MODE_READ_SEGMENT_ACK, -+ DDC_MODE_WRITE_MUTIL_NO_ACK, -+ DDC_MODE_WRITE_MUTIL_ACK, -+ DDC_MODE_BUTT -+} ddc_issue_mode; -+ -+typedef enum { -+ DDC_FUNC_TYPE_EDID, -+ DDC_FUNC_TYPE_HDCP, -+ DDC_FUNC_TYPE_SCDC, -+ DDC_FUNC_TYPE_BUTT -+} ddc_func_type; -+ -+ -+ -+#define CEA_VIDEO_CODE_MAX 44 -+ -+#if 0 -+typedef enum { -+ /HDMI_PICTURE_ASPECT_NONE, -+ HDMI_PICTURE_ASPECT_4_3 = 1, -+ HDMI_PICTURE_ASPECT_16_9, -+ HDMI_PICTURE_ASPECT_64_27, -+ HDMI_PICTURE_ASPECT_256_135, -+ HDMI_PICTURE_ASPECT_FUTURE, -+ HDMI_PICTURE_ASPECT_BUTT -+} hdmi_picture_aspect; -+#endif -+ -+typedef enum { -+ HDMI_640X480P60_4_3 = 1, -+ HDMI_720X480P60_4_3, -+ HDMI_720X480P60_16_9, -+ HDMI_1280X720P60_16_9, -+ HDMI_1920X1080I60_16_9, -+ HDMI_1440X480I60_4_3, -+ HDMI_1440X480I60_16_9, // 7 -+ HDMI_1440X240P60_4_3, -+ HDMI_1440X240P60_16_9, -+ HDMI_2880X480I60_4_3, -+ HDMI_2880X480I60_16_9, -+ HDMI_2880X240P60_4_3, // 12 -+ HDMI_2880X240P60_16_9, -+ HDMI_1440X480P60_4_3, -+ HDMI_1440X480P60_16_9, -+ HDMI_1920X1080P60_16_9, -+ HDMI_720X576P50_4_3, -+ HDMI_720X576P50_16_9, -+ HDMI_1280X720P50_16_9, -+ HDMI_1920X1080I50_16_9, -+ HDMI_1440X576I50_4_3, -+ HDMI_1440X576I50_16_9, -+ HDMI_1440X288P50_4_3, -+ HDMI_1440X288P50_16_9, // 24 -+ HDMI_2880X576I50_4_3, -+ HDMI_2880X576I50_16_9, -+ HDMI_2880X288P50_4_3, -+ HDMI_2880X288P50_16_9, -+ HDMI_1440X576P50_4_3, -+ HDMI_1440X576P50_16_9, // 30 -+ HDMI_1920X1080P50_16_9, -+ HDMI_1920X1080P24_16_9, -+ HDMI_1920X1080P25_16_9, -+ HDMI_1920X1080P30_16_9, -+ HDMI_2880X480P60_4_3, -+ HDMI_2880X480P60_16_9, -+ HDMI_2880X576P50_4_3, -+ HDMI_2880X576P50_16_9, // 38 -+ HDMI_1920X1080I50_16_9_1250, -+ HDMI_1920X1080I100_16_9, -+ HDMI_1280X720P100_16_9, -+ HDMI_720X576P100_4_3, -+ HDMI_720X576P100_16_9, -+ HDMI_1440X576I100_4_3, -+ HDMI_1440X576I100_16_9, // 45 -+ HDMI_1920X1080I120_16_9, -+ HDMI_1280X720P120_16_9, -+ HDMI_720X480P120_4_3, -+ HDMI_720X480P120_16_9, -+ HDMI_1440X480I120_4_3, -+ HDMI_1440X480I120_16_9, // 51 -+ HDMI_720X576P200_4_3, -+ HDMI_720X576P200_16_9, -+ HDMI_1440X576I200_4_3, -+ HDMI_1440X576I200_16_9, -+ HDMI_720X480P240_4_3, -+ HDMI_720X480P240_16_9, -+ HDMI_1440X480I240_4_3, -+ HDMI_1440X480I240_16_9, // 59 -+ HDMI_1280X720P24_16_9, -+ HDMI_1280X720P25_16_9, -+ HDMI_1280X720P30_16_9, -+ HDMI_1920X1080P120_16_9, -+ HDMI_1920X1080P100_16_9, -+ HDMI_1280X720P24_64_27, -+ HDMI_1280X720P25_64_27, -+ HDMI_1280X720P30_64_27, -+ HDMI_1280X720P50_64_27, -+ HDMI_1280X720P60_64_27, // 69 -+ HDMI_1280X720P100_64_27, -+ HDMI_1280X720P120_64_27, -+ HDMI_1920X1080P24_64_27, -+ HDMI_1920X1080P25_64_27, -+ HDMI_1920X1080P30_64_27, -+ HDMI_1920X1080P50_64_27, -+ HDMI_1920X1080P60_64_27, // 76 -+ HDMI_1920X1080P100_64_27, -+ HDMI_1920X1080P120_64_27, -+ HDMI_1680X720P24_64_27, -+ HDMI_1680X720P25_64_27, -+ HDMI_1680X720P30_64_27, -+ HDMI_1680X720P50_64_27, -+ HDMI_1680X720P60_64_27, // 83 -+ HDMI_1680X720P100_64_27, -+ HDMI_1680X720P120_64_27, -+ HDMI_2560X1080P24_64_27, -+ HDMI_2560X1080P25_64_27, -+ HDMI_2560X1080P30_64_27, -+ HDMI_2560X1080P50_64_27, -+ HDMI_2560X1080P60_64_27, -+ HDMI_2560X1080P100_64_27, -+ HDMI_2560X1080P120_64_27, // 92 -+ HDMI_3840X2160P24_16_9, -+ HDMI_3840X2160P25_16_9, -+ HDMI_3840X2160P30_16_9, -+ HDMI_3840X2160P50_16_9, -+ HDMI_3840X2160P60_16_9, -+ HDMI_4096X2160P24_256_135, -+ HDMI_4096X2160P25_256_135, -+ HDMI_4096X2160P30_256_135, -+ HDMI_4096X2160P50_256_135, -+ HDMI_4096X2160P60_256_135, -+ HDMI_3840X2160P24_64_27, -+ HDMI_3840X2160P25_64_27, -+ HDMI_3840X2160P30_64_27, -+ HDMI_3840X2160P50_64_27, -+ HDMI_3840X2160P60_64_27, // 107 -+ HDMI_1280X720P48_16_9, -+ HDMI_1280X720P48_64_27, -+ HDMI_1680X720P48_64_27, -+ HDMI_1920X1080P48_16_9, -+ HDMI_1920X1080P48_64_27, -+ HDMI_2560X1080P48_64_27, -+ HDMI_3840X2160P48_16_9, -+ HDMI_4096X2160P48_256_135, -+ HDMI_3840X2160P48_64_27, -+ HDMI_3840X2160P100_16_9, -+ HDMI_3840X2160P120_16_9, -+ HDMI_3840X2160P100_64_27, -+ HDMI_3840X2160P120_64_27, -+ HDMI_5120X2160P24_64_27, // 121 -+ HDMI_5120X2160P25_64_27, -+ HDMI_5120X2160P30_64_27, -+ HDMI_5120X2160P48_64_27, -+ HDMI_5120X2160P50_64_27, -+ HDMI_5120X2160P60_64_27, -+ HDMI_5120X2160P100_64_27, // 127 -+ HDMI_5120X2160P120_64_27 = 193, -+ HDMI_7680X4320P24_16_9, -+ HDMI_7680X4320P25_16_9, -+ HDMI_7680X4320P30_16_9, -+ HDMI_7680X4320P48_16_9, -+ HDMI_7680X4320P50_16_9, -+ HDMI_7680X4320P60_16_9, -+ HDMI_7680X4320P100_16_9, // 200 -+ HDMI_7680X4320P120_16_9, -+ HDMI_7680X4320P24_64_27, -+ HDMI_7680X4320P25_64_27, -+ HDMI_7680X4320P30_64_27, -+ HDMI_7680X4320P48_64_27, -+ HDMI_7680X4320P50_64_27, -+ HDMI_7680X4320P60_64_27, -+ HDMI_7680X4320P100_64_27, -+ HDMI_7680X4320P120_64_27, -+ HDMI_10240X4320P24_64_27, -+ HDMI_10240X4320P25_64_27, -+ HDMI_10240X4320P30_64_27, -+ HDMI_10240X4320P48_64_27, -+ HDMI_10240X4320P50_64_27, // 214 -+ HDMI_10240X4320P60_64_27, -+ HDMI_10240X4320P100_64_27, -+ HDMI_10240X4320P120_64_27, -+ HDMI_4096X2160P100_256_135, -+ HDMI_4096X2160P120_256_135, // 219 -+ HDMI_VIDEO_CODE_BUTT -+} hdmi_video_code_vic; -+ -+typedef enum { -+ HDMI_VIDEO_TIMING_UNKNOWN, -+ HDMI_VIDEO_TIMING_640X480P_60000, -+ HDMI_VIDEO_TIMING_720X480P_60000, -+ HDMI_VIDEO_TIMING_720X480P_120000, -+ HDMI_VIDEO_TIMING_720X480P_240000, // 4 -+ HDMI_VIDEO_TIMING_720X576P_50000, -+ HDMI_VIDEO_TIMING_720X576P_100000, -+ HDMI_VIDEO_TIMING_720X576P_200000, // 7 -+ HDMI_VIDEO_TIMING_1280X720P_24000, -+ HDMI_VIDEO_TIMING_1280X720P_25000, -+ HDMI_VIDEO_TIMING_1280X720P_30000, // 10 -+ HDMI_VIDEO_TIMING_1280X720P_48000, -+ HDMI_VIDEO_TIMING_1280X720P_50000, -+ HDMI_VIDEO_TIMING_1280X720P_60000, -+ HDMI_VIDEO_TIMING_1280X720P_100000, -+ HDMI_VIDEO_TIMING_1280X720P_120000, -+ HDMI_VIDEO_TIMING_1440X240P_60000, // 16 -+ HDMI_VIDEO_TIMING_1440X288P_50000, -+ HDMI_VIDEO_TIMING_1440X480I_60000, -+ HDMI_VIDEO_TIMING_1440X480P_60000, -+ HDMI_VIDEO_TIMING_1440X480I_120000, -+ HDMI_VIDEO_TIMING_1440X480I_240000, -+ HDMI_VIDEO_TIMING_1440X576I_50000, // 22 -+ HDMI_VIDEO_TIMING_1440X576P_50000, -+ HDMI_VIDEO_TIMING_1440X576I_60000, -+ HDMI_VIDEO_TIMING_1440X576I_100000, -+ HDMI_VIDEO_TIMING_1440X576I_200000, -+ HDMI_VIDEO_TIMING_2880X288P_50000, // 27 -+ HDMI_VIDEO_TIMING_2880X480I_60000, -+ HDMI_VIDEO_TIMING_2880X480P_60000, -+ HDMI_VIDEO_TIMING_2880X240I_60000, -+ HDMI_VIDEO_TIMING_2880X576I_50000, -+ HDMI_VIDEO_TIMING_2880X576P_50000, -+ HDMI_VIDEO_TIMING_1680X720P_24000, // 33 -+ HDMI_VIDEO_TIMING_1680X720P_25000, -+ HDMI_VIDEO_TIMING_1680X720P_30000, -+ HDMI_VIDEO_TIMING_1680X720P_48000, -+ HDMI_VIDEO_TIMING_1680X720P_50000, -+ HDMI_VIDEO_TIMING_1680X720P_60000, -+ HDMI_VIDEO_TIMING_1680X720P_100000, -+ HDMI_VIDEO_TIMING_1680X720P_120000, -+ HDMI_VIDEO_TIMING_2560X1080P_24000, // 41 -+ HDMI_VIDEO_TIMING_2560X1080P_25000, -+ HDMI_VIDEO_TIMING_2560X1080P_30000, -+ HDMI_VIDEO_TIMING_2560X1080P_48000, -+ HDMI_VIDEO_TIMING_2560X1080P_50000, -+ HDMI_VIDEO_TIMING_2560X1080P_60000, -+ HDMI_VIDEO_TIMING_2560X1080P_100000, -+ HDMI_VIDEO_TIMING_2560X1080P_120000, // 48 -+ HDMI_VIDEO_TIMING_1920X1080I_60000, -+ HDMI_VIDEO_TIMING_1920X1080P_60000, -+ HDMI_VIDEO_TIMING_1920X1080I_50000, -+ HDMI_VIDEO_TIMING_1920X1080P_50000, -+ HDMI_VIDEO_TIMING_1920X1080P_24000, -+ HDMI_VIDEO_TIMING_1920X1080P_25000, -+ HDMI_VIDEO_TIMING_1920X1080P_30000, -+ HDMI_VIDEO_TIMING_1920X1080P_48000, -+ HDMI_VIDEO_TIMING_1920X1080I_100000, -+ HDMI_VIDEO_TIMING_1920X1080I_120000, -+ HDMI_VIDEO_TIMING_1920X1080P_120000, -+ HDMI_VIDEO_TIMING_1920X1080P_100000, // 60 -+ HDMI_VIDEO_TIMING_3840X2160P_24000, -+ HDMI_VIDEO_TIMING_3840X2160P_25000, -+ HDMI_VIDEO_TIMING_3840X2160P_30000, -+ HDMI_VIDEO_TIMING_3840X2160P_48000, -+ HDMI_VIDEO_TIMING_3840X2160P_50000, -+ HDMI_VIDEO_TIMING_3840X2160P_60000, -+ HDMI_VIDEO_TIMING_3840X2160P_100000, -+ HDMI_VIDEO_TIMING_3840X2160P_120000, -+ HDMI_VIDEO_TIMING_4096X2160P_24000, -+ HDMI_VIDEO_TIMING_4096X2160P_25000, -+ HDMI_VIDEO_TIMING_4096X2160P_30000, -+ HDMI_VIDEO_TIMING_4096X2160P_48000, -+ HDMI_VIDEO_TIMING_4096X2160P_50000, -+ HDMI_VIDEO_TIMING_4096X2160P_60000, // 74 -+ HDMI_VIDEO_TIMING_4096X2160P_100000, -+ HDMI_VIDEO_TIMING_4096X2160P_120000, -+ HDMI_VIDEO_TIMING_5120X2160P_24000, -+ HDMI_VIDEO_TIMING_5120X2160P_25000, -+ HDMI_VIDEO_TIMING_5120X2160P_30000, -+ HDMI_VIDEO_TIMING_5120X2160P_48000, -+ HDMI_VIDEO_TIMING_5120X2160P_50000, -+ HDMI_VIDEO_TIMING_5120X2160P_60000, -+ HDMI_VIDEO_TIMING_5120X2160P_100000, -+ HDMI_VIDEO_TIMING_5120X2160P_120000, -+ HDMI_VIDEO_TIMING_7680X4320P_24000, -+ HDMI_VIDEO_TIMING_7680X4320P_25000, -+ HDMI_VIDEO_TIMING_7680X4320P_30000, -+ HDMI_VIDEO_TIMING_7680X4320P_48000, -+ HDMI_VIDEO_TIMING_7680X4320P_50000, -+ HDMI_VIDEO_TIMING_7680X4320P_60000, -+ HDMI_VIDEO_TIMING_7680X4320P_100000, -+ HDMI_VIDEO_TIMING_7680X4320P_120000, -+ HDMI_VIDEO_TIMING_10240X4320P_24000, -+ HDMI_VIDEO_TIMING_10240X4320P_25000, -+ HDMI_VIDEO_TIMING_10240X4320P_30000, -+ HDMI_VIDEO_TIMING_10240X4320P_48000, -+ HDMI_VIDEO_TIMING_10240X4320P_50000, -+ HDMI_VIDEO_TIMING_10240X4320P_60000, -+ HDMI_VIDEO_TIMING_10240X4320P_100000, -+ HDMI_VIDEO_TIMING_10240X4320P_120000, -+ HDMI_VIDEO_TIMING_VESA_DEFINE, -+ HDMI_VIDEO_TIMING_VESA_800X600_60, -+ HDMI_VIDEO_TIMING_VESA_848X480_60, -+ HDMI_VIDEO_TIMING_VESA_1024X768_60, -+ HDMI_VIDEO_TIMING_VESA_1280X720_60, -+ HDMI_VIDEO_TIMING_VESA_1280X768_60, -+ HDMI_VIDEO_TIMING_VESA_1280X768_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1280X800_60, -+ HDMI_VIDEO_TIMING_VESA_1280X800_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1280X960_60, -+ HDMI_VIDEO_TIMING_VESA_1280X1024_60, -+ HDMI_VIDEO_TIMING_VESA_1360X768_60, -+ HDMI_VIDEO_TIMING_VESA_1366X768_60, -+ HDMI_VIDEO_TIMING_VESA_1400X1050_60, -+ HDMI_VIDEO_TIMING_VESA_1440X900_60, -+ HDMI_VIDEO_TIMING_VESA_1440X900_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1440X1050_60, -+ HDMI_VIDEO_TIMING_VESA_1440X1050_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1600X900_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1600X1200_60, -+ HDMI_VIDEO_TIMING_VESA_1680X1050_60, -+ HDMI_VIDEO_TIMING_VESA_1680X1050_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1792X1344_60, -+ HDMI_VIDEO_TIMING_VESA_1856X1392_60, -+ HDMI_VIDEO_TIMING_VESA_1920X1080_60, -+ HDMI_VIDEO_TIMING_VESA_1920X1200_60, -+ HDMI_VIDEO_TIMING_VESA_1920X1200_60_RB, -+ HDMI_VIDEO_TIMING_VESA_1920X1440_60, -+ HDMI_VIDEO_TIMING_VESA_2048X1152_60, -+ HDMI_VIDEO_TIMING_VESA_2560X1440_60_RB, -+ HDMI_VIDEO_TIMING_VESA_2560X1600_60, -+ HDMI_VIDEO_TIMING_VESA_2560X1600_60_RB, -+ HDMI_VIDEO_TIMING_USER_DEFINE, -+ HDMI_VIDEO_TIMING_USER_1920X2160_30, -+ HDMI_VIDEO_TIMING_USER_2560X1440_30, -+ HDMI_VIDEO_TIMING_USER_2560X1440_60, -+ HDMI_VIDEO_TIMING_USER_1280X720_60, -+ HDMI_VIDEO_TIMING_USER_1366X768_60, -+ HDMI_VIDEO_TIMING_USER_1600X900_60_RB, -+ HDMI_VIDEO_TIMING_USER_1920X1080_60, -+ HDMI_VIDEO_TIMING_USER_2048X1152_60, -+ HDMI_VIDEO_TIMING_BUTT -+} hdmi_video_timing; -+ -+typedef enum { -+ HDMI_VIDEO_UNKNOWN, -+ HDMI_VIDEO_PROGRESSIVE, -+ HDMI_VIDEO_INTERLACE, -+ HDMI_VIDEO_BUTT -+} hdmi_video_format_type; -+ -+struct hdmi_video_def { -+ hdmi_video_code_vic video_code; -+ unsigned int pixclk; -+ unsigned int rate; -+ unsigned int hactive; -+ unsigned int vactive; -+ unsigned int hblank; -+ unsigned int vblank; -+ unsigned int hfront; -+ unsigned int hsync; -+ unsigned int hback; -+ unsigned int vfront; -+ unsigned int vsync; -+ unsigned int vback; -+ unsigned int aspect_ratio; -+ hdmi_video_timing timing; -+ hdmi_video_format_type pi_type; -+ char *fmt_str; -+}; -+ -+#define hdmi_array_size(a) (sizeof(a) / sizeof(a[0])) -+ -+#define CTRL_CHANNEL0_Y 0x0 -+#define CTRL_CHANNEL0_Y422 0x3 -+#define CTRL_CHANNEL1_CB 0x1 -+#define CTRL_CHANNEL1_Y422 0x4 -+#define CTRL_CHANNEL2_CR 0x2 -+#define CTRL_CHANNEL2_Y422 0x3 -+#define CTRL_COLORMETRY_OUT_MASK 0xfc -+#define CTRL_COLORMETRY_OUT_BIT 0 /* out colormetry offset in reg_csc_mode */ -+#define CTRL_COLORMETRY_IN_MASK 0xcf -+#define CTRL_COLORMETRY_IN_BIT 0x4 /* in colormetry offset in reg_csc_mode */ -+#define CTRL_COLORMETRY_MASK 0x3 -+#define CTRL_RGB_OUT_BIT 0x3 /* out color space offset in reg_csc_mode */ -+#define CTRL_RGB_IN_BIT 0x7 /* in color space offset in reg_csc_mode */ -+#define CTRL_QUANTIZAION_OUT_BIT 0x2 /* out quantization offset in reg_csc_mode */ -+#define CTRL_QUANTIZAION_IN_BIT 0x6 /* in quantization offset in reg_csc_mode */ -+#define CTRL_SYCN_POL_V_BIT 0 /* vsync offset in reg_inver_sync */ -+#define CTRL_SYCN_POL_H_BIT 1 /* hsync offset in reg_inver_sync */ -+#define CTRL_SYCN_POL_DE_BIT 0x3 /* DE offset in reg_inver_sync */ -+#define CTRL_BLACK_Y_CB_CR 0x000000 -+#define CTRL_BLACK_DATA_YUV_CR 0x200 /* cr val for yuv black */ -+#define CTRL_BLACK_DATA_YUV_Y 0x40 /* y val for yuv black */ -+#define CTRL_BLACK_DATA_YUV_CB 0x200 /* cb val for yuv black */ -+#define CTRL_BLACK_DATA_RGB_R 0x40 /* r val for rgb black */ -+#define CTRL_BLACK_DATA_RGB_G 0x40 /* g val for rgb black */ -+#define CTRL_BLACK_DATA_RGB_B 0x40 /* b val for rgb black */ -+#define CTRL_AUDIO_INVALID_CFG 0xff -+#define CTRL_AUDIO_INVALID_RATE 0xffffffff -+#define CTRL_REAET_WAIT_TIME 5 -+#define HDMI_INFOFRAME_DATA_SIZE 31 -+ -+#define hdmi_set_bit(var, bit) \ -+ do { \ -+ (var) |= 1 << (bit); \ -+ } while (0) -+ -+#define hdmi_clr_bit(var, bit) \ -+ do { \ -+ (var) &= ~(1 << (bit)); \ -+ } while (0) -+ -+typedef enum { -+ HDMI_TMDS_MODE_NONE, -+ HDMI_TMDS_MODE_DVI, -+ HDMI_TMDS_MODE_HDMI_1_4, -+ HDMI_TMDS_MODE_HDMI_2_0, -+ HDMI_TMDS_MODE_AUTO, -+ HDMI_TMDS_MODE_HDMI_2_1, -+ HDMI_TMDS_MODE_BUTT -+} hdmi_tmds_mode; -+ -+typedef enum { -+ HDMI_PHY_MODE_CFG_TMDS, -+ HDMI_PHY_MODE_CFG_FRL, -+ HDMI_PHY_MODE_CFG_TXFFE -+} hdmi_phy_mode_cfg; -+ -+struct dphy_spec_en { -+ bool drv_post2_en; -+ bool drv_post1_en; -+ bool drv_pre_en; -+}; -+ -+struct dphy_spec_params { -+ unsigned char drv_post2; -+ unsigned char drv_post1; -+ unsigned char drv_main; -+ unsigned char drv_pre; -+}; -+ -+struct aphy_spec_params { -+ unsigned char offset_0; -+ unsigned char offset_1; -+ unsigned char offset_2; -+ unsigned char offset_3; -+ unsigned char offset_4; -+ unsigned char offset_5; -+ unsigned char offset_8; -+ unsigned char offset_9; -+ unsigned char offset_a; -+ unsigned char offset_b; -+}; -+ -+struct spec_params { -+ struct dphy_spec_en en; -+ struct dphy_spec_params dphy; -+ struct aphy_spec_params aphy; -+}; -+ -+struct tmds_spec_params { -+ u32 min_tmds_clk; -+ u32 max_tmds_clk; -+ struct spec_params data; -+ struct spec_params clock; -+}; -+ -+static const struct tmds_spec_params g_tmds_spec[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x1e, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x25, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 1.0 inch */ -+static const struct tmds_spec_params g_tmds_spec_1inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xE6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x1c, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x24, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x16, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 1.5 inch */ -+static const struct tmds_spec_params g_tmds_spec_1p5inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x1d, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x24, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x16, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 2.0 inch */ -+static const struct tmds_spec_params g_tmds_spec_2inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x1e, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x25, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 2.5 inch */ -+static const struct tmds_spec_params g_tmds_spec_2p5inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x01, 0x1e, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb7, 0x03, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x25, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 3.0 inch */ -+static const struct tmds_spec_params g_tmds_spec_3inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x1e, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xc7, 0x05, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x25, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 3.5 inch */ -+static const struct tmds_spec_params g_tmds_spec_3p5inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x01, 0x1e, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xc7, 0x05, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x01, 0x26, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 4 inch */ -+static const struct tmds_spec_params g_tmds_spec_4inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x02, 0x1e, 0x02 }, -+ { 0x7f, 0x7e, 0x3e, 0xc7, 0x05, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x02, 0x27, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 4.5 inch */ -+static const struct tmds_spec_params g_tmds_spec_4p5inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x03, 0x1e, 0x03 }, -+ { 0x7f, 0x7e, 0x3e, 0xf7, 0x06, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x03, 0x28, 0x02 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+/* 5 inch */ -+static const struct tmds_spec_params g_tmds_spec_5inch[] = { -+ { 25000, 100000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xb6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x13, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 100000, 165000, -+ {{ 0, 1, 0 }, -+ { 0x00, 0x02, 0x15, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0xe6, 0x07, 0x2d, 0x48, 0x80, 0x00, 0x70 }}, -+ {{ 0, 0, 0 }, -+ { 0x00, 0x00, 0x14, 0x00 }, -+ { 0x7f, 0x3e, 0x3e, 0x06, 0x00, 0x2d, 0x48, 0x80, 0x00, 0x70 }} -+ }, -+ { 165000, 340000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x04, 0x1e, 0x05 }, -+ { 0x7f, 0x7e, 0x3e, 0xf7, 0x06, 0x2d, 0x6c, 0x80, 0x00, 0x60 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x00, 0x17, 0x00 }, -+ { 0x7f, 0x7e, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x80, 0x00, 0x60 }} -+ }, -+ { 340000, 600000, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x04, 0x29, 0x05 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }}, -+ {{ 0, 1, 1 }, -+ { 0x00, 0x05, 0x17, 0x00 }, -+ { 0x7f, 0x7f, 0x3e, 0x06, 0x00, 0x2d, 0x6c, 0x81, 0x00, 0x50 }} -+ } -+}; -+ -+#define HDMI_EDID_MAX_HDMI14_TMDS_RATE 340000 // in khz -+#define HDMI_EDID_MAX_HDMI20_TMDS_RATE 600000 -+ -+//phy -+typedef enum { -+ PHY_RPRE_50, -+ PHY_RPRE_56, -+ PHY_RPRE_71, -+ PHY_RPRE_83, -+ PHY_RPRE_100, -+ PHY_RPRE_125, -+ PHY_RPRE_250, -+ PHY_RPRE_500, -+ PHY_RPRE_BUTT -+} phy_rpre; -+ -+typedef enum { -+ PHY_RTERM_MODE_SINGLE, -+ PHY_RTERM_MODE_SOURCE, -+ PHY_RTERM_MODE_LOAD, -+ PHY_RTERM_MODE_BUTT -+} phy_rterm_mode; -+ -+typedef enum { -+ HDMI_DEEP_COLOR_24BIT, -+ HDMI_DEEP_COLOR_30BIT, -+ HDMI_DEEP_COLOR_36BIT, -+ HDMI_DEEP_COLOR_48BIT, -+ HDMI_DEEP_COLOR_OFF = 0xff, -+ HDMI_DEEP_COLOR_BUTT -+} hdmi_deep_color; -+ -+typedef enum { -+ HDMI_TRACE_LEN_0, /* 1.0 inch */ -+ HDMI_TRACE_LEN_1, /* 1.5 inch */ -+ HDMI_TRACE_LEN_2, /* 2.0 inch */ -+ HDMI_TRACE_LEN_3, /* 2.5 inch */ -+ HDMI_TRACE_LEN_4, /* 3.0 inch */ -+ HDMI_TRACE_LEN_5, /* 3.5 inch */ -+ HDMI_TRACE_LEN_6, /* 4.0 inch */ -+ HDMI_TRACE_LEN_7, /* 4.5 inch */ -+ HDMI_TRACE_LEN_8, /* 5.0 inch */ -+ HDMI_TRACE_DEFAULT, /* default config */ -+ HDMI_TRACE_BUTT -+} hdmi_trace_len; -+ -+typedef struct { -+ unsigned int ssc_amptd; /* 1/1M ppm(spread rate range) */ -+ unsigned int ssc_freq; /* 1_hz(spread the frequency) */ -+} phy_ssc_cfg; -+ -+typedef struct { -+ bool ssc_enable; -+ bool ssc_debug_en; -+ phy_ssc_cfg ssc_cfg; -+} hdmi_phy_ssc; -+ -+typedef struct { -+ unsigned int pix_clk; /* pixel colck, in k_hz */ -+ unsigned int tmds_clk; /* TMDS colck, in k_hz */ -+ hdmi_deep_color deep_color; /* deep color(color depth) */ -+ hdmi_phy_ssc phy_ssc; /* spread spectrum ctrl(ssc) para */ -+} hdmi_phy_ssc_cfg; -+ -+typedef struct { -+ unsigned int i_main_clk; -+ unsigned int i_main_d0; -+ unsigned int i_main_d1; -+ unsigned int i_main_d2; -+ unsigned int i_pre_clk; -+ unsigned int i_pre_d0; -+ unsigned int i_pre_d1; -+ unsigned int i_pre_d2; -+ phy_rpre r_pre_clk; -+ phy_rpre r_pre_d0; -+ phy_rpre r_pre_d1; -+ phy_rpre r_pre_d2; -+ phy_rterm_mode r_term_mode_clk; -+ unsigned int r_term_clk; -+ phy_rterm_mode r_term_mode_d0; -+ unsigned int r_term_d0; -+ phy_rterm_mode r_term_mode_d1; -+ unsigned int r_term_d1; -+ phy_rterm_mode r_term_mode_d2; -+ unsigned int r_term_d2; -+} phy_hw_spec_cfg; -+ -+typedef struct { -+ bool hw_spec_debug_en; -+ phy_hw_spec_cfg spec_cfg; -+} hdmi_phy_hw_spec; -+ -+typedef struct { -+ unsigned int tmds_clk; /* TMDS colck, in k_hz */ -+ unsigned char frl_dat_rat; /* FRL_DATA_RATA */ -+ hdmi_trace_len trace_len; -+ hdmi_phy_hw_spec hdmi_phy_spec; /* phy specification para */ -+} hdmi_phy_hw_spec_cfg; -+ -+typedef struct { -+ unsigned int pixel_clk; -+ unsigned int tmds_clk; /* TMDS colck, in k_hz */ -+ bool emi_enable; -+ hdmi_deep_color deep_color; /* deep color(color depth) */ -+ hdmi_phy_mode_cfg mode_cfg; /* TMDS/FRL/tx_ffe */ -+ hdmi_trace_len trace_len; -+} hdmi_phy_tmds_cfg; -+ -+ -+typedef struct { -+ unsigned int i_de_main_clk; -+ unsigned int i_de_main_data; -+ unsigned int i_main_clk; -+ unsigned int i_main_data; -+ unsigned int ft_cap_clk; -+ unsigned int ft_cap_data; -+} hdmi_hw_param; -+ -+typedef struct { -+ hdmi_hw_param hw_param[HDMI_HW_PARAM_LEN]; -+} hdmi_hw_spec; -+ -+#define HDMI_TRACE_COUNT 10 -+typedef struct { -+ bool init; -+ bool power_enable; -+ bool oe_enable; -+ hdmi_phy_tmds_cfg tmds_cfg; -+ hdmi_phy_ssc ssc_cfg; -+ phy_hw_spec_cfg hw_spec_cfg; -+ hdmi_hw_spec spec_user[HDMI_TRACE_COUNT]; /* user set crg */ -+ hdmi_hw_spec hw_spec[HDMI_TRACE_COUNT]; /* drv use now = chip def + use set */ -+} hdmi_phy_info; -+ -+typedef struct { -+ hdmi_hw_spec hw_spec_cfg; -+ hdmi_hw_spec hw_spec_def; /* chip default cfg */ -+ hdmi_hw_param hw_param_cur; /* reg cfg now */ -+ hdmi_hw_spec spec_drv_use; /* drv use now */ -+ hdmi_hw_spec spec_user_set; /* user set cfg */ -+} hdmi_phy_hw_param; -+ -+typedef enum { -+ APHY_OFFSET_0, -+ APHY_OFFSET_1, -+ APHY_OFFSET_2, -+ APHY_OFFSET_3, -+ APHY_OFFSET_4, -+ APHY_OFFSET_5, -+ APHY_OFFSET_6, -+ APHY_OFFSET_7, -+ APHY_OFFSET_8, -+ APHY_OFFSET_9, -+ APHY_OFFSET_A, -+ APHY_OFFSET_B, -+ APHY_OFFSET_C, -+ APHY_OFFSET_D, -+ APHY_OFFSET_E, -+ APHY_OFFSET_F, -+ APHY_OFFSET_BUTT -+} aphy_offset_addr; -+ -+typedef struct { -+ unsigned int cs; -+ aphy_offset_addr aphy_offset; -+ unsigned char msb; -+ unsigned char lsb; -+ unsigned int wdata; -+} write_param; -+ -+ -+#define APHY_CS_0 0x1 -+#define APHY_CS_1 0x2 -+#define APHY_CS_2 0x4 -+#define APHY_CS_3 0x8 -+#define APHY_CS_4 0x10 -+#define APHY_CS_012 0x7 -+#define APHY_CS_4567 0xf0 -+#define APHY_CS_8 0x100 -+#define APHY_CS_9 0x200 -+#define TMDS_CLOCK_340M 340000 -+#define PHY_POW_BASE_NUM 2 -+#define PHY_POW_INDEX_NUM 24 -+#define TMDS_CLK_FREQ_MUITIPLE 5 -+#define MOD_N_MULTI_COEFFICIENT 10000 -+#define MOD_D_MULTI_COEFFICIENT 100000 -+#define PHY_HWSPEC_I_16 16 -+#define PHY_HWSPEC_I_8 8 -+#define HDMI_HW_PARAM_NUM 4 -+ -+typedef struct { -+ unsigned int clk_min; -+ unsigned int clk_max; -+} phy_clk_range; -+ -+typedef struct { -+ phy_clk_range clk_range; -+ unsigned char seek_value; -+} phy_clk_range_value; -+ -+static const phy_clk_range_value g_phy_hw_fcd_step_set[] = { -+ {{ 0, 37500 }, 4}, -+ {{ 37500, 75000 }, 3}, -+ {{ 75000, 150000 }, 2}, -+ {{ 150000, 300000 }, 1}, -+ {{ 300000, 600000 }, 0} -+}; -+ -+static const phy_clk_range_value g_phy_hw_def_clk_div[] = { -+ {{ 0, 37500 }, 0}, -+ {{ 37500, 75000 }, 1}, -+ {{ 75000, 150000 }, 2}, -+ {{ 150000, 300000 }, 3}, -+ {{ 300000, 600000 }, 4} -+}; -+typedef struct { -+ phy_clk_range phy_tmds_clk_range; -+ phy_ssc_cfg ssc_cfg; -+} phy_ssc; -+ -+static const phy_clk_range_value g_phy_hw_tmds_divn_sel[] = { -+ {{ 300000, 600000 }, 0}, -+ {{ 150000, 300000 }, 1}, -+ {{ 75000, 150000 }, 2}, -+ {{ 37500, 75000 }, 3}, -+ {{ 25000, 37500 }, 4} -+}; -+ -+typedef struct { -+ unsigned char ref_clk_div; -+ unsigned char vp_divnsel; -+ unsigned char cpzs; -+ unsigned char tmds_divnsel; -+ unsigned char vp_mode; -+ unsigned char fcd_step; -+ hdmi_phy_tmds_cfg tmds_cfg; -+} phy_clk_set; -+ -+typedef struct { -+ unsigned char m_val; -+ unsigned char n_val; -+ unsigned int pll_ref_clk; -+ unsigned int mn_value; -+} phy_mnx; -+ -+ -+static phy_mnx g_mnx_get; -+static hdmi_phy_info g_hdmi_phy_info[HDMI_ID_MAX]; -+ -+#define AEN_TX_FFE_LEN 4 -+#define MAX_FRL_RATE 6 -+#define HDMI_FRL_LANE_MAX_NUM 4 -+#define CEA_VIDEO_CODE_MAX 44 -+#define VESA_VIDEO_CODE_MAX 31 -+#define CEA861_F_VIDEO_CODES_MAX_4K 4 -+#define HDMI_INFO_FRAME_MAX_SIZE 31 -+#define SCDC_TMDS_BIT_CLK_RATIO_10X 10 -+#define SCDC_TMDS_BIT_CLK_RATIO_40X 40 -+#define HDMI_DECIMAL 10 -+#define HDMI_HUNDRED 100 -+#define HDMI_THOUSAND 1000 -+#define FMT_PIX_CLK_13400 13400 -+#define FMT_PIX_CLK_74250 74250 -+#define FMT_PIX_CLK_165000 165000 -+#define FMT_PIX_CLK_190000 190000 -+#define FMT_PIX_CLK_297000 297000 -+#define FMT_PIX_CLK_340000 340000 -+#define ZERO_DRMIF_SEND_TIME 2000 /* unit: ms */ -+#define HDRMODE_CHANGE_TIME 500 /* unit: ms */ -+ -+ -+#define TMDS_DRV_CFG_CH0 0x510 -+#define cfg_hdmi_ffe_sel(x) (((x) & 0x1) << 30) -+#define CFG_HDMI_FFE_SEL_M (0x1 << 30) -+#define cfg_drv_post2_ch0(x) (((x) & 0x3f) << 24) -+#define CFG_DRV_POST2_CH0_M (0x3f << 24) -+#define cfg_drv_post1_ch0(x) (((x) & 0x3f) << 16) -+#define CFG_DRV_POST1_CH0_M (0x3f << 16) -+#define cfg_drv_m_ch0(x) (((x) & 0x3f) << 8) -+#define CFG_DRV_M_CH0_M (0x3f << 8) -+#define cfg_drv_pre_ch0(x) (((x) & 0x3f) << 0) -+#define CFG_DRV_PRE_CH0_M (0x3f << 0) -+ -+#define TMDS_DRV_CFG_CH1 0x514 -+#define cfg_drv_post2_ch1(x) (((x) & 0x3f) << 24) -+#define CFG_DRV_POST2_CH1_M (0x3f << 24) -+#define cfg_drv_post1_ch1(x) (((x) & 0x3f) << 16) -+#define CFG_DRV_POST1_CH1_M (0x3f << 16) -+#define cfg_drv_m_ch1(x) (((x) & 0x3f) << 8) -+#define CFG_DRV_M_CH1_M (0x3f << 8) -+#define cfg_drv_pre_ch1(x) (((x) & 0x3f) << 0) -+#define CFG_DRV_PRE_CH1_M (0x3f << 0) -+ -+#define TMDS_DRV_CFG_CH2 0x518 -+#define cfg_drv_post2_ch2(x) (((x) & 0x3f) << 24) -+#define CFG_DRV_POST2_CH2_M (0x3f << 24) -+#define cfg_drv_post1_ch2(x) (((x) & 0x3f) << 16) -+#define CFG_DRV_POST1_CH2_M (0x3f << 16) -+#define cfg_drv_m_ch2(x) (((x) & 0x3f) << 8) -+#define CFG_DRV_M_CH2_M (0x3f << 8) -+#define cfg_drv_pre_ch2(x) (((x) & 0x3f) << 0) -+#define CFG_DRV_PRE_CH2_M (0x3f << 0) -+ -+#define TMDS_DRV_CFG_CH3 0x51C -+#define cfg_drv_post2_ch3(x) (((x) & 0x3f) << 24) -+#define CFG_DRV_POST2_CH3_M (0x3f << 24) -+#define cfg_drv_post1_ch3(x) (((x) & 0x3f) << 16) -+#define CFG_DRV_POST1_CH3_M (0x3f << 16) -+#define cfg_drv_m_ch3(x) (((x) & 0x3f) << 8) -+#define CFG_DRV_M_CH3_M (0x3f << 8) -+#define cfg_drv_pre_ch3(x) (((x) & 0x3f) << 0) -+#define CFG_DRV_PRE_CH3_M (0x3f << 0) -+ -+#define FFE_EN_CFG 0x67C -+#define cfg_c3_pre_en(x) (((x) & 0x1) << 11) -+#define CFG_C3_PRE_EN_M (1 << 11) -+#define cfg_c3_post1_en(x) (((x) & 0x1) << 10) -+#define CFG_C3_POST1_EN_M (1 << 10) -+#define cfg_c3_post2_en(x) (((x) & 0x1) << 9) -+#define CFG_C3_POST2_EN_M (1 << 9) -+#define cfg_c2_pre_en(x) (((x) & 0x1) << 8) -+#define CFG_C2_PRE_EN_M (1 << 8) -+#define cfg_c2_post1_en(x) (((x) & 0x1) << 7) -+#define CFG_C2_POST1_EN_M (1 << 7) -+#define cfg_c2_post2_en(x) (((x) & 0x1) << 6) -+#define CFG_C2_POST2_EN_M (1 << 6) -+#define cfg_c1_pre_en(x) (((x) & 0x1) << 5) -+#define CFG_C1_PRE_EN_M (1 << 5) -+#define cfg_c1_post1_en(x) (((x) & 0x1) << 4) -+#define CFG_C1_POST1_EN_M (1 << 4) -+#define cfg_c1_post2_en(x) (((x) & 0x1) << 3) -+#define CFG_C1_POST2_EN_M (1 << 3) -+#define cfg_c0_pre_en(x) (((x) & 0x1) << 2) -+#define CFG_C0_PRE_EN_M (1 << 2) -+#define cfg_c0_post1_en(x) (((x) & 0x1) << 1) -+#define CFG_C0_POST1_EN_M (1 << 1) -+#define cfg_c0_post2_en(x) (((x) & 0x1) << 0) -+#define CFG_C0_POST2_EN_M (1 << 0) -+ -+#define HDMI_OE_CFG 0x520 -+#define cfg_oe_sync_en(x) (((x) & 0x1) << 4) -+#define CFG_OE_SYNC_EN_M (1 << 4) -+#define cfg_hdmi_oe_ch3(x) (((x) & 0x1) << 3) -+#define CFG_HDMI_OE_CH3_M (1 << 3) -+#define cfg_hdmi_oe_ch2(x) (((x) & 0x1) << 2) -+#define CFG_HDMI_OE_CH2_M (1 << 2) -+#define cfg_hdmi_oe_ch1(x) (((x) & 0x1) << 1) -+#define CFG_HDMI_OE_CH1_M (1 << 1) -+#define cfg_hdmi_oe_ch0(x) (((x) & 0x1) << 0) -+#define CFG_HDMI_OE_CH0_M (1 << 0) -+ -+typedef enum { -+ HDMI_VIDEO_DITHER_12_10, -+ HDMI_VIDEO_DITHER_12_8, -+ HDMI_VIDEO_DITHER_10_8, -+ HDMI_VIDEO_DITHER_DISALBE -+} hdmi_video_dither; -+#define HDMI_INFOFRAME_BUFFER_SIZE 32 -+ -+ -+#define CTRL_REAET_WAIT_TIME 5 -+#define CTRL_RESET_WAIT 20 -+#define CTRL_BLACK_DATA_YUV_CR 0x200 /* cr val for yuv black */ -+#define CTRL_BLACK_DATA_YUV_Y 0x40 /* y val for yuv black */ -+#define CTRL_BLACK_DATA_YUV_CB 0x200 /* cb val for yuv black */ -+#define CTRL_BLACK_DATA_RGB_R 0x40 /* r val for rgb black */ -+#define CTRL_BLACK_DATA_RGB_G 0x40 /* g val for rgb black */ -+#define CTRL_BLACK_DATA_RGB_B 0x40 /* b val for rgb black */ -+ -+#endif /* __HI3403V100_HDMI_H__ */ -+ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.c b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.c -new file mode 100755 -index 0000000..8d24374 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.c -@@ -0,0 +1,5306 @@ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+ -+#include "smart_vo.h" -+#include "ot_board.h" -+ -+ -+#define to_vop(x) container_of(x, struct vop, crtc) -+ -+ -+/* -+ * The coefficients of the following matrix are all fixed points. -+ * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. -+ * They are all represented in two's complement. -+ */ -+ -+struct vop { -+ struct drm_crtc crtc; -+ struct device *dev; -+ struct drm_device *drm_dev; -+ bool is_enabled; -+ -+ struct completion dsp_hold_completion; -+ unsigned int win_enabled; -+ -+ /* protected by dev->event_lock */ -+ struct drm_pending_vblank_event *event; -+ -+ struct drm_flip_work fb_unref_work; -+ unsigned long pending; -+ -+ struct completion line_flag_completion; -+ struct drm_plane primary_plane; -+ -+ void __iomem *regs; -+ -+ -+ /* physical map length of vop register */ -+ uint32_t len; -+ -+ /* one time only one process allowed to config the register */ -+ spinlock_t reg_lock; -+ /* lock vop irq reg */ -+ spinlock_t irq_lock; -+ /* protects crtc enable/disable */ -+ struct mutex vop_lock; -+ -+ unsigned int irq; -+ -+ ot_vo_dev vo_dev; -+ ot_vo_csc csc; -+ -+ bool vblank_enabled; -+ phys_addr_t phys_addr; -+ void *virt_addr; -+ -+ struct sg_table *sgt; -+ size_t size; -+}; -+ -+ -+static void vop_crtc_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop *vop = to_vop(crtc); -+ -+ WARN_ON(vop->event); -+ drm_crtc_vblank_off(crtc); -+ -+ mutex_lock(&vop->vop_lock); -+ vop->is_enabled = false; -+ mutex_unlock(&vop->vop_lock); -+ -+out: -+ if (crtc->state->event && !crtc->state->active) { -+ spin_lock_irq(&crtc->dev->event_lock); -+ drm_crtc_send_vblank_event(crtc, crtc->state->event); -+ spin_unlock_irq(&crtc->dev->event_lock); -+ crtc->state->event = NULL; -+ } -+} -+ -+static void vop_plane_destroy(struct drm_plane *plane) -+{ -+ drm_plane_cleanup(plane); -+} -+ -+static bool smart_mod_supported(struct drm_plane *plane, -+ u32 format, u64 modifier) -+{ -+ int i; -+ /* -+ * We always have to allow these modifiers: -+ * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. -+ * 2. Not passing any modifiers is the same as explicitly passing INVALID. -+ */ -+ if (modifier == DRM_FORMAT_MOD_LINEAR) { -+ return true; -+ } -+ /* Check that the modifier is on the list of the plane's supported modifiers. */ -+ for (i = 0; i < plane->modifier_count; i++) { -+ if (modifier == plane->modifiers[i]) -+ break; -+ } -+ if (i == plane->modifier_count) -+ return false; -+ return true; -+} -+ -+static int vop_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc_state *crtc_state; -+ int ret; -+ -+ if (!plane_state->fb || !plane_state->crtc) -+ return 0; -+ -+ -+ crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc); -+ if (IS_ERR(crtc_state)) -+ return PTR_ERR(crtc_state); -+ ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, -+ DRM_PLANE_NO_SCALING, -+ DRM_PLANE_NO_SCALING, -+ true, true); -+ -+ return ret; -+} -+ -+static void vop_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, -+ plane); -+ if (!old_state->crtc) -+ return; -+ -+} -+/* no ddr reg */ -+void hal_write_reg(unsigned int *address, unsigned int value) -+{ -+ if (address == NULL) { -+ return; -+ } -+ *(volatile unsigned int *)address = value; -+} -+ -+unsigned int hal_read_reg(const unsigned int *address) -+{ -+ if (address == NULL) { -+ return 0; -+ } -+ return *(volatile unsigned int *)(address); -+} -+ -+volatile vdp_regs_type *g_gfbg_reg = NULL; -+ -+static unsigned long fb_vou_get_gfx_abs_addr(hal_disp_layer layer, unsigned long reg) -+{ -+ volatile unsigned long reg_abs_addr; -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: -+ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GRF_REGS_LEN; -+ break; -+ default: -+ printk("Error layer id found in FUNC:%s,LINE:%d\n", __FUNCTION__, __LINE__); -+ return 0; -+ } -+ -+ return reg_abs_addr; -+} -+ -+unsigned long vou_get_gfx_abs_addr(hal_disp_layer layer, unsigned long reg) -+{ -+ volatile unsigned long reg_abs_addr; -+ switch (layer) { -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GRF_REGS_LEN; -+ break; -+ -+ case HAL_DISP_LAYER_GFX3: -+ reg_abs_addr = reg + 3 * GRF_REGS_LEN; /* 3 lens */ -+ break; -+ -+ default: -+ printk("invalid layer %d!\n", layer); -+ reg_abs_addr = reg; -+ break; -+ } -+ -+ return reg_abs_addr; -+} -+ -+ -+bool fb_hal_graphic_set_gfx_ext(hal_disp_layer layer, hal_gfx_bitextend mode) -+{ -+ volatile u_gfx_out_ctrl gfx_out_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); -+ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_out_ctrl.bits.bitext = mode; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); -+ } else { -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ return true; -+} -+ -+bool fb_hal_graphic_set_gfx_palpha(hal_disp_layer layer, unsigned int alpha_en, unsigned int arange, -+ unsigned char alpha0, unsigned char alpha1) -+{ -+ volatile u_gfx_out_ctrl gfx_out_ctrl; -+ volatile u_gfx_1555_alpha gfx_1555_alpha; -+ volatile unsigned long addr_reg; -+ -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); -+ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_out_ctrl.bits.palpha_en = alpha_en; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); -+ -+ if (alpha_en == true) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); -+ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_1555_alpha.bits.alpha_1 = alpha1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); -+ -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); -+ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_1555_alpha.bits.alpha_0 = alpha0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); -+ } else { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); -+ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_1555_alpha.bits.alpha_1 = 0xff; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); -+ -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_1555_alpha.u32)); -+ gfx_1555_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_1555_alpha.bits.alpha_0 = 0xff; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_1555_alpha.u32); -+ } -+ } else { -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ return true; -+} -+/***************************************************************************** -+ Prototype : fb_vou_get_abs_addr -+ Description : Get the absolute address of the layer (video layer and graphics layer) -+*****************************************************************************/ -+static unsigned long fb_vou_get_abs_addr(hal_disp_layer layer, unsigned long reg) -+{ -+ unsigned long reg_abs_addr; -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: -+ reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_VHD0) * VHD_REGS_LEN; -+ break; -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: -+ reg_abs_addr = (reg) + (layer - HAL_DISP_LAYER_GFX0) * GFX_REGS_LEN; -+ break; -+ /* one wbc dev */ -+ case HAL_DISP_LAYER_WBC: -+ reg_abs_addr = (reg); -+ break; -+ default: -+ printk("Error channel id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return 0; -+ } -+ return reg_abs_addr; -+} -+ -+unsigned long vou_get_abs_addr(hal_disp_layer layer, unsigned long reg) -+{ -+ volatile unsigned long reg_abs_addr; -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: -+ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_VHD0) * VHD_REGS_LEN; -+ break; -+ -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_GFX0) * GFX_REGS_LEN; -+ break; -+ -+ case HAL_DISP_LAYER_GFX3: -+ reg_abs_addr = reg + 3 * GFX_REGS_LEN; /* 3 lens */ -+ break; -+ -+ default: -+ printk("invalid layer %d!\n", layer); -+ reg_abs_addr = reg; -+ break; -+ } -+ -+ return reg_abs_addr; -+} -+ -+/* -+ * Name : hal_layer_set_layer_galpha -+ * Desc : Set video/graphic layer's global alpha -+ */ -+bool fb_hal_layer_set_layer_galpha(hal_disp_layer layer, unsigned char alpha0) -+{ -+ volatile u_v0_ctrl v0_ctrl; -+ volatile u_g0_ctrl g0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->v0_ctrl.u32)); -+ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_ctrl.bits.galpha = alpha0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); -+ break; -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ctrl.u32)); -+ g0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ctrl.bits.galpha = alpha0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ctrl.u32); -+ break; -+ default: -+ printk("Error layer id %d found in %s: L%d\n", layer, __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+static void fb_hal_layer_csc_set_ck_gt_en(hal_disp_layer layer, bool ck_gt_en) -+{ -+ volatile u_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long )(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_ctrl.u32)); -+ g0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_ctrl.bits.ot_pp_csc_ck_gt_en = ck_gt_en; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_ctrl.u32); -+ } -+} -+ -+static void fb_hal_layer_csc_set_enable(hal_disp_layer layer, bool csc_en) -+{ -+ volatile u_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long )(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_ctrl.u32)); -+ g0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_ctrl.bits.ot_pp_csc_en = csc_en; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_ctrl.u32); -+ } -+} -+ -+bool fb_hal_layer_set_csc_en(hal_disp_layer layer, bool csc_en) -+{ -+ if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX4)) { -+ printk("Error, Wrong layer ID!%d\n", __LINE__); -+ return false; -+ } -+ fb_hal_layer_csc_set_ck_gt_en(layer, false); -+ fb_hal_layer_csc_set_enable(layer, csc_en); -+ -+ return true; -+} -+ -+/* for gfx decompress */ -+bool fb_hal_graphic_set_gfx_dcmp_enable(hal_disp_layer layer, unsigned int enable) -+{ -+ volatile u_gfx_src_info gfx_src_info; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_src_info.u32)); -+ -+ gfx_src_info.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_src_info.bits.dcmp_en = enable; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_src_info.u32); -+ } else { -+ printk("Error layer id %d not support dcmp in %s: L%d\n", (int)layer, __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+/* -+ * Name : fb_hal_layer_set_reg_up -+ * Desc : Set layer(video or graphic) register update. -+ */ -+bool fb_hal_layer_set_reg_up(hal_disp_layer layer) -+{ -+ volatile u_v0_upd v0_upd; -+ volatile u_g0_upd g0_upd; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->v0_upd.u32)); -+ v0_upd.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ /* video layer register update */ -+ v0_upd.bits.regup = 0x1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_upd.u32); -+ break; -+ } -+ -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_upd.u32)); -+ g0_upd.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ /* graphic layer register update */ -+ g0_upd.bits.regup = 0x1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_upd.u32); -+ break; -+ } -+ default: { -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ } -+ return true; -+} -+ -+/* layer stride */ -+bool fb_hal_graphic_set_gfx_stride(hal_disp_layer layer, unsigned short pitch) -+{ -+ volatile u_gfx_stride gfx_stride; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_stride.u32)); -+ gfx_stride.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_stride.bits.surface_stride = pitch; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_stride.u32); -+ } else { -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+bool fb_hal_layer_set_layer_out_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { -+ return true; -+ } else { -+ printk("Error:layer id not found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+} -+ -+bool fb_hal_layer_set_layer_in_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_gfx_ireso gfx_ireso; -+ volatile unsigned long addr_reg; -+ -+ if ((g_gfbg_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_ireso.u32)); -+ gfx_ireso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_ireso.bits.ireso_w = rect->width - 1; -+ gfx_ireso.bits.ireso_h = rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_ireso.u32); -+ } else { -+ printk("Error layer id found in %s, %d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+/* -+ * Name : fb_hal_set_layer_enable -+ * Desc : Set layer enable -+ */ -+bool fb_hal_set_layer_enable(hal_disp_layer layer, unsigned int enable) -+{ -+ volatile u_v0_ctrl v0_ctrl; -+ volatile u_g0_ctrl g0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->v0_ctrl.u32)); -+ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_ctrl.bits.surface_en = enable; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); -+ break; -+ } -+ -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ctrl.u32)); -+ g0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ctrl.bits.surface_en = enable; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ctrl.u32); -+ break; -+ default: -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+/* Desc : Set layer data type */ -+bool fb_hal_layer_set_layer_data_fmt(hal_disp_layer layer, hal_disp_pixel_format data_fmt) -+{ -+ volatile u_gfx_src_info gfx_src_info; -+ volatile unsigned long addr_reg; -+ -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_src_info.u32)); -+ gfx_src_info.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_src_info.bits.ifmt = data_fmt; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_src_info.u32); -+ } else { -+ printk("Error layer id%d found in %s: L%d\n", layer, __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+__inline static unsigned int get_low_addr(unsigned long long phys_addr) -+{ -+ return (unsigned int)phys_addr; -+} -+ -+__inline static unsigned int get_high_addr(unsigned long long phys_addr) -+{ -+ return (unsigned int)(phys_addr >> 32); /* 32bit low addr */ -+} -+ -+/* set layer addr */ -+bool fb_hal_graphic_set_gfx_addr(hal_disp_layer layer, phys_addr_t laddr) -+{ -+ volatile unsigned long gfx_addr_h; -+ volatile unsigned long gfx_addr_l; -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ /* Write low address to register. */ -+ gfx_addr_l = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_l)); -+ hal_write_reg((unsigned int *)(uintptr_t)gfx_addr_l, get_low_addr(laddr)); -+ -+ /* Write high address to register. */ -+ gfx_addr_h = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_h)); -+ hal_write_reg((unsigned int *)(uintptr_t)gfx_addr_h, get_high_addr(laddr)); -+ } else { -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ return true; -+} -+ -+bool fb_hal_layer_set_src_resolution(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_gfx_src_reso gfx_src_reso; -+ volatile unsigned long addr_reg; -+ -+ if ((g_gfbg_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_src_reso.u32)); -+ gfx_src_reso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_src_reso.bits.src_w = rect->width - 1; -+ gfx_src_reso.bits.src_h = rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_src_reso.u32); -+ } else { -+ printk("Error:layer id not found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+static unsigned int hal_get_addr_abs(volatile unsigned long *addr_reg, hal_disp_layer layer, const volatile unsigned int *value) -+{ -+ *addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)value); -+ return hal_read_reg((unsigned int *)(uintptr_t)(*addr_reg)); -+} -+ -+static void fb_hal_layer_csc_set_coef(hal_disp_layer layer, const vdp_csc_coef *coef) -+{ -+ volatile u_g0_ot_pp_csc_coef00 g0_ot_pp_csc_coef00; -+ volatile u_g0_ot_pp_csc_coef01 g0_ot_pp_csc_coef01; -+ volatile u_g0_ot_pp_csc_coef02 g0_ot_pp_csc_coef02; -+ volatile u_g0_ot_pp_csc_coef10 g0_ot_pp_csc_coef10; -+ volatile u_g0_ot_pp_csc_coef11 g0_ot_pp_csc_coef11; -+ volatile u_g0_ot_pp_csc_coef12 g0_ot_pp_csc_coef12; -+ volatile u_g0_ot_pp_csc_coef20 g0_ot_pp_csc_coef20; -+ volatile u_g0_ot_pp_csc_coef21 g0_ot_pp_csc_coef21; -+ volatile u_g0_ot_pp_csc_coef22 g0_ot_pp_csc_coef22; -+ volatile unsigned long addr_reg; -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { -+ g0_ot_pp_csc_coef00.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef00.u32)); -+ g0_ot_pp_csc_coef00.bits.ot_pp_csc_coef00 = coef->csc_coef00; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef00.u32); -+ -+ g0_ot_pp_csc_coef01.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef01.u32)); -+ g0_ot_pp_csc_coef01.bits.ot_pp_csc_coef01 = coef->csc_coef01; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef01.u32); -+ -+ g0_ot_pp_csc_coef02.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef02.u32)); -+ g0_ot_pp_csc_coef02.bits.ot_pp_csc_coef02 = coef->csc_coef02; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef02.u32); -+ -+ g0_ot_pp_csc_coef10.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef10.u32)); -+ g0_ot_pp_csc_coef10.bits.ot_pp_csc_coef10 = coef->csc_coef10; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef10.u32); -+ -+ g0_ot_pp_csc_coef11.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef11.u32)); -+ g0_ot_pp_csc_coef11.bits.ot_pp_csc_coef11 = coef->csc_coef11; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef11.u32); -+ -+ g0_ot_pp_csc_coef12.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef12.u32)); -+ g0_ot_pp_csc_coef12.bits.ot_pp_csc_coef12 = coef->csc_coef12; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef12.u32); -+ -+ g0_ot_pp_csc_coef20.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef20.u32)); -+ g0_ot_pp_csc_coef20.bits.ot_pp_csc_coef20 = coef->csc_coef20; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef20.u32); -+ -+ g0_ot_pp_csc_coef21.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef21.u32)); -+ g0_ot_pp_csc_coef21.bits.ot_pp_csc_coef21 = coef->csc_coef21; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef21.u32); -+ -+ g0_ot_pp_csc_coef22.u32 = hal_get_addr_abs(&addr_reg, layer, &(g_gfbg_reg->g0_ot_pp_csc_coef22.u32)); -+ g0_ot_pp_csc_coef22.bits.ot_pp_csc_coef22 = coef->csc_coef22; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_coef22.u32); -+ } else { -+ printk("Error layer id found in %s, %d\n", __FUNCTION__, __LINE__); -+ } -+ return; -+} -+ -+static void fb_hal_layer_csc_set_dc_coef(hal_disp_layer layer, const vdp_csc_dc_coef *csc_dc_coef) -+{ -+ volatile u_g0_ot_pp_csc_idc0 g0_ot_pp_csc_idc0; -+ volatile u_g0_ot_pp_csc_idc1 g0_ot_pp_csc_idc1; -+ volatile u_g0_ot_pp_csc_idc2 g0_ot_pp_csc_idc2; -+ volatile u_g0_ot_pp_csc_odc0 g0_ot_pp_csc_odc0; -+ volatile u_g0_ot_pp_csc_odc1 g0_ot_pp_csc_odc1; -+ volatile u_g0_ot_pp_csc_odc2 g0_ot_pp_csc_odc2; -+ volatile unsigned long addr_reg; -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_idc0.u32)); -+ g0_ot_pp_csc_idc0.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_idc0.bits.ot_pp_csc_idc0 = csc_dc_coef->csc_in_dc0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_idc0.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_idc1.u32)); -+ g0_ot_pp_csc_idc1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_idc1.bits.ot_pp_csc_idc1 = csc_dc_coef->csc_in_dc1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_idc1.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_idc2.u32)); -+ g0_ot_pp_csc_idc2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_idc2.bits.ot_pp_csc_idc2 = csc_dc_coef->csc_in_dc2; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_idc2.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_odc0.u32)); -+ g0_ot_pp_csc_odc0.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_odc0.bits.ot_pp_csc_odc0 = csc_dc_coef->csc_out_dc0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_odc0.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_odc1.u32)); -+ g0_ot_pp_csc_odc1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_odc1.bits.ot_pp_csc_odc1 = csc_dc_coef->csc_out_dc1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_odc1.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_odc2.u32)); -+ g0_ot_pp_csc_odc2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_odc2.bits.ot_pp_csc_odc2 = csc_dc_coef->csc_out_dc2; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_odc2.u32); -+ } else { -+ printk("Error layer id found in %s, %d\n", __FUNCTION__, __LINE__); -+ } -+} -+ -+static void fb_hal_layer_csc_set_param(hal_disp_layer layer, const csc_coef_param *coef_param) -+{ -+ volatile u_g0_ot_pp_csc_scale g0_ot_pp_csc_scale; -+ volatile u_g0_ot_pp_csc_min_y g0_ot_pp_csc_min_y; -+ volatile u_g0_ot_pp_csc_min_c g0_ot_pp_csc_min_c; -+ volatile u_g0_ot_pp_csc_max_y g0_ot_pp_csc_max_y; -+ volatile u_g0_ot_pp_csc_max_c g0_ot_pp_csc_max_c; -+ volatile unsigned long addr_reg; -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ if ((layer >= LAYER_GFX_START) && (layer <= LAYER_GFX_END)) { -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_scale.u32)); -+ g0_ot_pp_csc_scale.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_scale.bits.ot_pp_csc_scale = coef_param->csc_scale2p; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_scale.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_min_y.u32)); -+ g0_ot_pp_csc_min_y.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_min_y.bits.ot_pp_csc_min_y = coef_param->csc_clip_min; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_min_y.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_min_c.u32)); -+ g0_ot_pp_csc_min_c.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_min_c.bits.ot_pp_csc_min_c = coef_param->csc_clip_min; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_min_c.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_max_y.u32)); -+ g0_ot_pp_csc_max_y.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_max_y.bits.ot_pp_csc_max_y = coef_param->csc_clip_max; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_max_y.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_ot_pp_csc_max_c.u32)); -+ g0_ot_pp_csc_max_c.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ot_pp_csc_max_c.bits.ot_pp_csc_max_c = coef_param->csc_clip_max; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ot_pp_csc_max_c.u32); -+ } -+} -+ -+bool fb_hal_layer_set_csc_coef(hal_disp_layer layer, const csc_coef *coef) -+{ -+ if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX4)) { -+ printk("Error, Wrong layer ID!%d\n", __LINE__); -+ return false; -+ } -+ if (coef == NULL) { -+ printk("Error, null pointer\n"); -+ return false; -+ } -+ fb_hal_layer_csc_set_dc_coef(layer, (vdp_csc_dc_coef *)(&coef->csc_in_dc0)); -+ fb_hal_layer_csc_set_coef(layer, (vdp_csc_coef *)(&coef->csc_coef00)); -+ fb_hal_layer_csc_set_param(layer, (csc_coef_param *)(&coef->new_csc_scale2p)); -+ return true; -+} -+ -+//void *drm_gem_object_vmap(struct drm_gem_object *obj); -+const csc_coef g_csc_identity_limit = { -+ /* csc coef */ -+ 1024, 0, 0, 0, 1024, 0, 0, 0, 1024, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_identity_full = { -+ /* csc coef */ -+ 1024, 0, 0, 0, 1024, 0, 0, 0, 1024, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601full_to_yuv601limit = { -+ /* csc coef */ -+ 880, 0, 0, 0, 899, 0, 0, 0, 899, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv709limit_to_yuv601limit = { -+ /* csc coef */ -+ 1024, 102, 196, 0, 1014, -113, 0, -74, 1007, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv709full_to_yuv601limit = { -+ /* csc coef */ -+ 879, 89, 172, 0, 890, -100, 0, -65, 885, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601limit_to_yuv709limit = { -+ /* csc coef */ -+ 1024, -118, -213, 0, 1043, 117, 0, 77, 1050, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601full_to_yuv709limit = { -+ /* csc coef */ -+ 880, -103, -187, 0, 916, 102, 0, 67, 922, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv709full_to_yuv709limit = { -+ /* csc coef */ -+ 880, 0, 0, 0, 899, 0, 0, 0, 899, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601limit_to_yuv601full = { -+ /* csc coef */ -+ 1192, 0, 0, 0, 1165, 0, 0, 0, 1165, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv709limit_to_yuv601full = { -+ /* csc coef */ -+ 1192, 117, 222, 0, 1154, -128, 0, -84, 1146, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv709full_to_yuv601full = { -+ /* csc coef */ -+ 1024, 102, 196, 0, 1014, -113, 0, -74, 1007, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601limit_to_yuv709full = { -+ /* csc coef */ -+ 1192, -137, -248, 0, 1188, 133, 0, 87, 1194, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601full_to_yuv709full = { -+ /* csc coef */ -+ 1024, -118, -213, 0, 1043, 117, 0, 77, 1050, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv709limit_to_yuv709full = { -+ /* csc coef */ -+ 1192, 0, 0, 0, 1165, 0, 0, 0, 1165, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_yuv601limit_to_rgbfull = { -+ /* csc coef */ -+ 1192, 0, 1634, 1192, -400, -833, 1192, 2066, 0, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 0, 0, 0 -+}; -+ -+const csc_coef g_csc_yuv601full_to_rgbfull = { -+ /* csc coef */ -+ 1024, 0, 1436, 1024, -352, -731, 1024, 1815, 0, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 0, 0, 0 -+}; -+ -+const csc_coef g_csc_yuv709limit_to_rgbfull = { -+ /* csc coef */ -+ 1192, 0, 1836, 1192, -218, -547, 1192, 2166, 0, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 0, 0, 0 -+}; -+ -+const csc_coef g_csc_yuv709full_to_rgbfull = { -+ /* csc coef */ -+ 1024, 0, 1613, 1024, -192, -479, 1024, 1900, 0, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 0, 0, 0 -+}; -+ -+const csc_coef g_csc_yuv601limit_to_rgblimit = { -+ /* csc coef */ -+ 1024, 0, 1404, 1024, -344, -716, 1024, 1775, 0, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 16, 16, 16 -+}; -+ -+const csc_coef g_csc_yuv601full_to_rgblimit = { -+ /* csc coef */ -+ 880, 0, 1233, 880, -302, -629, 880, 1599, 0, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 16, 16, 16 -+}; -+ -+const csc_coef g_csc_yuv709limit_to_rgblimit = { -+ /* csc coef */ -+ 1024, 0, 1578, 1024, -187, -470, 1024, 1861, 0, -+ /* csc input dc */ -+ -16, -128, -128, -+ /* csc output dc */ -+ 16, 16, 16 -+}; -+ -+const csc_coef g_csc_yuv709full_to_rgblimit = { -+ /* csc coef */ -+ 880, 0, 1385, 880, -164, -413, 880, 1634, 0, -+ /* csc input dc */ -+ 0, -128, -128, -+ /* csc output dc */ -+ 16, 16, 16 -+}; -+ -+const csc_coef g_csc_rgbfull_to_yuv601limit = { -+ /* csc coef */ -+ 264, 516, 100, -152, -298, 450, 450, -377, -73, -+ /* csc input dc */ -+ 0, 0, 0, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_rgbfull_to_yuv601full = { -+ /* csc coef */ -+ 306, 601, 117, -173, -339, 512, 512, -429, -83, -+ /* csc input dc */ -+ 0, 0, 0, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+const csc_coef g_csc_rgbfull_to_yuv709limit = { -+ /* csc coef */ -+ 188, 629, 63, -103, -347, 450, 450, -409, -41, -+ /* csc input dc */ -+ 0, 0, 0, -+ /* csc output dc */ -+ 16, 128, 128 -+}; -+ -+const csc_coef g_csc_rgbfull_to_yuv709full = { -+ /* csc coef */ -+ 218, 732, 74, -117, -395, 512, 512, -465, -47, -+ /* csc input dc */ -+ 0, 0, 0, -+ /* csc output dc */ -+ 0, 128, 128 -+}; -+ -+/* sin table value, theta angle range[-30, 30], premultiplied by 1000 */ -+const int g_sin_table[61] = { /* 61 theta */ -+ -500, -485, -469, -454, -438, -422, -407, -391, -374, -358, -+ -342, -325, -309, -292, -276, -259, -242, -225, -208, -191, -+ -174, -156, -139, -122, -104, -87, -70, -52, -35, -17, -+ 0, 17, 35, 52, 70, 87, 104, 122, 139, 156, -+ 174, 191, 208, 225, 242, 259, 276, 292, 309, 325, -+ 342, 358, 374, 391, 407, 422, 438, 454, 469, 485, -+ 500 -+}; -+ -+/* cos table value, theta angle range[-30, 30], premultiplied by 1000 */ -+const int g_cos_table[61] = { /* 61 theta */ -+ 866, 875, 883, 891, 899, 906, 914, 921, 927, 934, -+ 940, 946, 951, 956, 961, 966, 970, 974, 978, 982, -+ 985, 988, 990, 993, 995, 996, 998, 999, 999, 1000, -+ 1000, 1000, 999, 999, 998, 996, 995, 993, 990, 988, -+ 985, 982, 978, 974, 970, 966, 961, 956, 951, 946, -+ 940, 934, 927, 921, 914, 906, 899, 891, 883, 875, -+ 866 -+}; -+ -+const csc_coef *g_csc_coef[OT_VO_CSC_MATRIX_BUTT] = { -+ &g_csc_identity_limit, -+ &g_csc_yuv601full_to_yuv601limit, -+ &g_csc_yuv709limit_to_yuv601limit, -+ &g_csc_yuv709full_to_yuv601limit, -+ &g_csc_yuv601limit_to_yuv709limit, -+ &g_csc_yuv601full_to_yuv709limit, -+ &g_csc_identity_limit, -+ &g_csc_yuv709full_to_yuv709limit, -+ &g_csc_yuv601limit_to_yuv601full, -+ &g_csc_identity_full, -+ &g_csc_yuv709limit_to_yuv601full, -+ &g_csc_yuv709full_to_yuv601full, -+ &g_csc_yuv601limit_to_yuv709full, -+ &g_csc_yuv601full_to_yuv709full, -+ &g_csc_yuv709limit_to_yuv709full, -+ &g_csc_identity_full, -+ &g_csc_yuv601limit_to_rgbfull, -+ &g_csc_yuv601full_to_rgbfull, -+ &g_csc_yuv709limit_to_rgbfull, -+ &g_csc_yuv709full_to_rgbfull, -+ &g_csc_yuv601limit_to_rgblimit, -+ &g_csc_yuv601full_to_rgblimit, -+ &g_csc_yuv709limit_to_rgblimit, -+ &g_csc_yuv709full_to_rgblimit, -+ &g_csc_rgbfull_to_yuv601limit, -+ &g_csc_rgbfull_to_yuv601full, -+ &g_csc_rgbfull_to_yuv709limit, -+ &g_csc_rgbfull_to_yuv709full, -+}; -+ -+bool fb_hal_graphic_set_gfx_key_mode(hal_disp_layer layer, unsigned int key_out) -+{ -+ volatile u_gfx_out_ctrl gfx_out_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); -+ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_out_ctrl.bits.key_mode = key_out; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); -+ } else { -+ printk("Error layer id %d not support colorkey mode in %s: L%d\n", -+ (int)layer, __FUNCTION__, __LINE__); -+ return false; -+ } -+ return true; -+} -+ -+bool fb_hal_graphic_set_gfx_key_en(hal_disp_layer layer, unsigned int key_enable) -+{ -+ volatile u_gfx_out_ctrl gfx_out_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_out_ctrl.u32)); -+ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_out_ctrl.bits.enable = key_enable; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); -+ } else { -+ printk("Error layer id %d not support colorkey in %s: L%d\n", -+ (int)layer, __FUNCTION__, __LINE__); -+ return false; -+ } -+ return true; -+} -+/* -+ * Name : hal_graphic_get_gfx_addr -+ * Desc : get layer addr. -+ */ -+bool fb_hal_graphic_get_gfx_addr(hal_disp_layer layer, phys_addr_t *gfx_addr) -+{ -+ volatile unsigned long addr_reg; -+ volatile phys_addr_t addr_h = 0x0; -+ volatile phys_addr_t addr_l = 0x0; -+ -+ if ((g_gfbg_reg == NULL) || (gfx_addr == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ if (layer == HAL_DISP_LAYER_GFX0 || -+ layer == HAL_DISP_LAYER_GFX1 || -+ layer == HAL_DISP_LAYER_GFX2 || -+ layer == HAL_DISP_LAYER_GFX3 || -+ layer == HAL_DISP_LAYER_GFX4) { -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_l)); -+ addr_l = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ addr_reg = fb_vou_get_gfx_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->gfx_addr_h)); -+ addr_h = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ } else { -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ *gfx_addr = addr_l + ((unsigned long long)addr_h << 32); /* 32 max address */ -+ return true; -+} -+ -+static void graphic_drv_cfg_zme_info(gf_zme_cfg *cfg) -+{ -+ cfg->ck_gt_en = 1; -+ cfg->out_pro = VDP_RMODE_PROGRESSIVE; -+ cfg->lhmid_en = 1; -+ cfg->ahmid_en = 1; -+ cfg->lhfir_mode = 1; -+ cfg->ahfir_mode = 1; -+ cfg->lvmid_en = 1; -+ cfg->avmid_en = 1; -+ cfg->lvfir_mode = 1; -+ cfg->avfir_mode = 1; -+} -+ -+/********************************************************************************** -+* Begin : Graphic layer ZME relative hal functions. -+**********************************************************************************/ -+void hal_g0_zme_set_ck_gt_en(unsigned int ck_gt_en) -+{ -+ volatile u_g0_zme_hinfo g0_zme_hinfo; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32)); -+ g0_zme_hinfo.bits.ck_gt_en = ck_gt_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32), g0_zme_hinfo.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_out_width(unsigned int out_width) -+{ -+ volatile u_g0_zme_hinfo g0_zme_hinfo; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32)); -+ g0_zme_hinfo.bits.out_width = out_width - 1; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hinfo.u32), g0_zme_hinfo.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_hfir_en(unsigned int hfir_en) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.hfir_en = hfir_en; -+ -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_ahfir_mid_en(unsigned int ahfir_mid_en) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.ahfir_mid_en = ahfir_mid_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_lhfir_mid_en(unsigned int lhfir_mid_en) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.lhfir_mid_en = lhfir_mid_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_chfir_mid_en(unsigned int chfir_mid_en) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.chfir_mid_en = chfir_mid_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_lhfir_mode(unsigned int lhfir_mode) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.lhfir_mode = lhfir_mode; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_ahfir_mode(unsigned int ahfir_mode) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.ahfir_mode = ahfir_mode; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_hfir_order(unsigned int hfir_order) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.hfir_order = hfir_order; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_hratio(unsigned int hratio) -+{ -+ volatile u_g0_zme_hsp g0_zme_hsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32)); -+ g0_zme_hsp.bits.hratio = hratio; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hsp.u32), g0_zme_hsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_lhfir_offset(unsigned int lhfir_offset) -+{ -+ volatile u_g0_zme_hloffset g0_zme_hloffset; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hloffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hloffset.u32)); -+ g0_zme_hloffset.bits.lhfir_offset = lhfir_offset; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hloffset.u32), g0_zme_hloffset.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_chfir_offset(unsigned int chfir_offset) -+{ -+ volatile u_g0_zme_hcoffset g0_zme_hcoffset; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_hcoffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hcoffset.u32)); -+ g0_zme_hcoffset.bits.chfir_offset = chfir_offset; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_hcoffset.u32), g0_zme_hcoffset.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_out_pro(unsigned int out_pro) -+{ -+ volatile u_g0_zme_vinfo g0_zme_vinfo; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32)); -+ g0_zme_vinfo.bits.out_pro = out_pro; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32), g0_zme_vinfo.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_out_height(unsigned int out_height) -+{ -+ volatile u_g0_zme_vinfo g0_zme_vinfo; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vinfo.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32)); -+ g0_zme_vinfo.bits.out_height = out_height - 1; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vinfo.u32), g0_zme_vinfo.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_vfir_en(unsigned int vfir_en) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.vfir_en = vfir_en; -+ -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_avfir_mid_en(unsigned int avfir_mid_en) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.avfir_mid_en = avfir_mid_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_lvfir_mid_en(unsigned int lvfir_mid_en) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.lvfir_mid_en = lvfir_mid_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_cvfir_mid_en(unsigned int cvfir_mid_en) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.cvfir_mid_en = cvfir_mid_en; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_lvfir_mode(unsigned int lvfir_mode) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.lvfir_mode = lvfir_mode; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_vafir_mode(unsigned int vafir_mode) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.vafir_mode = vafir_mode; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_vratio(unsigned int vratio) -+{ -+ volatile u_g0_zme_vsp g0_zme_vsp; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_vsp.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32)); -+ g0_zme_vsp.bits.vratio = vratio; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_vsp.u32), g0_zme_vsp.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_vtp_offset(unsigned int vtp_offset) -+{ -+ volatile u_g0_zme_voffset g0_zme_voffset; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_voffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32)); -+ g0_zme_voffset.bits.vtp_offset = vtp_offset; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32), g0_zme_voffset.u32); -+ -+ return; -+} -+ -+void hal_g0_zme_set_vbtm_offset(unsigned int vbtm_offset) -+{ -+ volatile u_g0_zme_voffset g0_zme_voffset; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ g0_zme_voffset.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32)); -+ g0_zme_voffset.bits.vbtm_offset = vbtm_offset; -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->g0_zme_voffset.u32), g0_zme_voffset.u32); -+ -+ return; -+} -+ -+void gf_func_set_g0zme_mode(unsigned int layer, gf_g0_zme_mode g0_zme_mode, const gf_zme_cfg *cfg) -+{ -+ /* filed declare */ -+ const unsigned int hfir_order = 1; -+ int lhfir_offset = 0; -+ int chfir_offset = 0; -+ int vtp_offset = 0; -+ int vbtm_offset = 0; -+ -+ const unsigned long zme_hprec = ZME_HPREC; -+ const unsigned long zme_vprec = ZME_VPREC; -+ unsigned int hratio, vratio; -+ -+ -+ if (cfg == NULL) { -+ return; -+ } -+ hratio = (cfg->in_width * zme_hprec) / cfg->out_width; -+ vratio = (cfg->in_height * zme_vprec) / cfg->out_height; -+ if (g0_zme_mode == VDP_G0_ZME_TYP) { -+ /* typ mode */ -+ lhfir_offset = 0; -+ chfir_offset = 0; -+ vtp_offset = 0; -+ vbtm_offset = (-1) * (long long)zme_vprec / 2; /* 2 alg data */ -+ } -+ /* drv transfer */ -+ hal_g0_zme_set_ck_gt_en(cfg->ck_gt_en); -+ hal_g0_zme_set_out_width(cfg->out_width); -+ hal_g0_zme_set_hfir_en(cfg->hfir_en); -+ hal_g0_zme_set_ahfir_mid_en(cfg->ahmid_en); -+ hal_g0_zme_set_lhfir_mid_en(cfg->lhmid_en); -+ hal_g0_zme_set_chfir_mid_en(cfg->lhmid_en); -+ hal_g0_zme_set_lhfir_mode(cfg->lhfir_mode); -+ hal_g0_zme_set_ahfir_mode(cfg->ahfir_mode); -+ hal_g0_zme_set_hfir_order(hfir_order); -+ hal_g0_zme_set_hratio(hratio); -+ hal_g0_zme_set_lhfir_offset(lhfir_offset); -+ hal_g0_zme_set_chfir_offset(chfir_offset); -+ hal_g0_zme_set_out_pro(cfg->out_pro); -+ hal_g0_zme_set_out_height(cfg->out_height); -+ hal_g0_zme_set_vfir_en(cfg->vfir_en); -+ hal_g0_zme_set_avfir_mid_en(cfg->avmid_en); -+ hal_g0_zme_set_lvfir_mid_en(cfg->lvmid_en); -+ hal_g0_zme_set_cvfir_mid_en(cfg->lvmid_en); -+ hal_g0_zme_set_lvfir_mode(cfg->lvfir_mode); -+ hal_g0_zme_set_vafir_mode(cfg->avfir_mode); -+ hal_g0_zme_set_vratio(vratio); -+ hal_g0_zme_set_vtp_offset(vtp_offset); -+ hal_g0_zme_set_vbtm_offset(vbtm_offset); -+} -+ -+bool fb_hal_video_set_layer_disp_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_g0_dfpos g0_dfpos; -+ volatile u_g0_dlpos g0_dlpos; -+ volatile unsigned long addr_reg; -+ -+ if ((g_gfbg_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_dfpos.u32)); -+ g0_dfpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_dfpos.bits.disp_xfpos = rect->x; -+ g0_dfpos.bits.disp_yfpos = rect->y; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_dfpos.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_dlpos.u32)); -+ g0_dlpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_dlpos.bits.disp_xlpos = rect->x + rect->width - 1; -+ g0_dlpos.bits.disp_ylpos = rect->y + rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_dlpos.u32); -+ break; -+ default: -+ printk("Error layer id found in %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+bool fb_hal_video_set_layer_video_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_g0_vfpos g0_vfpos; -+ volatile u_g0_vlpos g0_vlpos; -+ volatile unsigned long addr_reg; -+ -+ if ((g_gfbg_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_GFX0: -+ case HAL_DISP_LAYER_GFX1: -+ case HAL_DISP_LAYER_GFX2: -+ case HAL_DISP_LAYER_GFX3: -+ case HAL_DISP_LAYER_GFX4: -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_vfpos.u32)); -+ g0_vfpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_vfpos.bits.video_xfpos = rect->x; -+ g0_vfpos.bits.video_yfpos = rect->y; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_vfpos.u32); -+ -+ addr_reg = fb_vou_get_abs_addr(layer, (unsigned long)(uintptr_t)&(g_gfbg_reg->g0_vlpos.u32)); -+ g0_vlpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_vlpos.bits.video_xlpos = rect->x + rect->width - 1; -+ g0_vlpos.bits.video_ylpos = rect->y + rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_vlpos.u32); -+ break; -+ default: -+ printk("Error layer id %d# found in %s: L%d\n", layer, __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ return true; -+} -+ -+const csc_coef *vo_get_csc_coef(ot_vo_csc_matrix csc_matrix) -+{ -+ if ((csc_matrix >= OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT601LIMIT) && -+ (csc_matrix < OT_VO_CSC_MATRIX_BUTT)) { -+ return g_csc_coef[csc_matrix]; -+ } -+ -+ return NULL; -+} -+ -+int vo_drv_get_csc_matrix(ot_vo_csc_matrix csc_matrix, const csc_coef **csc_tmp) -+{ -+ *csc_tmp = vo_get_csc_coef(csc_matrix); -+ if (*csc_tmp == NULL) { -+ return -1; -+ } -+ return 0; -+} -+ -+static int graphic_drv_calc_csc_matrix(const vo_csc *csc, hal_csc_mode csc_mode, csc_coef *coef) -+{ -+ int luma, contrast, hue, satu; -+ -+ const csc_coef *csc_tmp = NULL; -+ int ret; -+ -+ luma = (int)csc->luma * 64 / 100 - 32; /* 64 100 32 alg data */ -+ contrast = ((int)csc->contrast - 50) * 2 + 100; /* 50 2 100 alg data */ -+ hue = (int)csc->hue * 60 / 100; /* 60 100 alg data */ -+ satu = ((int)csc->satuature - 50) * 2 + 100; /* 50 2 100 alg data */ -+ -+ ret = vo_drv_get_csc_matrix(csc_mode, &csc_tmp); -+ if (ret != 0) { -+ return ret; -+ } -+ coef->csc_in_dc0 = csc_tmp->csc_in_dc0; -+ coef->csc_in_dc1 = csc_tmp->csc_in_dc1; -+ coef->csc_in_dc2 = csc_tmp->csc_in_dc2; -+ coef->csc_out_dc0 = csc_tmp->csc_out_dc0; -+ coef->csc_out_dc1 = csc_tmp->csc_out_dc1; -+ coef->csc_out_dc2 = csc_tmp->csc_out_dc2; -+ /* -+ * C_ratio normally is 0~1.99, C_ratio=s32Contrast/100 -+ * S normally is 0~1.99,S=s32Satu/100 -+ * Hue -30~30, using the lut to get COS and SIN and then /1000 -+ */ -+ coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / 100; /* 100 alg data */ -+ coef->csc_coef01 = (contrast * csc_tmp->csc_coef01) / 100; /* 100 alg data */ -+ coef->csc_coef02 = (contrast * csc_tmp->csc_coef02) / 100; /* 100 alg data */ -+ if (hue >= GFX_MAX_CSC_TABLE) { -+ printk("hue(%u) is invalid!\n", (unsigned int)hue); -+ return -1; -+ } -+ coef->csc_coef10 = (contrast * satu * ((csc_tmp->csc_coef10 * g_cos_table[hue] + -+ csc_tmp->csc_coef20 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ -+ coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * g_cos_table[hue] + -+ csc_tmp->csc_coef21 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ -+ coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef12 * g_cos_table[hue] + -+ csc_tmp->csc_coef22 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ -+ coef->csc_coef20 = (contrast * satu * ((csc_tmp->csc_coef20 * g_cos_table[hue] - -+ csc_tmp->csc_coef10 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ -+ coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * g_cos_table[hue] - -+ csc_tmp->csc_coef11 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ -+ coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef22 * g_cos_table[hue] - -+ csc_tmp->csc_coef12 * g_sin_table[hue]) / 1000)) / 10000; /* 1000 10000 alg data */ -+ coef->csc_out_dc0 += luma; -+ -+ return 0; -+} -+ -+int fb_graphic_drv_set_csc_coef(hal_disp_layer gfx_layer, const vo_csc *gfx_csc, const csc_coef_param *csc_param) -+{ -+ csc_coef coef; -+ hal_csc_mode csc_mode = gfx_csc->csc_matrix;//HAL_CSC_MODE_BT601FULL_TO_BT601FULL;//HAL_CSC_MODE_BT709FULL_TO_RGBFULL; -+ int ret; -+ const unsigned int dc_pre = 4; -+ unsigned int layer_index; -+ -+ if (gfx_csc == NULL || csc_param == NULL) { -+ return -1; -+ } -+ -+ /* cal CSC coef and CSC dc coef */ -+ ret = graphic_drv_calc_csc_matrix(gfx_csc, csc_mode, &coef); -+ if (ret != 0) { -+ printk("gfx_layer(%u) calculate CSC materix failed!\n", (unsigned int)gfx_layer); -+ return ret; -+ } -+ -+ coef.new_csc_clip_max = GFX_CSC_CLIP_MAX; -+ coef.new_csc_clip_min = GFX_CSC_CLIP_MIN; -+ coef.new_csc_scale2p = GFX_CSC_SCALE; -+ -+ coef.csc_in_dc0 = (int)dc_pre * coef.csc_in_dc0; -+ coef.csc_in_dc1 = (int)dc_pre * coef.csc_in_dc1; -+ coef.csc_in_dc2 = (int)dc_pre * coef.csc_in_dc2; -+ -+ coef.csc_out_dc0 = (int)dc_pre * coef.csc_out_dc0; -+ coef.csc_out_dc1 = (int)dc_pre * coef.csc_out_dc1; -+ coef.csc_out_dc2 = (int)dc_pre * coef.csc_out_dc2; -+ -+ /* set CSC coef and CSC dc coef */ -+ fb_hal_layer_set_csc_coef(gfx_layer, &coef); -+ -+ -+ return 0; -+} -+ -+void fb_hal_set_layer_ck_gt_en(hal_disp_layer layer, unsigned int ck_gt_en) -+{ -+ volatile u_voctrl voctrl; -+ volatile unsigned long addr_reg; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return; -+ } -+ -+ addr_reg = (unsigned long)(uintptr_t)&(g_gfbg_reg->voctrl.u32); -+ voctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_GFX0: -+ voctrl.bits.g0_ck_gt_en = ck_gt_en; -+ break; -+ case HAL_DISP_LAYER_GFX1: -+ voctrl.bits.g1_ck_gt_en = ck_gt_en; -+ break; -+ case HAL_DISP_LAYER_GFX3: -+ voctrl.bits.g3_ck_gt_en = ck_gt_en; -+ break; -+ default: -+ /* Logic aren't configured for G2. Don't write the configuration to avoid affecting other layers. */ -+ return; -+ } -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, voctrl.u32); -+} -+ -+ -+extern int drm_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map); -+extern void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map); -+bool vo_hal_is_video_layer(hal_disp_layer layer) -+{ -+ if ((layer >= LAYER_VID_START) && (layer <= LAYER_VID_END)) { -+ return true; -+ } -+ -+ return false; -+} -+static volatile reg_vdp_regs *g_vo_reg = NULL; -+ -+volatile reg_vdp_regs *vo_hal_get_reg(void) -+{ -+ return g_vo_reg; -+} -+ -+void hal_video_set_layer_alpha(hal_disp_layer layer, unsigned int alpha) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_alpha v0_alpha; -+ volatile reg_g0_alpha g0_alpha; -+ volatile unsigned long addr_reg; -+ -+ -+ if (vo_hal_is_video_layer(layer)) { -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_alpha.u32)); -+ v0_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_alpha.bits.vbk_alpha = alpha; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_alpha.u32); -+ return; -+ } -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->g0_alpha.u32)); -+ g0_alpha.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_alpha.bits.vbk_alpha = alpha; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_alpha.u32); -+} -+ -+void hal_layer_set_layer_global_alpha(hal_disp_layer layer, unsigned char alpha0) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_ctrl v0_ctrl; -+ volatile reg_g0_ctrl g0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ if (vo_hal_is_video_layer(layer)) { -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_ctrl.u32)); -+ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_ctrl.bits.galpha = alpha0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); -+ return; -+ } -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->g0_ctrl.u32)); -+ g0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ g0_ctrl.bits.galpha = alpha0; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, g0_ctrl.u32); -+} -+ -+void hal_gfx_set_pixel_alpha_range(hal_disp_layer layer, unsigned int alpha_range) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_gfx_out_ctrl gfx_out_ctrl; -+ volatile unsigned long addr_reg; -+ addr_reg = vou_get_gfx_abs_addr(layer, (uintptr_t)&(vo_reg->gfx_out_ctrl.u32)); -+ gfx_out_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ gfx_out_ctrl.bits.palpha_range = alpha_range; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, gfx_out_ctrl.u32); -+} -+ -+void hal_video_hfir_set_hfir_mode(hal_disp_layer layer, unsigned int hfir_mode) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfir_ctrl.u32)); -+ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_ctrl.bits.hfir_mode = hfir_mode; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); -+} -+ -+void hal_video_hfir_set_coef(hal_disp_layer layer, const hfir_coef *coef) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_hfircoef01 v0_hfir_coef01; -+ volatile reg_v0_hfircoef23 v0_hfir_coef23; -+ volatile reg_v0_hfircoef45 v0_hfir_coef45; -+ volatile reg_v0_hfircoef67 v0_hfir_coef67; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef01.u32)); -+ v0_hfir_coef01.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_coef01.bits.coef0 = coef->coef0; -+ v0_hfir_coef01.bits.coef1 = coef->coef1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef01.u32); -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef23.u32)); -+ v0_hfir_coef23.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_coef23.bits.coef2 = coef->coef2; -+ v0_hfir_coef23.bits.coef3 = coef->coef3; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef23.u32); -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef45.u32)); -+ v0_hfir_coef45.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_coef45.bits.coef4 = coef->coef4; -+ v0_hfir_coef45.bits.coef5 = coef->coef5; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef45.u32); -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfircoef67.u32)); -+ v0_hfir_coef67.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_coef67.bits.coef6 = coef->coef6; -+ v0_hfir_coef67.bits.coef7 = coef->coef7; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_coef67.u32); -+} -+ -+void hal_video_hfir_set_mid_en(hal_disp_layer layer, unsigned int mid_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; -+ volatile unsigned long addr_reg; -+ -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfir_ctrl.u32)); -+ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_ctrl.bits.mid_en = mid_en; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); -+} -+ -+unsigned long vou_get_chn_abs_addr(ot_vo_dev dev, unsigned long reg) -+{ -+ volatile unsigned long reg_abs_addr; -+ -+ switch (dev) { -+ case VO_DEV_DHD0: -+ case VO_DEV_DHD1: -+ reg_abs_addr = reg + (dev - VO_DEV_DHD0) * DHD_REGS_LEN; -+ break; -+ -+ default: -+ printk("invalid dev %d!\n", dev); -+ reg_abs_addr = reg; -+ break; -+ } -+ -+ return reg_abs_addr; -+} -+ -+void hal_disp_set_reg_up(ot_vo_dev dev) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_dhd0_ctrl dhd0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); -+ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_ctrl.bits.regup = 0x1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); -+} -+ -+void hal_video_hfir_set_ck_gt_en(hal_disp_layer layer, unsigned int ck_gt_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_hfir_ctrl.u32)); -+ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_hfir_ctrl.bits.ck_gt_en = ck_gt_en; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); -+} -+ -+void hal_layer_enable_layer(hal_disp_layer layer, unsigned int enable) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_v0_ctrl v0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_abs_addr(layer, (uintptr_t)&(vo_reg->v0_ctrl.u32)); -+ v0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_ctrl.bits.surface_en = enable; -+ v0_ctrl.bits.nosec_flag = 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_ctrl.u32); -+} -+ -+void hal_video_set_layer_ck_gt_en(hal_disp_layer layer, bool ck_gt_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_voctrl voctrl; -+ /* v3 not support to return */ -+ if (layer > HAL_DISP_LAYER_VHD2) { -+ return; -+ } -+ -+ voctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->voctrl.u32)); -+ if (layer == HAL_DISP_LAYER_VHD0) { -+ voctrl.bits.v0_ck_gt_en = ck_gt_en; -+ } else if (layer == HAL_DISP_LAYER_VHD1) { -+ voctrl.bits.v1_ck_gt_en = ck_gt_en; -+ } else { -+ voctrl.bits.v2_ck_gt_en = ck_gt_en; -+ } -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->voctrl.u32), voctrl.u32); -+} -+ -+unsigned long vou_get_vid_abs_addr(hal_disp_layer layer, unsigned long reg) -+{ -+ volatile unsigned long reg_abs_addr; -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: -+ reg_abs_addr = reg + (layer - HAL_DISP_LAYER_VHD0) * VID_REGS_LEN; -+ break; -+ -+ default: -+ printk("invalid layer %d!\n", layer); -+ reg_abs_addr = reg; -+ break; -+ } -+ -+ return reg_abs_addr; -+} -+ -+void hal_layer_set_layer_data_fmt(hal_disp_layer layer, hal_disp_pixel_format data_fmt) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vid_src_info vid_src_info; -+ volatile unsigned long addr_reg; -+ -+ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(vo_reg->vid_src_info.u32)); -+ vid_src_info.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ vid_src_info.bits.data_type = data_fmt; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, vid_src_info.u32); -+} -+ -+bool hal_layer_set_src_resolution(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_vid_src_reso vid_src_reso; -+ volatile unsigned long addr_reg; -+ -+ if ((g_vo_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->vid_src_reso.u32); -+ vid_src_reso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ vid_src_reso.bits.src_w = rect->width - 1; -+ vid_src_reso.bits.src_h = rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, vid_src_reso.u32); -+ return true; -+} -+ -+bool hal_layer_set_layer_in_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_vid_in_reso vid_in_reso; -+ volatile unsigned long addr_reg; -+ -+ if ((g_vo_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ -+ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->vid_in_reso.u32); -+ vid_in_reso.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ vid_in_reso.bits.ireso_w = rect->width - 1; -+ vid_in_reso.bits.ireso_h = rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, vid_in_reso.u32); -+ -+ return true; -+} -+ -+bool hal_video_set_layer_disp_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_v0_dfpos v0_dfpos; -+ volatile u_v0_dlpos v0_dlpos; -+ volatile unsigned long addr_reg; -+ -+ if ((g_vo_reg == NULL) || (rect == NULL)) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->v0_dfpos.u32); -+ v0_dfpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_dfpos.bits.disp_xfpos = rect->x; -+ v0_dfpos.bits.disp_yfpos = rect->y; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_dfpos.u32); -+ -+ addr_reg = (unsigned long)(uintptr_t)&(g_vo_reg->v0_dlpos.u32); -+ v0_dlpos.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ v0_dlpos.bits.disp_xlpos = rect->x + rect->width - 1; -+ v0_dlpos.bits.disp_ylpos = rect->y + rect->height - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, v0_dlpos.u32); -+ -+ return true; -+} -+ -+const int *vo_get_sin_table(void) -+{ -+ return g_sin_table; -+} -+ -+const int *vo_get_cos_table(void) -+{ -+ return g_cos_table; -+} -+ -+void vo_drv_calculate_yuv2rgb(const hal_csc_value *csc_value, const csc_coef *csc_tmp, csc_coef *coef) -+{ -+ int luma; -+ int contrast; -+ int hue; -+ int satu; -+ const int csc_value_times = 100; -+ const int table_times = 1000; -+ int square_cv_times = csc_value_times * csc_value_times; -+ const int *cos_table = vo_get_cos_table(); -+ const int *sin_table = vo_get_sin_table(); -+ -+ luma = csc_value->luma; -+ contrast = csc_value->cont; -+ hue = csc_value->hue; -+ satu = csc_value->satu; -+ -+ /* yuv->rgb */ -+ coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / csc_value_times; -+ coef->csc_coef01 = (contrast * satu * ((csc_tmp->csc_coef01 * cos_table[hue] - csc_tmp->csc_coef02 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef02 = (contrast * satu * ((csc_tmp->csc_coef01 * sin_table[hue] + csc_tmp->csc_coef02 * -+ cos_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef10 = (contrast * csc_tmp->csc_coef10) / csc_value_times; -+ coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * cos_table[hue] - csc_tmp->csc_coef12 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef11 * sin_table[hue] + csc_tmp->csc_coef12 * -+ cos_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef20 = (contrast * csc_tmp->csc_coef20) / csc_value_times; -+ coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * cos_table[hue] - csc_tmp->csc_coef22 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef21 * sin_table[hue] + csc_tmp->csc_coef22 * -+ cos_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_in_dc0 += ((contrast != 0) ? (luma * 100 / contrast) : (luma * 100)); /* 100 : trans coef */ -+} -+ -+void vo_drv_calculate_rgb2yuv(const hal_csc_value *csc_value, const csc_coef *csc_tmp, csc_coef *coef) -+{ -+ int luma; -+ int contrast; -+ int hue; -+ int satu; -+ const int csc_value_times = 100; -+ const int table_times = 1000; -+ int square_cv_times = csc_value_times * csc_value_times; -+ const int *cos_table = vo_get_cos_table(); -+ const int *sin_table = vo_get_sin_table(); -+ -+ luma = csc_value->luma; -+ contrast = csc_value->cont; -+ hue = csc_value->hue; -+ satu = csc_value->satu; -+ -+ /* rgb->yuv or yuv->yuv */ -+ coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / csc_value_times; -+ coef->csc_coef01 = (contrast * csc_tmp->csc_coef01) / csc_value_times; -+ coef->csc_coef02 = (contrast * csc_tmp->csc_coef02) / csc_value_times; -+ coef->csc_coef10 = (contrast * satu * ((csc_tmp->csc_coef10 * cos_table[hue] + csc_tmp->csc_coef20 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * cos_table[hue] + csc_tmp->csc_coef21 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef12 * cos_table[hue] + csc_tmp->csc_coef22 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef20 = (contrast * satu * ((csc_tmp->csc_coef20 * cos_table[hue] - csc_tmp->csc_coef10 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * cos_table[hue] - csc_tmp->csc_coef11 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef22 * cos_table[hue] - csc_tmp->csc_coef12 * -+ sin_table[hue]) / table_times)) / square_cv_times; -+ coef->csc_out_dc0 += luma; -+} -+ -+void vou_drv_calc_csc_matrix(const ot_vo_csc *csc, ot_vo_csc_matrix csc_matrix, csc_coef *coef) -+{ -+ int ret; -+ const csc_coef *csc_tmp = NULL; -+ hal_csc_value csc_value; -+ -+ if (csc->ex_csc_en == 0) { -+ csc_value.luma = (int)csc->luma * 64 / 100 - 32; /* 64: -32~32 100: trans coef */ -+ } else { -+ csc_value.luma = (int)csc->luma * 256 / 100 - 128; /* 256: -128~128 128 100 */ -+ } -+ -+ csc_value.cont = ((int)csc->contrast - 50) * 2 + 100; /* 50 2 100 trans coef */ -+ csc_value.hue = (int)csc->hue * 60 / 100; /* 60 100 trans coef */ -+ csc_value.satu = ((int)csc->saturation - 50) * 2 + 100; /* 50 2 100 trans coef */ -+ -+ ret = vo_drv_get_csc_matrix(csc_matrix, &csc_tmp); -+ if (ret != 0) { -+ return; -+ } -+ -+ coef->csc_in_dc0 = csc_tmp->csc_in_dc0; -+ coef->csc_in_dc1 = csc_tmp->csc_in_dc1; -+ coef->csc_in_dc2 = csc_tmp->csc_in_dc2; -+ coef->csc_out_dc0 = csc_tmp->csc_out_dc0; -+ coef->csc_out_dc1 = csc_tmp->csc_out_dc1; -+ coef->csc_out_dc2 = csc_tmp->csc_out_dc2; -+ -+ /* -+ * c_ratio的调节范围一般是0�?1.99, c_ratio=contrast/100 -+ * S的调节范围一般为0~1.99, S=satu/100 -+ * 色调调节参数的范围一般为-30°~30°, 通过查表法求得COS和SIN值并/1000 -+ */ -+ if ((csc_matrix >= OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBFULL) && -+ (csc_matrix <= OT_VO_CSC_MATRIX_BT709FULL_TO_RGBLIMIT)) { -+ vo_drv_calculate_yuv2rgb(&csc_value, csc_tmp, coef); -+ } else { -+ vo_drv_calculate_rgb2yuv(&csc_value, csc_tmp, coef); -+ } -+} -+ -+void vo_drv_csc_trans_to_register(csc_coef *coef) -+{ -+ const int dc_precision = 4; /* 4: reg precision is 10bit coef dc precision, need trans 10-8=2,2^2=4 */ -+ /* csc coef is 1024 precision, no need trans */ -+ coef->csc_in_dc0 = dc_precision * coef->csc_in_dc0; -+ coef->csc_in_dc1 = dc_precision * coef->csc_in_dc1; -+ coef->csc_in_dc2 = dc_precision * coef->csc_in_dc2; -+ -+ coef->csc_out_dc0 = dc_precision * coef->csc_out_dc0; -+ coef->csc_out_dc1 = dc_precision * coef->csc_out_dc1; -+ coef->csc_out_dc2 = dc_precision * coef->csc_out_dc2; -+} -+ -+void vo_hal_intf_set_hdmi_csc_dc_coef(const vdp_csc_dc_coef *csc_dc_coef); -+void vo_hal_intf_set_hdmi_csc_coef(const vdp_csc_coef *coef); -+ -+void vo_hal_intf_set_csc_cfg(ot_vo_intf_type intf, const csc_coef *csc_cfg) -+{ -+ const vdp_csc_dc_coef *csc_dc_coef = (vdp_csc_dc_coef *)(&csc_cfg->csc_in_dc0); -+ const vdp_csc_coef *coef = (vdp_csc_coef *)(&csc_cfg->csc_coef00); -+ -+ switch (intf) { -+ case OT_VO_INTF_HDMI: -+ vo_hal_intf_set_hdmi_csc_dc_coef(csc_dc_coef); -+ vo_hal_intf_set_hdmi_csc_coef(coef); -+ break; -+ default: -+ return; -+ } -+} -+ -+void vou_drv_intf_csc_config(ot_vo_intf_type intf, const ot_vo_csc *csc) -+{ -+ csc_coef coef; -+ (void)memset(&coef, 0x0, sizeof(csc_coef)); -+ vou_drv_calc_csc_matrix(csc, csc->csc_matrix, &coef); -+ vo_drv_csc_trans_to_register(&coef); -+ vo_hal_intf_set_csc_cfg(intf, &coef); -+} -+ -+void hal_disp_set_hdmi_mode(ot_vo_dev dev, unsigned int color_space) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_dhd0_ctrl dhd0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); -+ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_ctrl.bits.hdmi_mode = color_space; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); -+} -+ -+static void vo_drv_set_hdmi_mode(ot_vo_dev dev, const struct vop *hdmi_param) -+{ -+ if ((hdmi_param->csc.csc_matrix >= OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBFULL) && -+ (hdmi_param->csc.csc_matrix <= OT_VO_CSC_MATRIX_BT709FULL_TO_RGBLIMIT)) { -+ hal_disp_set_hdmi_mode(dev, 1); /* 1: RGB */ -+ } else { -+ hal_disp_set_hdmi_mode(dev, 0); /* 0: YUV */ -+ } -+} -+ -+bool hal_overlay_set_gfx_addr(hal_disp_layer layer, phys_addr_t laddr) -+{ -+ volatile unsigned long vid_addr_h; -+ volatile unsigned long vid_addr_l; -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ /* Write low address to register. */ -+ vid_addr_l = (unsigned long)(uintptr_t)&(g_gfbg_reg->vid_addr_l); -+ hal_write_reg((unsigned int *)(uintptr_t)vid_addr_l, get_low_addr(laddr)); -+ -+ /* Write high address to register. */ -+ vid_addr_h = (unsigned long)(uintptr_t)&(g_gfbg_reg->vid_addr_h); -+ hal_write_reg((unsigned int *)(uintptr_t)vid_addr_h, get_high_addr(laddr)); -+ -+ return true; -+} -+ -+bool hal_video_set_multi_area_l_addr(hal_disp_layer layer, unsigned int area_num, unsigned long l_addr, unsigned short stride) -+{ -+ volatile unsigned long vid_addr; -+ volatile unsigned long vid_addr_stride; -+ volatile u_vid_stride vid_stride; /* 0x10270 */ -+ -+ if ((layer == HAL_DISP_LAYER_VHD0) || (layer == HAL_DISP_LAYER_VHD1)) { -+ vid_addr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_addr_l)); -+ hal_write_reg((unsigned int*)(uintptr_t)vid_addr, get_low_addr(l_addr)); -+ -+ vid_addr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_addr_h)); -+ hal_write_reg((unsigned int*)(uintptr_t)vid_addr, get_high_addr(l_addr)); -+ -+ vid_addr_stride = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_stride)); -+ vid_stride.u32 = hal_read_reg((unsigned int*)(uintptr_t)vid_addr_stride); -+ vid_stride.bits.lm_stride = stride; -+ hal_write_reg((unsigned int*)(uintptr_t)vid_addr_stride, vid_stride.u32); -+ } else { -+ return false; -+ } -+ -+ return true; -+} -+ -+bool hal_video_set_multi_area_c_addr(hal_disp_layer layer, unsigned int area_num, unsigned long c_addr, unsigned short stride) -+{ -+ volatile unsigned long vid_caddr; /* 0x10258 */ -+ volatile unsigned long vid_addr_stride; -+ volatile u_vid_stride vid_stride; /* 0x10270 */ -+ -+ -+ -+ if ((layer == HAL_DISP_LAYER_VHD0) || (layer == HAL_DISP_LAYER_VHD1)) { -+ vid_caddr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_caddr_l)); -+ hal_write_reg((unsigned int*)(uintptr_t)vid_caddr, get_low_addr(c_addr)); -+ -+ vid_caddr = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_caddr_h)); -+ hal_write_reg((unsigned int*)(uintptr_t)vid_caddr, get_high_addr(c_addr)); -+ -+ vid_addr_stride = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->vid_stride.u32)); -+ vid_stride.u32 = hal_read_reg((unsigned int*)(uintptr_t)vid_addr_stride); -+ vid_stride.bits.chm_stride = stride; -+ hal_write_reg((unsigned int*)(uintptr_t)vid_addr_stride, vid_stride.u32); -+ } else { -+ return false; -+ } -+ -+ return true; -+} -+ -+/* vou zoom enable */ -+bool hal_layer_set_zme_enable(hal_disp_layer layer, -+ hal_disp_zmemode mode, -+ unsigned int enable) -+{ -+ -+ -+ -+ volatile u_v0_zme_hsp v0_zme_hsp; /* 0x1304 */ -+ volatile u_v0_zme_vsp v0_zme_vsp; /* 0x1404 */ -+ volatile u_v1_cvfir_vsp v1_cvfir_vsp; /* 0x2404 */ -+ -+ -+ volatile unsigned long addr_reg; -+ -+ if (layer == HAL_DISP_LAYER_VHD0) { -+ if ((mode == HAL_DISP_ZMEMODE_HORL) || (mode == HAL_DISP_ZMEMODE_HOR) || (mode == HAL_DISP_ZMEMODE_ALL)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_hsp.u32)); -+ v0_zme_hsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_zme_hsp.bits.lhfir_en = enable; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_hsp.u32); -+ } -+ -+ if ((mode == HAL_DISP_ZMEMODE_HORC) || (mode == HAL_DISP_ZMEMODE_HOR) || (mode == HAL_DISP_ZMEMODE_ALL)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_hsp.u32)); -+ v0_zme_hsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_zme_hsp.bits.chfir_en = enable; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_hsp.u32); -+ } -+ -+ if ((mode == HAL_DISP_ZMEMODE_VERL) || (mode == HAL_DISP_ZMEMODE_VER) || (mode == HAL_DISP_ZMEMODE_ALL)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_vsp.u32)); -+ v0_zme_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_zme_vsp.bits.lvfir_en = enable; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_vsp.u32); -+ } -+ -+ if ((mode == HAL_DISP_ZMEMODE_VERC) || (mode == HAL_DISP_ZMEMODE_VER) || (mode == HAL_DISP_ZMEMODE_ALL)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_zme_vsp.u32)); -+ v0_zme_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_zme_vsp.bits.cvfir_en = enable; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_vsp.u32); -+ } -+ } else if (layer == HAL_DISP_LAYER_VHD1) { -+ if ((mode == HAL_DISP_ZMEMODE_VERL) || (mode == HAL_DISP_ZMEMODE_VER) || (mode == HAL_DISP_ZMEMODE_ALL)) { -+ addr_reg = (uintptr_t)&(g_vo_reg->v1_cvfir_vsp.u32); -+ v1_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v1_cvfir_vsp.bits.cvfir_en = enable; -+ v1_cvfir_vsp.bits.cvmid_en = enable; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v1_cvfir_vsp.u32); -+ } -+ } else { -+ return false; -+ } -+ return true; -+} -+ -+bool hal_video_set_layer_video_rect(hal_disp_layer layer, const ot_fb_rect *rect) -+{ -+ volatile u_v0_vfpos v0_vfpos;/* 0x1088 */ -+ volatile u_v0_vlpos v0_vlpos;/* 0x108c */ -+ volatile unsigned long addr_reg; -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: -+ case HAL_DISP_LAYER_VHD2: { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_vfpos.u32)); -+ v0_vfpos.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_vfpos.bits.video_xfpos = rect->x; -+ v0_vfpos.bits.video_yfpos = rect->y; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_vfpos.u32); -+ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_vlpos.u32)); -+ v0_vlpos.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_vlpos.bits.video_xlpos = rect->x + rect->width - 1; -+ v0_vlpos.bits.video_ylpos = rect->y + rect->height - 1; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_vlpos.u32); -+ -+ break; -+ } -+ -+ default: { -+ printk("error layer id,%s,%d\n",__func__,__LINE__); -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+bool hal_layer_set_zme_info(hal_disp_layer layer, unsigned int width, unsigned int height, -+ hal_disp_zme_outfmt zme_out_fmt) -+{ -+ volatile u_v0_zme_hinfo v0_zme_hinfo; /* 0x1300 */ -+ volatile u_v0_zme_vinfo v0_zme_vinfo; /* 0x1400 */ -+ volatile u_v1_cvfir_vinfo v1_cvfir_vinfo; /* 0x2400 */ -+ -+ volatile unsigned long addr_reg; -+ -+ if (layer == HAL_DISP_LAYER_VHD0) { -+ addr_reg = (uintptr_t)&(g_vo_reg->v0_zme_hinfo.u32); -+ v0_zme_hinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_zme_hinfo.bits.out_width = width - 1; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_hinfo.u32); -+ -+ addr_reg = (uintptr_t)&(g_vo_reg->v0_zme_vinfo.u32); -+ v0_zme_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_zme_vinfo.bits.out_pro = 1; -+ v0_zme_vinfo.bits.out_height = height - 1; -+ v0_zme_vinfo.bits.out_fmt = zme_out_fmt; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_zme_vinfo.u32); -+ } else if (layer == HAL_DISP_LAYER_VHD1) { -+ addr_reg = (uintptr_t)&(g_vo_reg->v1_cvfir_vinfo.u32); -+ v1_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v1_cvfir_vinfo.bits.vzme_ck_gt_en = 1; -+ v1_cvfir_vinfo.bits.out_pro = 1; -+ v1_cvfir_vinfo.bits.out_height = height; -+ v1_cvfir_vinfo.bits.out_fmt = zme_out_fmt; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v1_cvfir_vinfo.u32); -+ } else { -+ return false; -+ } -+ -+ return true; -+} -+ -+void hal_layer_csc_set_enable(hal_disp_layer layer, bool csc_en) -+{ -+ volatile u_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; -+ -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_ot_pp_csc_ctrl.u32)); -+ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_en = csc_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); -+ } else if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->g0_ot_pp_csc_ctrl.u32)); -+ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_en = csc_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); -+ } -+} -+ -+void hal_layer_csc_set_ck_gt_en(hal_disp_layer layer, bool ck_gt_en) -+{ -+ volatile u_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; -+ -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_ot_pp_csc_ctrl.u32)); -+ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_ck_gt_en = ck_gt_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); -+ } else if ((layer >= HAL_DISP_LAYER_GFX0) && (layer <= HAL_DISP_LAYER_GFX4)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->g0_ot_pp_csc_ctrl.u32)); -+ v0_ot_pp_csc_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_ot_pp_csc_ctrl.bits.ot_pp_csc_ck_gt_en = ck_gt_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_ot_pp_csc_ctrl.u32); -+ } -+} -+ -+ -+bool hal_layer_set_csc_en(hal_disp_layer layer, bool csc_en) -+{ -+ if ((layer < HAL_DISP_LAYER_VHD0) || (layer > HAL_DISP_LAYER_GFX3)) { -+ printk("error, wrong layer ID,%s,%d\n",__func__,__LINE__); -+ return false; -+ } -+ hal_layer_csc_set_ck_gt_en(layer, csc_en); -+ hal_layer_csc_set_enable(layer, csc_en); -+ return true; -+} -+ -+bool hal_video_set_hfir_mode(hal_disp_layer layer, hal_hfirmode mode) -+{ -+ volatile u_v0_hfir_ctrl v0_hfir_ctrl; -+ volatile u_wd_hpzme_ctrl wd_hpzme_ctrl; -+ volatile u_wd_hcds_ctrl wd_hcds_ctrl; -+ -+ volatile unsigned long addr_reg; -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfir_ctrl.u32)); -+ v0_hfir_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_hfir_ctrl.bits.hfir_mode = mode; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfir_ctrl.u32); -+ break; -+ } -+ -+ case HAL_DISP_LAYER_WBC: { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->wd_hpzme_ctrl.u32)); -+ wd_hpzme_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ wd_hpzme_ctrl.bits.ck_gt_en = 1; -+ wd_hpzme_ctrl.bits.hfir_mode = mode; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, wd_hpzme_ctrl.u32); -+ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->wd_hcds_ctrl.u32)); -+ wd_hcds_ctrl.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ wd_hcds_ctrl.bits.ck_gt_en = 1; -+ wd_hcds_ctrl.bits.hfir_en = 1; -+ wd_hcds_ctrl.bits.hfir_mode = 0x0; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, wd_hcds_ctrl.u32); -+ -+ break; -+ } -+ -+ default: { -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+bool hal_video_set_hfir_coef(hal_disp_layer layer, const int *coef) -+{ -+ volatile u_v0_hfircoef01 v0_hfircoef01; -+ volatile u_v0_hfircoef23 v0_hfircoef23; -+ volatile u_v0_hfircoef45 v0_hfircoef45; -+ volatile u_v0_hfircoef67 v0_hfircoef67; -+ volatile unsigned long addr_reg; -+ -+ switch (layer) { -+ case HAL_DISP_LAYER_VHD0: -+ case HAL_DISP_LAYER_VHD1: { -+ /* the number is to get the value from the coef array */ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef01.u32)); -+ v0_hfircoef01.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_hfircoef01.bits.coef0 = coef[0]; -+ v0_hfircoef01.bits.coef1 = coef[1]; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef01.u32); -+ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef23.u32)); -+ v0_hfircoef23.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_hfircoef23.bits.coef2 = coef[2]; -+ v0_hfircoef23.bits.coef3 = coef[3]; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef23.u32); -+ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef45.u32)); -+ v0_hfircoef45.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_hfircoef45.bits.coef4 = coef[4]; -+ v0_hfircoef45.bits.coef5 = coef[5]; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef45.u32); -+ -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_hfircoef67.u32)); -+ v0_hfircoef67.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_hfircoef67.bits.coef6 = coef[6]; -+ v0_hfircoef67.bits.coef7 = coef[7]; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_hfircoef67.u32); -+ break; -+ } -+ -+ default: { -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+void hal_video_cvfir_set_out_height(hal_disp_layer layer, unsigned int out_height) -+{ -+ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); -+ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vinfo.bits.out_height = out_height - 1; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_out_fmt(hal_disp_layer layer, unsigned int out_fmt) -+{ -+ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); -+ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vinfo.bits.out_fmt = out_fmt; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_out_pro(hal_disp_layer layer, unsigned int out_pro) -+{ -+ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); -+ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vinfo.bits.out_pro = out_pro; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_vzme_ck_gt_en(hal_disp_layer layer, bool vzme_ck_gt_en) -+{ -+ volatile u_v0_cvfir_vinfo v0_cvfir_vinfo; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vinfo.u32)); -+ v0_cvfir_vinfo.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vinfo.bits.vzme_ck_gt_en = vzme_ck_gt_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vinfo.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_cvfir_en(hal_disp_layer layer, unsigned int cvfir_en) -+{ -+ volatile u_v0_cvfir_vsp v0_cvfir_vsp; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); -+ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vsp.bits.cvfir_en = cvfir_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_cvmid_en(hal_disp_layer layer, unsigned int cvmid_en) -+{ -+ volatile u_v0_cvfir_vsp v0_cvfir_vsp; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); -+ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vsp.bits.cvmid_en = cvmid_en; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_cvfir_mode(hal_disp_layer layer, unsigned int cvfir_mode) -+{ -+ volatile u_v0_cvfir_vsp v0_cvfir_vsp; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); -+ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vsp.bits.cvfir_mode = cvfir_mode; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_vratio(hal_disp_layer layer, unsigned int vratio) -+{ -+ volatile u_v0_cvfir_vsp v0_cvfir_vsp; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vsp.u32)); -+ v0_cvfir_vsp.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vsp.bits.vratio = vratio; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vsp.u32); -+ } -+ -+ return; -+} -+ -+ -+void hal_video_cvfir_set_v_chroma_offset(hal_disp_layer layer, unsigned int vchroma_offset) -+{ -+ volatile u_v0_cvfir_voffset v0_cvfir_voffset; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_voffset.u32)); -+ v0_cvfir_voffset.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_voffset.bits.vchroma_offset = vchroma_offset; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_voffset.u32); -+ } -+ -+ return; -+} -+ -+void hal_video_cvfir_set_vb_chroma_offset(hal_disp_layer layer, unsigned int vbchroma_offset) -+{ -+ volatile u_v0_cvfir_vboffset v0_cvfir_vboffset; -+ volatile unsigned long addr_reg; -+ -+ if ((layer >= HAL_DISP_LAYER_VHD0) && (layer <= HAL_DISP_LAYER_VHD1)) { -+ addr_reg = vou_get_vid_abs_addr(layer, (uintptr_t)&(g_vo_reg->v0_cvfir_vboffset.u32)); -+ v0_cvfir_vboffset.u32 = hal_read_reg((unsigned int*)(uintptr_t)addr_reg); -+ v0_cvfir_vboffset.bits.vbchroma_offset = vbchroma_offset; -+ hal_write_reg((unsigned int*)(uintptr_t)addr_reg, v0_cvfir_vboffset.u32); -+ } -+ -+ return; -+} -+ -+void vo_drv_func_get_cvfir_pq_cfg(vo_zme_ds_info *ds_info, vo_zme_mode zme_mode, -+ vo_zme_comm_pq_cfg *comm_pq_cfg) -+{ -+ unsigned int zme_vprec; -+ /* the zme num is from algorithm, not magic num */ -+ if (zme_mode == VO_ZME_TYP) { -+ zme_vprec = ds_info->zme_vprec; -+ comm_pq_cfg->vluma_offset = 0; -+ comm_pq_cfg->vchroma_offset = 0; -+ comm_pq_cfg->vbluma_offset = MIN_OFFSET * (int)zme_vprec / 2; -+ comm_pq_cfg->vbchroma_offset = MIN_OFFSET * (int)zme_vprec / 2; -+ comm_pq_cfg->vl_flatdect_mode = 1; -+ comm_pq_cfg->vl_coringadj_en = 1; -+ comm_pq_cfg->vl_gain = 32; -+ comm_pq_cfg->vl_coring = 16; -+ comm_pq_cfg->vc_flatdect_mode = 1; -+ comm_pq_cfg->vc_coringadj_en = 1; -+ comm_pq_cfg->vc_gain = 32; -+ comm_pq_cfg->vc_coring = 16; -+ comm_pq_cfg->lhfir_offset = 0; -+ comm_pq_cfg->chfir_offset = 0; -+ comm_pq_cfg->hl_flatdect_mode = 1; -+ comm_pq_cfg->hl_coringadj_en = 1; -+ comm_pq_cfg->hl_gain = 32; -+ comm_pq_cfg->hl_coring = 16; -+ comm_pq_cfg->hc_flatdect_mode = 1; -+ comm_pq_cfg->hc_coringadj_en = 1; -+ comm_pq_cfg->hc_gain = 32; -+ comm_pq_cfg->hc_coring = 16; -+ } -+} -+ -+static void vo_drv_set_layer_cvfir_mode(unsigned int layer, vo_zme_mode zme_mode, const vdp_v1_cvfir_cfg *cfg) -+{ -+ unsigned int vzme_ck_gt_en; -+ unsigned int out_pro; -+ unsigned int out_fmt; -+ unsigned int out_height; -+ unsigned int cvfir_en; -+ unsigned int cvmid_en; -+ unsigned int cvfir_mode; -+ unsigned int vratio; -+ unsigned int vchroma_offset; -+ unsigned int vbchroma_offset; -+ vo_zme_ds_info ds_info = {0}; -+ vo_zme_comm_pq_cfg comm_pq_cfg = {0}; -+ -+ ds_info.zme_vprec = ZME_VPREC; -+ ds_info.zme_hprec = ZME_HPREC; -+ -+ vzme_ck_gt_en = cfg->ck_gt_en; -+ cvfir_en = cfg->cvfir_en; -+ cvfir_mode = cfg->cvfir_mode; -+ cvmid_en = cfg->cvmid_en; -+ out_pro = cfg->out_pro; -+ out_fmt = cfg->out_fmt; -+ out_height = (unsigned int)cfg->in_height; -+ vratio = ds_info.zme_vprec; -+ -+ vo_drv_func_get_cvfir_pq_cfg(&ds_info, zme_mode, &comm_pq_cfg); -+ -+ vchroma_offset = comm_pq_cfg.vchroma_offset; -+ vbchroma_offset = comm_pq_cfg.vbchroma_offset; -+ -+ hal_video_cvfir_set_out_height(layer, out_height); -+ hal_video_cvfir_set_out_fmt(layer, out_fmt); -+ hal_video_cvfir_set_out_pro(layer, out_pro); -+ hal_video_cvfir_set_vzme_ck_gt_en(layer, vzme_ck_gt_en); -+ -+ -+ hal_video_cvfir_set_cvfir_en(layer, cvfir_en); -+ hal_video_cvfir_set_cvmid_en(layer, cvmid_en); -+ hal_video_cvfir_set_cvfir_mode(layer, cvfir_mode); -+ hal_video_cvfir_set_vratio(layer, vratio); -+ -+ -+ hal_video_cvfir_set_v_chroma_offset(layer, vchroma_offset); -+ hal_video_cvfir_set_vb_chroma_offset(layer, vbchroma_offset); -+} -+ -+void vo_vid_set_zme_enable(unsigned int layer, const vdp_vid_ip_cfg *vid_cfg) -+{ -+ /* the numbers is from algorithm, not magic numbers */ -+ vdp_v1_cvfir_cfg cvfir_cfg; -+ cvfir_cfg.hfir_order = 0; -+ cvfir_cfg.lhfir_en = 0; -+ cvfir_cfg.chfir_en = 0; -+ cvfir_cfg.lhmid_en = 0; -+ cvfir_cfg.chmid_en = 0; -+ cvfir_cfg.lhfir_mode = 0; -+ cvfir_cfg.chfir_mode = 0; -+ cvfir_cfg.hl_shootctrl_en = 0; -+ cvfir_cfg.hl_shootctrl_mode = 0; -+ cvfir_cfg.hc_shootctrl_en = 0; -+ cvfir_cfg.hc_shootctrl_mode = 0; -+ cvfir_cfg.lvfir_en = 0; -+ cvfir_cfg.lvmid_en = 0; -+ cvfir_cfg.lvfir_mode = 0; -+ cvfir_cfg.vl_shootctrl_en = 0; -+ cvfir_cfg.vl_shootctrl_mode = 0; -+ cvfir_cfg.vc_shootctrl_en = 0; -+ cvfir_cfg.vc_shootctrl_mode = 0; -+ -+ /* CVFIR */ -+ cvfir_cfg.ck_gt_en = 0; -+ cvfir_cfg.cvfir_en = 1; -+ cvfir_cfg.cvmid_en = 0; -+ cvfir_cfg.cvfir_mode = 0; -+ cvfir_cfg.out_pro = VDP_RMODE_PROGRESSIVE; -+ cvfir_cfg.out_fmt = VDP_PROC_FMT_SP_422; -+ cvfir_cfg.in_width = vid_cfg->vid_iw; -+ cvfir_cfg.in_height = vid_cfg->vid_ih; -+ cvfir_cfg.out_width = vid_cfg->vid_ow; -+ cvfir_cfg.out_height = vid_cfg->vid_oh; -+ vo_drv_set_layer_cvfir_mode(layer, VO_ZME_TYP, &cvfir_cfg); -+} -+ -+static void video_layer_set_zme_cfg(unsigned int layer, const ot_fb_rect *disp_rect) -+{ -+ vdp_vid_ip_cfg vid_cfg = {0}; -+ vid_cfg.csc_en = 0; -+ vid_cfg.hfir_en = 1; -+ vid_cfg.vid_iw = disp_rect->width; -+ vid_cfg.vid_ih = disp_rect->height; -+ -+ vid_cfg.vid_ow = disp_rect->width; -+ vid_cfg.vid_oh = disp_rect->height; -+ vid_cfg.zme_en = false; -+ vo_vid_set_zme_enable(layer, &vid_cfg); -+} -+ -+void drm_overlay_update(ot_video_frame_info *p_frame_info) -+{ -+ int i = 0; -+ ot_fb_rect rect = {0}; -+ unsigned short stride = 0; -+ const int as32_hfir_coef[2][8] = { /* 2 8 hfir coef array */ -+ { 0x3f9, 0xc, 0x3ef, 0x19, 0x3da, 0x3a, 0x397, 0x148 }, -+ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a } -+ }; -+ hal_disp_layer disp_layer = HAL_DISP_LAYER_VHD0; -+ -+ rect.x = 0; -+ rect.y = 0; -+ rect.width = p_frame_info->video_frame.width; -+ rect.height = p_frame_info->video_frame.height; -+ stride = p_frame_info->video_frame.stride[0]; -+ hal_layer_set_layer_global_alpha(disp_layer, VO_ALPHA_OPACITY); /* global alpha max 255 */ -+ hal_video_set_layer_alpha(disp_layer, VO_ALPHA_OPACITY); /* alpha max 255 */ -+ //hal_layer_set_layer_data_fmt(disp_layer, HAL_INPUTFMT_YCBCR_SEMIPLANAR_420); -+ hal_layer_set_layer_data_fmt(disp_layer, VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_420); -+ hal_layer_set_csc_en(disp_layer, false); -+ for (i = 0; i <= HAL_DISP_LAYER_VHD1; i++) { -+ hal_video_set_hfir_mode(i, HAL_HFIRMODE_COPY); -+ hal_video_set_hfir_coef(i, as32_hfir_coef[i]); -+ } -+ hal_video_hfir_set_ck_gt_en(disp_layer, true); -+ hal_video_set_layer_disp_rect(disp_layer, &rect); -+ hal_video_set_layer_video_rect(disp_layer, &rect); -+ hal_layer_set_layer_in_rect(disp_layer, &rect); -+ fb_hal_layer_set_layer_galpha(disp_layer, GRAPHIC_ALPHA_OPACITY); -+ hal_layer_set_src_resolution(disp_layer, &rect); -+ -+ video_layer_set_zme_cfg(disp_layer, &rect); -+ -+ hal_layer_set_zme_enable(disp_layer, HAL_DISP_ZMEMODE_ALL, false); -+ hal_layer_set_zme_info(disp_layer, rect.width, rect.height, HAL_DISP_ZME_OUTFMT420); -+ -+ /* area 0 */ -+ hal_video_set_multi_area_l_addr(disp_layer, 0, p_frame_info->video_frame.phys_addr[0], stride); -+ hal_video_set_multi_area_c_addr(disp_layer, 0, p_frame_info->video_frame.phys_addr[1], stride); /* align 16 */ -+ -+ hal_layer_enable_layer(disp_layer, true); -+ hal_disp_set_reg_up(disp_layer); -+ fb_hal_layer_set_reg_up(disp_layer); -+ return; -+} -+ -+static void vop_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc *crtc = new_state->crtc; -+ struct vop *vop = to_vop(new_state->crtc); -+ struct drm_framebuffer *drm_fb = new_state->fb; -+ struct drm_rect *src = &new_state->src; -+ hal_disp_layer disp_layer = HAL_DISP_LAYER_GFX0; -+ ot_fb_rect rect = {0}; -+ size_t size = drm_fb->height * drm_fb->pitches[0]; -+ int ret = 0; -+ gf_zme_cfg cfg = {0}; -+ vo_csc gfx_csc = {0}; -+ csc_coef_param csc_param = {0}; -+ struct drm_gem_object *obj = drm_fb->obj[0]; -+ struct iosys_map map; -+ void *vaddr; -+ -+ rect.x = 0; -+ rect.y = 0; -+ rect.width = drm_fb->width; -+ rect.height = drm_fb->height; -+ -+ ret = drm_gem_vmap(obj, &map); -+ if (ret) { -+ printk("Failed to map GEM object: %d\n", ret); -+ return; -+ } -+ memcpy(vop->virt_addr, map.vaddr, size); -+ drm_gem_vunmap(obj, &map); -+ //gfbg_drv_layer_default_setting -+ spin_lock(&vop->reg_lock); -+ fb_hal_graphic_set_gfx_key_mode(disp_layer, FB_VOU_COLORKEY_IN); -+ fb_hal_graphic_set_gfx_key_en(disp_layer, false); -+ fb_hal_graphic_set_gfx_ext(disp_layer, FB_VOU_BITEXT_LOW_HIGHBITS); -+ fb_hal_graphic_set_gfx_palpha(disp_layer, true, true, 0, GRAPHIC_ALPHA_OPACITY); -+ fb_hal_layer_set_layer_galpha(disp_layer, GRAPHIC_ALPHA_OPACITY); -+ gfx_csc.csc_matrix = OT_VO_CSC_MATRIX_RGBFULL_TO_BT709LIMIT; -+ gfx_csc.luma = VO_CSC_DEF_VAL; -+ gfx_csc.contrast = VO_CSC_DEF_VAL; -+ gfx_csc.hue = VO_CSC_DEF_VAL; -+ gfx_csc.satuature = VO_CSC_DEF_VAL; -+ -+ /* CSC extra coef */ -+ csc_param.csc_scale2p = GFX_CSC_SCALE; -+ csc_param.csc_clip_min = GFX_CSC_CLIP_MIN; -+ csc_param.csc_clip_max = GFX_CSC_CLIP_MAX; -+ fb_graphic_drv_set_csc_coef(disp_layer, &gfx_csc, &csc_param); -+ fb_hal_layer_set_csc_en(disp_layer, true); -+ -+ //gfbg_drv_set_layer_alpha -+ fb_hal_layer_set_layer_data_fmt(disp_layer, HAL_INPUTFMT_ARGB_8888); -+ fb_hal_graphic_set_gfx_dcmp_enable(disp_layer, false); -+ //gfbg_drv_set_layer_rect -+ fb_hal_layer_set_layer_out_rect(disp_layer ,&rect); -+ fb_hal_layer_set_layer_in_rect(disp_layer ,&rect); -+ fb_hal_video_set_layer_disp_rect(disp_layer ,&rect); -+ fb_hal_video_set_layer_video_rect(disp_layer ,&rect); -+ //gfbg_drv_set_layer_src_image_reso -+ fb_hal_layer_set_src_resolution(disp_layer, &rect); -+ //graphic_drv_enable_zme -+ graphic_drv_cfg_zme_info(&cfg); -+ cfg.in_width = drm_fb->width; -+ cfg.in_height = drm_fb->height; -+ cfg.out_width = drm_fb->width; -+ cfg.out_height = drm_fb->height; -+ cfg.hfir_en = 0; -+ cfg.vfir_en = 0; -+ if (disp_layer == HAL_DISP_LAYER_GFX0) { -+ gf_func_set_g0zme_mode(disp_layer, VDP_G0_ZME_TYP, &cfg); -+ } -+ -+ fb_hal_graphic_set_gfx_stride(disp_layer, drm_fb->pitches[0]>>4);//gfbg_drv_set_layer_stride -+ fb_hal_graphic_set_gfx_addr(disp_layer, vop->phys_addr); -+ fb_hal_set_layer_enable(disp_layer, 1);//gfbg_drv_set_layer_enable -+ fb_hal_set_layer_ck_gt_en(disp_layer, 1); -+ fb_hal_graphic_set_gfx_dcmp_enable(disp_layer, false);//gfbg_drv_enable_dcmp -+ fb_hal_layer_set_reg_up(disp_layer); -+ spin_unlock(&vop->reg_lock); -+ -+ -+ /* -+ * can't update plane when vop is disabled. -+ */ -+ if (WARN_ON(!crtc)) -+ return; -+ -+ if (WARN_ON(!vop->is_enabled)) -+ return; -+ -+ if (!new_state->visible) { -+ vop_plane_atomic_disable(plane, state); -+ return; -+ } -+} -+ -+static int vop_plane_atomic_async_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ int min_scale = DRM_PLANE_NO_SCALING; -+ int max_scale = DRM_PLANE_NO_SCALING; -+ struct drm_crtc_state *crtc_state; -+ if (plane != new_plane_state->crtc->cursor) -+ return -EINVAL; -+ -+ if (!plane->state) -+ return -EINVAL; -+ -+ if (!plane->state->fb) -+ return -EINVAL; -+ -+ crtc_state = drm_atomic_get_existing_crtc_state(state, new_plane_state->crtc); -+ -+ /* Special case for asynchronous cursor updates. */ -+ if (!crtc_state) -+ crtc_state = plane->crtc->state; -+ -+ return drm_atomic_helper_check_plane_state(plane->state, crtc_state, -+ min_scale, max_scale, -+ true, true); -+} -+ -+static void vop_plane_atomic_async_update(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct vop *vop = to_vop(plane->state->crtc); -+ struct drm_framebuffer *old_fb = plane->state->fb; -+ -+ plane->state->crtc_x = new_state->crtc_x; -+ plane->state->crtc_y = new_state->crtc_y; -+ plane->state->crtc_h = new_state->crtc_h; -+ plane->state->crtc_w = new_state->crtc_w; -+ plane->state->src_x = new_state->src_x; -+ plane->state->src_y = new_state->src_y; -+ plane->state->src_h = new_state->src_h; -+ plane->state->src_w = new_state->src_w; -+ swap(plane->state->fb, new_state->fb); -+ -+ if (vop->is_enabled) { -+ vop_plane_atomic_update(plane, state); -+ } -+} -+ -+static const struct drm_plane_helper_funcs plane_helper_funcs = { -+ .atomic_check = vop_plane_atomic_check, -+ .atomic_update = vop_plane_atomic_update, -+ .atomic_disable = vop_plane_atomic_disable, -+ .atomic_async_check = vop_plane_atomic_async_check, -+ .atomic_async_update = vop_plane_atomic_async_update, -+}; -+ -+static const struct drm_plane_funcs vop_plane_funcs = { -+ .update_plane = drm_atomic_helper_update_plane, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .destroy = vop_plane_destroy, -+ .reset = drm_atomic_helper_plane_reset, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .format_mod_supported = smart_mod_supported, -+}; -+ -+static int vop_crtc_enable_vblank(struct drm_crtc *crtc) -+{ -+ struct vop *vop = to_vop(crtc); -+ unsigned long flags; -+ -+ if (WARN_ON(!vop->is_enabled)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&vop->irq_lock, flags); -+ vop->vblank_enabled = true; -+ spin_unlock_irqrestore(&vop->irq_lock, flags); -+ return 0; -+} -+ -+static void vop_crtc_disable_vblank(struct drm_crtc *crtc) -+{ -+ -+ struct vop *vop = to_vop(crtc); -+ unsigned long flags; -+ -+ if (WARN_ON(!vop->is_enabled)) -+ return; -+ -+ spin_lock_irqsave(&vop->irq_lock, flags); -+ vop->vblank_enabled = false; -+ spin_unlock_irqrestore(&vop->irq_lock, flags); -+} -+ -+static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode) -+{ -+ struct vop *vop = to_vop(crtc); -+ return MODE_OK; -+} -+ -+static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+ struct vop *vop = to_vop(crtc); -+ -+ return true; -+} -+ -+static void vop_crtc_atomic_begin(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop *vop = to_vop(crtc); -+ -+ -+} -+ -+ -+void vo_hal_set_reg(volatile reg_vdp_regs *reg) -+{ -+ g_vo_reg = reg; -+} -+ -+void vo_hal_intf_set_dac_cablectr(ot_vo_intf_type intf_type, unsigned int cablectr) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vo_dac0_ctrl vo_dac0_ctrl; -+ volatile reg_vo_dac1_ctrl vo_dac1_ctrl; -+ volatile reg_vo_dac2_ctrl vo_dac2_ctrl; -+ volatile reg_vo_dac3_ctrl vo_dac3_ctrl; -+ if (intf_type == OT_VO_INTF_VGA) { -+ vo_dac0_ctrl.u32 = vo_reg->vo_dac0_ctrl.u32; -+ vo_dac1_ctrl.u32 = vo_reg->vo_dac1_ctrl.u32; -+ vo_dac2_ctrl.u32 = vo_reg->vo_dac2_ctrl.u32; -+ vo_dac0_ctrl.bits.cablectr = cablectr; -+ vo_dac1_ctrl.bits.cablectr = cablectr; -+ vo_dac2_ctrl.bits.cablectr = cablectr; -+ vo_reg->vo_dac0_ctrl.u32 = vo_dac0_ctrl.u32; -+ vo_reg->vo_dac1_ctrl.u32 = vo_dac1_ctrl.u32; -+ vo_reg->vo_dac2_ctrl.u32 = vo_dac2_ctrl.u32; -+ } else { /* dac3: CVBS */ -+ vo_dac3_ctrl.u32 = vo_reg->vo_dac3_ctrl.u32; -+ vo_dac3_ctrl.bits.cablectr = cablectr; -+ vo_reg->vo_dac3_ctrl.u32 = vo_dac3_ctrl.u32; -+ } -+} -+ -+static void vo_hal_intf_set_mux_sel_hd(ot_vo_dev dev, ot_vo_intf_type intf) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vo_mux vo_mux; -+ vo_mux.u32 = vo_reg->vo_mux.u32; -+ -+ switch (intf) { -+ case OT_VO_INTF_HDMI: -+ vo_mux.bits.hdmi_sel = dev; -+ break; -+ -+ case OT_VO_INTF_MIPI: -+ case OT_VO_INTF_MIPI_SLAVE: -+ vo_mux.bits.mipi_sel = dev; -+ break; -+ -+ case OT_VO_INTF_CVBS: -+ vo_mux.bits.sddate_sel = dev; -+ break; -+ -+ case OT_VO_INTF_BT1120: -+ vo_mux.bits.digital_sel = 0; -+ vo_mux.bits.bt_sel = dev; -+ break; -+ -+ case OT_VO_INTF_BT656: -+ vo_mux.bits.digital_sel = 0x1; -+ vo_mux.bits.bt_sel = dev; -+ break; -+ -+ case OT_VO_INTF_RGB_6BIT: -+ case OT_VO_INTF_RGB_8BIT: -+ case OT_VO_INTF_RGB_16BIT: -+ case OT_VO_INTF_RGB_18BIT: -+ case OT_VO_INTF_RGB_24BIT: -+ vo_mux.bits.digital_sel = 0x2; -+ vo_mux.bits.lcd_sel = dev; -+ break; -+ -+ default: -+ return; -+ } -+ -+ vo_reg->vo_mux.u32 = vo_mux.u32; -+} -+ -+void vo_hal_intf_set_hdmi_sync_inv(const hal_disp_syncinv *inv) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_intf_hdmi_sync_inv intf_hdmi_sync_inv; -+ -+ intf_hdmi_sync_inv.u32 = vo_reg->intf_hdmi_sync_inv.u32; -+ intf_hdmi_sync_inv.bits.dv_inv = inv->dv_inv; -+ intf_hdmi_sync_inv.bits.hs_inv = inv->hs_inv; -+ intf_hdmi_sync_inv.bits.vs_inv = inv->vs_inv; -+ intf_hdmi_sync_inv.bits.f_inv = inv->f_inv; -+ vo_reg->intf_hdmi_sync_inv.u32 = intf_hdmi_sync_inv.u32; -+} -+ -+void vo_hal_intf_set_sync_info_hvsync(ot_vo_dev dev, -+ const hal_disp_syncinfo *sync_info) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_dhd0_hsync1 dhd0_hsync1; -+ volatile reg_dhd0_hsync2 dhd0_hsync2; -+ volatile reg_dhd0_vsync1 dhd0_vsync1; -+ volatile reg_dhd0_vsync2 dhd0_vsync2; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_hsync1.u32)); -+ dhd0_hsync1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_hsync1.bits.hact = sync_info->hact - 1; -+ dhd0_hsync1.bits.hbb = (sync_info->hbb) - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_hsync1.u32); -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_hsync2.u32)); -+ dhd0_hsync2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_hsync2.bits.hmid = (sync_info->hmid == 0) ? 0 : (sync_info->hmid - 1); -+ dhd0_hsync2.bits.hfb = (sync_info->hfb) - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_hsync2.u32); -+ -+ /* config VHD interface vertical timing */ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_vsync1.u32)); -+ dhd0_vsync1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_vsync1.bits.vact = sync_info->vact - 1; -+ dhd0_vsync1.bits.vbb = sync_info->vbb - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vsync1.u32); -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_vsync2.u32)); -+ dhd0_vsync2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_vsync2.bits.vfb = sync_info->vfb - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vsync2.u32); -+} -+ -+void vo_hal_intf_set_sync_info_other(ot_vo_dev dev, -+ const hal_disp_syncinfo *sync_info) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_dhd0_ctrl dhd0_ctrl; -+ volatile reg_dhd0_vplus1 dhd0_vplus1; -+ volatile reg_dhd0_vplus2 dhd0_vplus2; -+ volatile reg_dhd0_pwr dhd0_pwr; -+ volatile unsigned long addr_reg; -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); -+ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_ctrl.bits.iop = sync_info->iop; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); -+ -+ /* config VHD interface vertical bottom timing, no use in progressive mode */ -+ addr_reg = vou_get_chn_abs_addr(dev, (unsigned long)(uintptr_t)&(vo_reg->dhd0_vplus1.u32)); -+ dhd0_vplus1.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_vplus1.bits.bvact = sync_info->bvact - 1; -+ dhd0_vplus1.bits.bvbb = sync_info->bvbb - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vplus1.u32); -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_vplus2.u32)); -+ dhd0_vplus2.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_vplus2.bits.bvfb = sync_info->bvfb - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_vplus2.u32); -+ -+ /* config VHD interface vertical bottom timing, */ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_pwr.u32)); -+ dhd0_pwr.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_pwr.bits.hpw = sync_info->hpw - 1; -+ dhd0_pwr.bits.vpw = sync_info->vpw - 1; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_pwr.u32); -+} -+ -+hal_disp_syncinfo g_sync_timing[OT_VO_OUT_BUTT] = { -+/* -+ * |--INTFACE---||-----TOP-----||----HORIZON--------||----BOTTOM-----||-PULSE-||-INVERSE-| -+ * syncm,iop, itf, vact, vbb, vfb, hact, hbb, hfb, hmid,bvact,bvbb,bvfb, hpw, vpw,idv, ihs, ivs -+ */ -+ { 0, 0, 0, 288, 22, 2, 720, 132, 12, 1, 288, 23, 2, 126, 3, 0, 0, 0 }, /* 576I(PAL) */ -+ { 0, 0, 0, 240, 18, 4, 720, 119, 19, 1, 240, 19, 4, 124, 3, 0, 0, 0 }, /* 480I(NTSC) */ -+ { 0, 0, 0, 288, 22, 2, 960, 176, 16, 1, 288, 23, 2, 168, 3, 0, 0, 0 }, /* 960H(PAL) */ -+ { 0, 0, 0, 240, 18, 4, 960, 163, 21, 1, 240, 19, 4, 168, 3, 0, 0, 0 }, /* 960H(NTSC) */ -+ -+ { 1, 1, 2, 480, 35, 10, 640, 144, 16, 1, 1, 1, 1, 96, 2, 0, 1, 1 }, /* 640*480@60_hz CVT */ -+ { 1, 1, 1, 480, 36, 9, 720, 122, 16, 1, 1, 1, 1, 62, 6, 0, 0, 0 }, /* 480P@60_hz */ -+ { 1, 1, 1, 576, 44, 5, 720, 132, 12, 1, 1, 1, 1, 64, 5, 0, 0, 0 }, /* 576P@50_hz */ -+ { 1, 1, 2, 600, 27, 1, 800, 216, 40, 1, 1, 1, 1, 128, 4, 0, 0, 0 }, /* 800*600@60_hz VGA@60_hz */ -+ { 1, 1, 2, 768, 35, 3, 1024, 296, 24, 1, 1, 1, 1, 136, 6, 0, 1, 1 }, /* 1024x768@60_hz */ -+ { 0, 1, 1, 720, 25, 5, 1280, 260, 440, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@50_hz */ -+ { 0, 1, 1, 720, 25, 5, 1280, 260, 110, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@60_hz */ -+ { 1, 1, 2, 800, 28, 3, 1280, 328, 72, 1, 1, 1, 1, 128, 6, 0, 1, 0 }, /* 1280*800@60_hz VGA@60_hz */ -+ { 1, 1, 2, 1024, 41, 1, 1280, 360, 48, 1, 1, 1, 1, 112, 3, 0, 0, 0 }, /* 1280x1024@60_hz */ -+ { 1, 1, 2, 768, 27, 3, 1366, 356, 70, 1, 1, 1, 1, 143, 3, 0, 0, 0 }, /* 1366x768@60_hz */ -+ { 1, 1, 2, 1050, 36, 3, 1400, 376, 88, 1, 1, 1, 1, 144, 4, 0, 0, 0 }, /* 1400x1050@60_hz */ -+ { 1, 1, 2, 900, 31, 3, 1440, 384, 80, 1, 1, 1, 1, 152, 6, 0, 1, 0 }, /* 1440x900@60_hz */ -+ { 1, 1, 2, 1050, 36, 3, 1680, 456, 104, 1, 1, 1, 1, 176, 6, 0, 1, 0 }, /* 1680*1050@60_hz */ -+ -+ { 0, 1, 1, 1080, 41, 4, 1920, 192, 638, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@24_hz */ -+ { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@25_hz */ -+ { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@30_hz */ -+ { 0, 0, 1, 540, 20, 2, 1920, 192, 528, 1128, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@50_hz */ -+ { 0, 0, 1, 540, 20, 2, 1920, 192, 88, 908, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@60_hz */ -+ { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@50_hz */ -+ { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@60_hz */ -+ -+ { 1, 1, 2, 1200, 49, 1, 1600, 496, 64, 1, 1, 1, 1, 192, 3, 0, 0, 0 }, /* 1600*1200@60_hz */ -+ { 1, 1, 2, 1200, 32, 3, 1920, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 1920*1200@60_hz CVT (reduced blanking) */ -+ { 0, 1, 1, 2160, 72, 8, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1920*2160@30_hz */ -+ { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@30_hz */ -+ { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@60_hz */ -+ { 0, 1, 2, 1600, 43, 3, 2560, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 2560*1600@60_hz CVT (reduced blanking) */ -+ { 0, 1, 1, 2160, 82, 8, 3840, 384, 1276, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@24_hz */ -+ { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@25_hz */ -+ { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@30_hz */ -+ { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@50_hz */ -+ { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@60_hz */ -+ -+ { 0, 1, 1, 2160, 82, 8, 4096, 384, 1020, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@24 */ -+ { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@25 */ -+ { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@30 */ -+ { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@50 */ -+ { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@60 */ -+ { 0, 1, 1, 4320, 64, 16, 7680, 768, 552, 1, 1, 1, 1, 176, 20, 0, 0, 0 }, /* 7680x4320@30 */ -+ -+ { 0, 1, 1, 320, 10, 4, 240, 30, 10, 1, 1, 1, 1, 10, 2, 0, 0, 0 }, /* 240X320@50 6bit LCD */ -+ { 0, 1, 1, 240, 2, 2, 320, 5, 10, 1, 1, 1, 1, 10, 1, 0, 0, 0 }, /* 320X240@50 6bit LCD */ -+ { 0, 1, 1, 320, 4, 8, 240, 20, 10, 1, 1, 1, 1, 2, 2, 0, 0, 0 }, /* 240X320@60 16bit LCD */ -+ { 0, 1, 1, 240, 15, 9, 320, 65, 7, 1, 240, 14, 9, 1, 1, 0, 0, 0 }, /* 320X240@60 8bit LCD */ -+ { 0, 1, 1, 600, 23, 12, 800, 210, 46, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 800X600@60 24bit LCD */ -+ -+ { 0, 1, 1, 1280, 24, 8, 720, 123, 99, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* for MIPI DSI tx 720 x1280 at 60 hz */ -+ { 0, 1, 1, 1920, 36, 16, 1080, 28, 130, 1, 1, 1, 1, 8, 10, 0, 0, 0 }, /* for MIPI DSI tx 1080 x1920 at 60 hz */ -+ {} /* user sync info by user, empty configuration */ -+}; -+ -+hal_disp_syncinfo *vo_drv_comm_get_sync_timing(ot_vo_intf_sync sync) -+{ -+ return &g_sync_timing[sync]; -+} -+ -+void vo_drv_get_sync_info(ot_vo_dev dev, hal_disp_syncinfo *sync_info) -+{ -+ hal_disp_syncinfo *hal_sync = NULL; -+ -+ /* standard sync info */ -+ hal_sync = vo_drv_comm_get_sync_timing(OT_VO_OUT_1080P60); -+ memcpy(sync_info, hal_sync, sizeof(hal_disp_syncinfo)); -+} -+ -+static void vo_drv_get_sync_inv(ot_vo_dev dev, hal_disp_syncinv *inv) -+{ -+ hal_disp_syncinfo sync_info; -+ ot_vo_intf_type intf_type; -+ ot_vo_intf_sync intf_sync; -+ -+ intf_type = OT_VO_INTF_HDMI;//vo_drv_get_dev_intf_type(dev); -+ intf_sync = OT_VO_OUT_1080P60;//vo_drv_get_dev_intf_sync(dev); -+ -+ vo_drv_get_sync_info(dev, &sync_info); -+ -+ inv->hs_inv = sync_info.ihs ? 1 : 0; -+ inv->vs_inv = sync_info.ivs ? 1 : 0; -+ inv->dv_inv = sync_info.idv ? 1 : 0; -+ -+ if ((OT_VO_INTF_HDMI & intf_type) != 0) { -+ /* vsync/hsync should be 1 for hdmi test */ -+ if ((intf_sync == OT_VO_OUT_576P50) || (intf_sync == OT_VO_OUT_480P60)) { -+ inv->hs_inv = 1 - inv->hs_inv; -+ inv->vs_inv = 1 - inv->vs_inv; -+ } -+ } -+ -+ if ((OT_VO_INTF_BT656 & intf_type) != 0) { -+ inv->hs_inv = 1; -+ } -+ -+ if ((OT_VO_INTF_CVBS & intf_type) != 0) { -+ inv->hs_inv = 1; -+ } -+} -+ -+void vo_hal_intf_set_csc_enable(ot_vo_intf_type intf, bool enable) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_hdmi_csc_idc hdmi_csc_idc; -+ volatile reg_mipi_csc_idc mipi_csc_idc; -+ volatile reg_lcd_csc_idc rgb_csc_idc; -+ -+ switch (intf) { -+ case OT_VO_INTF_HDMI: -+ hdmi_csc_idc.u32 = vo_reg->hdmi_csc_idc.u32; -+ hdmi_csc_idc.bits.csc_en = enable; -+ vo_reg->hdmi_csc_idc.u32 = hdmi_csc_idc.u32; -+ break; -+ -+ case OT_VO_INTF_MIPI: -+ case OT_VO_INTF_MIPI_SLAVE: -+ mipi_csc_idc.u32 = vo_reg->mipi_csc_idc.u32; -+ mipi_csc_idc.bits.csc_en = enable; -+ vo_reg->mipi_csc_idc.u32 = mipi_csc_idc.u32; -+ break; -+ -+ case OT_VO_INTF_RGB_6BIT: -+ case OT_VO_INTF_RGB_8BIT: -+ case OT_VO_INTF_RGB_16BIT: -+ case OT_VO_INTF_RGB_18BIT: -+ case OT_VO_INTF_RGB_24BIT: -+ rgb_csc_idc.u32 = vo_reg->lcd_csc_idc.u32; -+ rgb_csc_idc.bits.csc_en = enable; -+ vo_reg->lcd_csc_idc.u32 = rgb_csc_idc.u32; -+ break; -+ -+ default: -+ return; -+ } -+} -+ -+void vo_hal_intf_set_hdmi_csc_dc_coef(const vdp_csc_dc_coef *csc_dc_coef) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_hdmi_csc_idc hdmi_csc_idc; -+ volatile reg_hdmi_csc_odc hdmi_csc_odc; -+ volatile reg_hdmi_csc_iodc hdmi_csc_iodc; -+ -+ -+ hdmi_csc_idc.u32 = vo_reg->hdmi_csc_idc.u32; -+ hdmi_csc_odc.u32 = vo_reg->hdmi_csc_odc.u32; -+ hdmi_csc_iodc.u32 = vo_reg->hdmi_csc_iodc.u32; -+ -+ /* the configuration is reversed. */ -+ hdmi_csc_idc.bits.cscidc0 = csc_dc_coef->csc_in_dc2; -+ hdmi_csc_idc.bits.cscidc1 = csc_dc_coef->csc_in_dc1; -+ hdmi_csc_iodc.bits.cscidc2 = csc_dc_coef->csc_in_dc0; -+ -+ hdmi_csc_odc.bits.cscodc0 = csc_dc_coef->csc_out_dc2; -+ -+ hdmi_csc_odc.bits.cscodc1 = csc_dc_coef->csc_out_dc1; -+ hdmi_csc_iodc.bits.cscodc2 = csc_dc_coef->csc_out_dc0; -+ -+ vo_reg->hdmi_csc_idc.u32 = hdmi_csc_idc.u32; -+ vo_reg->hdmi_csc_odc.u32 = hdmi_csc_odc.u32; -+ vo_reg->hdmi_csc_iodc.u32 = hdmi_csc_iodc.u32; -+} -+ -+void vo_hal_intf_set_hdmi_csc_coef(const vdp_csc_coef *coef) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_hdmi_csc_p0 hdmi_csc_p0; -+ volatile reg_hdmi_csc_p1 hdmi_csc_p1; -+ volatile reg_hdmi_csc_p2 hdmi_csc_p2; -+ volatile reg_hdmi_csc_p3 hdmi_csc_p3; -+ volatile reg_hdmi_csc_p4 hdmi_csc_p4; -+ -+ hdmi_csc_p0.u32 = vo_reg->hdmi_csc_p0.u32; -+ hdmi_csc_p1.u32 = vo_reg->hdmi_csc_p1.u32; -+ hdmi_csc_p2.u32 = vo_reg->hdmi_csc_p2.u32; -+ hdmi_csc_p3.u32 = vo_reg->hdmi_csc_p3.u32; -+ hdmi_csc_p4.u32 = vo_reg->hdmi_csc_p4.u32; -+ -+ hdmi_csc_p0.bits.cscp00 = coef->csc_coef00; -+ hdmi_csc_p0.bits.cscp01 = coef->csc_coef01; -+ hdmi_csc_p1.bits.cscp02 = coef->csc_coef02; -+ hdmi_csc_p1.bits.cscp10 = coef->csc_coef10; -+ hdmi_csc_p2.bits.cscp11 = coef->csc_coef11; -+ hdmi_csc_p2.bits.cscp12 = coef->csc_coef12; -+ hdmi_csc_p3.bits.cscp20 = coef->csc_coef20; -+ hdmi_csc_p3.bits.cscp21 = coef->csc_coef21; -+ hdmi_csc_p4.bits.cscp22 = coef->csc_coef22; -+ -+ vo_reg->hdmi_csc_p0.u32 = hdmi_csc_p0.u32; -+ vo_reg->hdmi_csc_p1.u32 = hdmi_csc_p1.u32; -+ vo_reg->hdmi_csc_p2.u32 = hdmi_csc_p2.u32; -+ vo_reg->hdmi_csc_p3.u32 = hdmi_csc_p3.u32; -+ vo_reg->hdmi_csc_p4.u32 = hdmi_csc_p4.u32; -+} -+ -+int vo_init(struct vop *vop); -+ -+static void vop_crtc_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ -+ struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, -+ crtc); -+ struct vop *vop = to_vop(crtc); -+ struct smart_crtc_state *s = to_smart_crtc_state(crtc->state); -+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; -+ u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; -+ u16 hdisplay = adjusted_mode->hdisplay; -+ u16 htotal = adjusted_mode->htotal; -+ u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; -+ u16 hact_end = hact_st + hdisplay; -+ u16 vdisplay = adjusted_mode->vdisplay; -+ u16 vtotal = adjusted_mode->vtotal; -+ u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; -+ u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; -+ u16 vact_end = vact_st + vdisplay; -+ ot_vo_dev dev = vop->vo_dev; -+ -+ hal_disp_syncinfo sync_info; -+ hal_disp_syncinv inv = {0}; -+ uint32_t pin_pol, val; -+ int ret; -+ -+ if (old_state && old_state->self_refresh_active) { -+ drm_crtc_vblank_on(crtc); -+ return; -+ } -+ mutex_lock(&vop->vop_lock); -+ vo_init(vop); -+ WARN_ON(vop->event); -+ vop->is_enabled = true; -+ mutex_unlock(&vop->vop_lock); -+ drm_crtc_vblank_on(crtc); -+} -+ -+static int vop_crtc_atomic_check(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); -+ struct vop *vop = to_vop(crtc); -+ struct drm_plane *plane; -+ struct drm_plane_state *plane_state; -+ struct smart_crtc_state *s; -+ int afbc_planes = 0; -+ -+ drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { -+ plane_state = -+ drm_atomic_get_plane_state(crtc_state->state, plane); -+ if (IS_ERR(plane_state)) { -+ printk("Cannot get plane state for plane %s\n", -+ plane->name); -+ return PTR_ERR(plane_state); -+ } -+ -+ if (drm_is_afbc(plane_state->fb->modifier)) -+ ++afbc_planes; -+ } -+ -+ -+ return 0; -+} -+ -+static void vop_crtc_atomic_flush(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct drm_pending_vblank_event *event = crtc->state->event; -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); -+ struct drm_atomic_state *old_state = old_crtc_state->state; -+ struct drm_plane_state *old_plane_state, *new_plane_state; -+ struct vop *vop = to_vop(crtc); -+ struct drm_plane *plane; -+ struct smart_crtc_state *s; -+ int i; -+ -+ if (event) { -+ WARN_ON(drm_crtc_vblank_get(crtc) != 0); -+ -+ spin_lock_irq(&crtc->dev->event_lock); -+ drm_crtc_arm_vblank_event(crtc, event); -+ spin_unlock_irq(&crtc->dev->event_lock); -+ crtc->state->event = NULL; -+ } -+ -+ -+ for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, -+ new_plane_state, i) { -+ if (!old_plane_state->fb) -+ continue; -+ -+ if (old_plane_state->fb == new_plane_state->fb) -+ continue; -+ -+ drm_framebuffer_get(old_plane_state->fb); -+ WARN_ON(drm_crtc_vblank_get(crtc) != 0); -+ drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); -+ } -+} -+ -+static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { -+ .mode_valid = vop_crtc_mode_valid, -+ .mode_fixup = vop_crtc_mode_fixup, -+ .atomic_check = vop_crtc_atomic_check, -+ .atomic_begin = vop_crtc_atomic_begin, -+ .atomic_flush = vop_crtc_atomic_flush, -+ .atomic_enable = vop_crtc_atomic_enable, -+ .atomic_disable = vop_crtc_atomic_disable, -+}; -+ -+static void vop_crtc_destroy(struct drm_crtc *crtc) -+{ -+ drm_crtc_cleanup(crtc); -+} -+ -+static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) -+{ -+ struct smart_crtc_state *smart_state; -+ if (WARN_ON(!crtc->state)) -+ return NULL; -+ -+ smart_state = kmemdup(to_smart_crtc_state(crtc->state), -+ sizeof(*smart_state), GFP_KERNEL); -+ if (!smart_state) -+ return NULL; -+ -+ __drm_atomic_helper_crtc_duplicate_state(crtc, &smart_state->base); -+ return &smart_state->base; -+} -+ -+static void vop_crtc_destroy_state(struct drm_crtc *crtc, -+ struct drm_crtc_state *state) -+{ -+ struct smart_crtc_state *s = to_smart_crtc_state(state); -+ __drm_atomic_helper_crtc_destroy_state(&s->base); -+ kfree(s); -+} -+ -+static void vop_crtc_reset(struct drm_crtc *crtc) -+{ -+ struct smart_crtc_state *state; -+ if (crtc->state) { -+ __drm_atomic_helper_crtc_destroy_state(crtc->state); -+ state = to_smart_crtc_state(crtc->state); -+ kfree(state); -+ crtc->state = NULL; -+ } -+ -+ state = kzalloc(sizeof(*state), GFP_KERNEL); -+ if (state == NULL) -+ return; -+ -+ __drm_atomic_helper_crtc_reset(crtc, &state->base); -+ state->intf_type = OT_VO_INTF_HDMI; -+ state->intf_sync = OT_VO_OUT_1080P60; -+ state->bg_color = COLOR_RGB_BLUE; -+ state->encoder_type = DRM_MODE_ENCODER_TMDS; -+} -+ -+static int vop_crtc_set_crc_source(struct drm_crtc *crtc, -+ const char *source_name) -+{ -+ -+ return -ENODEV; -+} -+ -+static int -+vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, -+ size_t *values_cnt) -+{ -+ -+ return -ENODEV; -+} -+ -+ -+static const struct drm_crtc_funcs vop_crtc_funcs = { -+ .set_config = drm_atomic_helper_set_config, -+ .page_flip = drm_atomic_helper_page_flip, -+ .destroy = vop_crtc_destroy, -+ .reset = vop_crtc_reset, -+ .atomic_duplicate_state = vop_crtc_duplicate_state, -+ .atomic_destroy_state = vop_crtc_destroy_state, -+ .enable_vblank = vop_crtc_enable_vblank, -+ .disable_vblank = vop_crtc_disable_vblank, -+ .set_crc_source = vop_crtc_set_crc_source, -+ .verify_crc_source = vop_crtc_verify_crc_source, -+}; -+ -+static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) -+{ -+ struct vop *vop = container_of(work, struct vop, fb_unref_work); -+ struct drm_framebuffer *fb = val; -+ drm_crtc_vblank_put(&vop->crtc); -+ drm_framebuffer_put(fb); -+} -+ -+void hal_disp_get_int_state_vblank(ot_vo_dev dev, bool *vblank) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_dhd0_state dhd0_state; -+ volatile unsigned long addr_reg; -+ -+ -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_state.u32)); -+ dhd0_state.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ *vblank = dhd0_state.bits.vblank; -+} -+ -+static const uint32_t formats_win_full[] = { -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_NV12, -+ DRM_FORMAT_YUYV, -+}; -+ -+const size_t formats_win_full_size = ARRAY_SIZE(formats_win_full); -+ -+static const uint32_t formats_win_overlay[] = { -+ DRM_FORMAT_NV12, -+ DRM_FORMAT_YUYV, -+ DRM_FORMAT_YUV420, /* Planar YUV420 */ -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_ABGR8888, -+}; -+ -+const size_t formats_win_overlay_size = ARRAY_SIZE(formats_win_overlay); -+ -+static const uint64_t format_modifiers_win_full[] = { -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID, -+}; -+ -+static int vop_create_crtc(struct vop *vop) -+{ -+ struct device *dev = vop->dev; -+ struct drm_device *drm_dev = vop->drm_dev; -+ struct drm_plane *plane, *tmp; -+ struct drm_crtc *crtc = &vop->crtc; -+ struct device_node *port; -+ int ret; -+ int i; -+ -+ /* -+ * Create drm_plane for primary and cursor planes first, since we need -+ * to pass them to drm_crtc_init_with_planes, which sets the -+ * "possible_crtcs" to the newly initialized crtc. -+ */ -+ plane = &vop->primary_plane; -+ ret = drm_universal_plane_init(vop->drm_dev, plane, -+ 1 << drm_crtc_index(crtc), &vop_plane_funcs, -+ formats_win_full, -+ formats_win_full_size, -+ format_modifiers_win_full, -+ DRM_PLANE_TYPE_PRIMARY, NULL); -+ -+ if (ret) { -+ printk("failed to init plane %d\n", -+ ret); -+ goto err_cleanup_planes; -+ } -+ -+ drm_plane_helper_add(plane, &plane_helper_funcs); -+ drm_plane_create_zpos_immutable_property(plane, 0); -+ drm_plane_create_alpha_property(plane); -+ drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, -+ DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | -+ DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y); -+ -+ -+ -+ -+ ret = drm_crtc_init_with_planes(drm_dev, crtc, &vop->primary_plane, NULL, -+ &vop_crtc_funcs, NULL); -+ if (ret) -+ goto err_cleanup_planes; -+ -+ drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); -+ -+ -+ port = of_get_child_by_name(dev->of_node, "port"); -+ if (!port) { -+ DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", -+ dev->of_node); -+ ret = -ENOENT; -+ goto err_cleanup_crtc; -+ } -+ drm_flip_work_init(&vop->fb_unref_work, "fb_unref", -+ vop_fb_unref_worker); -+ -+ crtc->port = port; -+ -+ ret = drm_self_refresh_helper_init(crtc); -+ if (ret) -+ DRM_DEV_DEBUG_KMS(vop->dev, -+ "Failed to init %s with SR helpers %d, ignoring\n", -+ crtc->name, ret); -+ return 0; -+ -+err_cleanup_crtc: -+ drm_crtc_cleanup(crtc); -+ -+err_cleanup_planes: -+ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, -+ head) -+ drm_plane_cleanup(plane); -+ printk("Failed to %s,ret:%d\n",__func__,ret); -+ return ret; -+} -+ -+static void vop_destroy_crtc(struct vop *vop) -+{ -+ struct drm_crtc *crtc = &vop->crtc; -+ struct drm_device *drm_dev = vop->drm_dev; -+ struct drm_plane *plane, *tmp; -+ -+ drm_self_refresh_helper_cleanup(crtc); -+ -+ of_node_put(crtc->port); -+ -+ /* -+ * We need to cleanup the planes now. Why? -+ * -+ * The planes are "&vop->win[i].base". That means the memory is -+ * all part of the big "struct vop" chunk of memory. That memory -+ * was devm allocated and associated with this component. We need to -+ * free it ourselves before vop_unbind() finishes. -+ */ -+ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, -+ head) -+ vop_plane_destroy(plane); -+ -+ /* -+ * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() -+ * references the CRTC. -+ */ -+ drm_crtc_cleanup(crtc); -+ drm_flip_work_cleanup(&vop->fb_unref_work); -+} -+ -+static void *g_reg_crg_base_addr = NULL; -+static void *g_reg_sys_base_addr = NULL; -+static void *g_reg_ddr0_base_addr = NULL; -+static void *g_reg_misc_base_addr = NULL; -+static void *g_reg_crg_pll_addr = NULL; -+static void *g_reg_otp_user_base_addr = NULL; -+ -+#define io_crg_address(x) ((uintptr_t)g_reg_crg_base_addr + ((x) - (CRG_REGS_ADDR) - (CRG_REGS_ADDR_OFFSET))) -+#define io_sys_address(x) ((uintptr_t)g_reg_sys_base_addr + ((x) - (SYS_REGS_ADDR))) -+#define io_ddr0_address(x) ((uintptr_t)g_reg_ddr0_base_addr + ((x) - (DDRC0_REG_ADDR))) -+#define io_misc_address(x) ((uintptr_t)g_reg_misc_base_addr + ((x) - (MISC_REGS_ADDR))) -+#define io_crg_pll_address(x) ((uintptr_t)g_reg_crg_pll_addr + ((x) - (CRG_REGS_ADDR))) -+#define io_otp_user_address(x) ((uintptr_t)g_reg_otp_user_base_addr + ((x) - (OTP_USER_REGS_ADDR))) -+ -+static inline int sys_hal_remap_reg(void **reg_ptr, phys_addr_t phys_addr, unsigned long size) -+{ -+ if (*reg_ptr == NULL) { -+ *reg_ptr = (void *)ioremap(phys_addr, size); -+ if (*reg_ptr == NULL) { -+ return -1; -+ } -+ } -+ -+ return 0; -+} -+ -+void sys_hal_exit(void) -+{ -+ if (g_reg_crg_base_addr != NULL) { -+ iounmap(g_reg_crg_base_addr); -+ g_reg_crg_base_addr = NULL; -+ } -+ -+ if (g_reg_sys_base_addr != NULL) { -+ iounmap(g_reg_sys_base_addr); -+ g_reg_sys_base_addr = NULL; -+ } -+ if (g_reg_ddr0_base_addr != NULL) { -+ iounmap(g_reg_ddr0_base_addr); -+ g_reg_ddr0_base_addr = NULL; -+ } -+ -+ if (g_reg_misc_base_addr != NULL) { -+ iounmap(g_reg_misc_base_addr); -+ g_reg_misc_base_addr = NULL; -+ } -+ -+ -+ if (g_reg_crg_pll_addr != NULL) { -+ iounmap((void *)g_reg_crg_pll_addr); -+ g_reg_crg_pll_addr = NULL; -+ } -+ -+ if (g_reg_otp_user_base_addr != NULL) { -+ iounmap(g_reg_otp_user_base_addr); -+ g_reg_otp_user_base_addr = NULL; -+ } -+ -+} -+ -+int sys_hal_init(void) -+{ -+ -+ if (sys_hal_remap_reg(&g_reg_crg_base_addr, CRG_REGS_ADDR + CRG_REGS_ADDR_OFFSET, CRG_REGS_SIZE) != 0) { -+ printk("remap crg reg fail, line: %d.\n", __LINE__); -+ goto sys_hal_fail; -+ } -+ -+ if (sys_hal_remap_reg(&g_reg_crg_pll_addr, CRG_REGS_ADDR, CRG_REGS_ADDR_OFFSET) != 0) { -+ printk("remap crg pll reg fail, line: %d.\n", __LINE__); -+ goto sys_hal_fail; -+ } -+ -+ if (sys_hal_remap_reg(&g_reg_sys_base_addr, SYS_REGS_ADDR, SYS_REGS_SIZE) != 0) { -+ printk("remap sys reg fail, line: %d.\n", __LINE__); -+ goto sys_hal_fail; -+ } -+ -+ if (sys_hal_remap_reg(&g_reg_ddr0_base_addr, DDRC0_REG_ADDR, DDRC_REGS_SIZE) != 0) { -+ printk("remap ddr0 reg fail, line: %d.\n", __LINE__); -+ goto sys_hal_fail; -+ } -+ -+ if (sys_hal_remap_reg(&g_reg_misc_base_addr, MISC_REGS_ADDR, MISC_REGS_SIZE) != 0) { -+ printk("remap MISC reg fail, line: %d.\n", __LINE__); -+ goto sys_hal_fail; -+ } -+ if (sys_hal_remap_reg(&g_reg_otp_user_base_addr, OTP_USER_REGS_ADDR, OTP_USER_REGS_SIZE) != 0) { -+ goto sys_hal_fail; -+ } -+ -+ return 0; -+ -+sys_hal_fail: -+ sys_hal_exit(); -+ return -1; -+} -+ -+static void ot_reg_set_bit(unsigned long value, unsigned long offset, unsigned long addr) -+{ -+ unsigned long t, mask; -+ unsigned long ul_flags; -+ -+ mask = 1 << offset; -+ t = readl((const volatile void *)(uintptr_t)addr); -+ t &= ~mask; -+ t |= (value << offset) & mask; -+ writel(t, (volatile void *)(uintptr_t)addr); -+} -+ -+int sys_hal_vo_bus_reset_sel(bool reset) -+{ -+ const unsigned int tmp = (reset == 1) ? 1 : 0; -+ const unsigned int bit = 0; /* 0: 0bit */ -+ -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8336_ADDR)); -+ return 0; -+} -+ -+void vo_lpw_bus_reset(bool reset) -+{ -+ sys_hal_vo_bus_reset_sel(reset); -+} -+ -+static void vo_init_set_sys_clk(void) -+{ -+ /* 撤销复位 */ -+ vo_lpw_bus_reset(0); -+} -+ -+int sys_hal_vo_cfg_clk_en(bool clk_en) -+{ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ const unsigned int bit = 6; /* 6: 6bit */ -+ -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8340_ADDR)); -+ -+ return 0; -+} -+ -+int sys_hal_vo_apb_clk_en(bool clk_en) -+{ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ const unsigned int bit = 8; /* 8: 8bit */ -+ -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8336_ADDR)); -+ -+ return 0; -+} -+ -+/* VO AXI BUS CLK */ -+int sys_hal_vo_bus_clk_en(bool clk_en) -+{ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ const unsigned int bit = 9; /* 9: 9bit */ -+ -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8336_ADDR)); -+ return 0; -+} -+ -+/* PPC */ -+int sys_hal_vo_core_clk_en(int dev, bool clk_en) -+{ -+ const unsigned int bit = 5; /* 5: 5bit */ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ unsigned long rval = 0; -+ -+ if ((dev == 0) || (dev == 1)) { -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8340_ADDR)); -+ return 0; -+ } -+ return -1; -+} -+ -+/* VO SD DATE */ -+int sys_hal_vo_sd_date_clk_en(int vo_dev, bool clk_en) -+{ -+ const unsigned int bit = 4; /* 4: 4bit */ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ -+ if (vo_dev != 1) { -+ return -1; -+ } -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8342_ADDR)); -+ return 0; -+} -+ -+void vo_drv_set_all_crg_clk(int vo_dev,bool clk_en) -+{ -+ sys_hal_vo_cfg_clk_en(clk_en); -+ sys_hal_vo_apb_clk_en(clk_en); -+ sys_hal_vo_bus_clk_en(clk_en); -+ sys_hal_vo_core_clk_en(vo_dev, clk_en); -+ -+ /* need open sd date crg */ -+ sys_hal_vo_sd_date_clk_en(vo_dev, clk_en); -+} -+ -+ -+static void vo_init_crg_clk(int vo_dev) -+{ -+ vo_drv_set_all_crg_clk(vo_dev,1); -+} -+ -+int sys_hal_vo_hdmi_clk_en(int vo_dev, bool hdmi_clk_en) -+{ -+ const unsigned int bit_pixel = 4; /* 4: 4bit */ -+ const unsigned int bit_vdp = 5; /* 5: 5bit */ -+ const unsigned int tmp = (hdmi_clk_en == 1) ? 1 : 0; -+ -+ ot_reg_set_bit(tmp, bit_pixel, io_crg_address(CRG_PERCTL8351_ADDR)); -+ ot_reg_set_bit(tmp, bit_vdp, io_crg_address(CRG_PERCTL8351_ADDR)); -+ -+ return 0; -+} -+ -+static void ot_reg_write32(unsigned long value, unsigned long mask, unsigned long addr) -+{ -+ unsigned long t; -+ -+ t = readl((const volatile void *)(uintptr_t)addr); -+ t &= ~mask; -+ t |= value & mask; -+ writel(t, (volatile void *)(uintptr_t)addr); -+} -+ -+int sys_hal_vo_hdmi_clk_sel(int vo_dev, unsigned int clk_ch_sel) -+{ -+ const unsigned int bit = 20; /* 20: 20bit */ -+ const unsigned int mask = 0x1; -+ -+ if (vo_dev == 0) { -+ ot_reg_write32(clk_ch_sel << bit, mask << bit, io_crg_address(CRG_PERCTL8351_ADDR)); -+ return 0; -+ } -+ return -1; -+} -+ -+static void vo_drv_set_intf_hdmi_cfg(ot_vo_dev dev) -+{ -+ bool hdmi_clk_en = 1; -+ bool hdmi_clk_sel = dev; -+ sys_hal_vo_hdmi_clk_en(dev, hdmi_clk_en); -+ sys_hal_vo_hdmi_clk_sel(dev, hdmi_clk_sel); -+ vo_hal_intf_set_mux_sel_hd(dev, OT_VO_INTF_HDMI); -+} -+void vo_drv_get_pll_cfg_no_div(ot_vo_intf_sync intf_sync, ot_vo_pll *pll) -+{ -+ vo_pll_param pll_init = {OT_VO_OUT_1080P60, {99, 0, 1, 4, 4}, 0}; -+ vo_pll_param *pll_ret = &pll_init; -+ pll->post_div2 = pll_ret->pll.post_div2; -+ pll->post_div1 = pll_ret->pll.post_div1; -+ pll->frac = pll_ret->pll.frac; -+ pll->fb_div = pll_ret->pll.fb_div; -+ pll->ref_div = pll_ret->pll.ref_div; -+} -+ -+void vo_drv_dev_get_pll_cfg(ot_vo_dev dev, ot_vo_pll *pll) -+{ -+ vo_drv_get_pll_cfg_no_div(OT_VO_OUT_1080P60, pll); -+} -+ -+int sys_hal_vo_set_pll_power_ctrl(int pll, bool power_down) -+{ -+ const unsigned int bit = 20; /* 20: 20bit */ -+ const unsigned int tmp = (power_down == 1) ? 1 : 0; -+ -+ if (pll != 0) { -+ return -1; -+ } -+ -+ ot_reg_set_bit(tmp, bit, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); -+ -+ return 0; -+} -+ -+static void vo_drv_dev_set_pll_power_down(ot_vo_dev dev, bool power_down) -+{ -+ sys_hal_vo_set_pll_power_ctrl(0, power_down); -+} -+ -+int sys_hal_vo_set_pll_fbdiv(int pll, unsigned int bits_set) -+{ -+ const unsigned int bit = 0; /* 0: 0bit */ -+ const unsigned int mask = 0xfff; -+ if (pll != 0) { -+ return -1; -+ } -+ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); -+ -+ return 0; -+} -+ -+int sys_hal_vo_set_pll_frac(int pll, unsigned int bits_set) -+{ -+ const unsigned int bit = 0; -+ const unsigned int bit_dsmpd = 25; /* 25: 25bit fractional or integer mode */ -+ const unsigned int mask = 0xffffff; -+ -+ if (pll != 0) { -+ return -1; -+ } -+ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL224_ADDR)); -+ if (bits_set == 0) { -+ ot_reg_set_bit(1, bit_dsmpd, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); /* 1: integer */ -+ } else { -+ ot_reg_set_bit(0, bit_dsmpd, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); /* 0: fractional */ -+ } -+ return 0; -+} -+ -+int sys_hal_vo_set_pll_refdiv(int pll, unsigned int bits_set) -+{ -+ const unsigned int bit = 12; /* 12: 12bit */ -+ const unsigned int mask = 0x3f; -+ -+ -+ if (pll != 0) { -+ return -1; -+ } -+ -+ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL225_ADDR)); -+ -+ return 0; -+} -+ -+int sys_hal_vo_set_pll_postdiv2(int pll, unsigned int bits_set) -+{ -+ const unsigned int bit = 28; /* 28: 28bit */ -+ const unsigned int mask = 0x7; -+ -+ -+ if (pll != 0) { -+ return -1; -+ } -+ -+ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL224_ADDR)); -+ -+ return 0; -+} -+ -+int sys_hal_vo_set_pll_postdiv1(int pll, unsigned int bits_set) -+{ -+ const unsigned int bit = 24; /* 24: 24bit */ -+ const unsigned int mask = 0x7; -+ -+ -+ if (pll != 0) { -+ return -1; -+ } -+ -+ ot_reg_write32(bits_set << bit, mask << bit, io_crg_pll_address(CRG_PERCTL_PLL224_ADDR)); -+ -+ -+ return 0; -+} -+ -+void vo_drv_dev_set_pll_cfg(ot_vo_dev dev, ot_vo_pll *pll) -+{ -+ vo_drv_dev_set_pll_power_down(dev, 1); -+ sys_hal_vo_set_pll_fbdiv(0, pll->fb_div); -+ sys_hal_vo_set_pll_frac(0, pll->frac); -+ sys_hal_vo_set_pll_refdiv(0, pll->ref_div); -+ sys_hal_vo_set_pll_postdiv1(0, pll->post_div1); -+ sys_hal_vo_set_pll_postdiv2(0, pll->post_div2); -+ vo_drv_dev_set_pll_power_down(dev, 0); -+} -+ -+static void vo_drv_set_hd_clk(ot_vo_dev dev) -+{ -+ ot_vo_pll pll = {0}; -+ if (dev == VO_DEV_DHD0) { -+ vo_drv_dev_get_pll_cfg(dev, &pll); -+ vo_drv_dev_set_pll_cfg(dev, &pll); -+ return; -+ } -+} -+ -+void vo_drv_set_dev_clk(ot_vo_dev dev) -+{ -+ vo_drv_set_hd_clk(dev); -+} -+ -+int sys_hal_vo_dev_clk_en(int vo_dev, bool clk_en) -+{ -+ const unsigned int bit = 4; /* 4: 4bit */ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ -+ if (vo_dev == 0) { -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8340_ADDR)); -+ } else if (vo_dev == 1) { -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8341_ADDR)); -+ } else { -+ return -1; -+ } -+ return 0; -+} -+ -+int sys_hal_vo_lcd_clk_en(int vo_dev, bool clk_en) -+{ -+ const unsigned int tmp = (clk_en == 1) ? 1 : 0; -+ const unsigned int bit = 27; /* 27: 27bit */ -+ -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8346_ADDR)); -+ -+ return 0; -+} -+ -+void vo_drv_set_dev_clk_en(ot_vo_dev dev, bool clk_en) -+{ -+ bool vo_clk_en = clk_en; -+ if ((dev == VO_DEV_DHD0) || (dev == VO_DEV_DHD1)) { -+ sys_hal_vo_dev_clk_en(dev, vo_clk_en); -+ } -+ if (dev == VO_DEV_DHD1) { -+ sys_hal_vo_lcd_clk_en(dev, vo_clk_en); -+ } -+} -+ -+int sys_hal_vo_hd_clk_sel(int dev, unsigned int clk_sel) -+{ -+ const unsigned int bit = 12; /* 12: 12bit */ -+ const unsigned int mask = 0xf; -+ -+ if (dev == 0) { -+ ot_reg_set_bit(clk_sel, bit, io_crg_address(CRG_PERCTL8340_ADDR)); -+ } else if (dev == 1) { -+ ot_reg_write32(clk_sel << bit, mask << bit, io_crg_address(CRG_PERCTL8341_ADDR)); -+ } else { -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+void vo_drv_set_dev_clk_sel(ot_vo_dev dev, unsigned int clk_sel) -+{ -+ unsigned int hd_clk_sel = clk_sel; /* hd0默认HPLL */ -+ -+ /* -+ * hd0选择时钟�? 注：hd1已经按照时序和接口在配置时钟大小的同时也配时钟源 -+ * 这里不能再配置hd1的时钟源，因为时钟源跟大小是绑定的�?? -+ */ -+ if (dev == VO_DEV_DHD0) { -+ sys_hal_vo_hd_clk_sel(dev, hd_clk_sel); -+ } -+} -+ -+/* rgbfull to yuv601full */ -+__inline static void rgb_to_yc_full(unsigned short r, unsigned short g, unsigned short b, unsigned short *y, unsigned short *cb, unsigned short *cr) -+{ -+ unsigned short y_tmp, cb_tmp, cr_tmp; -+ -+ y_tmp = (unsigned short)(((r * 76 + g * 150 + b * 29) >> 8) * 4); -+ cb_tmp = (unsigned short)(clip_min(((((b * 128 - r * 43) - g * 84) >> 8) + 128), 0) * 4); -+ cr_tmp = (unsigned short)(clip_min(((((r * 128 - g * 107) - b * 20) >> 8) + 128), 0) * 4); -+ -+ *y = MAX2(MIN2(y_tmp, 1023), 0); -+ *cb = MAX2(MIN2(cb_tmp, 1023), 0); -+ *cr = MAX2(MIN2(cr_tmp, 1023), 0); -+} -+ -+__inline static unsigned int rgb_to_yuv_full(unsigned int rgb) -+{ -+ unsigned short y, u, v; -+ -+ rgb_to_yc_full(RGB_R(rgb), RGB_G(rgb), RGB_B(rgb), &y, &u, &v); -+ -+ return YUV(y, u, v); -+} -+ -+void hal_cbm_set_cbm_bkg(hal_cbmmix mixer, const hal_disp_bkcolor *bkg) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_cbm_bkg1 cbm_bkg1; -+ volatile reg_cbm_bkg2 cbm_bkg2; -+ -+ if (mixer == HAL_CBMMIX1) { -+ cbm_bkg1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg1.u32)); -+ cbm_bkg1.bits.cbm_bkgy1 = (bkg->bkg_y); -+ cbm_bkg1.bits.cbm_bkgcb1 = (bkg->bkg_cb); -+ cbm_bkg1.bits.cbm_bkgcr1 = (bkg->bkg_cr); -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg1.u32), cbm_bkg1.u32); -+ } else if (mixer == HAL_CBMMIX2) { -+ cbm_bkg2.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg2.u32)); -+ cbm_bkg2.bits.cbm_bkgy2 = (bkg->bkg_y); -+ cbm_bkg2.bits.cbm_bkgcb2 = (bkg->bkg_cb); -+ cbm_bkg2.bits.cbm_bkgcr2 = (bkg->bkg_cr); -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_bkg2.u32), cbm_bkg2.u32); -+ } -+} -+ -+static void vo_drv_set_cbm_bkg(ot_vo_dev dev) -+{ -+ hal_disp_bkcolor bkg; -+ unsigned int bg_color; -+ unsigned int yuv_bk_grd; -+ hal_cbmmix mixer = dev; -+ -+ /* bg_color only yuv output */ -+ bg_color = COLOR_RGB_RED;//vo_drv_get_dev_bg_color(dev); -+ yuv_bk_grd = rgb_to_yuv_full(bg_color); -+ bkg.bkg_y = YUV_Y(yuv_bk_grd); -+ bkg.bkg_cb = YUV_U(yuv_bk_grd); -+ bkg.bkg_cr = YUV_V(yuv_bk_grd); -+ -+ hal_cbm_set_cbm_bkg(mixer, &bkg); -+} -+ -+bool vo_drv_is_rgb_intf(ot_vo_intf_type intf_type) -+{ -+ if (((intf_type & OT_VO_INTF_RGB_6BIT) != 0) || -+ ((intf_type & OT_VO_INTF_RGB_8BIT) != 0) || -+ ((intf_type & OT_VO_INTF_RGB_16BIT) != 0) || -+ ((intf_type & OT_VO_INTF_RGB_18BIT) != 0) || -+ ((intf_type & OT_VO_INTF_RGB_24BIT) != 0)) { -+ return 1; -+ } -+ return 0; -+} -+ -+static void vo_drv_get_div_mod_by_rgb_intf(ot_vo_intf_type intf_type, unsigned int *div_mode) -+{ -+ if ((OT_VO_INTF_RGB_8BIT & intf_type) != 0) { -+ *div_mode = 3; /* 3: 4div */ -+ } else if ((OT_VO_INTF_RGB_6BIT & intf_type) != 0) { -+ *div_mode = 2; /* 2: 3div */ -+ } else if (((OT_VO_INTF_RGB_16BIT & intf_type) != 0) || -+ ((OT_VO_INTF_RGB_18BIT & intf_type) != 0) || -+ ((OT_VO_INTF_RGB_24BIT & intf_type) != 0)) { -+ *div_mode = 0; /* 0: 1div */ -+ } -+} -+ -+void vo_drv_get_div_mod(ot_vo_dev dev, unsigned int *div_mode) -+{ -+ ot_vo_intf_type intf_type = OT_VO_INTF_HDMI; -+ -+ if ((OT_VO_INTF_HDMI & intf_type) != 0) { -+ *div_mode = 0; /* 0: 1div */ -+ } -+ -+ if ((OT_VO_INTF_BT1120 & intf_type) != 0) { -+ *div_mode = 0; /* 0: 1div */ -+ } -+ -+ if ((OT_VO_INTF_BT656 & intf_type) != 0) { -+ *div_mode = 1; /* 1: 2div */ -+ } -+ -+ if ((OT_VO_INTF_CVBS & intf_type) != 0) { -+ *div_mode = 3; /* 0: 1div, 1: 2div, 2: 3div, 3: 4div */ -+ } -+ -+ if (vo_drv_is_rgb_intf(intf_type)) { -+ vo_drv_get_div_mod_by_rgb_intf(intf_type, div_mode); -+ } -+} -+ -+/* VO HD dev div_mode */ -+int sys_hal_vo_dev_div_mode(int vo_dev, unsigned int div_mod) -+{ -+ const unsigned int bit = 24; /* 24: 24bit */ -+ const unsigned int mask = 0x3; -+ -+ if (vo_dev == 0) { -+ ot_reg_write32(div_mod << bit, mask << bit, io_crg_address(CRG_PERCTL8340_ADDR)); -+ } else if (vo_dev == 1) { -+ ot_reg_write32(div_mod << bit, mask << bit, io_crg_address(CRG_PERCTL8341_ADDR)); -+ } else { -+ return -1; -+ } -+ return 0; -+} -+ -+static void vo_drv_set_div_mod(ot_vo_dev dev, unsigned int div_mode) -+{ -+ sys_hal_vo_dev_div_mode(dev, div_mode); -+} -+ -+bool vo_drv_is_bt_intf(ot_vo_intf_type intf_type) -+{ -+ if (((intf_type & OT_VO_INTF_BT1120) != 0) || ((intf_type & OT_VO_INTF_BT656) != 0)) { -+ return 1; -+ } -+ return 0; -+} -+ -+int sys_hal_vo_out_hd_phase_ctrl(int vo_dev, bool reverse) -+{ -+ const unsigned int tmp = (reverse == 1) ? 1 : 0; -+ const unsigned int bit = 20; /* 20: 20bit */ -+ -+ if ((vo_dev != 0) && (vo_dev != 1)) { -+ return -1; -+ } -+ -+ ot_reg_set_bit(tmp, bit, io_crg_address(CRG_PERCTL8338_ADDR)); -+ return 0; -+} -+ -+void vo_drv_set_clk_reverse(ot_vo_dev dev, bool reverse) -+{ -+ ot_vo_intf_type intf_type = OT_VO_INTF_HDMI; -+ if ((vo_drv_is_rgb_intf(intf_type) != 1) && (vo_drv_is_bt_intf(intf_type) != 1)) { -+ return; -+ } -+ sys_hal_vo_out_hd_phase_ctrl(dev, reverse); -+} -+ -+static bool vo_drv_get_dev_clk_reverse(ot_vo_dev dev) -+{ -+ bool clk_reverse_en = 1; -+ ot_vo_intf_type intf_type = OT_VO_INTF_HDMI; -+ if ((intf_type & OT_VO_INTF_RGB_24BIT) != 0) { -+ clk_reverse_en = 0; -+ } -+ -+ return clk_reverse_en; -+} -+ -+static void vo_drv_set_dev_clk_reverse(ot_vo_dev dev) -+{ -+ -+ bool clk_reverse_en = vo_drv_get_dev_clk_reverse(dev); -+ vo_drv_set_clk_reverse(dev, clk_reverse_en); -+} -+ -+/* 打开、关闭中�? */ -+void hal_disp_set_int_mask(unsigned int mask_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vointmsk vo_intmsk; -+ /* display interrupt mask enable */ -+ vo_intmsk.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32)); -+ vo_intmsk.u32 = vo_intmsk.u32 | mask_en; -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32), vo_intmsk.u32); -+} -+ -+void hal_disp_clr_int_mask(unsigned int mask_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vointmsk vo_intmsk; -+ /* display interrupt mask enable */ -+ vo_intmsk.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32)); -+ vo_intmsk.u32 = vo_intmsk.u32 & (~mask_en); -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk.u32), vo_intmsk.u32); -+} -+/* -+ * VTTHD1 : VO 垂直时序中断 -+ */ -+static unsigned int vo_drv_get_basic_int_type(ot_vo_dev dev) -+{ -+ unsigned int int_type = 0; -+ -+ if (dev == VO_DEV_DHD0) { -+ int_type = VO_INTMSK_DHD0_VTTHD1; -+ } else if (dev == VO_DEV_DHD1) { -+ int_type = VO_INTMSK_DHD1_VTTHD1 | VO_INTMSK_CVBS_VDAC; -+ } -+ return int_type; -+} -+ -+static void vo_drv_dev_vo_int_enable(ot_vo_dev dev, bool enable) -+{ -+ unsigned int int_type; -+ -+ int_type = vo_drv_get_basic_int_type(dev); -+ if (enable == 1) { -+ hal_disp_set_int_mask(int_type); -+ } else { -+ hal_disp_clr_int_mask(int_type); -+ } -+} -+/* -+ * VTTHD2 : gfbg 垂直时序中断 -+ * VTTHD3 : gfbg 帧起始中�? -+ */ -+static unsigned int vo_drv_get_gfbg_basic_int_type(ot_vo_dev dev) -+{ -+ unsigned int gfbg_int_type = 0; -+ -+ if (dev == VO_DEV_DHD0) { -+ gfbg_int_type = VO_INTMSK_DHD0_VTTHD2 | VO_INTMSK_DHD0_VTTHD3; -+ } else if (dev == VO_DEV_DHD1) { -+ gfbg_int_type = VO_INTMSK_DHD1_VTTHD2 | VO_INTMSK_DHD1_VTTHD3; -+ } -+ return gfbg_int_type; -+} -+ -+void hal_disp_set_int_mask1(unsigned int mask_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vointmsk1 vo_intmsk1; -+ /* display interrupt mask enable */ -+ vo_intmsk1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32)); -+ vo_intmsk1.u32 = vo_intmsk1.u32 | mask_en; -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32), vo_intmsk1.u32); -+} -+ -+void hal_disp_clr_int_mask1(unsigned int mask_en) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_vointmsk1 vo_intmsk1; -+ /* display interrupt mask enable */ -+ vo_intmsk1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32)); -+ vo_intmsk1.u32 = vo_intmsk1.u32 & (~mask_en); -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vointmsk1.u32), vo_intmsk1.u32); -+} -+ -+static void vo_drv_dev_gfbg_int_enable(ot_vo_dev dev, bool enable) -+{ -+ unsigned int gfbg_int_type; -+ gfbg_int_type = vo_drv_get_gfbg_basic_int_type(dev); -+ if (enable == 1) { -+ hal_disp_set_int_mask1(gfbg_int_type); -+ } else { -+ hal_disp_clr_int_mask1(gfbg_int_type); -+ } -+} -+ -+void vo_drv_dev_int_enable(ot_vo_dev dev, bool enable) -+{ -+ vo_drv_dev_vo_int_enable(dev, enable); -+ vo_drv_dev_gfbg_int_enable(dev, enable); -+} -+ -+static void vo_set_drv_dev_int_enable(void) -+{ -+ ot_vo_dev dev; -+ for (dev = 0; dev < OT_VO_MAX_PHYS_DEV_NUM; dev++) { -+ vo_drv_dev_int_enable(dev, 1); -+ } -+} -+ -+void hal_cbm_set_cbm_attr(hal_disp_layer layer, ot_vo_dev dev) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_link_ctrl link_ctrl; -+ link_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->link_ctrl.u32)); -+ if (layer == HAL_DISP_LAYER_VHD2) { -+ link_ctrl.bits.v2_link = dev; -+ } else if (layer == HAL_DISP_LAYER_GFX3) { -+ link_ctrl.bits.g3_link = dev; -+ } -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->link_ctrl.u32), link_ctrl.u32); -+} -+ -+bool hal_cbm_get_cbm_mixer_layer_id(const vo_hal_cbm_mixer *cbm_mixer, unsigned int cbm_len, -+ ot_vo_layer layer, unsigned char *layer_id) -+{ -+ unsigned int index; -+ for (index = 0; index < cbm_len; index++) { -+ if (layer == cbm_mixer[index].layer) { -+ *layer_id = cbm_mixer[index].layer_id; -+ return true; -+ } -+ } -+ -+ printk("error layer id %d found\n", layer); -+ return false; -+} -+ -+static bool hal_cbm_get_cbm1_mixer_layer_id(ot_vo_layer layer, unsigned char *layer_id) -+{ -+ const vo_hal_cbm_mixer cbm1_mixer[] = { -+ { OT_VO_LAYER_V0, 0x1 }, -+ { OT_VO_LAYER_V2, 0x3 }, -+ { OT_VO_LAYER_G0, 0x2 }, -+ { OT_VO_LAYER_G3, 0x4 }, -+ { VO_LAYER_BUTT, 0x0 } -+ }; -+ -+ unsigned int cbm1_len = sizeof(cbm1_mixer) / sizeof(vo_hal_cbm_mixer); -+ return hal_cbm_get_cbm_mixer_layer_id(cbm1_mixer, cbm1_len, layer, layer_id); -+} -+ -+static bool hal_cbm_get_cbm2_mixer_layer_id(ot_vo_layer layer, unsigned char *layer_id) -+{ -+ const vo_hal_cbm_mixer cbm2_mixer[] = { -+ { OT_VO_LAYER_V1, 0x1 }, -+ { OT_VO_LAYER_V2, 0x3 }, -+ { OT_VO_LAYER_G1, 0x2 }, -+ { OT_VO_LAYER_G3, 0x4 }, -+ { VO_LAYER_BUTT, 0x0 } -+ }; -+ -+ unsigned int cbm2_len = sizeof(cbm2_mixer) / sizeof(vo_hal_cbm_mixer); -+ return hal_cbm_get_cbm_mixer_layer_id(cbm2_mixer, cbm2_len, layer, layer_id); -+} -+ -+static void hal_cbm_set_cbm1_mixer_prio(ot_vo_layer layer, unsigned char prio) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_cbm_mix1 cbm_mix1; -+ unsigned char layer_id = 0; -+ -+ /* check layer availability */ -+ if (hal_cbm_get_cbm1_mixer_layer_id(layer, &layer_id) != true) { -+ return; -+ } -+ -+ /* set mixer prio */ -+ cbm_mix1.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix1.u32)); -+ -+ switch (prio) { -+ case 0: /* 0: prio 0 */ -+ cbm_mix1.bits.mixer_prio0 = layer_id; -+ break; -+ -+ case 1: /* 1: prio 1 */ -+ cbm_mix1.bits.mixer_prio1 = layer_id; -+ break; -+ -+ case 2: /* 2: prio 2 */ -+ cbm_mix1.bits.mixer_prio2 = layer_id; -+ break; -+ -+ case 3: /* 3: prio 3 */ -+ cbm_mix1.bits.mixer_prio3 = layer_id; -+ break; -+ -+ default: -+ printk("error priority id %d found\n", prio); -+ return; -+ } -+ -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix1.u32), cbm_mix1.u32); -+} -+ -+static void hal_cbm_set_cbm2_mixer_prio(ot_vo_layer layer, unsigned char prio) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_cbm_mix2 cbm_mix2; -+ unsigned char layer_id = 0; -+ -+ /* check layer availability */ -+ if (hal_cbm_get_cbm2_mixer_layer_id(layer, &layer_id) != true) { -+ return; -+ } -+ -+ /* set mixer prio */ -+ cbm_mix2.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix2.u32)); -+ -+ switch (prio) { -+ case 0: /* 0: prio 0 */ -+ cbm_mix2.bits.mixer_prio0 = layer_id; -+ break; -+ -+ case 1: /* 1: prio 1 */ -+ cbm_mix2.bits.mixer_prio1 = layer_id; -+ break; -+ -+ case 2: /* 2: prio 2 */ -+ cbm_mix2.bits.mixer_prio2 = layer_id; -+ break; -+ -+ case 3: /* 3: prio 3 */ -+ cbm_mix2.bits.mixer_prio3 = layer_id; -+ break; -+ -+ default: -+ printk("error priority id %d found\n", prio); -+ return; -+ } -+ -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->cbm_mix2.u32), cbm_mix2.u32); -+} -+ -+void hal_cbm_set_cbm_mixer_prio(ot_vo_layer layer, unsigned char prio, unsigned char mixer_id) -+{ -+ if (mixer_id == HAL_CBMMIX1) { -+ hal_cbm_set_cbm1_mixer_prio(layer, prio); -+ } else if (mixer_id == HAL_CBMMIX2) { -+ hal_cbm_set_cbm2_mixer_prio(layer, prio); -+ } -+} -+ -+void vou_drv_set_layer_priority(ot_vo_dev dev, ot_vo_layer layer, unsigned int priority) -+{ -+ -+ hal_cbm_set_cbm_mixer_prio(layer, priority, dev); -+ -+ /* need regup */ -+ hal_disp_set_reg_up(dev); -+} -+ -+void vou_drv_def_layer_bind_dev(void) -+{ -+ /* default cbm */ -+ hal_cbm_set_cbm_attr(HAL_DISP_LAYER_VHD2, VO_DEV_DHD0); -+ hal_cbm_set_cbm_attr(HAL_DISP_LAYER_GFX3, VO_DEV_DHD0); -+ -+ /* default priority dhd0 */ -+ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_V0, VOU_MIX_PRIO0); -+ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_V2, VOU_MIX_PRIO1); -+ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_G0, VOU_MIX_PRIO2); -+ vou_drv_set_layer_priority(VO_DEV_DHD0, OT_VO_LAYER_G3, VOU_MIX_PRIO3); -+ -+ /* default priority dhd1 */ -+ vou_drv_set_layer_priority(VO_DEV_DHD1, OT_VO_LAYER_V1, VOU_MIX_PRIO0); -+ vou_drv_set_layer_priority(VO_DEV_DHD1, OT_VO_LAYER_G1, VOU_MIX_PRIO2); -+ -+ /* need regup */ -+ hal_disp_set_reg_up(VO_DEV_DHD0); -+ hal_disp_set_reg_up(VO_DEV_DHD1); -+} -+ -+void hal_sys_set_outstanding(void) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_mac_outstanding mac_outstanding; -+ -+ mac_outstanding.u32 = hal_read_reg((unsigned int *)(uintptr_t)&(vo_reg->mac_outstanding.u32)); -+ mac_outstanding.bits.mstr0_routstanding = 0xf; /* 0xf: master 0 read outstanding */ -+ mac_outstanding.bits.mstr0_woutstanding = 0x7; /* 0x7: master 0 write outstanding */ -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->mac_outstanding.u32), mac_outstanding.u32); -+} -+ -+void hal_disp_clear_int_status(unsigned int int_msk) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ -+ /* read interrupt status */ -+ hal_write_reg((unsigned int *)(uintptr_t)&(vo_reg->vomskintsta.u32), int_msk); -+} -+ -+ot_vo_layer vo_drv_get_hw_layer(ot_vo_layer layer) -+{ -+ return layer; -+} -+ -+void vou_drv_layer_enable(ot_vo_layer layer, bool enable) -+{ -+ ot_vo_layer hw_layer = vo_drv_get_hw_layer(layer); -+ hal_video_hfir_set_ck_gt_en(hw_layer, enable); -+ hal_layer_enable_layer(hw_layer, enable); -+ hal_video_set_layer_ck_gt_en(hw_layer, enable); -+} -+ -+hal_disp_layer vou_drv_convert_layer(ot_vo_layer layer) -+{ -+ hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT; -+ switch (layer) { -+ case VO_HAL_LAYER_VHD0: -+ disp_layer = HAL_DISP_LAYER_VHD0; -+ break; -+ -+ case VO_HAL_LAYER_VHD1: -+ disp_layer = HAL_DISP_LAYER_VHD1; -+ break; -+ -+ case VO_HAL_LAYER_VHD2: -+ disp_layer = HAL_DISP_LAYER_VHD2; -+ break; -+ -+ default: -+ break; -+ } -+ -+ return disp_layer; -+} -+ -+hal_disp_pixel_format vo_drv_convert_data_format(vou_layer_pixel_format data_fmt) -+{ -+ hal_disp_pixel_format pixel_format; -+ -+ if (data_fmt == VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_420) { -+ pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_420; -+ } else if (data_fmt == VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_422) { -+ pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_422; -+ } else { -+ pixel_format = HAL_INPUTFMT_YCBCR_SEMIPLANAR_400; -+ } -+ -+ return pixel_format; -+} -+ -+void vou_drv_set_layer_data_fmt(ot_vo_layer layer, vou_layer_pixel_format data_fmt) -+{ -+ ot_vo_layer hw_layer = vo_drv_get_hw_layer(layer); -+ hal_disp_layer hal_layer; -+ hal_disp_pixel_format disp_data_fmt; -+ -+ hal_layer = vou_drv_convert_layer(hw_layer); -+ disp_data_fmt = vo_drv_convert_data_format(data_fmt); -+ hal_layer_set_layer_data_fmt(hal_layer, disp_data_fmt); -+} -+ -+void vo_drv_default_setting(void) -+{ -+ unsigned int i; -+ hfir_coef h_coef[LAYER_VID_END + 1] = { -+ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a }, -+ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a }, -+ { 0x3f5, 0xf, 0x3ec, 0x1c, 0x3d8, 0x3d, 0x395, 0x14a } -+ }; -+ /* set dac default cablectr */ -+ vo_hal_intf_set_dac_cablectr(OT_VO_INTF_CVBS, VO_DAC_CABLE_CTR_DEF); -+ -+ /* set each video/graphic layer global alpha */ -+ for (i = LAYER_VID_START; i <= LAYER_GFX_END; i++) { -+ hal_layer_set_layer_global_alpha(i, VO_ALPHA_OPACITY); /* global alpha max 255 */ -+ hal_video_set_layer_alpha(i, VO_ALPHA_OPACITY); /* alpha max 255 */ -+ } -+ -+ /* select graphic layer's alpha range(0: 0~128,1:0~255) */ -+ for (i = LAYER_GFX_START; i <= LAYER_GFX_END; i++) { -+ hal_gfx_set_pixel_alpha_range(i, 1); -+ } -+ -+ /* set video layer hfir enable */ -+ for (i = LAYER_VID_START; i <= LAYER_VID_END; i++) { -+ hal_video_hfir_set_hfir_mode(i, HAL_HFIRMODE_COPY); -+ hal_video_hfir_set_coef(i, &h_coef[i]); -+ hal_video_hfir_set_mid_en(i, true); -+ } -+ -+ /* set each cross bar default PRI */ -+ vou_drv_def_layer_bind_dev(); -+ -+ /* outstanding */ -+ hal_sys_set_outstanding(); -+ -+ hal_disp_clear_int_status(VO_INTREPORT_ALL); -+ -+ /* only set video layer */ -+ for (i = LAYER_VID_START; i <= LAYER_VID_END; i++) { -+ vou_drv_layer_enable(i, false); -+ vou_drv_set_layer_data_fmt(i, VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_422); -+ } -+} -+ -+static void vo_init_default_setting(void) -+{ -+ vo_drv_default_setting(); -+} -+ -+void hal_disp_set_intf_enable(ot_vo_dev dev, bool intf) -+{ -+ volatile reg_vdp_regs *vo_reg = vo_hal_get_reg(); -+ volatile reg_dhd0_ctrl dhd0_ctrl; -+ volatile unsigned long addr_reg; -+ -+ -+ addr_reg = vou_get_chn_abs_addr(dev, (uintptr_t)&(vo_reg->dhd0_ctrl.u32)); -+ dhd0_ctrl.u32 = hal_read_reg((unsigned int *)(uintptr_t)addr_reg); -+ dhd0_ctrl.bits.intf_en = intf; -+ hal_write_reg((unsigned int *)(uintptr_t)addr_reg, dhd0_ctrl.u32); -+} -+ -+int vo_init(struct vop *vop) -+{ -+ int vo_dev = vop->vo_dev; -+ hal_disp_syncinfo sync_info; -+ hal_disp_syncinv inv = {0}; -+ unsigned int div_mode = 0; -+ -+ -+ if(sys_hal_init() != 0) { -+ printk("sys_hal_init,%s,%d bad\n",__func__,__LINE__); -+ return -1; -+ } -+ -+ vo_init_set_sys_clk(); -+ -+ /* 使能时钟 */ -+ vo_init_crg_clk(vo_dev); -+ vo_drv_set_dev_clk(vo_dev); -+ vo_drv_set_dev_clk_en(vo_dev, 1); -+ vo_drv_set_dev_clk_sel(vo_dev, 0); -+ vo_drv_set_cbm_bkg(vo_dev); -+ vo_drv_set_intf_hdmi_cfg(vo_dev); -+ -+ vo_hal_intf_set_mux_sel_hd(vo_dev, OT_VO_INTF_HDMI); -+ vo_drv_get_sync_inv(vo_dev, &inv); -+ -+ //vo_drv_set_sync_inv -+ vo_hal_intf_set_hdmi_sync_inv(&inv); -+ vo_drv_get_sync_info(vo_dev, &sync_info); -+ vo_hal_intf_set_sync_info_hvsync(vo_dev,&sync_info); -+ vo_hal_intf_set_sync_info_other(vo_dev,&sync_info); -+ vo_drv_get_div_mod(vo_dev, &div_mode); -+ vo_drv_set_div_mod(vo_dev, div_mode); -+ vo_drv_set_dev_clk_reverse(vo_dev); -+ -+ //vo_drv_set_hdmi_param -+ vo_hal_intf_set_csc_enable(OT_VO_INTF_HDMI,1); -+ vou_drv_intf_csc_config(OT_VO_INTF_HDMI, &vop->csc); -+ vo_drv_set_hdmi_mode(vo_dev, vop); -+ hal_disp_set_reg_up(vo_dev); -+ -+ /* 默认硬件配置 */ -+ vo_init_default_setting(); -+ hal_disp_set_intf_enable(vo_dev, true); -+ vo_set_drv_dev_int_enable(); -+ hal_disp_set_reg_up(vo_dev); -+ return 0; -+} -+ -+unsigned int fb_hal_disp_get_int_status(unsigned int int_msk) -+{ -+ volatile u_vomskintsta1 vomskintsta1; -+ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return 0; -+ } -+ /* read interrupt status */ -+ vomskintsta1.u32 = hal_read_reg((unsigned int *)&(g_gfbg_reg->vomskintsta1.u32)); -+ -+ return (vomskintsta1.u32 & int_msk); -+} -+/* -+ * Name : fb_hal_disp_clear_int_status -+ * Desc : Clear interrupt status. -+ */ -+bool fb_hal_disp_clear_int_status(unsigned int int_msk) -+{ -+ if (g_gfbg_reg == NULL) { -+ printk("NULL pointer %s: L%d\n", __FUNCTION__, __LINE__); -+ return false; -+ } -+ -+ hal_write_reg((unsigned int *)&(g_gfbg_reg->vomskintsta1.u32), int_msk); -+ return true; -+} -+ -+enum irqreturn vop_isr(int irq, void *data) -+{ -+ struct vop *vop = data; -+ unsigned int int_status = fb_hal_disp_get_int_status(GFBG_INTREPORT_ALL); -+ -+ -+ if (int_status & GFBG_INTMSK_DHD0_VTTHD2) { -+ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD0_VTTHD2); -+ } else if (int_status & GFBG_INTMSK_DHD0_VTTHD3) { -+ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD0_VTTHD3); -+ } else if (int_status & GFBG_INTMSK_DHD1_VTTHD2) { -+ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD1_VTTHD2); -+ } else if (int_status & GFBG_INTMSK_DHD1_VTTHD3) { -+ fb_hal_disp_clear_int_status(GFBG_INTMSK_DHD1_VTTHD3); -+ } else if (int_status & GFBG_INTMSK_DSD_VTTHD2) { -+ fb_hal_disp_clear_int_status(GFBG_INTMSK_DSD_VTTHD2); -+ } else if (int_status & GFBG_INTMSK_DSD_VTTHD3) { -+ fb_hal_disp_clear_int_status(GFBG_INTMSK_DSD_VTTHD3); -+ } -+ -+ if (vop->vblank_enabled) { -+ drm_crtc_handle_vblank(&vop->crtc); -+ spin_lock(&vop->crtc.dev->event_lock); -+ if (vop->event) { -+ drm_crtc_send_vblank_event(&vop->crtc, vop->event); -+ drm_crtc_vblank_put(&vop->crtc); -+ vop->event = NULL; -+ } -+ spin_unlock(&vop->crtc.dev->event_lock); -+ } -+ return IRQ_HANDLED; -+} -+ -+static int vop_bind(struct device *dev, struct device *master, void *data) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct drm_device *drm_dev = data; -+ struct vop *vop; -+ struct resource *res; -+ ot_vo_dev vo_dev; -+ int ret; -+ vop = devm_kzalloc(dev, sizeof(*vop),GFP_KERNEL); -+ if (!vop) { -+ printk("devm_kzalloc,%s,%d error\n",__func__,__LINE__); -+ return -ENOMEM; -+ } -+ vop->size = 4 * 1920 * 1080; -+ vop->dev = dev; -+ vop->drm_dev = drm_dev; -+ vop->vo_dev = VO_DEV_DHD0; -+ vop->csc.csc_matrix = OT_VO_CSC_MATRIX_BT709FULL_TO_RGBFULL; -+ //vop->csc.csc_matrix = OT_VO_CSC_MATRIX_BT601FULL_TO_BT601FULL; -+ vop->csc.luma = VO_CSC_DEF_VAL; -+ vop->csc.contrast = VO_CSC_DEF_VAL; -+ vop->csc.hue = VO_CSC_DEF_VAL; -+ vop->csc.saturation = VO_CSC_DEF_VAL; -+ vop->csc.ex_csc_en = 0; -+ vop->is_enabled = false; -+ vop->vblank_enabled = false; -+ vop->irq = VOU1_IRQ_NR; -+ -+ vop->sgt = dma_alloc_noncontiguous(dev, vop->size, DMA_BIDIRECTIONAL, GFP_KERNEL, 0); -+ if (!vop->sgt) { -+ printk("CMA allocation of %zu bytes failed\n", vop->size); -+ return -ENOMEM; -+ } -+ -+ vop->phys_addr = (phys_addr_t)sg_dma_address(vop->sgt->sgl); -+ vop->virt_addr = dma_vmap_noncontiguous(dev, vop->size, vop->sgt); -+ if (!vop->virt_addr) { -+ printk("Failed to map DMA memory\n"); -+ ret = -ENOMEM; -+ goto err_free_main_sgt; -+ } -+ -+ spin_lock_init(&vop->reg_lock); -+ spin_lock_init(&vop->irq_lock); -+ mutex_init(&vop->vop_lock); -+ -+ dev_set_drvdata(dev, vop); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ vop->regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(vop->regs)) -+ return PTR_ERR(vop->regs); -+ vo_hal_set_reg(vop->regs); -+ g_gfbg_reg = (volatile vdp_regs_type *)vop->regs; -+ vop->len = resource_size(res); -+ vo_init(vop); -+ ret = vop_create_crtc(vop); -+ if (ret) -+ return ret; -+ -+ vop->irq = platform_get_irq_byname(pdev, "gfbg"); -+ ret = request_threaded_irq(vop->irq , vop_isr, NULL, IRQF_SHARED, "DRM Int", vop); -+ if (ret) -+ goto err_destroy_crtc; -+ printk("%s,%d OK\n",__func__,__LINE__); -+ return 0; -+ -+err_destroy_crtc: -+ vop_destroy_crtc(vop); -+err_unmap_main: -+ dma_vunmap_noncontiguous(dev, vop->virt_addr); -+err_free_main_sgt: -+ dma_free_noncontiguous(dev, vop->size, vop->sgt, DMA_BIDIRECTIONAL); -+ printk("%s,ret:%d\n",__func__,ret); -+ return ret; -+} -+ -+static void vop_unbind(struct device *dev, struct device *master, void *data) -+{ -+ struct vop *vop = dev_get_drvdata(dev); -+ free_irq(vop->irq , vop_isr); -+ -+ if (vop->virt_addr) { -+ dma_vunmap_noncontiguous(dev, vop->virt_addr); -+ vop->virt_addr = NULL; -+ } -+ -+ if (vop->sgt) { -+ dma_free_noncontiguous(dev, vop->size, vop->sgt, DMA_BIDIRECTIONAL); -+ vop->sgt = NULL; -+ } -+ -+ vop->phys_addr = 0; -+ vop_destroy_crtc(vop); -+} -+ -+const struct component_ops vop_component_ops = { -+ .bind = vop_bind, -+ .unbind = vop_unbind, -+}; -+ -+ -+static int vop_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ return component_add(dev, &vop_component_ops); -+} -+ -+static void vop_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &vop_component_ops); -+} -+EXPORT_SYMBOL_GPL(vop_component_ops); -+ -+static const struct of_device_id vop_driver_dt_match[] = { -+ { .compatible = "vendor,gfbg"}, -+ { /* sentinel */ }, -+}; -+struct platform_driver smart_vop_driver = { -+ .probe = vop_probe, -+ .remove_new = vop_remove, -+ .driver = { -+ .name = "hi3403v100-vop", -+ .of_match_table = vop_driver_dt_match, -+ }, -+}; -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.h b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.h -new file mode 100755 -index 0000000..f6c5267 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/smart_vo.h -@@ -0,0 +1,1197 @@ -+ -+#ifndef _SMART_VOP_REG_H -+#define _SMART_VOP_REG_H -+ -+#include "smart_drm_drv.h" -+#include "hal_vo_reg.h" -+#include "hal_vo_def.h" -+#include "drv_vo_comm.h" -+ -+#include "gfbg_reg.h" -+ -+//bad -+/* AFBC supports a number of configurable modes. Relevant to us is block size -+ * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like -+ * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode -+ * could be enabled via the hreg_block_split register, but is not currently -+ * handled. The colourspace transform is implicitly always assumed by the -+ * decoder, so consumers must use this transform as well. -+ * -+ * Failure to match modifiers will cause errors displaying AFBC buffers -+ * produced by conformant AFBC producers, including Mesa. -+ */ -+ -+struct vop_rect { -+ int width; -+ int height; -+}; -+ -+struct vop_reg { -+ uint32_t mask; -+ uint16_t offset; -+ uint8_t shift; -+ bool write_mask; -+ bool relaxed; -+}; -+ -+struct vop_win_phy { -+ const uint32_t *data_formats; -+ uint32_t nformats; -+ const uint64_t *format_modifiers; -+ -+}; -+ -+struct vop_win_data { -+ uint32_t base; -+ const struct vop_win_phy *phy; -+ enum drm_plane_type type; -+}; -+ -+struct vop_data { -+ uint32_t version; -+ const struct vop_win_data *win; -+ unsigned int win_size; -+ unsigned int lut_size; -+ struct vop_rect max_output; -+ u64 feature; -+}; -+ -+/* VO video output interface type */ -+#define OT_VO_INTF_CVBS (0x01L << 0) -+#define OT_VO_INTF_VGA (0x01L << 1) -+#define OT_VO_INTF_BT656 (0x01L << 2) -+#define OT_VO_INTF_BT1120 (0x01L << 3) -+#define OT_VO_INTF_HDMI (0x01L << 4) -+#define OT_VO_INTF_RGB_6BIT (0x01L << 5) -+#define OT_VO_INTF_RGB_8BIT (0x01L << 6) -+#define OT_VO_INTF_RGB_16BIT (0x01L << 7) -+#define OT_VO_INTF_RGB_18BIT (0x01L << 8) -+#define OT_VO_INTF_RGB_24BIT (0x01L << 9) -+#define OT_VO_INTF_MIPI (0x01L << 10) -+#define OT_VO_INTF_MIPI_SLAVE (0x01L << 11) -+#define OT_VO_INTF_HDMI1 (0x01L << 12) -+ -+typedef enum { -+ OT_VO_OUT_PAL = 0, /* PAL standard */ -+ OT_VO_OUT_NTSC = 1, /* NTSC standard */ -+ OT_VO_OUT_960H_PAL = 2, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */ -+ OT_VO_OUT_960H_NTSC = 3, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */ -+ -+ OT_VO_OUT_640x480_60 = 4, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */ -+ OT_VO_OUT_480P60 = 5, /* 720 x 480 at 60 Hz. */ -+ OT_VO_OUT_576P50 = 6, /* 720 x 576 at 50 Hz. */ -+ OT_VO_OUT_800x600_60 = 7, /* VESA 800 x 600 at 60 Hz (non-interlaced) */ -+ OT_VO_OUT_1024x768_60 = 8, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */ -+ OT_VO_OUT_720P50 = 9, /* 1280 x 720 at 50 Hz. */ -+ OT_VO_OUT_720P60 = 10, /* 1280 x 720 at 60 Hz. */ -+ OT_VO_OUT_1280x800_60 = 11, /* 1280*800@60Hz VGA@60Hz */ -+ OT_VO_OUT_1280x1024_60 = 12, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */ -+ OT_VO_OUT_1366x768_60 = 13, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */ -+ OT_VO_OUT_1400x1050_60 = 14, /* VESA 1400 x 1050 at 60 Hz (non-interlaced) CVT */ -+ OT_VO_OUT_1440x900_60 = 15, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */ -+ OT_VO_OUT_1680x1050_60 = 16, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */ -+ -+ OT_VO_OUT_1080P24 = 17, /* 1920 x 1080 at 24 Hz. */ -+ OT_VO_OUT_1080P25 = 18, /* 1920 x 1080 at 25 Hz. */ -+ OT_VO_OUT_1080P30 = 19, /* 1920 x 1080 at 30 Hz. */ -+ OT_VO_OUT_1080I50 = 20, /* 1920 x 1080 at 50 Hz, interlaced. */ -+ OT_VO_OUT_1080I60 = 21, /* 1920 x 1080 at 60 Hz, interlaced. */ -+ OT_VO_OUT_1080P50 = 22, /* 1920 x 1080 at 50 Hz. */ -+ OT_VO_OUT_1080P60 = 23, /* 1920 x 1080 at 60 Hz. */ -+ -+ OT_VO_OUT_1600x1200_60 = 24, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */ -+ OT_VO_OUT_1920x1200_60 = 25, /* VESA 1920 x 1200 at 60 Hz (non-interlaced) CVT (Reduced Blanking) */ -+ OT_VO_OUT_1920x2160_30 = 26, /* 1920x2160_30 */ -+ OT_VO_OUT_2560x1440_30 = 27, /* 2560x1440_30 */ -+ OT_VO_OUT_2560x1440_60 = 28, /* 2560x1440_60 */ -+ OT_VO_OUT_2560x1600_60 = 29, /* 2560x1600_60 */ -+ -+ OT_VO_OUT_3840x2160_24 = 30, /* 3840x2160_24 */ -+ OT_VO_OUT_3840x2160_25 = 31, /* 3840x2160_25 */ -+ OT_VO_OUT_3840x2160_30 = 32, /* 3840x2160_30 */ -+ OT_VO_OUT_3840x2160_50 = 33, /* 3840x2160_50 */ -+ OT_VO_OUT_3840x2160_60 = 34, /* 3840x2160_60 */ -+ OT_VO_OUT_4096x2160_24 = 35, /* 4096x2160_24 */ -+ OT_VO_OUT_4096x2160_25 = 36, /* 4096x2160_25 */ -+ OT_VO_OUT_4096x2160_30 = 37, /* 4096x2160_30 */ -+ OT_VO_OUT_4096x2160_50 = 38, /* 4096x2160_50 */ -+ OT_VO_OUT_4096x2160_60 = 39, /* 4096x2160_60 */ -+ OT_VO_OUT_7680x4320_30 = 40, /* 7680x4320_30 */ -+ -+ OT_VO_OUT_240x320_50 = 41, /* 240x320_50 */ -+ OT_VO_OUT_320x240_50 = 42, /* 320x240_50 */ -+ OT_VO_OUT_240x320_60 = 43, /* 240x320_60 */ -+ OT_VO_OUT_320x240_60 = 44, /* 320x240_60 */ -+ OT_VO_OUT_800x600_50 = 45, /* 800x600_50 */ -+ -+ OT_VO_OUT_720x1280_60 = 46, /* For MIPI DSI Tx 720 x1280 at 60 Hz */ -+ OT_VO_OUT_1080x1920_60 = 47, /* For MIPI DSI Tx 1080x1920 at 60 Hz */ -+ -+ OT_VO_OUT_USER = 48, /* User timing. */ -+ -+ OT_VO_OUT_BUTT, -+} ot_vo_intf_sync; -+ -+typedef unsigned int ot_vo_intf_type; -+typedef int ot_vo_dev; -+#define VO_DAC_CABLE_CTR_DEF 3 -+typedef struct { -+ unsigned int syncm; -+ unsigned int iop; -+ unsigned char intfb; -+ -+ unsigned short vact; -+ unsigned short vbb; -+ unsigned short vfb; -+ -+ unsigned short hact; -+ unsigned short hbb; -+ unsigned short hfb; -+ unsigned short hmid; -+ -+ unsigned short bvact; -+ unsigned short bvbb; -+ unsigned short bvfb; -+ -+ unsigned short hpw; -+ unsigned short vpw; -+ -+ unsigned int idv; -+ unsigned int ihs; -+ unsigned int ivs; -+} hal_disp_syncinfo; -+ -+typedef struct { -+ unsigned int f_inv; -+ unsigned int vs_inv; -+ unsigned int hs_inv; -+ unsigned int dv_inv; -+} hal_disp_syncinv; -+ -+typedef enum { -+ VO_HD_HW_DEV = 0, /* HD dev */ -+ VO_SD_HW_DEV, /* SD dev */ -+ VO_UHD_HW_DEV, /* UHD dev */ -+ VO_CAS_DEV, /* cascade dev */ -+ VO_VIRT_DEV, /* virtual dev */ -+ VO_DEV_TYPE_BUTT, -+} vo_dev_type; -+ -+typedef struct { -+ vo_dev_type dev_type; /* dev type */ -+ bool support_wbc; /* WBC support or not */ -+} vo_dev_capability; -+ -+typedef struct { -+ /* 是否产生了VDAC中断,产生中断代表没有接负载 */ -+ bool int_ocurred; -+ bool detect_enabled; -+ bool is_connected; -+} vo_drv_load_detect_info; -+ -+typedef struct { -+ unsigned int bg_color; /* RW; background color of a device, in RGB format. */ -+ ot_vo_intf_type intf_type; /* RW; type of a VO interface */ -+ ot_vo_intf_sync intf_sync; /* RW; type of a VO interface timing */ -+ ot_vo_sync_info sync_info; /* RW; information about VO interface timing */ -+} ot_vo_pub_attr; -+ -+typedef struct { -+ bool vo_bypass_en; /* RW, range: [0, 1]; vo bypass enable */ -+} ot_vo_dev_param; -+ -+typedef enum { -+ OT_VO_CLK_EDGE_SINGLE = 0, /* single-edge mode */ -+ OT_VO_CLK_EDGE_DUAL, /* dual-edge mode */ -+ -+ OT_VO_CLK_EDGE_BUTT -+} ot_vo_clk_edge; -+typedef int ot_vo_layer; -+/* desc : device context, which contains device public attribute. */ -+typedef struct { -+ vo_dev_capability dev_cap; /* 设备能力级 */ -+ bool vo_enable; /* 设备使能标志 */ -+ bool config; /* 设备配置标志 */ -+ ot_vo_pub_attr vou_attr; /* 设备公共属性 */ -+ -+ unsigned int layer_num; /* 设备上包含层的数目 */ -+ unsigned int max_layer_num; /* 该设备上能包含的最多的层数，包括视频层和图形层 */ -+ ot_vo_layer layer[OT_VO_MAX_PRIORITY + 1]; /* 对应的优先级的层，如aen_layer[0]即该设备上优先级为0的层 */ -+ -+ unsigned int max_width; /* 设备分辨率最大宽度 */ -+ unsigned int max_height; /* 设备分辨率最大高度 */ -+ -+ bool less_buf_enable; /* 省BUF的标记 */ -+ bool user_notify_enable; /* 通知用户的标记 */ -+ unsigned int vtth; /* 提前完成中断垂直时序值 */ -+ unsigned int vtth2; /* 省BUF垂直时序值 */ -+ bool bt_param_config; /* bt_param配置标志，用于单双沿配置 */ -+ ot_vo_clk_edge clk_edge; /* 单双沿配置,默认单沿 */ -+ -+ bool dac_power_up; -+ vo_drv_load_detect_info load_detect_info; /* 负载检测 */ -+ unsigned int low_bandwidth_cnt; /* 统计VO低带宽信息 */ -+ unsigned long long bus_err; /* 统计VO bus err */ -+ unsigned int low_delay_err; /* 统计低延时错误 */ -+ -+ ot_vo_dev_param dev_param; -+} vo_drv_dev; -+ -+typedef enum { -+ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT601LIMIT = 0, /* Identity matrix. from BT.601 limit to BT.601 limit */ -+ OT_VO_CSC_MATRIX_BT601FULL_TO_BT601LIMIT = 1, /* Change color space from BT.601 full to BT.601 limit */ -+ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT601LIMIT = 2, /* Change color space from BT.709 limit to BT.601 limit */ -+ OT_VO_CSC_MATRIX_BT709FULL_TO_BT601LIMIT = 3, /* Change color space from BT.709 full to BT.601 limit */ -+ -+ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT709LIMIT = 4, /* Change color space from BT.601 limit to BT.709 limit */ -+ OT_VO_CSC_MATRIX_BT601FULL_TO_BT709LIMIT = 5, /* Change color space from BT.601 full to BT.709 limit */ -+ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT709LIMIT = 6, /* Identity matrix. from BT.709 limit to BT.709 limit */ -+ OT_VO_CSC_MATRIX_BT709FULL_TO_BT709LIMIT = 7, /* Change color space from BT.709 full to BT.709 limit */ -+ -+ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT601FULL = 8, /* Change color space from BT.601 limit to BT.601 full */ -+ OT_VO_CSC_MATRIX_BT601FULL_TO_BT601FULL = 9, /* Identity matrix. from BT.601 full to BT.601 full */ -+ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT601FULL = 10, /* Change color space from BT.709 limit to BT.601 full */ -+ OT_VO_CSC_MATRIX_BT709FULL_TO_BT601FULL = 11, /* Change color space from BT.709 full to BT.601 full */ -+ -+ OT_VO_CSC_MATRIX_BT601LIMIT_TO_BT709FULL = 12, /* Change color space from BT.601 limit to BT.709 full */ -+ OT_VO_CSC_MATRIX_BT601FULL_TO_BT709FULL = 13, /* Change color space from BT.601 full to BT.709 full */ -+ OT_VO_CSC_MATRIX_BT709LIMIT_TO_BT709FULL = 14, /* Change color space from BT.709 limit to BT.709 full */ -+ OT_VO_CSC_MATRIX_BT709FULL_TO_BT709FULL = 15, /* Identity matrix. from BT.709 full to BT.709 full */ -+ -+ OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBFULL = 16, /* Change color space from BT.601 limit to RGB full */ -+ OT_VO_CSC_MATRIX_BT601FULL_TO_RGBFULL = 17, /* Change color space from BT.601 full to RGB full */ -+ OT_VO_CSC_MATRIX_BT709LIMIT_TO_RGBFULL = 18, /* Change color space from BT.709 limit to RGB full */ -+ OT_VO_CSC_MATRIX_BT709FULL_TO_RGBFULL = 19, /* Change color space from BT.709 full to RGB full */ -+ -+ OT_VO_CSC_MATRIX_BT601LIMIT_TO_RGBLIMIT = 20, /* Change color space from BT.601 limit to RGB limit */ -+ OT_VO_CSC_MATRIX_BT601FULL_TO_RGBLIMIT = 21, /* Change color space from BT.709 full to RGB limit */ -+ OT_VO_CSC_MATRIX_BT709LIMIT_TO_RGBLIMIT = 22, /* Change color space from BT.601 limit to RGB limit */ -+ OT_VO_CSC_MATRIX_BT709FULL_TO_RGBLIMIT = 23, /* Change color space from BT.709 full to RGB limit */ -+ -+ OT_VO_CSC_MATRIX_RGBFULL_TO_BT601LIMIT = 24, /* Change color space from RGB full to BT.601 limit */ -+ OT_VO_CSC_MATRIX_RGBFULL_TO_BT601FULL = 25, /* Change color space from RGB full to BT.601 full */ -+ OT_VO_CSC_MATRIX_RGBFULL_TO_BT709LIMIT = 26, /* Change color space from RGB full to BT.709 limit */ -+ OT_VO_CSC_MATRIX_RGBFULL_TO_BT709FULL = 27, /* Change color space from RGB full to BT.709 full */ -+ -+ OT_VO_CSC_MATRIX_BUTT, -+} ot_vo_csc_matrix; -+ -+typedef struct { -+ ot_vo_csc_matrix csc_matrix; /* RW; CSC matrix */ -+ unsigned int luma; /* RW; range: [0, 100]; luminance, default: 50 */ -+ unsigned int contrast; /* RW; range: [0, 100]; contrast, default: 50 */ -+ unsigned int hue; /* RW; range: [0, 100]; hue, default: 50 */ -+ unsigned int saturation; /* RW; range: [0, 100]; saturation, default: 50 */ -+ bool ex_csc_en; /* RW; range: [0, 1]; extended csc switch for luminance, default: 0 */ -+} ot_vo_csc; -+ -+typedef struct { -+ int csc_coef00; -+ int csc_coef01; -+ int csc_coef02; -+ -+ int csc_coef10; -+ int csc_coef11; -+ int csc_coef12; -+ -+ int csc_coef20; -+ int csc_coef21; -+ int csc_coef22; -+} vdp_csc_coef; -+ -+typedef struct { -+ int csc_in_dc0; -+ int csc_in_dc1; -+ int csc_in_dc2; -+ -+ int csc_out_dc0; -+ int csc_out_dc1; -+ int csc_out_dc2; -+} vdp_csc_dc_coef; -+ -+typedef struct { -+ // for old version csc -+ int csc_coef00; -+ int csc_coef01; -+ int csc_coef02; -+ -+ int csc_coef10; -+ int csc_coef11; -+ int csc_coef12; -+ -+ int csc_coef20; -+ int csc_coef21; -+ int csc_coef22; -+ -+ int csc_in_dc0; -+ int csc_in_dc1; -+ int csc_in_dc2; -+ -+ int csc_out_dc0; -+ int csc_out_dc1; -+ int csc_out_dc2; -+ -+ int new_csc_scale2p; -+ int new_csc_clip_min; -+ int new_csc_clip_max; -+} csc_coef; -+ -+typedef struct { -+ int luma; -+ int cont; -+ int hue; -+ int satu; -+} hal_csc_value; -+ -+#define VO_CSC_DEF_VAL 50 -+#define VO_CSC_LUMA_MAX 100 -+#define VO_CSC_LUMA_MIN 0 -+#define VO_CSC_CONT_MAX 100 -+#define VO_CSC_CONT_MIN 0 -+#define VO_CSC_HUE_MAX 100 -+#define VO_CSC_HUE_MIN 0 -+#define VO_CSC_SAT_MAX 100 -+#define VO_CSC_SAT_MIN 0 -+ -+/* vou 的模块状态 */ -+#define VOU_STATE_STARTED 0 -+#define VOU_STATE_STOPPING 1 -+#define VOU_STATE_STOPPED 2 -+ -+typedef enum { -+ OT_ID_CMPI = 0, -+ OT_ID_VB = 1, -+ OT_ID_SYS = 2, -+ OT_ID_RGN = 3, -+ OT_ID_CHNL = 4, -+ OT_ID_VDEC = 5, -+ OT_ID_AVS = 6, -+ OT_ID_VPSS = 7, -+ OT_ID_VENC = 8, -+ OT_ID_SVP = 9, -+ OT_ID_H264E = 10, -+ OT_ID_JPEGE = 11, -+ OT_ID_H265E = 13, -+ OT_ID_JPEGD = 14, -+ OT_ID_VO = 15, -+ OT_ID_VI = 16, -+ OT_ID_DIS = 17, -+ OT_ID_VALG = 18, -+ OT_ID_RC = 19, -+ OT_ID_AIO = 20, -+ OT_ID_AI = 21, -+ OT_ID_AO = 22, -+ OT_ID_AENC = 23, -+ OT_ID_ADEC = 24, -+ OT_ID_VPU = 25, -+ OT_ID_PCIV = 26, -+ OT_ID_PCIVFMW = 27, -+ OT_ID_ISP = 28, -+ OT_ID_IVE = 29, -+ OT_ID_USER = 30, -+ OT_ID_PROC = 33, -+ OT_ID_LOG = 34, -+ OT_ID_VFMW = 35, -+ OT_ID_GDC = 37, -+ OT_ID_PHOTO = 38, -+ OT_ID_FB = 39, -+ OT_ID_HDMI = 40, -+ OT_ID_VOIE = 41, -+ OT_ID_TDE = 42, -+ OT_ID_HDR = 43, -+ OT_ID_PRORES = 44, -+ OT_ID_VGS = 45, -+ OT_ID_FD = 47, -+ OT_ID_OD = 48, -+ OT_ID_LPR = 50, -+ OT_ID_SVP_NNIE = 51, -+ OT_ID_SVP_DSP = 52, -+ OT_ID_DPU_RECT = 53, -+ OT_ID_DPU_MATCH = 54, -+ -+ OT_ID_MOTIONSENSOR = 55, -+ OT_ID_MOTIONFUSION = 56, -+ -+ OT_ID_GYRODIS = 57, -+ OT_ID_PM = 58, -+ OT_ID_SVP_ALG = 59, -+ OT_ID_IVP = 60, -+ OT_ID_MCF = 61, -+ OT_ID_SVP_MAU = 62, -+ OT_ID_VDA = 63, -+ OT_ID_VPP = 64, -+ OT_ID_KCF = 65, -+ OT_ID_PQP = 66, -+ -+ OT_ID_NPUDEV = 67, -+ OT_ID_AICPU = 68, -+ OT_ID_NPUDFX = 69, -+ OT_ID_TSFW = 70, -+ -+ OT_ID_CIPHER = 71, -+ OT_ID_KLAD = 72, -+ OT_ID_KEYSLOT = 73, -+ OT_ID_OTP = 74, -+ OT_ID_VDEC_ADAPT = 75, -+ OT_ID_DCC = 76, -+ OT_ID_VDEC_SERVER = 77, -+ OT_ID_VFMW_MDC = 78, -+ OT_ID_VB_LOG = 79, -+ OT_ID_MCF_CALIBRATION = 80, -+ OT_ID_SVP_NPU = 81, -+ OT_ID_HNR = 82, -+ OT_ID_SNAP = 83, -+ OT_ID_LOG_MDC = 84, -+ OT_ID_UVC = 85, -+ OT_ID_FISHEYE_CALIBRATION = 86, -+ OT_ID_SYNC = 87, -+ OT_ID_AIV = 88, -+ OT_ID_VO_DEV = 89, -+ OT_ID_IRQ = 90, -+ OT_ID_BUTT, -+} ot_mod_id; -+ -+typedef struct { -+ unsigned int fb_div; /* RW, range: [0, 0xfff]; frequency double division */ -+ unsigned int frac; /* RW, range: [0, 0xffffff]; fractional division */ -+ unsigned int ref_div; /* RW, range: (0, 0x3f]; reference clock division */ -+ unsigned int post_div1; /* RW, range: (0, 0x7]; level 1 post division */ -+ unsigned int post_div2; /* RW, range: (0, 0x7]; level 2 post division */ -+} ot_vo_pll; -+typedef enum { -+ SSC_VDP_DIV_340_TO_600 = 0, /* 340MHz~600MHz, 1div */ -+ SSC_VDP_DIV_200_TO_340 = 1, /* 200MHz~340MHz, 2div */ -+ SSC_VDP_DIV_100_TO_200 = 3, /* 100MHz~200MHz, 4div */ -+ SSC_VDP_DIV_50_TO_100 = 7, /* 50MHz~100MHz, 8div */ -+ SSC_VDP_DIV_25_TO_50 = 15, /* 25MHz~50MHz, 16div */ -+ -+ SSC_VDP_DIV_BUTT -+} vo_hdmi_ssc_vdp_div_mode; -+ -+typedef struct { -+ ot_vo_intf_sync index; -+ ot_vo_pll pll; -+ vo_hdmi_ssc_vdp_div_mode div; -+} vo_pll_param; -+ -+#define COLOR_RGB_RED 0xFF0000 -+#define COLOR_RGB_GREEN 0x00FF00 -+#define COLOR_RGB_BLUE 0x0000FF -+#define COLOR_RGB_BLACK 0x000000 -+#define COLOR_RGB_YELLOW 0xFFFF00 -+#define COLOR_RGB_CYN 0x00ffff -+#define COLOR_RGB_WHITE 0xffffff -+/* -+ * RGB(r,g,b) assemble the r,g,b to 24bit color -+ * RGB_R(c) get RED from 24bit color -+ * RGB_G(c) get GREEN from 24bit color -+ * RGB_B(c) get BLUE from 24bit color -+ */ -+#define RGB(r, g, b) ((((r) & 0xff) << 16) | (((g) & 0xff) << 8) | ((b) & 0xff)) -+#define RGB_R(c) (((c) & 0xff0000) >> 16) -+#define RGB_G(c) (((c) & 0xff00) >> 8) -+#define RGB_B(c) ((c) & 0xff) -+ -+/* -+ * YUV(y,u,v) assemble the y,u,v to 30bit color -+ * YUV_Y(c) get Y from 30bit color -+ * YUV_U(c) get U from 30bit color -+ * YUV_V(c) get V from 30bit color -+ */ -+#define YUV(y, u, v) ((((y) & 0x03ff) << 20) | (((u) & 0x03ff) << 10) | ((v) & 0x03ff)) -+#define YUV_Y(c) (((c) & 0x3ff00000) >> 20) -+#define YUV_U(c) (((c) & 0x000ffc00) >> 10) -+#define YUV_V(c) ((c) & 0x000003ff) -+/* -+ * MAX2(x,y) maximum of x and y -+ * MIN2(x,y) minimum of x and y -+ * MAX3(x,y,z) maximum of x, y and z -+ * MIN3(x,y,z) minimum of x, y and z -+ */ -+#define MAX2(x, y) ((x) > (y) ? (x) : (y)) -+#define MIN2(x, y) ((x) < (y) ? (x) : (y)) -+#define MAX3(x, y, z) ((x) > (y) ? MAX2(x, z) : MAX2(y, z)) -+#define MIN3(x, y, z) ((x) < (y) ? MIN2(x, z) : MIN2(y, z)) -+ -+/* -+ * CLIP3(x,min,max) clip x within [min,max] -+ * value_between(x,min.max) True if x is between [min,max] inclusively. -+ */ -+#define clip_min(x, min) (((x) >= (min)) ? (x) : (min)) -+#define clip3(x, min, max) ((x) < (min) ? (min) : ((x) > (max) ? (max) : (x))) -+#define clip_max(x, max) ((x) > (max) ? (max) : (x)) -+#define value_between(x, min, max) (((x) >= (min)) && ((x) <= (max))) -+ -+typedef struct { -+ unsigned short bkg_a; -+ unsigned short bkg_y; -+ unsigned short bkg_cb; -+ unsigned short bkg_cr; -+} hal_disp_bkcolor; -+ -+/* vou CBM MIXER */ -+typedef enum { -+ HAL_CBMMIX1 = 0, -+ HAL_CBMMIX2 = 1, -+ HAL_CBMMIX3 = 2, -+ -+ HAL_CBMMIX1_BUTT -+} hal_cbmmix; -+ -+/* vou mixer prio id */ -+typedef enum { -+ VOU_MIX_PRIO0 = 0, -+ VOU_MIX_PRIO1, -+ VOU_MIX_PRIO2, -+ VOU_MIX_PRIO3, -+ VOU_MIX_PRIO4, -+ VOU_MIX_BUTT -+} vou_mix_prio; -+#define OT_VO_MAX_PHYS_VIDEO_LAYER_NUM 3 /* max physical video layer num */ -+#define OT_VO_MAX_GFX_LAYER_NUM 3 /* max graphic layer num */ -+/* max physical layer num */ -+#define OT_VO_MAX_PHYS_LAYER_NUM (OT_VO_MAX_PHYS_VIDEO_LAYER_NUM + OT_VO_MAX_GFX_LAYER_NUM) -+#define VO_LAYER_BUTT OT_VO_MAX_PHYS_LAYER_NUM -+/* HFIR VCOEF */ -+typedef struct { -+ int coef0; -+ int coef1; -+ int coef2; -+ int coef3; -+ int coef4; -+ int coef5; -+ int coef6; -+ int coef7; -+} hfir_coef; -+typedef struct { -+ ot_vo_layer layer; -+ unsigned char layer_id; -+} vo_hal_cbm_mixer; -+typedef enum { -+ HAL_INPUTFMT_YCBCR_SEMIPLANAR_400 = 0x1, -+ HAL_INPUTFMT_YCBCR_SEMIPLANAR_420 = 0x2, -+ HAL_INPUTFMT_YCBCR_SEMIPLANAR_422 = 0x3, -+ HAL_INPUTFMT_YCBCR_SEMIPLANAR_444 = 0x4, -+ HAL_INPUTFMT_YCBCR_SEMIPLANAR_411_4X1 = 0x6, -+ HAL_INPUTFMT_YCBCR_SEMIPLANAR_422_2X1 = 0x7, -+ -+ HAL_INPUTFMT_CBYCRY_PACKAGE_422 = 0x9, -+ HAL_INPUTFMT_YCBYCR_PACKAGE_422 = 0xa, -+ HAL_INPUTFMT_YCRYCB_PACKAGE_422 = 0xb, -+ HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0x1000, -+ -+ HAL_INPUTFMT_CLUT_1BPP = 0x00, -+ HAL_INPUTFMT_CLUT_2BPP = 0x10, -+ HAL_INPUTFMT_CLUT_4BPP = 0x20, -+ HAL_INPUTFMT_CLUT_8BPP = 0x30, -+ HAL_INPUTFMT_ACLUT_44 = 0x38, -+ -+ HAL_INPUTFMT_RGB_444 = 0x40, -+ HAL_INPUTFMT_RGB_555 = 0x41, -+ HAL_INPUTFMT_RGB_565 = 0x42, -+ HAL_INPUTFMT_CBYCRY_PACKAGE_422_GRC = 0x43, -+ HAL_INPUTFMT_YCBYCR_PACKAGE_422_GRC = 0x44, -+ HAL_INPUTFMT_YCRYCB_PACKAGE_422_GRC = 0x45, -+ HAL_INPUTFMT_ACLUT_88 = 0x46, -+ HAL_INPUTFMT_ARGB_4444 = 0x48, -+ HAL_INPUTFMT_ARGB_1555 = 0x49, -+ -+ HAL_INPUTFMT_RGB_888 = 0x50, -+ HAL_INPUTFMT_YCBCR_888 = 0x51, -+ HAL_INPUTFMT_ARGB_8565 = 0x5a, -+ HAL_INPUTFMT_ARGB_6666 = 0x5b, -+ -+ HAL_INPUTFMT_KRGB_888 = 0x60, -+ HAL_INPUTFMT_ARGB_8888 = 0x68, -+ HAL_INPUTFMT_AYCBCR_8888 = 0x69, -+ -+ HAL_INPUTFMT_RGBA_4444 = 0xc8, -+ HAL_INPUTFMT_RGBA_5551 = 0xc9, -+ -+ HAL_INPUTFMT_RGBA_6666 = 0xd8, -+ HAL_INPUTFMT_RGBA_5658 = 0xda, -+ -+ HAL_INPUTFMT_RGBA_8888 = 0xe8, -+ HAL_INPUTFMT_YCBCRA_8888 = 0xe9, -+ -+ HAL_DISP_PIXELFORMAT_BUTT -+} hal_disp_pixel_format; -+#define VO_ALPHA_OPACITY 0xFF /* opacity alpha */ -+typedef enum { -+ HAL_HFIRMODE_MEDEN = 0, /* median filtering enable */ -+ HAL_HFIRMODE_COPY, /* chroma HFIR copy */ -+ HAL_HFIRMODE_DOUBLE, /* bilinear interpolation */ -+ HAL_HFIRMODE_6TAPFIR, /* 6 order FIR */ -+ -+ HAL_HFIRMODE_BUTT -+} hal_hfirmode; -+ -+/* vou graphic layer data extend mode */ -+typedef enum { -+ HAL_GFX_BITEXTEND_1ST = 0, -+ HAL_GFX_BITEXTEND_2ND = 0x2, -+ HAL_GFX_BITEXTEND_3RD = 0x3, -+ -+ HAL_GFX_BITEXTEND_BUTT -+} hal_gfx_bitextend; -+ -+typedef enum { -+ FB_VOU_BITEXT_LOW_ZERO = 0x0, -+ FB_VOU_BITEXT_LOW_HIGHBIT = 0x2, -+ FB_VOU_BITEXT_LOW_HIGHBITS = 0x3, -+ FB_VOU_BITEXT_BUTT -+} vou_bitext_mode; -+ -+typedef struct { -+ int x; -+ int y; -+ int width; -+ int height; -+} ot_fb_rect; -+#define GRAPHIC_ALPHA_OPACITY 0xff -+ -+/* vou interrupt mask type */ -+typedef enum { -+ GFBG_INTMSK_NONE = 0, -+ GFBG_INTMSK_DHD0_VTTHD1 = 0x1, -+ GFBG_INTMSK_DHD0_VTTHD2 = 0x2, -+ GFBG_INTMSK_DHD0_VTTHD3 = 0x4, -+ GFBG_INTMSK_DHD0_UFINT = 0x8, -+ -+ GFBG_INTMSK_DHD1_VTTHD1 = 0x10, -+ GFBG_INTMSK_DHD1_VTTHD2 = 0x20, -+ GFBG_INTMSK_DHD1_VTTHD3 = 0x40, -+ GFBG_INTMSK_DHD1_UFINT = 0x80, -+ -+ GFBG_INTMSK_DSD_VTTHD1 = 0x100, -+ GFBG_INTMSK_DSD_VTTHD2 = 0x200, -+ GFBG_INTMSK_DSD_VTTHD3 = 0x400, -+ GFBG_INTMSK_DSD_UFINT = 0x800, -+ -+ GFBG_INTMSK_B0_ERR = 0x1000, -+ GFBG_INTMSK_B1_ERR = 0x2000, -+ GFBG_INTMSK_B2_ERR = 0x4000, -+ -+ GFBG_INTMSK_WBC_DHDOVER = 0x8000, -+ GFBG_INTREPORT_ALL = 0xffffffff -+} gfbg_int_mask; -+ -+typedef struct { -+ int csc_scale2p; -+ int csc_clip_min; -+ int csc_clip_max; -+} csc_coef_param; -+ -+typedef enum { -+ FB_VOU_COLORKEY_IN = 0x0, -+ FB_VOU_COLORKEY_OUT = 0x1, -+ FB_VOU_COLORKEY_BUTT -+} vou_colorkey_mode; -+ -+typedef struct { -+ unsigned int ck_gt_en; -+ unsigned int in_width; -+ unsigned int out_width; -+ unsigned int out_pro; -+ -+ unsigned int hfir_en; -+ unsigned int lhmid_en; -+ unsigned int ahmid_en; -+ unsigned int lhfir_mode; -+ unsigned int ahfir_mode; -+ -+ unsigned int in_height; -+ unsigned int out_height; -+ -+ unsigned int vfir_en; -+ unsigned int lvmid_en; -+ unsigned int avmid_en; -+ unsigned int lvfir_mode; -+ unsigned int avfir_mode; -+} gf_zme_cfg; -+ -+typedef enum { -+ VDP_RMODE_INTERFACE = 0, -+ VDP_RMODE_INTERLACE = 0, -+ VDP_RMODE_PROGRESSIVE = 1, -+ VDP_RMODE_TOP = 2, -+ VDP_RMODE_BOTTOM = 3, -+ VDP_RMODE_PRO_TOP = 4, -+ VDP_RMODE_PRO_BOTTOM = 5, -+ VDP_RMODE_BUTT -+} vdp_data_rmode; -+ -+typedef enum { -+ VDP_G0_ZME_TYP = 0, -+ VDP_G0_ZME_TYP1, -+ VDP_G0_ZME_RAND, -+ VDP_G0_ZME_MAX, -+ VDP_G0_ZME_MIN, -+ VDP_G0_ZME_ZERO, -+ VDP_G0_ZME_BUTT -+} gf_g0_zme_mode; -+#define GFX_MAX_CSC_TABLE 61 -+typedef enum { -+ HAL_CSC_MODE_BT601LIMIT_TO_BT601LIMIT, /* BT601LIMIT to BT601LIMIT */ -+ HAL_CSC_MODE_BT601FULL_TO_BT601LIMIT, /* BT601FULL to BT601LIMIT */ -+ HAL_CSC_MODE_BT709LIMIT_TO_BT601LIMIT, /* BT709LIMIT to BT601LIMIT */ -+ HAL_CSC_MODE_BT709FULL_TO_BT601LIMIT, /* BT709FULL to BT601LIMIT */ -+ -+ HAL_CSC_MODE_BT601LIMIT_TO_BT709LIMIT, /* BT601LIMIT to BT709LIMIT */ -+ HAL_CSC_MODE_BT601FULL_TO_BT709LIMIT, /* BT601FULL to BT709LIMIT */ -+ HAL_CSC_MODE_BT709LIMIT_TO_BT709LIMIT, /* BT709LIMIT to BT709LIMIT */ -+ HAL_CSC_MODE_BT709FULL_TO_BT709LIMIT, /* BT709FULL to BT709LIMIT */ -+ -+ HAL_CSC_MODE_BT601LIMIT_TO_BT601FULL, /* BT601LIMIT to BT601FULL */ -+ HAL_CSC_MODE_BT601FULL_TO_BT601FULL, /* BT601FULL to BT601FULL */ -+ HAL_CSC_MODE_BT709LIMIT_TO_BT601FULL, /* BT709LIMIT to BT601FULL */ -+ HAL_CSC_MODE_BT709FULL_TO_BT601FULL, /* BT709FULL to BT601FULL */ -+ -+ HAL_CSC_MODE_BT601LIMIT_TO_BT709FULL, /* BT601LIMIT to BT709FULL */ -+ HAL_CSC_MODE_BT709LIMIT_TO_BT709FULL, /* BT709LIMIT to BT709FULL */ -+ HAL_CSC_MODE_BT601FULL_TO_BT709FULL, /* BT601FULL to BT709FULL */ -+ HAL_CSC_MODE_BT709FULL_TO_BT709FULL, /* BT709FULL to BT709FULL */ -+ -+ HAL_CSC_MODE_BT601LIMIT_TO_RGBFULL, /* BT601LIMIT to RGBFULL */ -+ HAL_CSC_MODE_BT601FULL_TO_RGBFULL, /* BT601FULL to RGBFULL */ -+ HAL_CSC_MODE_BT709LIMIT_TO_RGBFULL, /* BT709LIMIT to RGBFULL */ -+ HAL_CSC_MODE_BT709FULL_TO_RGBFULL, /* BT709FULL to RGBFULL */ -+ -+ HAL_CSC_MODE_BT601LIMIT_TO_RGBLIMIT, /* BT601LIMIT to RGBLIMIT */ -+ HAL_CSC_MODE_BT601FULL_TO_RGBLIMIT, /* BT601FULL to RGBLIMIT */ -+ HAL_CSC_MODE_BT709LIMIT_TO_RGBLIMIT, /* BT709LIMIT to RGBLIMIT */ -+ HAL_CSC_MODE_BT709FULL_TO_RGBLIMIT, /* BT709FULL to RGBLIMIT */ -+ -+ HAL_CSC_MODE_RGBFULL_TO_BT601LIMIT, /* RGBFULL to BT601LIMIT */ -+ HAL_CSC_MODE_RGBFULL_TO_BT601FULL, /* RGBFULL to BT601FULL */ -+ HAL_CSC_MODE_RGBFULL_TO_BT709LIMIT, /* RGBFULL to BT709LIMIT */ -+ HAL_CSC_MODE_RGBFULL_TO_BT709FULL, /* RGBFULL to BT709FULL */ -+ HAL_CSC_MODE_RGBFULL_TO_RGBFULL, /* RGBFULL to RGBFULL */ -+ HAL_CSC_MODE_RGBFULL_TO_RGBLIMIT, /* RGBFULLto RGBLIMIT */ -+ -+ HAL_CSC_MODE_BUTT -+} hal_csc_mode; -+ -+typedef struct { -+ ot_vo_csc_matrix csc_matrix; /* CSC matrix */ -+ unsigned int luma; /* RW Range: [0, 100] luminance, default: 50 */ -+ unsigned int contrast; /* RW Range: [0, 100] contrast, default: 50 */ -+ unsigned int hue; /* RW Range: [0, 100] hue, default: 50 */ -+ unsigned int satuature; /* RW Range: [0, 100] satuature, default: 50 */ -+} vo_csc; -+#define GFX_CSC_SCALE 0xa -+#define GFX_CSC_CLIP_MIN 0x0 -+#define GFX_CSC_CLIP_MAX 0x3ff -+#define VOU1_IRQ_NR 193 -+ -+typedef enum { -+ HAL_DISP_ZMEMODE_HORL = 0, -+ HAL_DISP_ZMEMODE_HORC, -+ HAL_DISP_ZMEMODE_VERL, -+ HAL_DISP_ZMEMODE_VERC, -+ -+ HAL_DISP_ZMEMODE_HOR, -+ HAL_DISP_ZMEMODE_VER, -+ HAL_DISP_ZMEMODE_ALPHA, -+ HAL_DISP_ZMEMODE_ALPHAV, -+ HAL_DISP_ZMEMODE_VERT, -+ HAL_DISP_ZMEMODE_VERB, -+ -+ HAL_DISP_ZMEMODE_ALL, -+ HAL_DISP_ZMEMODE_NONL, -+ HAL_DISP_ZMEMODE_BUTT -+} hal_disp_zmemode; -+ -+typedef enum { -+ HAL_DISP_ZME_OUTFMT420 = 0, -+ HAL_DISP_ZME_OUTFMT422, -+ HAL_DISP_ZME_OUTFMT444, -+ HAL_DISP_ZME_OUTFMT_BUTT -+} hal_disp_zme_outfmt; -+ -+typedef enum { -+ OT_VIDEO_FIELD_TOP = 1, /* even field */ -+ OT_VIDEO_FIELD_BOTTOM = 2, /* odd field */ -+ OT_VIDEO_FIELD_INTERLACED = 3, /* two interlaced fields */ -+ OT_VIDEO_FIELD_FRAME = 4, /* frame */ -+ -+ OT_VIDEO_FIELD_BUTT -+} ot_video_field; -+ -+/* we ONLY define picture format used, all unused will be deleted! */ -+typedef enum { -+ OT_PIXEL_FORMAT_RGB_444 = 0, -+ OT_PIXEL_FORMAT_RGB_555, -+ OT_PIXEL_FORMAT_RGB_565, -+ OT_PIXEL_FORMAT_RGB_888, -+ -+ OT_PIXEL_FORMAT_BGR_444, -+ OT_PIXEL_FORMAT_BGR_555, -+ OT_PIXEL_FORMAT_BGR_565, -+ OT_PIXEL_FORMAT_BGR_888, -+ -+ OT_PIXEL_FORMAT_ARGB_1555, -+ OT_PIXEL_FORMAT_ARGB_4444, -+ OT_PIXEL_FORMAT_ARGB_8565, -+ OT_PIXEL_FORMAT_ARGB_8888, -+ OT_PIXEL_FORMAT_ARGB_2BPP, -+ OT_PIXEL_FORMAT_ARGB_CLUT2, -+ OT_PIXEL_FORMAT_ARGB_CLUT4, -+ -+ OT_PIXEL_FORMAT_ABGR_1555, -+ OT_PIXEL_FORMAT_ABGR_4444, -+ OT_PIXEL_FORMAT_ABGR_8565, -+ OT_PIXEL_FORMAT_ABGR_8888, -+ -+ OT_PIXEL_FORMAT_RGB_BAYER_8BPP, -+ OT_PIXEL_FORMAT_RGB_BAYER_10BPP, -+ OT_PIXEL_FORMAT_RGB_BAYER_12BPP, -+ OT_PIXEL_FORMAT_RGB_BAYER_14BPP, -+ OT_PIXEL_FORMAT_RGB_BAYER_16BPP, -+ -+ OT_PIXEL_FORMAT_YVU_PLANAR_422, -+ OT_PIXEL_FORMAT_YVU_PLANAR_420, -+ OT_PIXEL_FORMAT_YVU_PLANAR_444, -+ -+ OT_PIXEL_FORMAT_YVU_SEMIPLANAR_422, -+ OT_PIXEL_FORMAT_YVU_SEMIPLANAR_420, -+ OT_PIXEL_FORMAT_YVU_SEMIPLANAR_444, -+ -+ OT_PIXEL_FORMAT_YUV_SEMIPLANAR_422, -+ OT_PIXEL_FORMAT_YUV_SEMIPLANAR_420, -+ OT_PIXEL_FORMAT_YUV_SEMIPLANAR_444, -+ -+ OT_PIXEL_FORMAT_YUYV_PACKAGE_422, -+ OT_PIXEL_FORMAT_YVYU_PACKAGE_422, -+ OT_PIXEL_FORMAT_UYVY_PACKAGE_422, -+ OT_PIXEL_FORMAT_VYUY_PACKAGE_422, -+ OT_PIXEL_FORMAT_YYUV_PACKAGE_422, -+ OT_PIXEL_FORMAT_YYVU_PACKAGE_422, -+ OT_PIXEL_FORMAT_UVYY_PACKAGE_422, -+ OT_PIXEL_FORMAT_VUYY_PACKAGE_422, -+ OT_PIXEL_FORMAT_VY1UY0_PACKAGE_422, -+ -+ OT_PIXEL_FORMAT_YUV_400, -+ OT_PIXEL_FORMAT_UV_420, -+ -+ /* SVP data format */ -+ OT_PIXEL_FORMAT_BGR_888_PLANAR, -+ OT_PIXEL_FORMAT_HSV_888_PACKAGE, -+ OT_PIXEL_FORMAT_HSV_888_PLANAR, -+ OT_PIXEL_FORMAT_LAB_888_PACKAGE, -+ OT_PIXEL_FORMAT_LAB_888_PLANAR, -+ OT_PIXEL_FORMAT_S8C1, -+ OT_PIXEL_FORMAT_S8C2_PACKAGE, -+ OT_PIXEL_FORMAT_S8C2_PLANAR, -+ OT_PIXEL_FORMAT_S8C3_PLANAR, -+ OT_PIXEL_FORMAT_S16C1, -+ OT_PIXEL_FORMAT_U8C1, -+ OT_PIXEL_FORMAT_U16C1, -+ OT_PIXEL_FORMAT_S32C1, -+ OT_PIXEL_FORMAT_U32C1, -+ OT_PIXEL_FORMAT_U64C1, -+ OT_PIXEL_FORMAT_S64C1, -+ -+ OT_PIXEL_FORMAT_BUTT -+} ot_pixel_format; -+ -+ -+typedef enum { -+ OT_VIDEO_FORMAT_LINEAR = 0, /* nature video line */ -+ OT_VIDEO_FORMAT_TILE_64x16, /* tile cell: 64pixel x 16line */ -+ OT_VIDEO_FORMAT_TILE_16x8, /* tile cell: 16pixel x 8line */ -+ OT_VIDEO_FORMAT_BUTT -+} ot_video_format; -+ -+typedef enum { -+ OT_COMPRESS_MODE_NONE = 0, /* no compress */ -+ OT_COMPRESS_MODE_SEG, /* compress unit is 256x1 bytes as a segment. */ -+ OT_COMPRESS_MODE_SEG_COMPACT, /* compact compress unit is 256x1 bytes as a segment. */ -+ OT_COMPRESS_MODE_TILE, /* compress unit is a tile. */ -+ OT_COMPRESS_MODE_LINE, /* compress unit is the whole line. */ -+ OT_COMPRESS_MODE_FRAME, /* compress unit is the whole frame. YUV for VPSS(3DNR) */ -+ -+ OT_COMPRESS_MODE_BUTT -+} ot_compress_mode; -+ -+typedef enum { -+ OT_DYNAMIC_RANGE_SDR8 = 0, -+ OT_DYNAMIC_RANGE_SDR10, -+ OT_DYNAMIC_RANGE_HDR10, -+ OT_DYNAMIC_RANGE_HLG, -+ OT_DYNAMIC_RANGE_SLF, -+ OT_DYNAMIC_RANGE_XDR, -+ OT_DYNAMIC_RANGE_BUTT -+} ot_dynamic_range; -+ -+ -+typedef enum { -+ OT_COLOR_GAMUT_BT601 = 0, -+ OT_COLOR_GAMUT_BT709, -+ OT_COLOR_GAMUT_BT2020, -+ OT_COLOR_GAMUT_USER, -+ OT_COLOR_GAMUT_BUTT -+} ot_color_gamut; -+#define OT_MAX_COLOR_COMPONENT 2 -+#define OT_ALIGN_NUM 8 -+#define ATTRIBUTE __attribute__((aligned(OT_ALIGN_NUM))) -+#define OT_MAX_USER_DATA_NUM 2 -+ -+typedef struct { -+ phys_addr_t misc_info_phys_addr; /* default allocated buffer */ -+ phys_addr_t jpeg_dcf_phys_addr; -+ phys_addr_t isp_info_phys_addr; -+ phys_addr_t low_delay_phys_addr; -+ phys_addr_t bnr_rnt_phys_addr; -+ phys_addr_t motion_data_phys_addr; -+ phys_addr_t frame_dng_phys_addr; -+ -+ void* ATTRIBUTE misc_info_virt_addr; /* misc info */ -+ void* ATTRIBUTE jpeg_dcf_virt_addr; /* jpeg_dcf, used in JPEG DCF */ -+ void* ATTRIBUTE isp_info_virt_addr; /* isp_frame_info, used in ISP debug, when get raw and send raw */ -+ void* ATTRIBUTE low_delay_virt_addr; /* used in low delay */ -+ void* ATTRIBUTE bnr_mot_virt_addr; /* used for 3dnr from bnr mot */ -+ void* ATTRIBUTE motion_data_virt_addr; /* vpss 3dnr use: gme motion data, filter motion data, gyro data. */ -+ void* ATTRIBUTE frame_dng_virt_addr; -+} ot_video_supplement; -+ -+typedef struct { -+ unsigned int width; -+ unsigned int height; -+ ot_video_field field; -+ ot_pixel_format pixel_format; -+ ot_video_format video_format; -+ ot_compress_mode compress_mode; -+ ot_dynamic_range dynamic_range; -+ ot_color_gamut color_gamut; -+ -+ unsigned int header_stride[OT_MAX_COLOR_COMPONENT]; -+ unsigned int stride[OT_MAX_COLOR_COMPONENT]; -+ -+ phys_addr_t header_phys_addr[OT_MAX_COLOR_COMPONENT]; -+ phys_addr_t phys_addr[OT_MAX_COLOR_COMPONENT]; -+ void* ATTRIBUTE header_virt_addr[OT_MAX_COLOR_COMPONENT]; -+ void* ATTRIBUTE virt_addr[OT_MAX_COLOR_COMPONENT]; -+ -+ unsigned int time_ref; -+ unsigned long long pts; -+ -+ unsigned long long user_data[OT_MAX_USER_DATA_NUM]; -+ unsigned int frame_flag; /* frame_flag, can be OR operation. */ -+ ot_video_supplement supplement; -+} ot_video_frame; -+ -+typedef struct { -+ ot_video_frame video_frame; -+ unsigned int pool_id; -+ ot_mod_id mod_id; -+} ot_video_frame_info; -+ -+#define MAX_OFFSET 3 -+#define MIN_OFFSET (-1) -+ -+typedef enum { -+ VO_ZME_TYP = 0, -+ VO_ZME_TYP1, -+ VO_ZME_RAND, -+ VO_ZME_MAX, -+ VO_ZME_MIN, -+ VO_ZME_ZERO, -+ VO_ZME_BUTT -+} vo_zme_mode; -+#if 0 -+typedef enum { -+ VO_INT_MODE_FRAME = 0x0, -+ VO_INT_MODE_FIELD = 0x1, -+ VO_INT_MODE_BUTT -+} vo_int_mode; -+#endif -+typedef struct { -+ unsigned int zme_vprec; -+ unsigned int zme_hprec; -+} vo_zme_ds_info; -+ -+typedef enum { -+ VDP_PROC_FMT_SP_420 = 0x0, -+ VDP_PROC_FMT_SP_422 = 0x1, -+ VDP_PROC_FMT_SP_444 = 0x2, -+ VDP_PROC_FMT_RGB_888 = 0x3, -+ VDP_PROC_FMT_RGB_444 = 0x4, -+ -+ VDP_PROC_FMT_BUTT -+} vdp_proc_fmt; -+ -+typedef struct { -+ unsigned int vluma_offset; -+ unsigned int vchroma_offset; -+ unsigned int vbluma_offset; -+ unsigned int vbchroma_offset; -+ unsigned int lhfir_offset; -+ unsigned int chfir_offset; -+ unsigned int vl_flatdect_mode; -+ unsigned int vl_coringadj_en; -+ unsigned int vl_gain; -+ unsigned int vl_coring; -+ unsigned int vc_flatdect_mode; -+ unsigned int vc_coringadj_en; -+ unsigned int vc_gain; -+ unsigned int vc_coring; -+ unsigned int hl_flatdect_mode; -+ unsigned int hl_coringadj_en; -+ unsigned int hl_gain; -+ unsigned int hl_coring; -+ unsigned int hc_flatdect_mode; -+ unsigned int hc_coringadj_en; -+ unsigned int hc_gain; -+ unsigned int hc_coring; -+} vo_zme_comm_pq_cfg; -+ -+typedef struct { -+ unsigned int ck_gt_en; -+ unsigned int out_pro; -+ unsigned int out_fmt; -+ unsigned long long in_height; -+ unsigned long long out_height; -+ unsigned long long in_width; -+ unsigned long long out_width; -+ unsigned int cvfir_en; -+ unsigned int cvmid_en; -+ unsigned int cvfir_mode; -+ -+ unsigned int hfir_order; -+ unsigned int lhfir_en; -+ unsigned int chfir_en; -+ unsigned int lhmid_en; -+ unsigned int chmid_en; -+ unsigned int non_lnr_en; -+ unsigned int lhfir_mode; -+ unsigned int chfir_mode; -+ unsigned int hl_shootctrl_en; -+ unsigned int hl_shootctrl_mode; -+ unsigned int hc_shootctrl_en; -+ unsigned int hc_shootctrl_mode; -+ -+ unsigned int in_pro; -+ unsigned int graphdet_en; -+ -+ unsigned int lvfir_en; -+ unsigned int lvmid_en; -+ unsigned int vfir_1tap_en; -+ unsigned int lvfir_mode; -+ unsigned int vl_shootctrl_en; -+ unsigned int vl_shootctrl_mode; -+ unsigned int vc_shootctrl_en; -+ unsigned int vc_shootctrl_mode; -+} vdp_v1_cvfir_cfg; -+ -+typedef struct { -+ unsigned int ck_gt_en; -+ unsigned int hfir_order; -+ unsigned int lhfir_en; -+ unsigned int chfir_en; -+ unsigned int lhmid_en; -+ unsigned int chmid_en; -+ unsigned int non_lnr_en; -+ unsigned int lhfir_mode; -+ unsigned int chfir_mode; -+ unsigned int hl_shootctrl_en; -+ unsigned int hl_shootctrl_mode; -+ unsigned int hc_shootctrl_en; -+ unsigned int hc_shootctrl_mode; -+ -+ unsigned int in_pro; -+ unsigned int out_pro; -+ unsigned int out_fmt; -+ unsigned long long in_height; -+ unsigned long long out_height; -+ unsigned long long in_width; -+ unsigned long long out_width; -+ unsigned int graphdet_en; -+ -+ unsigned int lvfir_en; -+ unsigned int cvfir_en; -+ unsigned int lvmid_en; -+ unsigned int cvmid_en; -+ unsigned int vfir_1tap_en; -+ unsigned int lvfir_mode; -+ unsigned int cvfir_mode; -+ unsigned int vl_shootctrl_en; -+ unsigned int vl_shootctrl_mode; -+ unsigned int vc_shootctrl_en; -+ unsigned int vc_shootctrl_mode; -+} vo_v0_zme_cfg; -+ -+typedef enum { -+ XDP_V0_HFIR_BYPASS = 0, -+ XDP_V0_HFIR_COPY, -+ XDP_V0_HFIR_BILT, -+ XDP_V0_HFIR_FILT, -+ XDP_V0_HFIR_BUTT -+} xdp_v0_hfir_mode; -+ -+typedef struct { -+ unsigned int ck_gt_en; -+ unsigned int mid_en; -+ xdp_v0_hfir_mode hfir_mode; -+} vo_v0_hfir_cfg; -+ -+typedef struct { -+ unsigned int ot_hdr_y2r_en; -+ unsigned int ot_hdr_y2r_ck_gt_en; -+ -+ unsigned int ot_hdr_v0_y2r_en; -+ unsigned int ot_hdr_v1_y2r_en; -+ unsigned int ot_hdr_v0_vhdr_en; -+ unsigned int ot_hdr_v1_vhdr_en; -+ unsigned int ot_hdr_v0_cl_en; -+ unsigned int ot_hdr_v1_cl_en; -+ -+ unsigned int ot_hdr_v_demo_en; -+ unsigned int ot_hdr_v_demo_mode; -+ unsigned int ot_hdr_v_demo_pos; -+} vo_csc_v0_cfg; -+ -+typedef struct { -+ unsigned int vhdr_en; -+ unsigned int vhdr_ck_gt_en; -+ unsigned int vhdr_degmm_en; -+ unsigned int vhdr_gamut_en; -+ unsigned int vhdr_tmap_en; -+ unsigned int vhdr_gmm_en; -+ unsigned int vhdr_dither_en; -+ unsigned int vhdr_r2y_en; -+ unsigned int vhdr_cadj_en; -+ unsigned int vhdr_gamut_bind; -+ -+ unsigned int vhdr_dither_round_unlim; -+ unsigned int vhdr_dither_round; -+ unsigned int vhdr_dither_domain_mode; -+ unsigned int vhdr_dither_tap_mode; -+} vo_ot_hdr_v_cfg; -+ -+typedef struct { -+ unsigned int vid_iw; -+ unsigned int vid_ih; -+ unsigned int vid_ow; -+ unsigned int vid_oh; -+ -+ unsigned int zme_en; -+ unsigned int hfir_en; -+ unsigned int csc_en; -+ unsigned int hdr_en; -+ -+ vo_v0_zme_cfg zme_cfg; -+ vo_v0_hfir_cfg hfir_cfg; -+ vo_csc_v0_cfg yuv2_rgb_cfg; -+ vo_ot_hdr_v_cfg v_ot_hdr_cfg; -+} vdp_vid_ip_cfg; -+ -+typedef struct { -+ int x; -+ int y; -+ unsigned int width; -+ unsigned int height; -+} ot_rect; -+ -+void drm_overlay_update(ot_video_frame_info *p_frame_info); -+#endif /* _SMART_VOP_REG_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include/drv_vo_comm.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include/drv_vo_comm.h -new file mode 100755 -index 0000000..55bc6e9 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/arch/comm/include/drv_vo_comm.h -@@ -0,0 +1,168 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef DRV_VO_COMM_H -+#define DRV_VO_COMM_H -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+///test start -+#define VO_MAX_ZME_PHASE 17 -+#define VO_MAX_ZME_TAP 8 -+ -+/* -+ * 严重注意: -+ * 寄存器上获取的比率 ratio = 输入分辨率/输出分辨率 -+ * 而算法给出的比率 ratio = 输出分辨率/输入分辨率 (HERE USE) -+ */ -+typedef enum { -+ VOU_ZOOM_COEF_UP_1 = 0, -+ VOU_ZOOM_COEF_EQU_1, -+ VOU_ZOOM_COEF_075, -+ VOU_ZOOM_COEF_0666, -+ VOU_ZOOM_COEF_05, -+ VOU_ZOOM_COEF_04, -+ VOU_ZOOM_COEF_0375, -+ VOU_ZOOM_COEF_033, -+ VOU_ZOOM_COEF_0, -+ VOU_ZOOM_COEF_BUTT -+} vou_zoom_coef; -+ -+typedef enum { -+ VOU_ZOOM_TAP_6LH = 0, -+ VOU_ZOOM_TAP_4CH, -+ VOU_ZOOM_TAP_4LV, -+ VOU_ZOOM_TAP_4CV, -+ VOU_ZOOM_TAP_BUTT -+} vou_zoom_tap; -+///test end -+ -+typedef enum { -+ /* for video surface interface */ -+ VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_400 = 0x1, -+ VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_420 = 0x2, -+ VOU_LAYER_PIXEL_FORMAT_SP_YCBCR_422 = 0x3, -+ VOU_LAYER_PIXEL_FORMAT_BUTT -+} vou_layer_pixel_format; -+ -+/* vou interrupt mask type */ -+typedef enum { -+ VO_INTMSK_NONE = 0, -+ VO_INTMSK_DHD0_VTTHD1 = 0x1, -+ VO_INTMSK_DHD0_VTTHD2 = 0x2, -+ VO_INTMSK_DHD0_VTTHD3 = 0x4, -+ VO_INTMSK_DHD0_UFINT = 0x8, -+ -+ VO_INTMSK_DHD1_VTTHD1 = 0x10, -+ VO_INTMSK_DHD1_VTTHD2 = 0x20, -+ VO_INTMSK_DHD1_VTTHD3 = 0x40, -+ VO_INTMSK_DHD1_UFINT = 0x80, -+ -+ VO_INTMSK_DSD_VTTHD1 = 0x100, -+ VO_INTMSK_DSD_VTTHD2 = 0x200, -+ VO_INTMSK_DSD_VTTHD3 = 0x400, -+ VO_INTMSK_DSD_UFINT = 0x800, -+ -+ VO_INTMSK_B0_ERR = 0x1000, -+ VO_INTMSK_B1_ERR = 0x2000, -+ VO_INTMSK_B2_ERR = 0x4000, -+ -+ VO_INTMSK_WBC_DHDOVER = 0x8000, -+ -+ VO_INTMSK_VGA_VDAC = 0x70000, /* INT VDAC0/VDAC1/VDAC2 */ -+ VO_INTMSK_CVBS_VDAC = 0x80000, /* INT VDAC3 */ -+ -+ VO_INTMSK_V0_TUNL_INT = 0x100000, -+ VO_INTMSK_V1_TUNL_INT = 0x200000, -+ -+ VO_INTREPORT_ALL = 0xffffffff -+} vo_int_mask; -+ -+typedef enum { -+ VO_INT_MODE_FRAME = 0x0, -+ VO_INT_MODE_FIELD = 0x1, -+ VO_INT_MODE_BUTT -+} vo_int_mode; -+ -+typedef struct vo_all_int_type { -+ int vtth_dev[OT_VO_MAX_PHYS_DEV_NUM]; -+ int vga_dev; -+ int cvbs_dev; -+} vo_int_type; -+ -+ -+typedef struct { -+ unsigned long long start_phys_addr; -+ void *start_vir_addr; -+ unsigned int size; -+} vo_mmz_buffer; -+ -+typedef struct { -+ vo_mmz_buffer buf_base_addr; -+ unsigned int u32size; -+ -+ unsigned char *coef_vir_addr[VO_COEF_BUF_BUTT]; -+ unsigned long long coef_phys_addr[VO_COEF_BUF_BUTT]; -+} vo_coef_addr; -+ -+typedef struct { -+ unsigned int data3; -+ unsigned int data2; -+ unsigned int data1; -+ unsigned int data0; -+ unsigned int depth; -+} vo_drv_u128; -+ -+typedef enum { -+ DRV_COEF_DATA_TYPE_U8 = 0, -+ DRV_COEF_DATA_TYPE_S8, -+ DRV_COEF_DATA_TYPE_U16, -+ DRV_COEF_DATA_TYPE_S16, -+ DRV_COEF_DATA_TYPE_U32, -+ DRV_COEF_DATA_TYPE_S32, -+ DRV_COEF_DATA_TYPE_BUTT -+} vo_drv_coef_data_type; -+ -+typedef enum { -+ VO_RM_COEF_MODE_TYP = 0x0, -+} vo_rm_coef_mode; -+ -+typedef struct { -+ vo_rm_coef_mode coef_mode; -+ unsigned int phase; -+ unsigned int tap; -+ short (*typ_lut)[VO_MAX_ZME_TAP]; -+ short (*gen_lut)[VO_MAX_ZME_TAP]; -+ short *max_val; -+ short *min_val; -+} vo_zme_coef_gen_info; -+ -+ -+ -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#endif /* end of DRV_VO_COMM_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo.h -new file mode 100755 -index 0000000..ec7a435 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo.h -@@ -0,0 +1,62 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HAL_VO_H -+#define HAL_VO_H -+ -+#include "hal_vo_reg.h" -+#include "hal_vo_def.h" -+#include "inner_vo.h" -+#include "sys_cmp.h" -+#include "hal_vo_comm.h" -+#include "hal_vo_dev.h" -+#include "hal_vo_video.h" -+#include "hal_vo_layer_comm.h" -+#include "hal_vo_gfx_comm.h" -+#include "mkp_vo.h" -+#include "ot_comm_irq.h" -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#if vo_desc("UBOOT_VO") -+ -+#if vo_desc("hal pub") -+volatile reg_vdp_regs *vo_hal_get_reg(td_void); -+td_void vo_hal_set_reg(volatile reg_vdp_regs *reg); -+#endif -+ -+#if vo_desc("get abs addr") -+td_ulong vou_get_abs_addr(hal_disp_layer layer, td_ulong reg); -+td_ulong vou_get_chn_abs_addr(ot_vo_dev dev, td_ulong reg); -+td_ulong vou_get_vid_abs_addr(hal_disp_layer layer, td_ulong reg); -+td_ulong vou_get_gfx_abs_addr(hal_disp_layer layer, td_ulong reg); -+#endif -+ -+#endif /* #if vo_desc("UBOOT_VO") */ -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#endif /* end of HAL_VO_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_def.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_def.h -new file mode 100755 -index 0000000..abc869a ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_def.h -@@ -0,0 +1,235 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HAL_VO_DEF_H -+#define HAL_VO_DEF_H -+ -+#include "ot_defines.h" -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+ -+ -+#define VHD_REGS_LEN 0x1000 /* len of V0's regs */ -+#define GFX_REGS_LEN 0x800 -+#define DHD_REGS_LEN 0x1000 -+#define VID_REGS_LEN 0x200 /* len of VID regs */ -+#define GRF_REGS_LEN 0x200 /* len of GFX regs */ -+ -+/* offset define */ -+/* 0x200 bytes, 0x200/4 regs */ -+#define FDR_VID_OFFSET (0x200 / 4) -+ -+#define ZME_HPREC (1 << 20) -+#define ZME_VPREC (1 << 12) -+ -+#define VO_INPUT_BIT_WIDTH_10 10 -+ -+#define VO_OUTPUT_BIT_WIDTH_10 10 -+#define VO_OUTPUT_BIT_WIDTH_6 6 -+ -+typedef enum { -+ VO_DEV_DHD0 = 0, /* ultra high definition device */ -+ VO_DEV_DHD1 = 1, /* high definition device */ -+ VO_DEV_BUTT -+} vo_hal_dev; -+ -+typedef enum { -+ VO_HAL_LAYER_VHD0 = 0, /* V0 layer */ -+ VO_HAL_LAYER_VHD1 = 1, /* V1 layer */ -+ VO_HAL_LAYER_VHD2 = 2, /* V2 layer */ -+ -+ VO_HAL_LAYER_BUTT -+} vo_hal_layer; -+ -+typedef enum { -+ VO_SW_LAYER_VHD0 = 0, -+ VO_SW_LAYER_VHD1 = 1, -+ VO_SW_LAYER_VHD2 = 2, -+ -+ VO_SW_LAYER_VIRT0 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_0), -+ VO_SW_LAYER_VIRT1 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_1), -+ VO_SW_LAYER_VIRT2 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_2), -+ VO_SW_LAYER_VIRT3 = ot_vo_get_virt_layer(OT_VO_VIRT_DEV_3), -+ VO_SW_LAYER_VIRT31 = (VO_SW_LAYER_VIRT0 + OT_VO_MAX_VIRT_DEV_NUM), -+ -+ VOU_SW_LAYER_BUTT -+} vo_sw_layer; -+#if 0 -+typedef enum { -+ HAL_DISP_LAYER_VHD0 = 0, -+ HAL_DISP_LAYER_VHD1 = 1, -+ HAL_DISP_LAYER_VHD2 = 2, -+ -+ HAL_DISP_LAYER_GFX0 = 3, -+ HAL_DISP_LAYER_GFX1 = 4, -+ HAL_DISP_LAYER_GFX3 = 5, -+ HAL_DISP_LAYER_BUTT, -+} hal_disp_layer; -+#endif -+ -+typedef enum { -+ HAL_DISP_LAYER_VHD0 = 0, -+ HAL_DISP_LAYER_VHD1 = 1, -+ HAL_DISP_LAYER_VHD2 = 2, -+ HAL_DISP_LAYER_VSD0 = 3, -+ -+ HAL_DISP_LAYER_GFX0 = 4, -+ HAL_DISP_LAYER_GFX1 = 5, -+ HAL_DISP_LAYER_GFX2 = 6, -+ HAL_DISP_LAYER_GFX3 = 7, -+ HAL_DISP_LAYER_GFX4 = 8, -+ -+ HAL_DISP_LAYER_WBC = 9, -+ HAL_DISP_LAYER_BUTT, -+} hal_disp_layer; -+ -+ -+#define DEV_PHY_START VO_DEV_DHD0 -+#define DEV_PHY_END VO_DEV_DHD1 -+ -+#define LAYER_VID_START HAL_DISP_LAYER_VHD0 /* VHD0 */ -+#define LAYER_VID_END HAL_DISP_LAYER_VHD2 /* VHD2 */ -+#define LAYER_PHY_END VO_SW_LAYER_VHD2 -+ -+#define LAYER_GFX_START HAL_DISP_LAYER_GFX0 /* GFX0 */ -+#define LAYER_GFX_END HAL_DISP_LAYER_GFX2 /* GFX3 */ -+ -+typedef struct { -+ unsigned int dither_sed_y0; -+ unsigned int dither_sed_u0; -+ unsigned int dither_sed_v0; -+ unsigned int dither_sed_w0; -+ -+ unsigned int dither_sed_y1; -+ unsigned int dither_sed_u1; -+ unsigned int dither_sed_v1; -+ unsigned int dither_sed_w1; -+ -+ unsigned int dither_sed_y2; -+ unsigned int dither_sed_u2; -+ unsigned int dither_sed_v2; -+ unsigned int dither_sed_w2; -+ -+ unsigned int dither_sed_y3; -+ unsigned int dither_sed_u3; -+ unsigned int dither_sed_v3; -+ unsigned int dither_sed_w3; -+} vo_dihter_sed; -+ -+typedef enum { -+ DITHER_IO_MODE_12_10 = 1, -+ DITHER_IO_MODE_12_8 = 2, /* for rgb24bit */ -+ DITHER_IO_MODE_10_8 = 3, -+ DITHER_IO_MODE_10_6 = 4, /* for rgb16bit, rgb18bit */ -+ DITHER_IO_MODE_BUTT -+} dither_io_mode; -+ -+typedef enum { -+ DITHER_MODE_10BIT = 0, -+ DITHER_MODE_8BIT = 1, -+ DITHER_MODE_BUTT -+} dither_mode; -+ -+typedef enum { -+ DITHER_OWIDTH_MODE_5BIT = 0, -+ DITHER_OWIDTH_MODE_6BIT = 1, -+ DITHER_OWIDTH_MODE_7BIT = 2, -+ DITHER_OWIDTH_MODE_8BIT = 3, -+ DITHER_OWIDTH_MODE_9BIT = 4, -+ DITHER_OWIDTH_MODE_10BIT = 5, -+ DITHER_OWIDTH_MODE_BUTT -+} dither_owidth_mode; -+ -+typedef enum { -+ DITHER_IWIDTH_MODE_8BIT = 0, -+ DITHER_IWIDTH_MODE_9BIT = 1, -+ DITHER_IWIDTH_MODE_10BIT = 2, -+ DITHER_IWIDTH_MODE_11BIT = 3, -+ DITHER_IWIDTH_MODE_12BIT = 4, -+ DITHER_IWIDTH_MODE_BUTT -+} dither_iwidth_mode; -+ -+typedef struct { -+ dither_io_mode io_mode; -+ -+ unsigned int dither_en; -+ unsigned int dither_mode; -+ unsigned int dither_round; -+ unsigned int dither_round_unlim; -+ unsigned int i_data_width_dither; -+ unsigned int o_data_width_dither; -+ unsigned int dither_domain_mode; -+ unsigned int dither_tap_mode; -+ vo_dihter_sed dither_sed; -+ unsigned int dither_thr_max; -+ unsigned int dither_thr_min; -+} vdp_dither_cfg; -+ -+ -+ -+ -+ -+#define MAX_REGION_NUM 64 -+#define V0_REGION_NUM 64 -+#define V1_REGION_NUM 1 -+#define V2_REGION_NUM 1 -+#define VIRT_LAYER_REGION_NUM 64 -+ -+/* 提前6ms（预估值）上报VTTH */ -+#define VO_DEAULT_VTTH_TIME 6 -+ -+#define MRG_REGS_LEN 0xc00 /* len of v0 mrg regs */ -+ -+#define MRG_OFFSET_ADDR 0x12000 -+ -+/* for CMP and DCMP */ -+#define CMP_SEG_OFFSET (0x80 / 4) -+#define DCMP_SEG_OFFSET (0x20 / 4) -+ -+#define VO_DEV_DSD_START VO_DEV_DSD0 -+#define VO_DEV_DSD_END VO_DEV_DSD0 -+ -+#define VO_DEV_DHD_START VO_DEV_DHD0 -+#define VO_DEV_DHD_END VO_DEV_DHD1 -+ -+typedef enum { -+ VO_COEF_BUF_REGION_V0 = 8, -+ VO_COEF_BUF_REGION_V1 = 9, -+ -+ VO_COEF_BUF_BUTT = 10 -+} vo_coef_buf; -+ -+#define VO_ALL_COEF_SIZE COEF_SIZE_REGION_V0 -+#define COEF_SIZE_REGION_V0 (192 * 128 / 8) -+ -+#define LAYER_MRG_START HAL_DISP_LAYER_VHD0 -+#define LAYER_MRG_END HAL_DISP_LAYER_VHD1 -+ -+ -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif -+#endif /* end of #ifdef __cplusplus */ -+#endif /* end of HAL_VO_DEF_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_dev.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_dev.h -new file mode 100755 -index 0000000..fdee23f ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_dev.h -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HAL_VO_DEV_H -+#define HAL_VO_DEV_H -+ -+#include "hal_vo_dev_comm.h" -+#include "inner_vo.h" -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#if vo_desc("UBOOT_VO") -+ -+td_void hal_sys_set_outstanding(td_void); -+ -+#if vo_desc("dev intf") -+#define VO_CVBS_DATE_PAL 0x628412dc -+#define VO_CVBS_DATE_NTSC 0x108412dc -+#define VO_CVBS_DATE_GAIN 0x8080958a -+#define VO_CVBS_DATE_PAL_GAIN VO_CVBS_DATE_GAIN -+#define VO_CVBS_DATE_NTSC_GAIN VO_CVBS_DATE_GAIN -+td_void vo_hal_intf_set_cvbs_dac_cfg(td_void); -+td_void vo_hal_intf_set_date_cvbs_gain(td_u32 data); -+td_void vo_hal_intf_set_date_cvbs_burst_start(td_void); -+td_void hal_disp_set_hdmi_mode(ot_vo_dev dev, td_u32 color_space); -+td_void vo_hal_intf_set_rgb_sync_inv(const hal_disp_syncinv *inv); -+td_void vo_hal_intf_set_mipi_sync_inv(const hal_disp_syncinv *inv); -+td_void vo_hal_intf_set_mux_sel(ot_vo_dev dev, ot_vo_intf_type intf); -+td_void vo_hal_intf_set_csc_enable(ot_vo_intf_type intf, td_bool enable); -+td_void vo_hal_intf_set_csc_cfg(ot_vo_intf_type intf, const csc_coef *csc_cfg); -+td_void vo_hal_set_intf_rgb_component_order(td_bool component_inverse_en); -+td_void vo_hal_set_intf_rgb_bit_inverse(td_bool bit_inverse_en); -+td_void hal_disp_set_lcd_serial_perd(td_u32 serial_perd); -+td_void vo_hal_set_intf_ctrl(ot_vo_intf_type intf, const td_u32 *ctrl_info); -+td_void vo_hal_set_dev_precharge_threshold(ot_vo_dev dev, td_bool te_enable); -+td_void vo_hal_intf_set_lcd_dither(const vdp_dither_cfg *cfg); -+#endif -+ -+#endif /* #if vo_desc("UBOOT_VO") */ -+ -+#if vo_desc("KERNEL_VO") -+ -+td_void hal_disp_set_int_mask1(td_u32 mask_en); -+td_void hal_disp_clr_int_mask1(td_u32 mask_en); -+td_void vo_hal_intf_set_dac_det_cable_en(ot_vo_dev dev, ot_vo_intf_type intf_type, td_bool enable); -+td_void vo_hal_intf_get_dec_det_high(ot_vo_intf_type intf_type, td_bool enable, -+ td_u32 *det_high); -+ -+#endif /* #if vo_desc("KERNEL_VO") */ -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#endif /* end of HAL_VO_DEV_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_reg.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_reg.h -new file mode 100755 -index 0000000..5106fb3 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_reg.h -@@ -0,0 +1,20459 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HAL_VO_REG_H -+#define HAL_VO_REG_H -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+/* define the union reg_voctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 23; /* [22..0] */ -+ unsigned int g3_ck_gt_en : 1; /* [23] */ -+ unsigned int v2_ck_gt_en : 1; /* [24] */ -+ unsigned int wbc_dhd_ck_gt_en : 1; /* [25] */ -+ unsigned int g1_ck_gt_en : 1; /* [26] */ -+ unsigned int g0_ck_gt_en : 1; /* [27] */ -+ unsigned int v1_ck_gt_en : 1; /* [28] */ -+ unsigned int v0_ck_gt_en : 1; /* [29] */ -+ unsigned int chk_sum_en : 1; /* [30] */ -+ unsigned int vo_ck_gt_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_voctrl; -+ -+/* define the union reg_vointsta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_int : 1; /* [0] */ -+ unsigned int dhd0vtthd2_int : 1; /* [1] */ -+ unsigned int dhd0vtthd3_int : 1; /* [2] */ -+ unsigned int dhd0uf_int : 1; /* [3] */ -+ unsigned int dhd1vtthd1_int : 1; /* [4] */ -+ unsigned int dhd1vtthd2_int : 1; /* [5] */ -+ unsigned int dhd1vtthd3_int : 1; /* [6] */ -+ unsigned int dhd1uf_int : 1; /* [7] */ -+ unsigned int dsdvtthd1_int : 1; /* [8] */ -+ unsigned int dsdvtthd2_int : 1; /* [9] */ -+ unsigned int dsdvtthd3_int : 1; /* [10] */ -+ unsigned int dsduf_int : 1; /* [11] */ -+ unsigned int b0_err_int : 1; /* [12] */ -+ unsigned int b1_err_int : 1; /* [13] */ -+ unsigned int b2_err_int : 1; /* [14] */ -+ unsigned int wbc_dhd_over_int : 1; /* [15] */ -+ unsigned int vdac0_int : 1; /* [16] */ -+ unsigned int vdac1_int : 1; /* [17] */ -+ unsigned int vdac2_int : 1; /* [18] */ -+ unsigned int vdac3_int : 1; /* [19] */ -+ unsigned int v0_tunl_int : 1; /* [20] */ -+ unsigned int v1_tunl_int : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vointsta; -+ -+/* define the union reg_vomskintsta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_clr : 1; /* [0] */ -+ unsigned int dhd0vtthd2_clr : 1; /* [1] */ -+ unsigned int dhd0vtthd3_clr : 1; /* [2] */ -+ unsigned int dhd0uf_clr : 1; /* [3] */ -+ unsigned int dhd1vtthd1_clr : 1; /* [4] */ -+ unsigned int dhd1vtthd2_clr : 1; /* [5] */ -+ unsigned int dhd1vtthd3_clr : 1; /* [6] */ -+ unsigned int dhd1uf_clr : 1; /* [7] */ -+ unsigned int dsdvtthd1_clr : 1; /* [8] */ -+ unsigned int dsdvtthd2_clr : 1; /* [9] */ -+ unsigned int dsdvtthd3_clr : 1; /* [10] */ -+ unsigned int dsduf_clr : 1; /* [11] */ -+ unsigned int b0_err_clr : 1; /* [12] */ -+ unsigned int b1_err_clr : 1; /* [13] */ -+ unsigned int b2_err_clr : 1; /* [14] */ -+ unsigned int wbc_dhd_over_clr : 1; /* [15] */ -+ unsigned int vdac0_clr : 1; /* [16] */ -+ unsigned int vdac1_clr : 1; /* [17] */ -+ unsigned int vdac2_clr : 1; /* [18] */ -+ unsigned int vdac3_clr : 1; /* [19] */ -+ unsigned int v0_tunl_clr : 1; /* [20] */ -+ unsigned int v1_tunl_clr : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vomskintsta; -+ -+/* define the union reg_vointmsk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ -+ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ -+ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ -+ unsigned int dhd0uf_intmask : 1; /* [3] */ -+ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ -+ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ -+ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ -+ unsigned int dhd1uf_intmask : 1; /* [7] */ -+ unsigned int dsdvtthd1_intmask : 1; /* [8] */ -+ unsigned int dsdvtthd2_intmask : 1; /* [9] */ -+ unsigned int dsdvtthd3_intmask : 1; /* [10] */ -+ unsigned int dsduf_intmask : 1; /* [11] */ -+ unsigned int b0_err_intmask : 1; /* [12] */ -+ unsigned int b1_err_intmask : 1; /* [13] */ -+ unsigned int b2_err_intmask : 1; /* [14] */ -+ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ -+ unsigned int vdac0_intmask : 1; /* [16] */ -+ unsigned int vdac1_intmask : 1; /* [17] */ -+ unsigned int vdac2_intmask : 1; /* [18] */ -+ unsigned int vdac3_intmask : 1; /* [19] */ -+ unsigned int v0_tunl_intmask : 1; /* [20] */ -+ unsigned int v1_tunl_intmask : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vointmsk; -+ -+/* define the union reg_vodebug */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rm_en_chn : 4; /* [3..0] */ -+ unsigned int dhd0_ff_info : 2; /* [5..4] */ -+ unsigned int dhd1_ff_info : 2; /* [7..6] */ -+ unsigned int dsd0_ff_info : 2; /* [9..8] */ -+ unsigned int bfm_vga_en : 1; /* [10] */ -+ unsigned int bfm_cvbs_en : 1; /* [11] */ -+ unsigned int bfm_lcd_en : 1; /* [12] */ -+ unsigned int bfm_bt1120_en : 1; /* [13] */ -+ unsigned int wbc2_ff_info : 2; /* [15..14] */ -+ unsigned int wbc_mode : 4; /* [19..16] */ -+ unsigned int node_num : 4; /* [23..20] */ -+ unsigned int wbc_cmp_mode : 2; /* [25..24] */ -+ unsigned int bfm_mode : 3; /* [28..26] */ -+ unsigned int bfm_clk_sel : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vodebug; -+ -+/* define the union reg_vointsta1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_int : 1; /* [0] */ -+ unsigned int dhd0vtthd2_int : 1; /* [1] */ -+ unsigned int dhd0vtthd3_int : 1; /* [2] */ -+ unsigned int dhd0uf_int : 1; /* [3] */ -+ unsigned int dhd1vtthd1_int : 1; /* [4] */ -+ unsigned int dhd1vtthd2_int : 1; /* [5] */ -+ unsigned int dhd1vtthd3_int : 1; /* [6] */ -+ unsigned int dhd1uf_int : 1; /* [7] */ -+ unsigned int dsdvtthd1_int : 1; /* [8] */ -+ unsigned int dsdvtthd2_int : 1; /* [9] */ -+ unsigned int dsdvtthd3_int : 1; /* [10] */ -+ unsigned int dsduf_int : 1; /* [11] */ -+ unsigned int b0_err_int : 1; /* [12] */ -+ unsigned int b1_err_int : 1; /* [13] */ -+ unsigned int b2_err_int : 1; /* [14] */ -+ unsigned int wbc_dhd_over_int : 1; /* [15] */ -+ unsigned int vdac0_int : 1; /* [16] */ -+ unsigned int vdac1_int : 1; /* [17] */ -+ unsigned int vdac2_int : 1; /* [18] */ -+ unsigned int vdac3_int : 1; /* [19] */ -+ unsigned int v0_tunl_int : 1; /* [20] */ -+ unsigned int v1_tunl_int : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vointsta1; -+ -+/* define the union reg_vomskintsta1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_clr : 1; /* [0] */ -+ unsigned int dhd0vtthd2_clr : 1; /* [1] */ -+ unsigned int dhd0vtthd3_clr : 1; /* [2] */ -+ unsigned int dhd0uf_clr : 1; /* [3] */ -+ unsigned int dhd1vtthd1_clr : 1; /* [4] */ -+ unsigned int dhd1vtthd2_clr : 1; /* [5] */ -+ unsigned int dhd1vtthd3_clr : 1; /* [6] */ -+ unsigned int dhd1uf_clr : 1; /* [7] */ -+ unsigned int dsdvtthd1_clr : 1; /* [8] */ -+ unsigned int dsdvtthd2_clr : 1; /* [9] */ -+ unsigned int dsdvtthd3_clr : 1; /* [10] */ -+ unsigned int dsduf_clr : 1; /* [11] */ -+ unsigned int b0_err_clr : 1; /* [12] */ -+ unsigned int b1_err_clr : 1; /* [13] */ -+ unsigned int b2_err_clr : 1; /* [14] */ -+ unsigned int wbc_dhd_over_clr : 1; /* [15] */ -+ unsigned int vdac0_clr : 1; /* [16] */ -+ unsigned int vdac1_clr : 1; /* [17] */ -+ unsigned int vdac2_clr : 1; /* [18] */ -+ unsigned int vdac3_clr : 1; /* [19] */ -+ unsigned int v0_tunl_clr : 1; /* [20] */ -+ unsigned int v1_tunl_clr : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vomskintsta1; -+ -+/* define the union reg_vointmsk1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dhd0vtthd1_intmask : 1; /* [0] */ -+ unsigned int dhd0vtthd2_intmask : 1; /* [1] */ -+ unsigned int dhd0vtthd3_intmask : 1; /* [2] */ -+ unsigned int dhd0uf_intmask : 1; /* [3] */ -+ unsigned int dhd1vtthd1_intmask : 1; /* [4] */ -+ unsigned int dhd1vtthd2_intmask : 1; /* [5] */ -+ unsigned int dhd1vtthd3_intmask : 1; /* [6] */ -+ unsigned int dhd1uf_intmask : 1; /* [7] */ -+ unsigned int dsdvtthd1_intmask : 1; /* [8] */ -+ unsigned int dsdvtthd2_intmask : 1; /* [9] */ -+ unsigned int dsdvtthd3_intmask : 1; /* [10] */ -+ unsigned int dsduf_intmask : 1; /* [11] */ -+ unsigned int b0_err_intmask : 1; /* [12] */ -+ unsigned int b1_err_intmask : 1; /* [13] */ -+ unsigned int b2_err_intmask : 1; /* [14] */ -+ unsigned int wbc_dhd_over_intmask : 1; /* [15] */ -+ unsigned int vdac0_intmask : 1; /* [16] */ -+ unsigned int vdac1_intmask : 1; /* [17] */ -+ unsigned int vdac2_intmask : 1; /* [18] */ -+ unsigned int vdac3_intmask : 1; /* [19] */ -+ unsigned int v0_tunl_intmask : 1; /* [20] */ -+ unsigned int v1_tunl_intmask : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vointmsk1; -+ -+/* define the union reg_volowpower_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rasehd_twac : 2; /* [1..0] */ -+ unsigned int rasehd_twa : 2; /* [3..2] */ -+ unsigned int rashd_tselw : 2; /* [5..4] */ -+ unsigned int rashd_tselr : 3; /* [8..6] */ -+ unsigned int rfshd_tselw : 2; /* [10..9] */ -+ unsigned int rfshd_tselr : 3; /* [13..11] */ -+ unsigned int rfsehd_tselw : 2; /* [15..14] */ -+ unsigned int rfsehd_tselr : 3; /* [18..16] */ -+ unsigned int rasehd_tselw : 2; /* [20..19] */ -+ unsigned int rasehd_tselr : 3; /* [23..21] */ -+ unsigned int rfthd_tselw : 2; /* [25..24] */ -+ unsigned int rfthd_tselr : 2; /* [27..26] */ -+ unsigned int rftehd_tselw : 2; /* [29..28] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_volowpower_ctrl; -+ -+/* define the union reg_voufsta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_uf_sta : 1; /* [0] */ -+ unsigned int v1_uf_sta : 1; /* [1] */ -+ unsigned int reserved_0 : 1; /* [2] */ -+ unsigned int v3_uf_sta : 1; /* [3] */ -+ unsigned int reserved_1 : 4; /* [7..4] */ -+ unsigned int g0_uf_sta : 1; /* [8] */ -+ unsigned int g1_uf_sta : 1; /* [9] */ -+ unsigned int g2_uf_sta : 1; /* [10] */ -+ unsigned int g3_uf_sta : 1; /* [11] */ -+ unsigned int g4_uf_sta : 1; /* [12] */ -+ unsigned int reserved_2 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_voufsta; -+ -+/* define the union reg_voufclr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_uf_clr : 1; /* [0] */ -+ unsigned int v1_uf_clr : 1; /* [1] */ -+ unsigned int reserved_0 : 1; /* [2] */ -+ unsigned int v3_uf_clr : 1; /* [3] */ -+ unsigned int reserved_1 : 4; /* [7..4] */ -+ unsigned int g0_uf_clr : 1; /* [8] */ -+ unsigned int g1_uf_clr : 1; /* [9] */ -+ unsigned int g2_uf_clr : 1; /* [10] */ -+ unsigned int g3_uf_clr : 1; /* [11] */ -+ unsigned int g4_uf_clr : 1; /* [12] */ -+ unsigned int reserved_2 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_voufclr; -+ -+/* define the union reg_vointproc_tim */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vointproc_time : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vointproc_tim; -+ -+/* define the union reg_volowpower_ctrl1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rftehd_tselr : 3; /* [2..0] */ -+ unsigned int rftehd_tselm : 2; /* [4..3] */ -+ unsigned int rasehd_test : 3; /* [7..5] */ -+ unsigned int rashd_test : 3; /* [10..8] */ -+ unsigned int rfsehd_test : 3; /* [13..11] */ -+ unsigned int rfshd_test : 3; /* [16..14] */ -+ unsigned int rftehd_test : 3; /* [19..17] */ -+ unsigned int rfthd_test : 3; /* [22..20] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_volowpower_ctrl1; -+ -+/* define the union reg_vofpgadef */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_hdr_v_def : 1; /* [0] */ -+ unsigned int ot_hdr_g_def : 1; /* [1] */ -+ unsigned int ot_hdr_wd_def : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vofpgadef; -+ -+/* define the union reg_volowpower_ctrl2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int s14_rfshd_rm : 4; /* [3..0] */ -+ unsigned int s14_rfshs_rm : 4; /* [7..4] */ -+ unsigned int s14_rasehd_rm : 4; /* [11..8] */ -+ unsigned int s14_rashd_rm : 4; /* [15..12] */ -+ unsigned int s14_rfshd_rme : 1; /* [16] */ -+ unsigned int s14_rfshs_rme : 1; /* [17] */ -+ unsigned int s14_rasehd_rme : 1; /* [18] */ -+ unsigned int s14_rashd_rme : 1; /* [19] */ -+ unsigned int s14_rfthd_rma : 4; /* [23..20] */ -+ unsigned int s14_rfthd_rmb : 4; /* [27..24] */ -+ unsigned int s14_rfthd_rmea : 1; /* [28] */ -+ unsigned int s14_rfthd_rmeb : 1; /* [29] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_volowpower_ctrl2; -+ -+/* define the union reg_volowpower_ctrl3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int s14_rom_rm : 4; /* [3..0] */ -+ unsigned int s14_rom_rme : 1; /* [4] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_volowpower_ctrl3; -+ -+/* define the union reg_vomux_dac */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dac0_sel : 4; /* [3..0] */ -+ unsigned int dac1_sel : 4; /* [7..4] */ -+ unsigned int dac2_sel : 4; /* [11..8] */ -+ unsigned int dac3_sel : 4; /* [15..12] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vomux_dac; -+ -+/* define the union reg_vomux_testsync */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int test_dv : 1; /* [0] */ -+ unsigned int test_hsync : 1; /* [1] */ -+ unsigned int test_vsync : 1; /* [2] */ -+ unsigned int test_field : 1; /* [3] */ -+ unsigned int reserved_0 : 27; /* [30..4] */ -+ unsigned int vo_test_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vomux_testsync; -+ -+/* define the union reg_vomux_testdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int test_data : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vomux_testdata; -+ -+/* define the union reg_vo_dac_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dac_reg_rev : 4; /* [3..0] */ -+ unsigned int dac_reg_rev1 : 6; /* [9..4] */ -+ unsigned int dac_reg_dac3_cable_en : 1; /* [10] */ -+ unsigned int dac_reg_rev2 : 3; /* [13..11] */ -+ unsigned int dac_reg_vref_cable : 1; /* [14] */ -+ unsigned int dac_reg_res_sel : 1; /* [15] */ -+ unsigned int enctr : 4; /* [19..16] */ -+ unsigned int enextref : 1; /* [20] */ -+ unsigned int pdchopper : 1; /* [21] */ -+ unsigned int envbg : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac_ctrl; -+ -+/* define the union reg_vo_dac_otp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dac_otp_rev0 : 3; /* [2..0] */ -+ unsigned int dac_otp_poly_step : 6; /* [8..3] */ -+ unsigned int dac_otp_rev1 : 5; /* [13..9] */ -+ unsigned int dac_otp_ch3_itrim : 1; /* [14] */ -+ unsigned int dac_otp_24k_12k_sel : 1; /* [15] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac_otp; -+ -+/* define the union reg_vo_dac0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac0_ctrl; -+ -+/* define the union reg_vo_dac1_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac1_ctrl; -+ -+/* define the union reg_vo_dac2_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac2_ctrl; -+ -+/* define the union reg_vo_dac3_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cablectr : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int dacgc : 6; /* [9..4] */ -+ unsigned int reserved_1 : 21; /* [30..10] */ -+ unsigned int dac_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac3_ctrl; -+ -+/* define the union reg_vo_dac_stat0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cableout0 : 1; /* [0] */ -+ unsigned int cableout1 : 1; /* [1] */ -+ unsigned int cableout2 : 1; /* [2] */ -+ unsigned int cableout3 : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_dac_stat0; -+ -+/* define the union reg_cbm_bkg1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cbm_bkgcr1 : 10; /* [9..0] */ -+ unsigned int cbm_bkgcb1 : 10; /* [19..10] */ -+ unsigned int cbm_bkgy1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_cbm_bkg1; -+ -+/* define the union reg_cbm_mix1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int mixer_prio4 : 4; /* [19..16] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_cbm_mix1; -+ -+/* define the union reg_wbc_bmp_thd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_bmp_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_bmp_thd; -+ -+/* define the union reg_cbm_bkg2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cbm_bkgcr2 : 10; /* [9..0] */ -+ unsigned int cbm_bkgcb2 : 10; /* [19..10] */ -+ unsigned int cbm_bkgy2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_cbm_bkg2; -+ -+/* define the union reg_cbm_mix2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int mixer_prio4 : 4; /* [19..16] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_cbm_mix2; -+ -+/* define the union reg_hc_bmp_thd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hc_bmp_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hc_bmp_thd; -+ -+/* define the union reg_cbm_bkg3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cbm_bkgcr3 : 10; /* [9..0] */ -+ unsigned int cbm_bkgcb3 : 10; /* [19..10] */ -+ unsigned int cbm_bkgy3 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_cbm_bkg3; -+ -+/* define the union reg_cbm_mix3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_cbm_mix3; -+ -+/* define the union reg_mixv0_bkg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_bkgcr : 10; /* [9..0] */ -+ unsigned int mixer_bkgcb : 10; /* [19..10] */ -+ unsigned int mixer_bkgy : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mixv0_bkg; -+ -+/* define the union reg_mixv0_mix */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mixv0_mix; -+ -+/* define the union reg_mixg0_bkg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_bkgcr : 10; /* [9..0] */ -+ unsigned int mixer_bkgcb : 10; /* [19..10] */ -+ unsigned int mixer_bkgy : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mixg0_bkg; -+ -+/* define the union reg_mixg0_bkalpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mixg0_bkalpha; -+ -+/* define the union reg_mixg0_mix */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mixer_prio0 : 4; /* [3..0] */ -+ unsigned int mixer_prio1 : 4; /* [7..4] */ -+ unsigned int mixer_prio2 : 4; /* [11..8] */ -+ unsigned int mixer_prio3 : 4; /* [15..12] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mixg0_mix; -+ -+/* define the union reg_link_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v2_link : 2; /* [1..0] */ -+ unsigned int g3_link : 2; /* [3..2] */ -+ unsigned int g2_link : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_link_ctrl; -+ -+/* define the union reg_vpss_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vpss_en : 1; /* [0] */ -+ unsigned int chk_sum_en : 1; /* [1] */ -+ unsigned int dei_en : 1; /* [2] */ -+ unsigned int mcdi_en : 1; /* [3] */ -+ unsigned int nx2_vc1_en : 1; /* [4] */ -+ unsigned int rgme_en : 1; /* [5] */ -+ unsigned int meds_en : 1; /* [6] */ -+ unsigned int hsp_en : 1; /* [7] */ -+ unsigned int snr_en : 1; /* [8] */ -+ unsigned int tnr_en : 1; /* [9] */ -+ unsigned int rfr_en : 1; /* [10] */ -+ unsigned int ifmd_en : 1; /* [11] */ -+ unsigned int igbm_en : 1; /* [12] */ -+ unsigned int cue_en : 1; /* [13] */ -+ unsigned int scd_en : 1; /* [14] */ -+ unsigned int blk_det_en : 1; /* [15] */ -+ unsigned int reserved_0 : 7; /* [22..16] */ -+ unsigned int vpss_node_init : 1; /* [23] */ -+ unsigned int ram_bank : 4; /* [27..24] */ -+ unsigned int dei_debug_en : 1; /* [28] */ -+ unsigned int dei_repeat_mode : 1; /* [29] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vpss_ctrl; -+ -+/* define the union reg_vpss_miscellaneous */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 4; /* [3..0] */ -+ unsigned int reserved_1 : 4; /* [7..4] */ -+ unsigned int reserved_2 : 16; /* [23..8] */ -+ unsigned int ck_gt_en : 1; /* [24] */ -+ unsigned int ck_gt_en_calc : 1; /* [25] */ -+ unsigned int reserved_3 : 2; /* [27..26] */ -+ unsigned int reserved_4 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vpss_miscellaneous; -+ -+/* define the union reg_vpss_ftconfig */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int node_rst_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vpss_ftconfig; -+ -+/* define the union reg_para_up_vhd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_up_vhd_chn00 : 1; /* [0] */ -+ unsigned int para_up_vhd_chn01 : 1; /* [1] */ -+ unsigned int para_up_vhd_chn02 : 1; /* [2] */ -+ unsigned int para_up_vhd_chn03 : 1; /* [3] */ -+ unsigned int para_up_vhd_chn04 : 1; /* [4] */ -+ unsigned int para_up_vhd_chn05 : 1; /* [5] */ -+ unsigned int para_up_vhd_chn06 : 1; /* [6] */ -+ unsigned int para_up_vhd_chn07 : 1; /* [7] */ -+ unsigned int para_up_vhd_chn08 : 1; /* [8] */ -+ unsigned int para_up_vhd_chn09 : 1; /* [9] */ -+ unsigned int para_up_vhd_chn10 : 1; /* [10] */ -+ unsigned int para_up_vhd_chn11 : 1; /* [11] */ -+ unsigned int para_up_vhd_chn12 : 1; /* [12] */ -+ unsigned int para_up_vhd_chn13 : 1; /* [13] */ -+ unsigned int para_up_vhd_chn14 : 1; /* [14] */ -+ unsigned int para_up_vhd_chn15 : 1; /* [15] */ -+ unsigned int para_up_vhd_chn16 : 1; /* [16] */ -+ unsigned int para_up_vhd_chn17 : 1; /* [17] */ -+ unsigned int para_up_vhd_chn18 : 1; /* [18] */ -+ unsigned int para_up_vhd_chn19 : 1; /* [19] */ -+ unsigned int para_up_vhd_chn20 : 1; /* [20] */ -+ unsigned int para_up_vhd_chn21 : 1; /* [21] */ -+ unsigned int para_up_vhd_chn22 : 1; /* [22] */ -+ unsigned int para_up_vhd_chn23 : 1; /* [23] */ -+ unsigned int para_up_vhd_chn24 : 1; /* [24] */ -+ unsigned int para_up_vhd_chn25 : 1; /* [25] */ -+ unsigned int para_up_vhd_chn26 : 1; /* [26] */ -+ unsigned int para_up_vhd_chn27 : 1; /* [27] */ -+ unsigned int para_up_vhd_chn28 : 1; /* [28] */ -+ unsigned int para_up_vhd_chn29 : 1; /* [29] */ -+ unsigned int para_up_vhd_chn30 : 1; /* [30] */ -+ unsigned int para_up_vhd_chn31 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_para_up_vhd; -+ -+/* define the union reg_para_up_vsd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_up_vsd_chn00 : 1; /* [0] */ -+ unsigned int para_up_vsd_chn01 : 1; /* [1] */ -+ unsigned int para_up_vsd_chn02 : 1; /* [2] */ -+ unsigned int para_up_vsd_chn03 : 1; /* [3] */ -+ unsigned int para_up_vsd_chn04 : 1; /* [4] */ -+ unsigned int para_up_vsd_chn05 : 1; /* [5] */ -+ unsigned int para_up_vsd_chn06 : 1; /* [6] */ -+ unsigned int para_up_vsd_chn07 : 1; /* [7] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_para_up_vsd; -+ -+/* define the union reg_para_conflict_clr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_conflict_clr_hd : 1; /* [0] */ -+ unsigned int para_conflict_clr_sd : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_para_conflict_clr; -+ -+/* define the union reg_para_conflict_sta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_conflict_hd : 1; /* [0] */ -+ unsigned int para_conflict_sd : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_para_conflict_sta; -+ -+/* define the union reg_v0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int mir_en : 1; /* [8] */ -+ unsigned int reserved_0 : 19; /* [27..9] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ctrl; -+ -+/* define the union reg_v0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_upd; -+ -+/* define the union reg_v0_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_0reso_read; -+ -+/* define the union reg_v0_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ireso; -+ -+/* define the union reg_v0_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_dfpos; -+ -+/* define the union reg_v0_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_dlpos; -+ -+/* define the union reg_v0_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_vfpos; -+ -+/* define the union reg_v0_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_vlpos; -+ -+/* define the union reg_v0_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_bk; -+ -+/* define the union reg_v0_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_alpha; -+ -+/* define the union reg_v0_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mute_bk; -+ -+/* define the union reg_v0_rimwidth */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_width : 5; /* [4..0] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_rimwidth; -+ -+/* define the union reg_v0_rimcol0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_v0 : 10; /* [9..0] */ -+ unsigned int v0_rim_u0 : 10; /* [19..10] */ -+ unsigned int v0_rim_y0 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_rimcol0; -+ -+/* define the union reg_v0_rimcol1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_v1 : 10; /* [9..0] */ -+ unsigned int v0_rim_u1 : 10; /* [19..10] */ -+ unsigned int v0_rim_y1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_rimcol1; -+ -+/* define the union reg_v0_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_ctrl; -+ -+/* define the union reg_v0_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef00; -+ -+/* define the union reg_v0_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef01; -+ -+/* define the union reg_v0_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef02; -+ -+/* define the union reg_v0_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef10; -+ -+/* define the union reg_v0_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef11; -+ -+/* define the union reg_v0_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef12; -+ -+/* define the union reg_v0_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef20; -+ -+/* define the union reg_v0_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef21; -+ -+/* define the union reg_v0_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_coef22; -+ -+/* define the union reg_v0_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_scale; -+ -+/* define the union reg_v0_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_idc0; -+ -+/* define the union reg_v0_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_idc1; -+ -+/* define the union reg_v0_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_idc2; -+ -+/* define the union reg_v0_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_odc0; -+ -+/* define the union reg_v0_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_odc1; -+ -+/* define the union reg_v0_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_odc2; -+ -+/* define the union reg_v0_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_min_y; -+ -+/* define the union reg_v0_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_min_c; -+ -+/* define the union reg_v0_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_max_y; -+ -+/* define the union reg_v0_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_max_c; -+ -+/* define the union reg_v0_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef00; -+ -+/* define the union reg_v0_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef01; -+ -+/* define the union reg_v0_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef02; -+ -+/* define the union reg_v0_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef10; -+ -+/* define the union reg_v0_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef11; -+ -+/* define the union reg_v0_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef12; -+ -+/* define the union reg_v0_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef20; -+ -+/* define the union reg_v0_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef21; -+ -+/* define the union reg_v0_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_coef22; -+ -+/* define the union reg_v0_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_scale; -+ -+/* define the union reg_v0_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_idc0; -+ -+/* define the union reg_v0_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_idc1; -+ -+/* define the union reg_v0_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_idc2; -+ -+/* define the union reg_v0_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_odc0; -+ -+/* define the union reg_v0_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_odc1; -+ -+/* define the union reg_v0_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_odc2; -+ -+/* define the union reg_v0_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_min_y; -+ -+/* define the union reg_v0_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_min_c; -+ -+/* define the union reg_v0_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_max_y; -+ -+/* define the union reg_v0_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc2_max_c; -+ -+/* define the union reg_v0_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_v0_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_ot_pp_csc_ink_pos; -+ -+/* define the union reg_v0_cvfir_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_vinfo; -+ -+/* define the union reg_v0_cvfir_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_vsp; -+ -+/* define the union reg_v0_cvfir_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_voffset; -+ -+/* define the union reg_v0_cvfir_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_vboffset; -+ -+/* define the union reg_v0_cvfir_vcoef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_vcoef0; -+ -+/* define the union reg_v0_cvfir_vcoef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_vcoef1; -+ -+/* define the union reg_v0_cvfir_vcoef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_cvfir_vcoef2; -+ -+/* define the union reg_v0_hfir_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_hfir_ctrl; -+ -+/* define the union reg_v0_hfircoef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_hfircoef01; -+ -+/* define the union reg_v0_hfircoef23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_hfircoef23; -+ -+/* define the union reg_v0_hfircoef45 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_hfircoef45; -+ -+/* define the union reg_v0_hfircoef67 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_hfircoef67; -+ -+/* define the union reg_v1_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ctrl; -+ -+/* define the union reg_v1_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_upd; -+ -+/* define the union reg_v1_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_0reso_read; -+ -+/* define the union reg_v1_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ireso; -+ -+/* define the union reg_v1_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_dfpos; -+ -+/* define the union reg_v1_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_dlpos; -+ -+/* define the union reg_v1_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_vfpos; -+ -+/* define the union reg_v1_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_vlpos; -+ -+/* define the union reg_v1_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_bk; -+ -+/* define the union reg_v1_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_alpha; -+ -+/* define the union reg_v1_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mute_bk; -+ -+/* define the union reg_v1_rimwidth */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_width : 5; /* [4..0] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_rimwidth; -+ -+/* define the union reg_v1_rimcol0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_v0 : 10; /* [9..0] */ -+ unsigned int v0_rim_u0 : 10; /* [19..10] */ -+ unsigned int v0_rim_y0 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_rimcol0; -+ -+/* define the union reg_v1_rimcol1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_v1 : 10; /* [9..0] */ -+ unsigned int v0_rim_u1 : 10; /* [19..10] */ -+ unsigned int v0_rim_y1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_rimcol1; -+ -+/* define the union reg_v1_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_ctrl; -+ -+/* define the union reg_v1_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef00; -+ -+/* define the union reg_v1_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef01; -+ -+/* define the union reg_v1_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef02; -+ -+/* define the union reg_v1_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef10; -+ -+/* define the union reg_v1_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef11; -+ -+/* define the union reg_v1_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef12; -+ -+/* define the union reg_v1_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef20; -+ -+/* define the union reg_v1_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef21; -+ -+/* define the union reg_v1_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_coef22; -+ -+/* define the union reg_v1_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_scale; -+ -+/* define the union reg_v1_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_idc0; -+ -+/* define the union reg_v1_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_idc1; -+ -+/* define the union reg_v1_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_idc2; -+ -+/* define the union reg_v1_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_odc0; -+ -+/* define the union reg_v1_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_odc1; -+ -+/* define the union reg_v1_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_odc2; -+ -+/* define the union reg_v1_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_min_y; -+ -+/* define the union reg_v1_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_min_c; -+ -+/* define the union reg_v1_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_max_y; -+ -+/* define the union reg_v1_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_max_c; -+ -+/* define the union reg_v1_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef00; -+ -+/* define the union reg_v1_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef01; -+ -+/* define the union reg_v1_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef02; -+ -+/* define the union reg_v1_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef10; -+ -+/* define the union reg_v1_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef11; -+ -+/* define the union reg_v1_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef12; -+ -+/* define the union reg_v1_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef20; -+ -+/* define the union reg_v1_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef21; -+ -+/* define the union reg_v1_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_coef22; -+ -+/* define the union reg_v1_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_scale; -+ -+/* define the union reg_v1_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_idc0; -+ -+/* define the union reg_v1_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_idc1; -+ -+/* define the union reg_v1_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_idc2; -+ -+/* define the union reg_v1_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_odc0; -+ -+/* define the union reg_v1_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_odc1; -+ -+/* define the union reg_v1_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_odc2; -+ -+/* define the union reg_v1_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_min_y; -+ -+/* define the union reg_v1_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_min_c; -+ -+/* define the union reg_v1_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_max_y; -+ -+/* define the union reg_v1_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc2_max_c; -+ -+/* define the union reg_v1_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_v1_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_ot_pp_csc_ink_pos; -+ -+/* define the union reg_v1_cvfir_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_vinfo; -+ -+/* define the union reg_v1_cvfir_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_vsp; -+ -+/* define the union reg_v1_cvfir_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_voffset; -+ -+/* define the union reg_v1_cvfir_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_vboffset; -+ -+/* define the union reg_v1_cvfir_vcoef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_vcoef0; -+ -+/* define the union reg_v1_cvfir_vcoef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_vcoef1; -+ -+/* define the union reg_v1_cvfir_vcoef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_cvfir_vcoef2; -+ -+/* define the union reg_v1_hfir_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_hfir_ctrl; -+ -+/* define the union reg_v1_hfircoef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_hfircoef01; -+ -+/* define the union reg_v1_hfircoef23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_hfircoef23; -+ -+/* define the union reg_v1_hfircoef45 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_hfircoef45; -+ -+/* define the union reg_v1_hfircoef67 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_hfircoef67; -+ -+/* define the union reg_v2_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ctrl; -+ -+/* define the union reg_v2_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_upd; -+ -+/* define the union reg_v2_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_0reso_read; -+ -+/* define the union reg_v2_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ireso; -+ -+/* define the union reg_v2_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_dfpos; -+ -+/* define the union reg_v2_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_dlpos; -+ -+/* define the union reg_v2_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_vfpos; -+ -+/* define the union reg_v2_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_vlpos; -+ -+/* define the union reg_v2_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_bk; -+ -+/* define the union reg_v2_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_alpha; -+ -+/* define the union reg_v2_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_mute_bk; -+ -+/* define the union reg_v2_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_ctrl; -+ -+/* define the union reg_v2_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef00; -+ -+/* define the union reg_v2_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef01; -+ -+/* define the union reg_v2_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef02; -+ -+/* define the union reg_v2_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef10; -+ -+/* define the union reg_v2_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef11; -+ -+/* define the union reg_v2_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef12; -+ -+/* define the union reg_v2_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef20; -+ -+/* define the union reg_v2_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef21; -+ -+/* define the union reg_v2_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_coef22; -+ -+/* define the union reg_v2_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_scale; -+ -+/* define the union reg_v2_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_idc0; -+ -+/* define the union reg_v2_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_idc1; -+ -+/* define the union reg_v2_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_idc2; -+ -+/* define the union reg_v2_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_odc0; -+ -+/* define the union reg_v2_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_odc1; -+ -+/* define the union reg_v2_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_odc2; -+ -+/* define the union reg_v2_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_min_y; -+ -+/* define the union reg_v2_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_min_c; -+ -+/* define the union reg_v2_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_max_y; -+ -+/* define the union reg_v2_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_max_c; -+ -+/* define the union reg_v2_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef00; -+ -+/* define the union reg_v2_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef01; -+ -+/* define the union reg_v2_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef02; -+ -+/* define the union reg_v2_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef10; -+ -+/* define the union reg_v2_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef11; -+ -+/* define the union reg_v2_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef12; -+ -+/* define the union reg_v2_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef20; -+ -+/* define the union reg_v2_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef21; -+ -+/* define the union reg_v2_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_coef22; -+ -+/* define the union reg_v2_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_scale; -+ -+/* define the union reg_v2_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_idc0; -+ -+/* define the union reg_v2_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_idc1; -+ -+/* define the union reg_v2_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_idc2; -+ -+/* define the union reg_v2_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_odc0; -+ -+/* define the union reg_v2_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_odc1; -+ -+/* define the union reg_v2_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_odc2; -+ -+/* define the union reg_v2_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_min_y; -+ -+/* define the union reg_v2_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_min_c; -+ -+/* define the union reg_v2_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_max_y; -+ -+/* define the union reg_v2_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc2_max_c; -+ -+/* define the union reg_v2_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_v2_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_ot_pp_csc_ink_pos; -+ -+/* define the union reg_v2_cvfir_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_vinfo; -+ -+/* define the union reg_v2_cvfir_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_vsp; -+ -+/* define the union reg_v2_cvfir_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_voffset; -+ -+/* define the union reg_v2_cvfir_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_vboffset; -+ -+/* define the union reg_v2_cvfir_vcoef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_vcoef0; -+ -+/* define the union reg_v2_cvfir_vcoef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_vcoef1; -+ -+/* define the union reg_v2_cvfir_vcoef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_cvfir_vcoef2; -+ -+/* define the union reg_v2_hfir_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_hfir_ctrl; -+ -+/* define the union reg_v2_hfircoef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_hfircoef01; -+ -+/* define the union reg_v2_hfircoef23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_hfircoef23; -+ -+/* define the union reg_v2_hfircoef45 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_hfircoef45; -+ -+/* define the union reg_v2_hfircoef67 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_hfircoef67; -+ -+/* define the union reg_v3_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 20; /* [27..8] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ctrl; -+ -+/* define the union reg_v3_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_upd; -+ -+/* define the union reg_v3_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_0reso_read; -+ -+/* define the union reg_v3_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ireso; -+ -+/* define the union reg_v3_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_dfpos; -+ -+/* define the union reg_v3_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_dlpos; -+ -+/* define the union reg_v3_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_vfpos; -+ -+/* define the union reg_v3_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_vlpos; -+ -+/* define the union reg_v3_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_bk; -+ -+/* define the union reg_v3_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_alpha; -+ -+/* define the union reg_v3_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_mute_bk; -+ -+/* define the union reg_v3_rimwidth */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_width : 5; /* [4..0] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_rimwidth; -+ -+/* define the union reg_v3_rimcol0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_v0 : 10; /* [9..0] */ -+ unsigned int v0_rim_u0 : 10; /* [19..10] */ -+ unsigned int v0_rim_y0 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_rimcol0; -+ -+/* define the union reg_v3_rimcol1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v0_rim_v1 : 10; /* [9..0] */ -+ unsigned int v0_rim_u1 : 10; /* [19..10] */ -+ unsigned int v0_rim_y1 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_rimcol1; -+ -+/* define the union reg_v3_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_ctrl; -+ -+/* define the union reg_v3_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef00; -+ -+/* define the union reg_v3_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef01; -+ -+/* define the union reg_v3_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef02; -+ -+/* define the union reg_v3_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef10; -+ -+/* define the union reg_v3_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef11; -+ -+/* define the union reg_v3_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef12; -+ -+/* define the union reg_v3_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef20; -+ -+/* define the union reg_v3_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef21; -+ -+/* define the union reg_v3_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_coef22; -+ -+/* define the union reg_v3_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_scale; -+ -+/* define the union reg_v3_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_idc0; -+ -+/* define the union reg_v3_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_idc1; -+ -+/* define the union reg_v3_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_idc2; -+ -+/* define the union reg_v3_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_odc0; -+ -+/* define the union reg_v3_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_odc1; -+ -+/* define the union reg_v3_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_odc2; -+ -+/* define the union reg_v3_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_min_y; -+ -+/* define the union reg_v3_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_min_c; -+ -+/* define the union reg_v3_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_max_y; -+ -+/* define the union reg_v3_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_max_c; -+ -+/* define the union reg_v3_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef00; -+ -+/* define the union reg_v3_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef01; -+ -+/* define the union reg_v3_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef02; -+ -+/* define the union reg_v3_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef10; -+ -+/* define the union reg_v3_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef11; -+ -+/* define the union reg_v3_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef12; -+ -+/* define the union reg_v3_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef20; -+ -+/* define the union reg_v3_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef21; -+ -+/* define the union reg_v3_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_coef22; -+ -+/* define the union reg_v3_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_scale; -+ -+/* define the union reg_v3_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_idc0; -+ -+/* define the union reg_v3_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_idc1; -+ -+/* define the union reg_v3_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_idc2; -+ -+/* define the union reg_v3_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_odc0; -+ -+/* define the union reg_v3_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_odc1; -+ -+/* define the union reg_v3_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_odc2; -+ -+/* define the union reg_v3_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_min_y; -+ -+/* define the union reg_v3_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_min_c; -+ -+/* define the union reg_v3_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_max_y; -+ -+/* define the union reg_v3_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc2_max_c; -+ -+/* define the union reg_v3_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_v3_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_ot_pp_csc_ink_pos; -+ -+/* define the union reg_v3_cvfir_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_vinfo; -+ -+/* define the union reg_v3_cvfir_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int reserved_2 : 1; /* [26] */ -+ unsigned int reserved_3 : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int reserved_4 : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int reserved_5 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_vsp; -+ -+/* define the union reg_v3_cvfir_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_voffset; -+ -+/* define the union reg_v3_cvfir_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_vboffset; -+ -+/* define the union reg_v3_cvfir_vcoef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef02 : 10; /* [9..0] */ -+ unsigned int vccoef01 : 10; /* [19..10] */ -+ unsigned int vccoef00 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_vcoef0; -+ -+/* define the union reg_v3_cvfir_vcoef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef11 : 10; /* [9..0] */ -+ unsigned int vccoef10 : 10; /* [19..10] */ -+ unsigned int vccoef03 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_vcoef1; -+ -+/* define the union reg_v3_cvfir_vcoef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vccoef13 : 10; /* [9..0] */ -+ unsigned int vccoef12 : 10; /* [19..10] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_cvfir_vcoef2; -+ -+/* define the union reg_v3_hfir_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_1 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_hfir_ctrl; -+ -+/* define the union reg_v3_hfircoef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_hfircoef01; -+ -+/* define the union reg_v3_hfircoef23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_hfircoef23; -+ -+/* define the union reg_v3_hfircoef45 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_hfircoef45; -+ -+/* define the union reg_v3_hfircoef67 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef7 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v3_hfircoef67; -+ -+/* define the union reg_vp0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_upd; -+ -+/* define the union reg_vp0_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_ireso; -+ -+/* define the union reg_vp0_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_lbox_ctrl; -+ -+/* define the union reg_vp0_galpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_galpha; -+ -+/* define the union reg_vp0_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 12; /* [11..0] */ -+ unsigned int disp_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_dfpos; -+ -+/* define the union reg_vp0_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 12; /* [11..0] */ -+ unsigned int disp_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_dlpos; -+ -+/* define the union reg_vp0_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 12; /* [11..0] */ -+ unsigned int video_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_vfpos; -+ -+/* define the union reg_vp0_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 12; /* [11..0] */ -+ unsigned int video_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_vlpos; -+ -+/* define the union reg_vp0_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_bk; -+ -+/* define the union reg_vp0_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_alpha; -+ -+/* define the union reg_vp0_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vp0_mute_bk; -+ -+/* define the union reg_g0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g0_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ctrl; -+ -+/* define the union reg_g0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_upd; -+ -+/* define the union reg_g0_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_0reso_read; -+ -+/* define the union reg_g0_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ireso; -+ -+/* define the union reg_g0_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_dfpos; -+ -+/* define the union reg_g0_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_dlpos; -+ -+/* define the union reg_g0_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_vfpos; -+ -+/* define the union reg_g0_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_vlpos; -+ -+/* define the union reg_g0_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_bk; -+ -+/* define the union reg_g0_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_alpha; -+ -+/* define the union reg_g0_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_mute_bk; -+ -+/* define the union reg_g0_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_lbox_ctrl; -+ -+/* define the union reg_g0_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_ctrl; -+ -+/* define the union reg_g0_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef00; -+ -+/* define the union reg_g0_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef01; -+ -+/* define the union reg_g0_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef02; -+ -+/* define the union reg_g0_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef10; -+ -+/* define the union reg_g0_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef11; -+ -+/* define the union reg_g0_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef12; -+ -+/* define the union reg_g0_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef20; -+ -+/* define the union reg_g0_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef21; -+ -+/* define the union reg_g0_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_coef22; -+ -+/* define the union reg_g0_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_scale; -+ -+/* define the union reg_g0_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_idc0; -+ -+/* define the union reg_g0_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_idc1; -+ -+/* define the union reg_g0_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_idc2; -+ -+/* define the union reg_g0_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_odc0; -+ -+/* define the union reg_g0_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_odc1; -+ -+/* define the union reg_g0_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_odc2; -+ -+/* define the union reg_g0_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_min_y; -+ -+/* define the union reg_g0_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_min_c; -+ -+/* define the union reg_g0_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_max_y; -+ -+/* define the union reg_g0_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_max_c; -+ -+/* define the union reg_g0_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef00; -+ -+/* define the union reg_g0_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef01; -+ -+/* define the union reg_g0_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef02; -+ -+/* define the union reg_g0_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef10; -+ -+/* define the union reg_g0_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef11; -+ -+/* define the union reg_g0_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef12; -+ -+/* define the union reg_g0_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef20; -+ -+/* define the union reg_g0_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef21; -+ -+/* define the union reg_g0_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_coef22; -+ -+/* define the union reg_g0_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_scale; -+ -+/* define the union reg_g0_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_idc0; -+ -+/* define the union reg_g0_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_idc1; -+ -+/* define the union reg_g0_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_idc2; -+ -+/* define the union reg_g0_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_odc0; -+ -+/* define the union reg_g0_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_odc1; -+ -+/* define the union reg_g0_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_odc2; -+ -+/* define the union reg_g0_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_min_y; -+ -+/* define the union reg_g0_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_min_c; -+ -+/* define the union reg_g0_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_max_y; -+ -+/* define the union reg_g0_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc2_max_c; -+ -+/* define the union reg_g0_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_g0_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_ot_pp_csc_ink_pos; -+ -+/* define the union reg_osb_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_v : 10; /* [9..0] */ -+ unsigned int osb_bk_u : 10; /* [19..10] */ -+ unsigned int osb_bk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int osb_mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_osb_mute_bk; -+ -+/* define the union reg_osb_bk_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_osb_bk_alpha; -+ -+/* define the union reg_osb_coef_rd_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_osb_coef_rd_en; -+ -+/* define the union reg_g0_zme_hinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_hinfo; -+ -+/* define the union reg_g0_zme_hsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int ahfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int chfir_mid_en : 1; /* [28] */ -+ unsigned int lhfir_mid_en : 1; /* [29] */ -+ unsigned int ahfir_mid_en : 1; /* [30] */ -+ unsigned int hfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_hsp; -+ -+/* define the union reg_g0_zme_hloffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_hloffset; -+ -+/* define the union reg_g0_zme_hcoffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_hcoffset; -+ -+/* define the union reg_g0_zme_coef_ren */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int apb_g0_vf_lren : 1; /* [1] */ -+ unsigned int reserved_1 : 1; /* [2] */ -+ unsigned int apb_g0_hf_lren : 1; /* [3] */ -+ unsigned int reserved_2 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_coef_ren; -+ -+/* define the union reg_g0_zme_coef_rdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_coef_rdata; -+ -+/* define the union reg_g0_zme_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int reserved_0 : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_vinfo; -+ -+/* define the union reg_g0_zme_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 9; /* [24..16] */ -+ unsigned int vafir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int reserved_1 : 1; /* [27] */ -+ unsigned int cvfir_mid_en : 1; /* [28] */ -+ unsigned int lvfir_mid_en : 1; /* [29] */ -+ unsigned int avfir_mid_en : 1; /* [30] */ -+ unsigned int vfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_vsp; -+ -+/* define the union reg_g0_zme_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbtm_offset : 16; /* [15..0] */ -+ unsigned int vtp_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g0_zme_voffset; -+ -+/* define the union reg_g1_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ctrl; -+ -+/* define the union reg_g1_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_upd; -+ -+/* define the union reg_g1_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_0reso_read; -+ -+/* define the union reg_g1_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ireso; -+ -+/* define the union reg_g1_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_dfpos; -+ -+/* define the union reg_g1_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_dlpos; -+ -+/* define the union reg_g1_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_vfpos; -+ -+/* define the union reg_g1_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_vlpos; -+ -+/* define the union reg_g1_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_bk; -+ -+/* define the union reg_g1_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_alpha; -+ -+/* define the union reg_g1_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_mute_bk; -+ -+/* define the union reg_g1_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_lbox_ctrl; -+ -+/* define the union reg_g1_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_ctrl; -+ -+/* define the union reg_g1_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef00; -+ -+/* define the union reg_g1_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef01; -+ -+/* define the union reg_g1_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef02; -+ -+/* define the union reg_g1_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef10; -+ -+/* define the union reg_g1_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef11; -+ -+/* define the union reg_g1_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef12; -+ -+/* define the union reg_g1_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef20; -+ -+/* define the union reg_g1_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef21; -+ -+/* define the union reg_g1_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_coef22; -+ -+/* define the union reg_g1_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_scale; -+ -+/* define the union reg_g1_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_idc0; -+ -+/* define the union reg_g1_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_idc1; -+ -+/* define the union reg_g1_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_idc2; -+ -+/* define the union reg_g1_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_odc0; -+ -+/* define the union reg_g1_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_odc1; -+ -+/* define the union reg_g1_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_odc2; -+ -+/* define the union reg_g1_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_min_y; -+ -+/* define the union reg_g1_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_min_c; -+ -+/* define the union reg_g1_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_max_y; -+ -+/* define the union reg_g1_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_max_c; -+ -+/* define the union reg_g1_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef00; -+ -+/* define the union reg_g1_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef01; -+ -+/* define the union reg_g1_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef02; -+ -+/* define the union reg_g1_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef10; -+ -+/* define the union reg_g1_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef11; -+ -+/* define the union reg_g1_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef12; -+ -+/* define the union reg_g1_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef20; -+ -+/* define the union reg_g1_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef21; -+ -+/* define the union reg_g1_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_coef22; -+ -+/* define the union reg_g1_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_scale; -+ -+/* define the union reg_g1_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_idc0; -+ -+/* define the union reg_g1_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_idc1; -+ -+/* define the union reg_g1_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_idc2; -+ -+/* define the union reg_g1_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_odc0; -+ -+/* define the union reg_g1_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_odc1; -+ -+/* define the union reg_g1_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_odc2; -+ -+/* define the union reg_g1_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_min_y; -+ -+/* define the union reg_g1_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_min_c; -+ -+/* define the union reg_g1_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_max_y; -+ -+/* define the union reg_g1_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc2_max_c; -+ -+/* define the union reg_g1_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_g1_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_ot_pp_csc_ink_pos; -+ -+/* define the union reg_g1_osb_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_v : 10; /* [9..0] */ -+ unsigned int osb_bk_u : 10; /* [19..10] */ -+ unsigned int osb_bk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int osb_mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_osb_mute_bk; -+ -+/* define the union reg_g1_osb_bk_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_osb_bk_alpha; -+ -+/* define the union reg_g1_osb_coef_rd_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_osb_coef_rd_en; -+ -+/* define the union reg_g1_zme_hinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_hinfo; -+ -+/* define the union reg_g1_zme_hsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int ahfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int chfir_mid_en : 1; /* [28] */ -+ unsigned int lhfir_mid_en : 1; /* [29] */ -+ unsigned int ahfir_mid_en : 1; /* [30] */ -+ unsigned int hfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_hsp; -+ -+/* define the union reg_g1_zme_hloffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_hloffset; -+ -+/* define the union reg_g1_zme_hcoffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 24; /* [23..0] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_hcoffset; -+ -+/* define the union reg_g1_zme_coef_ren */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int apb_g1_vf_lren : 1; /* [1] */ -+ unsigned int reserved_1 : 1; /* [2] */ -+ unsigned int apb_g1_hf_lren : 1; /* [3] */ -+ unsigned int reserved_2 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_coef_ren; -+ -+/* define the union reg_g1_zme_coef_rdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_coef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_coef_rdata; -+ -+/* define the union reg_g1_zme_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int reserved_0 : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_vinfo; -+ -+/* define the union reg_g1_zme_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 9; /* [24..16] */ -+ unsigned int vafir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int reserved_1 : 1; /* [27] */ -+ unsigned int cvfir_mid_en : 1; /* [28] */ -+ unsigned int lvfir_mid_en : 1; /* [29] */ -+ unsigned int avfir_mid_en : 1; /* [30] */ -+ unsigned int vfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_vsp; -+ -+/* define the union reg_g1_zme_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbtm_offset : 16; /* [15..0] */ -+ unsigned int vtp_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_zme_voffset; -+ -+/* define the union reg_g2_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ctrl; -+ -+/* define the union reg_g2_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_upd; -+ -+/* define the union reg_g2_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_0reso_read; -+ -+/* define the union reg_g2_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ireso; -+ -+/* define the union reg_g2_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_dfpos; -+ -+/* define the union reg_g2_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_dlpos; -+ -+/* define the union reg_g2_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_vfpos; -+ -+/* define the union reg_g2_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_vlpos; -+ -+/* define the union reg_g2_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_bk; -+ -+/* define the union reg_g2_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_alpha; -+ -+/* define the union reg_g2_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_mute_bk; -+ -+/* define the union reg_g2_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_lbox_ctrl; -+ -+/* define the union reg_g2_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_ctrl; -+ -+/* define the union reg_g2_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef00; -+ -+/* define the union reg_g2_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef01; -+ -+/* define the union reg_g2_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef02; -+ -+/* define the union reg_g2_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef10; -+ -+/* define the union reg_g2_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef11; -+ -+/* define the union reg_g2_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef12; -+ -+/* define the union reg_g2_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef20; -+ -+/* define the union reg_g2_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef21; -+ -+/* define the union reg_g2_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_coef22; -+ -+/* define the union reg_g2_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_scale; -+ -+/* define the union reg_g2_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_idc0; -+ -+/* define the union reg_g2_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_idc1; -+ -+/* define the union reg_g2_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_idc2; -+ -+/* define the union reg_g2_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_odc0; -+ -+/* define the union reg_g2_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_odc1; -+ -+/* define the union reg_g2_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_odc2; -+ -+/* define the union reg_g2_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_min_y; -+ -+/* define the union reg_g2_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_min_c; -+ -+/* define the union reg_g2_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_max_y; -+ -+/* define the union reg_g2_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_max_c; -+ -+/* define the union reg_g2_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef00; -+ -+/* define the union reg_g2_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef01; -+ -+/* define the union reg_g2_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef02; -+ -+/* define the union reg_g2_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef10; -+ -+/* define the union reg_g2_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef11; -+ -+/* define the union reg_g2_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef12; -+ -+/* define the union reg_g2_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef20; -+ -+/* define the union reg_g2_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef21; -+ -+/* define the union reg_g2_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_coef22; -+ -+/* define the union reg_g2_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_scale; -+ -+/* define the union reg_g2_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_idc0; -+ -+/* define the union reg_g2_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_idc1; -+ -+/* define the union reg_g2_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_idc2; -+ -+/* define the union reg_g2_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_odc0; -+ -+/* define the union reg_g2_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_odc1; -+ -+/* define the union reg_g2_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_odc2; -+ -+/* define the union reg_g2_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_min_y; -+ -+/* define the union reg_g2_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_min_c; -+ -+/* define the union reg_g2_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_max_y; -+ -+/* define the union reg_g2_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc2_max_c; -+ -+/* define the union reg_g2_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_g2_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g2_ot_pp_csc_ink_pos; -+ -+/* define the union reg_g3_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ctrl; -+ -+/* define the union reg_g3_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_upd; -+ -+/* define the union reg_g3_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_0reso_read; -+ -+/* define the union reg_g3_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ireso; -+ -+/* define the union reg_g3_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_dfpos; -+ -+/* define the union reg_g3_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_dlpos; -+ -+/* define the union reg_g3_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_vfpos; -+ -+/* define the union reg_g3_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_vlpos; -+ -+/* define the union reg_g3_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_bk; -+ -+/* define the union reg_g3_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_alpha; -+ -+/* define the union reg_g3_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_mute_bk; -+ -+/* define the union reg_g3_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_lbox_ctrl; -+ -+/* define the union reg_g3_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_ctrl; -+ -+/* define the union reg_g3_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef00; -+ -+/* define the union reg_g3_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef01; -+ -+/* define the union reg_g3_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef02; -+ -+/* define the union reg_g3_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef10; -+ -+/* define the union reg_g3_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef11; -+ -+/* define the union reg_g3_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef12; -+ -+/* define the union reg_g3_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef20; -+ -+/* define the union reg_g3_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef21; -+ -+/* define the union reg_g3_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_coef22; -+ -+/* define the union reg_g3_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_scale; -+ -+/* define the union reg_g3_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_idc0; -+ -+/* define the union reg_g3_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_idc1; -+ -+/* define the union reg_g3_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_idc2; -+ -+/* define the union reg_g3_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_odc0; -+ -+/* define the union reg_g3_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_odc1; -+ -+/* define the union reg_g3_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_odc2; -+ -+/* define the union reg_g3_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_min_y; -+ -+/* define the union reg_g3_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_min_c; -+ -+/* define the union reg_g3_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_max_y; -+ -+/* define the union reg_g3_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_max_c; -+ -+/* define the union reg_g3_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef00; -+ -+/* define the union reg_g3_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef01; -+ -+/* define the union reg_g3_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef02; -+ -+/* define the union reg_g3_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef10; -+ -+/* define the union reg_g3_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef11; -+ -+/* define the union reg_g3_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef12; -+ -+/* define the union reg_g3_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef20; -+ -+/* define the union reg_g3_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef21; -+ -+/* define the union reg_g3_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_coef22; -+ -+/* define the union reg_g3_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_scale; -+ -+/* define the union reg_g3_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_idc0; -+ -+/* define the union reg_g3_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_idc1; -+ -+/* define the union reg_g3_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_idc2; -+ -+/* define the union reg_g3_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_odc0; -+ -+/* define the union reg_g3_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_odc1; -+ -+/* define the union reg_g3_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_odc2; -+ -+/* define the union reg_g3_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_min_y; -+ -+/* define the union reg_g3_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_min_c; -+ -+/* define the union reg_g3_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_max_y; -+ -+/* define the union reg_g3_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc2_max_c; -+ -+/* define the union reg_g3_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_g3_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_ot_pp_csc_ink_pos; -+ -+/* define the union reg_g3_osb_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_v : 10; /* [9..0] */ -+ unsigned int osb_bk_u : 10; /* [19..10] */ -+ unsigned int osb_bk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int osb_mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_osb_mute_bk; -+ -+/* define the union reg_g3_osb_bk_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_osb_bk_alpha; -+ -+/* define the union reg_g3_osb_coef_rd_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_osb_coef_rd_en; -+ -+/* define the union reg_g4_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 19; /* [26..8] */ -+ unsigned int g1_depremult : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int surface_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ctrl; -+ -+/* define the union reg_g4_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_upd; -+ -+/* define the union reg_g4_0reso_read */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_0reso_read; -+ -+/* define the union reg_g4_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ireso; -+ -+/* define the union reg_g4_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 16; /* [15..0] */ -+ unsigned int disp_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_dfpos; -+ -+/* define the union reg_g4_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 16; /* [15..0] */ -+ unsigned int disp_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_dlpos; -+ -+/* define the union reg_g4_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 16; /* [15..0] */ -+ unsigned int video_yfpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_vfpos; -+ -+/* define the union reg_g4_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 16; /* [15..0] */ -+ unsigned int video_ylpos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_vlpos; -+ -+/* define the union reg_g4_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_bk; -+ -+/* define the union reg_g4_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_alpha; -+ -+/* define the union reg_g4_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_mute_bk; -+ -+/* define the union reg_g4_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_lbox_ctrl; -+ -+/* define the union reg_g4_ot_pp_csc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_en : 1; /* [0] */ -+ unsigned int ot_pp_csc_demo_en : 1; /* [1] */ -+ unsigned int ot_pp_csc_ck_gt_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_ctrl; -+ -+/* define the union reg_g4_ot_pp_csc_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef00 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef00; -+ -+/* define the union reg_g4_ot_pp_csc_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef01 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef01; -+ -+/* define the union reg_g4_ot_pp_csc_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef02 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef02; -+ -+/* define the union reg_g4_ot_pp_csc_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef10 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef10; -+ -+/* define the union reg_g4_ot_pp_csc_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef11 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef11; -+ -+/* define the union reg_g4_ot_pp_csc_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef12 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef12; -+ -+/* define the union reg_g4_ot_pp_csc_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef20 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef20; -+ -+/* define the union reg_g4_ot_pp_csc_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef21 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef21; -+ -+/* define the union reg_g4_ot_pp_csc_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_coef22 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_coef22; -+ -+/* define the union reg_g4_ot_pp_csc_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_scale; -+ -+/* define the union reg_g4_ot_pp_csc_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_idc0; -+ -+/* define the union reg_g4_ot_pp_csc_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_idc1; -+ -+/* define the union reg_g4_ot_pp_csc_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_idc2; -+ -+/* define the union reg_g4_ot_pp_csc_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_odc0; -+ -+/* define the union reg_g4_ot_pp_csc_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_odc1; -+ -+/* define the union reg_g4_ot_pp_csc_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_odc2; -+ -+/* define the union reg_g4_ot_pp_csc_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_min_y; -+ -+/* define the union reg_g4_ot_pp_csc_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_min_c; -+ -+/* define the union reg_g4_ot_pp_csc_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_max_y; -+ -+/* define the union reg_g4_ot_pp_csc_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_max_c; -+ -+/* define the union reg_g4_ot_pp_csc2_coef00 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef00 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef00; -+ -+/* define the union reg_g4_ot_pp_csc2_coef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef01 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef01; -+ -+/* define the union reg_g4_ot_pp_csc2_coef02 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef02 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef02; -+ -+/* define the union reg_g4_ot_pp_csc2_coef10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef10 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef10; -+ -+/* define the union reg_g4_ot_pp_csc2_coef11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef11 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef11; -+ -+/* define the union reg_g4_ot_pp_csc2_coef12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef12 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef12; -+ -+/* define the union reg_g4_ot_pp_csc2_coef20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef20 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef20; -+ -+/* define the union reg_g4_ot_pp_csc2_coef21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef21 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef21; -+ -+/* define the union reg_g4_ot_pp_csc2_coef22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_coef22 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_coef22; -+ -+/* define the union reg_g4_ot_pp_csc2_scale */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_scale : 4; /* [3..0] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_scale; -+ -+/* define the union reg_g4_ot_pp_csc2_idc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_idc0; -+ -+/* define the union reg_g4_ot_pp_csc2_idc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_idc1; -+ -+/* define the union reg_g4_ot_pp_csc2_idc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_idc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_idc2; -+ -+/* define the union reg_g4_ot_pp_csc2_odc0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_odc0; -+ -+/* define the union reg_g4_ot_pp_csc2_odc1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_odc1; -+ -+/* define the union reg_g4_ot_pp_csc2_odc2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_odc2 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_odc2; -+ -+/* define the union reg_g4_ot_pp_csc2_min_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_min_y; -+ -+/* define the union reg_g4_ot_pp_csc2_min_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_min_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_min_c; -+ -+/* define the union reg_g4_ot_pp_csc2_max_y */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_max_y; -+ -+/* define the union reg_g4_ot_pp_csc2_max_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ot_pp_csc2_max_c : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc2_max_c; -+ -+/* define the union reg_g4_ot_pp_csc_ink_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ink_en : 1; /* [0] */ -+ unsigned int ink_sel : 1; /* [1] */ -+ unsigned int data_fmt : 1; /* [2] */ -+ unsigned int cross_enable : 1; /* [3] */ -+ unsigned int color_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_ink_ctrl; -+ -+/* define the union reg_g4_ot_pp_csc_ink_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_pos : 16; /* [15..0] */ -+ unsigned int y_pos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_ot_pp_csc_ink_pos; -+ -+/* define the union reg_g4_osb_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_v : 10; /* [9..0] */ -+ unsigned int osb_bk_u : 10; /* [19..10] */ -+ unsigned int osb_bk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int osb_mute_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_osb_mute_bk; -+ -+/* define the union reg_g4_osb_bk_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_bk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_osb_bk_alpha; -+ -+/* define the union reg_g4_osb_coef_rd_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int osb_rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_osb_coef_rd_en; -+ -+/* define the union reg_gp0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_upd; -+ -+/* define the union reg_gp0_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int iw : 16; /* [15..0] */ -+ unsigned int ih : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_ireso; -+ -+/* define the union reg_gp0_lbox_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_lbox_ctrl; -+ -+/* define the union reg_gp0_galpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int galpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_galpha; -+ -+/* define the union reg_gp0_dfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xfpos : 12; /* [11..0] */ -+ unsigned int disp_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_dfpos; -+ -+/* define the union reg_gp0_dlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int disp_xlpos : 12; /* [11..0] */ -+ unsigned int disp_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_dlpos; -+ -+/* define the union reg_gp0_vfpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xfpos : 12; /* [11..0] */ -+ unsigned int video_yfpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_vfpos; -+ -+/* define the union reg_gp0_vlpos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_xlpos : 12; /* [11..0] */ -+ unsigned int video_ylpos : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_vlpos; -+ -+/* define the union reg_gp0_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_cr : 10; /* [9..0] */ -+ unsigned int vbk_cb : 10; /* [19..10] */ -+ unsigned int vbk_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_bk; -+ -+/* define the union reg_gp0_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbk_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_alpha; -+ -+/* define the union reg_gp0_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_mute_bk; -+ -+/* define the union reg_gp0_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_idc; -+ -+/* define the union reg_gp0_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_odc; -+ -+/* define the union reg_gp0_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_iodc; -+ -+/* define the union reg_gp0_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_p0; -+ -+/* define the union reg_gp0_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_p1; -+ -+/* define the union reg_gp0_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_p2; -+ -+/* define the union reg_gp0_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_p3; -+ -+/* define the union reg_gp0_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gp0_csc_p4; -+ -+/* define the union reg_wbc_g0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int auto_stop_en : 1; /* [10] */ -+ unsigned int reserved_0 : 15; /* [25..11] */ -+ unsigned int format_out : 2; /* [27..26] */ -+ unsigned int reserved_1 : 3; /* [30..28] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_ctrl; -+ -+/* define the union reg_wbc_g0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_upd; -+ -+/* define the union reg_wbc_g0_cmp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cmp_lossy_en : 1; /* [0] */ -+ unsigned int reserved_0 : 3; /* [3..1] */ -+ unsigned int cmp_drr : 4; /* [7..4] */ -+ unsigned int reserved_1 : 23; /* [30..8] */ -+ unsigned int cmp_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_cmp; -+ -+/* define the union reg_wbc_g0_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbcstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_stride; -+ -+/* define the union reg_wbc_g0_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_oreso; -+ -+/* define the union reg_wbc_g0_fcrop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wfcrop : 12; /* [11..0] */ -+ unsigned int hfcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_fcrop; -+ -+/* define the union reg_wbc_g0_lcrop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wlcrop : 12; /* [11..0] */ -+ unsigned int hlcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_g0_lcrop; -+ -+/* define the union reg_wbc_gp0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int auto_stop_en : 1; /* [10] */ -+ unsigned int reserved_0 : 1; /* [11] */ -+ unsigned int wbc_vtthd_mode : 1; /* [12] */ -+ unsigned int reserved_1 : 5; /* [17..13] */ -+ unsigned int three_d_mode : 2; /* [19..18] */ -+ unsigned int reserved_2 : 3; /* [22..20] */ -+ unsigned int flip_en : 1; /* [23] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int mode_out : 2; /* [29..28] */ -+ unsigned int reserved_3 : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_ctrl; -+ -+/* define the union reg_wbc_gp0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_upd; -+ -+/* define the union reg_wbc_gp0_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbclstride : 16; /* [15..0] */ -+ unsigned int wbccstride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_stride; -+ -+/* define the union reg_wbc_gp0_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_oreso; -+ -+/* define the union reg_wbc_gp0_fcrop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wfcrop : 12; /* [11..0] */ -+ unsigned int hfcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_fcrop; -+ -+/* define the union reg_wbc_gp0_lcrop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wlcrop : 12; /* [11..0] */ -+ unsigned int hlcrop : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_lcrop; -+ -+/* define the union reg_wbc_gp0_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int dither_round : 1; /* [29] */ -+ unsigned int dither_mode : 1; /* [30] */ -+ unsigned int dither_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_dither_ctrl; -+ -+/* define the union reg_wbc_gp0_dither_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_coef0 : 8; /* [7..0] */ -+ unsigned int dither_coef1 : 8; /* [15..8] */ -+ unsigned int dither_coef2 : 8; /* [23..16] */ -+ unsigned int dither_coef3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_dither_coef0; -+ -+/* define the union reg_wbc_gp0_dither_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_coef4 : 8; /* [7..0] */ -+ unsigned int dither_coef5 : 8; /* [15..8] */ -+ unsigned int dither_coef6 : 8; /* [23..16] */ -+ unsigned int dither_coef7 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_dither_coef1; -+ -+/* define the union reg_wbc_gp0_hpzme */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int hpzme_mode : 1; /* [29] */ -+ unsigned int hpzme_mid_en : 1; /* [30] */ -+ unsigned int hpzme_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_gp0_hpzme; -+ -+/* define the union reg_wbc_me_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 10; /* [19..10] */ -+ unsigned int ofl_master : 1; /* [20] */ -+ unsigned int reserved_1 : 2; /* [22..21] */ -+ unsigned int mad_data_mode : 1; /* [23] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int reserved_2 : 1; /* [28] */ -+ unsigned int c_wbc_en : 1; /* [29] */ -+ unsigned int reserved_3 : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_ctrl; -+ -+/* define the union reg_wbc_me_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_upd; -+ -+/* define the union reg_wbc_me_wlen_sel */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wlen_sel : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_wlen_sel; -+ -+/* define the union reg_wbc_me_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbclstride : 16; /* [15..0] */ -+ unsigned int wbccstride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_stride; -+ -+/* define the union reg_wbc_me_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_oreso; -+ -+/* define the union reg_wbc_me_smmu_bypass */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int l_bypass : 1; /* [0] */ -+ unsigned int c_bypass : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_smmu_bypass; -+ -+/* define the union reg_wbc_me_paraup */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_hlcoef_upd : 1; /* [0] */ -+ unsigned int wbc_hccoef_upd : 1; /* [1] */ -+ unsigned int wbc_vlcoef_upd : 1; /* [2] */ -+ unsigned int wbc_vccoef_upd : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_paraup; -+ -+/* define the union reg_wbc_me_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int dither_round : 1; /* [29] */ -+ unsigned int dither_mode : 1; /* [30] */ -+ unsigned int dither_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_dither_ctrl; -+ -+/* define the union reg_wbc_me_dither_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_coef0 : 8; /* [7..0] */ -+ unsigned int dither_coef1 : 8; /* [15..8] */ -+ unsigned int dither_coef2 : 8; /* [23..16] */ -+ unsigned int dither_coef3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_dither_coef0; -+ -+/* define the union reg_wbc_me_dither_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_coef4 : 8; /* [7..0] */ -+ unsigned int dither_coef5 : 8; /* [15..8] */ -+ unsigned int dither_coef6 : 8; /* [23..16] */ -+ unsigned int dither_coef7 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_dither_coef1; -+ -+/* define the union reg_wbc_me_zme_hsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int hchfir_en : 1; /* [25] */ -+ unsigned int hlfir_en : 1; /* [26] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int hchmid_en : 1; /* [28] */ -+ unsigned int hlmid_en : 1; /* [29] */ -+ unsigned int hchmsc_en : 1; /* [30] */ -+ unsigned int hlmsc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_hsp; -+ -+/* define the union reg_wbc_me_zme_hloffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hor_loffset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_hloffset; -+ -+/* define the union reg_wbc_me_zme_hcoffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hor_coffset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_hcoffset; -+ -+/* define the union reg_wbc_me_zme_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 19; /* [18..0] */ -+ unsigned int zme_in_fmt : 2; /* [20..19] */ -+ unsigned int zme_out_fmt : 2; /* [22..21] */ -+ unsigned int vchfir_en : 1; /* [23] */ -+ unsigned int vlfir_en : 1; /* [24] */ -+ unsigned int reserved_1 : 3; /* [27..25] */ -+ unsigned int vchmid_en : 1; /* [28] */ -+ unsigned int vlmid_en : 1; /* [29] */ -+ unsigned int vchmsc_en : 1; /* [30] */ -+ unsigned int vlmsc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_vsp; -+ -+/* define the union reg_wbc_me_zme_vsr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_vsr; -+ -+/* define the union reg_wbc_me_zme_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int vluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_voffset; -+ -+/* define the union reg_wbc_me_zme_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int vbluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_me_zme_vboffset; -+ -+/* define the union reg_wbc_fi_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 3; /* [12..10] */ -+ unsigned int addr_mode : 1; /* [13] */ -+ unsigned int fsize_mode : 1; /* [14] */ -+ unsigned int tnr_nrds_en : 1; /* [15] */ -+ unsigned int reserved_1 : 4; /* [19..16] */ -+ unsigned int ofl_master : 1; /* [20] */ -+ unsigned int data_width : 1; /* [21] */ -+ unsigned int reserved_2 : 2; /* [23..22] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int reserved_3 : 2; /* [29..28] */ -+ unsigned int cmp_en : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_ctrl; -+ -+/* define the union reg_wbc_fi_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_upd; -+ -+/* define the union reg_wbc_fi_wlen_sel */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wlen_sel : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_wlen_sel; -+ -+/* define the union reg_wbc_fi_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbclstride : 16; /* [15..0] */ -+ unsigned int wbccstride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_stride; -+ -+/* define the union reg_wbc_fi_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_oreso; -+ -+/* define the union reg_wbc_fi_smmu_bypass */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int l_bypass : 1; /* [0] */ -+ unsigned int c_bypass : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_smmu_bypass; -+ -+/* define the union reg_wbc_fi_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_size : 23; /* [22..0] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_frame_size; -+ -+/* define the union reg_wbc_fi_hcds */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 29; /* [28..0] */ -+ unsigned int hchfir_en : 1; /* [29] */ -+ unsigned int hchmid_en : 1; /* [30] */ -+ unsigned int hcds_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_hcds; -+ -+/* define the union reg_wbc_fi_hcds_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int coef1 : 10; /* [19..10] */ -+ unsigned int coef2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_hcds_coef0; -+ -+/* define the union reg_wbc_fi_hcds_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef3 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_hcds_coef1; -+ -+/* define the union reg_wbc_fi_cmp_mb */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mb_bits : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_mb; -+ -+/* define the union reg_wbc_fi_cmp_max_min */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int min_bits_cnt : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int max_bits_cnt : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_max_min; -+ -+/* define the union reg_wbc_fi_cmp_adj_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int adj_sad_thr : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int adj_sad_bit_thr : 8; /* [23..16] */ -+ unsigned int adj_spec_bit_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_adj_thr; -+ -+/* define the union reg_wbc_fi_cmp_big_grad */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int big_grad_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int big_grad_num_thr : 5; /* [12..8] */ -+ unsigned int reserved_1 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_big_grad; -+ -+/* define the union reg_wbc_fi_cmp_blk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smth_thr : 6; /* [5..0] */ -+ unsigned int reserved_0 : 2; /* [7..6] */ -+ unsigned int blk_comp_thr : 3; /* [10..8] */ -+ unsigned int reserved_1 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_blk; -+ -+/* define the union reg_wbc_fi_cmp_graphic_judge */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int graphic_en : 1; /* [0] */ -+ unsigned int reserved_0 : 15; /* [15..1] */ -+ unsigned int video_sad_thr : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_graphic_judge; -+ -+/* define the union reg_wbc_fi_cmp_rc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int sadbits_ngain : 3; /* [2..0] */ -+ unsigned int reserved_0 : 5; /* [7..3] */ -+ unsigned int rc_smth_gain : 3; /* [10..8] */ -+ unsigned int reserved_1 : 5; /* [15..11] */ -+ unsigned int max_trow_bits : 6; /* [21..16] */ -+ unsigned int reserved_2 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_rc; -+ -+/* define the union reg_wbc_fi_cmp_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_size : 21; /* [20..0] */ -+ unsigned int reserved_0 : 11; /* [31..21] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_fi_cmp_frame_size; -+ -+/* define the union reg_wbc_cmp_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int is_lossless : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int dw_mode : 1; /* [2] */ -+ unsigned int sep_cmp_en : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_glb_info; -+ -+/* define the union reg_wbc_cmp_framesize */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int frame_height : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_framesize; -+ -+/* define the union reg_wbc_cmp_rc_cfg0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mb_bits_y : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int min_mb_bits_y : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg0; -+ -+/* define the union reg_wbc_cmp_rc_cfg2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_qp_y : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int sad_bits_ngain : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int rc_smth_ngain : 3; /* [18..16] */ -+ unsigned int reserved_2 : 5; /* [23..19] */ -+ unsigned int max_trow_bits : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg2; -+ -+/* define the union reg_wbc_cmp_rc_cfg3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_sad_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int min_sad_thr : 7; /* [22..16] */ -+ unsigned int reserved_1 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg3; -+ -+/* define the union reg_wbc_cmp_rc_cfg4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smth_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int still_thr : 7; /* [14..8] */ -+ unsigned int reserved_1 : 1; /* [15] */ -+ unsigned int big_grad_thr : 10; /* [25..16] */ -+ unsigned int reserved_2 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg4; -+ -+/* define the union reg_wbc_cmp_rc_cfg5 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smth_pix_num_thr : 6; /* [5..0] */ -+ unsigned int reserved_0 : 2; /* [7..6] */ -+ unsigned int still_pix_num_thr : 6; /* [13..8] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_2 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg5; -+ -+/* define the union reg_wbc_cmp_rc_cfg6 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int noise_sad : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int pix_diff_thr : 9; /* [24..16] */ -+ unsigned int reserved_1 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg6; -+ -+/* define the union reg_wbc_cmp_rc_cfg7 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg7; -+ -+/* define the union reg_wbc_cmp_rc_cfg8 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr_y : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr_y : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr_y : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr_y : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg8; -+ -+/* define the union reg_wbc_cmp_rc_cfg10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int est_err_gain : 5; /* [4..0] */ -+ unsigned int reserved_0 : 11; /* [15..5] */ -+ unsigned int max_est_err_level : 9; /* [24..16] */ -+ unsigned int max_vbv_buf_loss_thr : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_rc_cfg10; -+ -+/* define the union reg_wbc_cmp_outsize0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_size0_reg : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_outsize0; -+ -+/* define the union reg_wbc_cmp_max_row */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_size1_reg : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_max_row; -+ -+/* define the union reg_wbc_bmp_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 10; /* [19..10] */ -+ unsigned int ofl_master : 1; /* [20] */ -+ unsigned int data_width : 1; /* [21] */ -+ unsigned int reserved_1 : 2; /* [23..22] */ -+ unsigned int format_out : 4; /* [27..24] */ -+ unsigned int reserved_2 : 3; /* [30..28] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_bmp_ctrl; -+ -+/* define the union reg_wbc_bmp_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_bmp_upd; -+ -+/* define the union reg_wbc_bmp_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_bmp_oreso; -+ -+/* define the union reg_wbc_bmp_sum */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bmp_sum : 25; /* [24..0] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_bmp_sum; -+ -+/* define the union reg_wbc_dhd0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int p2i_en : 1; /* [0] */ -+ unsigned int root_path : 2; /* [2..1] */ -+ unsigned int reserved_0 : 19; /* [21..3] */ -+ unsigned int mode_out : 2; /* [23..22] */ -+ unsigned int three_d_mode : 2; /* [25..24] */ -+ unsigned int auto_stop_en : 1; /* [26] */ -+ unsigned int wbc_vtthd_mode : 1; /* [27] */ -+ unsigned int rupd_field : 1; /* [28] */ -+ unsigned int rgup_mode : 1; /* [29] */ -+ unsigned int nosec_flag : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_dhd0_ctrl; -+ -+/* define the union reg_wbc_dhd0_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_dhd0_upd; -+ -+/* define the union reg_wbc_dhd0_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 16; /* [15..0] */ -+ unsigned int oh : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_dhd0_oreso; -+ -+/* define the union reg_wd_hpzme_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_en : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hpzme_ctrl; -+ -+/* define the union reg_wd_hpzmecoef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hpzmecoef01; -+ -+/* define the union reg_wd_hpzmecoef23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hpzmecoef23; -+ -+/* define the union reg_wd_hpzmecoef45 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hpzmecoef45; -+ -+/* define the union reg_wd_hpzmecoef67 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hpzmecoef67; -+ -+/* define the union reg_wd_hcds_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_en : 1; /* [0] */ -+ unsigned int hfir_mode : 2; /* [2..1] */ -+ unsigned int mid_en : 1; /* [3] */ -+ unsigned int ck_gt_en : 1; /* [4] */ -+ unsigned int reserved_0 : 27; /* [31..5] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hcds_ctrl; -+ -+/* define the union reg_wd_hcdscoef01 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hcdscoef01; -+ -+/* define the union reg_wd_hcdscoef23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hcdscoef23; -+ -+/* define the union reg_wd_hcdscoef45 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hcdscoef45; -+ -+/* define the union reg_wd_hcdscoef67 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 10; /* [9..0] */ -+ unsigned int reserved_1 : 6; /* [15..10] */ -+ unsigned int reserved_2 : 10; /* [25..16] */ -+ unsigned int reserved_3 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_hcdscoef67; -+ -+/* define the union reg_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_ctrl; -+ -+/* define the union reg_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_y0; -+ -+/* define the union reg_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_u0; -+ -+/* define the union reg_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_v0; -+ -+/* define the union reg_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_w0; -+ -+/* define the union reg_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_y1; -+ -+/* define the union reg_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_u1; -+ -+/* define the union reg_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_v1; -+ -+/* define the union reg_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_w1; -+ -+/* define the union reg_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_y2; -+ -+/* define the union reg_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_u2; -+ -+/* define the union reg_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_v2; -+ -+/* define the union reg_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_w2; -+ -+/* define the union reg_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_y3; -+ -+/* define the union reg_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_u3; -+ -+/* define the union reg_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_v3; -+ -+/* define the union reg_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_sed_w3; -+ -+/* define the union reg_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dither_thr; -+ -+/* define the union reg_wd_zme_hinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int hzme_ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hinfo; -+ -+/* define the union reg_wd_zme_hsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int chfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int non_lnr_en : 1; /* [27] */ -+ unsigned int chmid_en : 1; /* [28] */ -+ unsigned int lhmid_en : 1; /* [29] */ -+ unsigned int chfir_en : 1; /* [30] */ -+ unsigned int lhfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hsp; -+ -+/* define the union reg_wd_zme_hloffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hloffset; -+ -+/* define the union reg_wd_zme_hcoffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hcoffset; -+ -+/* define the union reg_wd_zme_hcoef_ren */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_hf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hcoef_ren; -+ -+/* define the union reg_wd_zme_hcoef_rdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hcoef_rdata; -+ -+/* define the union reg_wd_zme_hdraw */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hdraw_mode : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hdraw; -+ -+/* define the union reg_wd_zme_hratio */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hratio : 27; /* [26..0] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_hratio; -+ -+/* define the union reg_wd_zme_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vinfo; -+ -+/* define the union reg_wd_zme_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 16; /* [15..0] */ -+ unsigned int graphdet_en : 1; /* [16] */ -+ unsigned int reserved_1 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int vfir_1tap_en : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int lvmid_en : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int lvfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vsp; -+ -+/* define the union reg_wd_zme_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int vluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_voffset; -+ -+/* define the union reg_wd_zme_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int vbluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vboffset; -+ -+/* define the union reg_wd_zme_vcoef_ren */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_vf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vcoef_ren; -+ -+/* define the union reg_wd_zme_vcoef_rdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vcoef_rdata; -+ -+/* define the union reg_wd_zme_vdraw */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vdraw_mode : 2; /* [1..0] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vdraw; -+ -+/* define the union reg_wd_zme_vratio */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 19; /* [18..0] */ -+ unsigned int reserved_0 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wd_zme_vratio; -+ -+/* define the union reg_dhd0_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int disp_mode : 3; /* [3..1] */ -+ unsigned int iop : 1; /* [4] */ -+ unsigned int intf_ivs : 1; /* [5] */ -+ unsigned int intf_ihs : 1; /* [6] */ -+ unsigned int intf_idv : 1; /* [7] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int hdmi420c_sel : 1; /* [9] */ -+ unsigned int hdmi420_en : 1; /* [10] */ -+ unsigned int uf_offline_en : 1; /* [11] */ -+ unsigned int reserved_1 : 2; /* [13..12] */ -+ unsigned int hdmi_mode : 1; /* [14] */ -+ unsigned int twochn_debug : 1; /* [15] */ -+ unsigned int twochn_en : 1; /* [16] */ -+ unsigned int reserved_2 : 1; /* [17] */ -+ unsigned int cbar_mode : 1; /* [18] */ -+ unsigned int sin_en : 1; /* [19] */ -+ unsigned int fpga_lmt_width : 7; /* [26..20] */ -+ unsigned int fpga_lmt_en : 1; /* [27] */ -+ unsigned int p2i_en : 1; /* [28] */ -+ unsigned int cbar_sel : 1; /* [29] */ -+ unsigned int cbar_en : 1; /* [30] */ -+ unsigned int intf_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ctrl; -+ -+/* define the union reg_dhd0_vsync1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vact : 16; /* [15..0] */ -+ unsigned int vbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vsync1; -+ -+/* define the union reg_dhd0_vsync2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vsync2; -+ -+/* define the union reg_dhd0_hsync1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hact : 16; /* [15..0] */ -+ unsigned int hbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_hsync1; -+ -+/* define the union reg_dhd0_hsync2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfb : 16; /* [15..0] */ -+ unsigned int hmid : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_hsync2; -+ -+/* define the union reg_dhd0_vplus1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvact : 16; /* [15..0] */ -+ unsigned int bvbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vplus1; -+ -+/* define the union reg_dhd0_vplus2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vplus2; -+ -+/* define the union reg_dhd0_pwr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hpw : 16; /* [15..0] */ -+ unsigned int vpw : 8; /* [23..16] */ -+ unsigned int reserved_0 : 3; /* [26..24] */ -+ unsigned int multichn_en : 2; /* [28..27] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_pwr; -+ -+/* define the union reg_dhd0_vtthd3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vtmgthd3 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd3_mode : 1; /* [15] */ -+ unsigned int vtmgthd4 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd4_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vtthd3; -+ -+/* define the union reg_dhd0_vtthd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vtmgthd1 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd1_mode : 1; /* [15] */ -+ unsigned int vtmgthd2 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd2_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vtthd; -+ -+/* define the union reg_dhd0_parathd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int dfs_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_parathd; -+ -+/* define the union reg_dhd0_precharge_thd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tcon_precharge_thd : 17; /* [16..0] */ -+ unsigned int reserved_0 : 3; /* [19..17] */ -+ unsigned int vsync_te_mode : 1; /* [20] */ -+ unsigned int reserved_1 : 10; /* [30..21] */ -+ unsigned int dneed_en_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_precharge_thd; -+ -+/* define the union reg_dhd0_start_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int start_pos : 8; /* [7..0] */ -+ unsigned int timing_start_pos : 8; /* [15..8] */ -+ unsigned int fi_start_pos : 4; /* [19..16] */ -+ unsigned int req_start_pos : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_start_pos; -+ -+/* define the union reg_dhd0_start_pos1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_start_pos1 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_start_pos1; -+ -+/* define the union reg_dhd0_paraup */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int paraup_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_paraup; -+ -+/* define the union reg_dhd0_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lcd_dv_inv : 1; /* [0] */ -+ unsigned int lcd_hs_inv : 1; /* [1] */ -+ unsigned int lcd_vs_inv : 1; /* [2] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int vga_dv_inv : 1; /* [4] */ -+ unsigned int vga_hs_inv : 1; /* [5] */ -+ unsigned int vga_vs_inv : 1; /* [6] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int hdmi_dv_inv : 1; /* [8] */ -+ unsigned int hdmi_hs_inv : 1; /* [9] */ -+ unsigned int hdmi_vs_inv : 1; /* [10] */ -+ unsigned int hdmi_f_inv : 1; /* [11] */ -+ unsigned int date_dv_inv : 1; /* [12] */ -+ unsigned int date_hs_inv : 1; /* [13] */ -+ unsigned int date_vs_inv : 1; /* [14] */ -+ unsigned int date_f_inv : 1; /* [15] */ -+ unsigned int reserved_2 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_sync_inv; -+ -+/* define the union reg_dhd0_clk_dv_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_clk_mux : 1; /* [0] */ -+ unsigned int intf_dv_mux : 1; /* [1] */ -+ unsigned int no_active_area_pos : 16; /* [17..2] */ -+ unsigned int reserved_0 : 14; /* [31..18] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_clk_dv_ctrl; -+ -+/* define the union reg_dhd0_rgb_fix_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fix_b : 10; /* [9..0] */ -+ unsigned int fix_g : 10; /* [19..10] */ -+ unsigned int fix_r : 10; /* [29..20] */ -+ unsigned int rgb_fix_mux : 1; /* [30] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_rgb_fix_ctrl; -+ -+/* define the union reg_dhd0_lockcfg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int measure_en : 1; /* [0] */ -+ unsigned int lock_cnt_en : 1; /* [1] */ -+ unsigned int vdp_measure_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_lockcfg; -+ -+/* define the union reg_dhd0_intf_chksum_high1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int r0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_intf_chksum_high1; -+ -+/* define the union reg_dhd0_intf_chksum_high2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int r1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_intf_chksum_high2; -+ -+/* define the union reg_dhd0_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vback_blank : 1; /* [0] */ -+ unsigned int vblank : 1; /* [1] */ -+ unsigned int bottom_field : 1; /* [2] */ -+ unsigned int vcnt : 13; /* [15..3] */ -+ unsigned int count_int : 8; /* [23..16] */ -+ unsigned int dhd_even : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_state; -+ -+/* define the union reg_dhd0_uf_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ud_first_cnt : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int start_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_uf_state; -+ -+/* define the union reg_vo_mux */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mipi_sel : 4; /* [3..0] */ -+ unsigned int lcd_sel : 4; /* [7..4] */ -+ unsigned int bt_sel : 4; /* [11..8] */ -+ unsigned int sddate_sel : 4; /* [15..12] */ -+ unsigned int hdmi_sel : 4; /* [19..16] */ -+ unsigned int hdmi1_sel : 4; /* [23..20] */ -+ unsigned int vga_sel : 4; /* [27..24] */ -+ unsigned int digital_sel : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_mux; -+ -+/* define the union reg_vo_mux_sync */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int sync_dv : 1; /* [0] */ -+ unsigned int sync_hsync : 1; /* [1] */ -+ unsigned int sync_vsync : 1; /* [2] */ -+ unsigned int sync_field : 1; /* [3] */ -+ unsigned int reserved_0 : 27; /* [30..4] */ -+ unsigned int sync_test_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_mux_sync; -+ -+/* define the union reg_vo_mux_data */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vomux_data : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vo_mux_data; -+ -+/* define the union reg_dhd0_vsync_te_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vsync_te_start_sta : 8; /* [7..0] */ -+ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ -+ unsigned int vsync_te_end_sta : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vsync_te_state; -+ -+/* define the union reg_dhd0_vsync_te_state1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vsync_te_vfb : 16; /* [15..0] */ -+ unsigned int vsync_te_width : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_vsync_te_state1; -+ -+/* define the union reg_dhd0_ccdoimgmod */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int img_mode : 7; /* [6..0] */ -+ unsigned int img_right : 1; /* [7] */ -+ unsigned int img_id : 2; /* [9..8] */ -+ unsigned int slave_mode : 1; /* [10] */ -+ unsigned int ccd_en : 1; /* [11] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int vbi_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ccdoimgmod; -+ -+/* define the union reg_dhd0_ccdoposmskh */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int p32_en : 1; /* [0] */ -+ unsigned int p33_en : 1; /* [1] */ -+ unsigned int p34_en : 1; /* [2] */ -+ unsigned int p35_en : 1; /* [3] */ -+ unsigned int p36_en : 1; /* [4] */ -+ unsigned int p37_en : 1; /* [5] */ -+ unsigned int p38_en : 1; /* [6] */ -+ unsigned int p39_en : 1; /* [7] */ -+ unsigned int p40_en : 1; /* [8] */ -+ unsigned int p41_en : 1; /* [9] */ -+ unsigned int p42_en : 1; /* [10] */ -+ unsigned int p43_en : 1; /* [11] */ -+ unsigned int p44_en : 1; /* [12] */ -+ unsigned int p45_en : 1; /* [13] */ -+ unsigned int p46_en : 1; /* [14] */ -+ unsigned int p47_en : 1; /* [15] */ -+ unsigned int p48_en : 1; /* [16] */ -+ unsigned int p49_en : 1; /* [17] */ -+ unsigned int p50_en : 1; /* [18] */ -+ unsigned int p51_en : 1; /* [19] */ -+ unsigned int p52_en : 1; /* [20] */ -+ unsigned int p53_en : 1; /* [21] */ -+ unsigned int p54_en : 1; /* [22] */ -+ unsigned int p55_en : 1; /* [23] */ -+ unsigned int p56_en : 1; /* [24] */ -+ unsigned int p57_en : 1; /* [25] */ -+ unsigned int p58_en : 1; /* [26] */ -+ unsigned int p59_en : 1; /* [27] */ -+ unsigned int p60_en : 1; /* [28] */ -+ unsigned int p61_en : 1; /* [29] */ -+ unsigned int p62_en : 1; /* [30] */ -+ unsigned int p63_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ccdoposmskh; -+ -+/* define the union reg_dhd0_ccdoposmskl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int p0_en : 1; /* [0] */ -+ unsigned int p1_en : 1; /* [1] */ -+ unsigned int p2_en : 1; /* [2] */ -+ unsigned int p3_en : 1; /* [3] */ -+ unsigned int p4_en : 1; /* [4] */ -+ unsigned int p5_en : 1; /* [5] */ -+ unsigned int p6_en : 1; /* [6] */ -+ unsigned int p7_en : 1; /* [7] */ -+ unsigned int p8_en : 1; /* [8] */ -+ unsigned int p9_en : 1; /* [9] */ -+ unsigned int p10_en : 1; /* [10] */ -+ unsigned int p11_en : 1; /* [11] */ -+ unsigned int p12_en : 1; /* [12] */ -+ unsigned int p13_en : 1; /* [13] */ -+ unsigned int p14_en : 1; /* [14] */ -+ unsigned int p15_en : 1; /* [15] */ -+ unsigned int p16_en : 1; /* [16] */ -+ unsigned int p17_en : 1; /* [17] */ -+ unsigned int p18_en : 1; /* [18] */ -+ unsigned int p19_en : 1; /* [19] */ -+ unsigned int p20_en : 1; /* [20] */ -+ unsigned int p21_en : 1; /* [21] */ -+ unsigned int p22_en : 1; /* [22] */ -+ unsigned int p23_en : 1; /* [23] */ -+ unsigned int p24_en : 1; /* [24] */ -+ unsigned int p25_en : 1; /* [25] */ -+ unsigned int p26_en : 1; /* [26] */ -+ unsigned int p27_en : 1; /* [27] */ -+ unsigned int p28_en : 1; /* [28] */ -+ unsigned int p29_en : 1; /* [29] */ -+ unsigned int p30_en : 1; /* [30] */ -+ unsigned int p31_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ccdoposmskl; -+ -+/* define the union reg_dhd0_dacdet1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vdac_det_high : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int det_line : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_dacdet1; -+ -+/* define the union reg_dhd0_dacdet2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int det_pixel_sta : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int det_pixel_wid : 11; /* [26..16] */ -+ unsigned int reserved_1 : 4; /* [30..27] */ -+ unsigned int vdac_det_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_dacdet2; -+ -+/* define the union reg_dhd0_ccd_info1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int img_mode : 7; /* [6..0] */ -+ unsigned int img_right : 1; /* [7] */ -+ unsigned int img_id : 2; /* [9..8] */ -+ unsigned int reserved_0 : 1; /* [10] */ -+ unsigned int ccd_en : 1; /* [11] */ -+ unsigned int reserved_1 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ccd_info1; -+ -+/* define the union reg_dhd0_ccd_info2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int p32_en : 1; /* [0] */ -+ unsigned int p33_en : 1; /* [1] */ -+ unsigned int p34_en : 1; /* [2] */ -+ unsigned int p35_en : 1; /* [3] */ -+ unsigned int p36_en : 1; /* [4] */ -+ unsigned int p37_en : 1; /* [5] */ -+ unsigned int p38_en : 1; /* [6] */ -+ unsigned int p39_en : 1; /* [7] */ -+ unsigned int p40_en : 1; /* [8] */ -+ unsigned int p41_en : 1; /* [9] */ -+ unsigned int p42_en : 1; /* [10] */ -+ unsigned int p43_en : 1; /* [11] */ -+ unsigned int p44_en : 1; /* [12] */ -+ unsigned int p45_en : 1; /* [13] */ -+ unsigned int p46_en : 1; /* [14] */ -+ unsigned int p47_en : 1; /* [15] */ -+ unsigned int p48_en : 1; /* [16] */ -+ unsigned int p49_en : 1; /* [17] */ -+ unsigned int p50_en : 1; /* [18] */ -+ unsigned int p51_en : 1; /* [19] */ -+ unsigned int p52_en : 1; /* [20] */ -+ unsigned int p53_en : 1; /* [21] */ -+ unsigned int p54_en : 1; /* [22] */ -+ unsigned int p55_en : 1; /* [23] */ -+ unsigned int p56_en : 1; /* [24] */ -+ unsigned int p57_en : 1; /* [25] */ -+ unsigned int p58_en : 1; /* [26] */ -+ unsigned int p59_en : 1; /* [27] */ -+ unsigned int p60_en : 1; /* [28] */ -+ unsigned int p61_en : 1; /* [29] */ -+ unsigned int p62_en : 1; /* [30] */ -+ unsigned int p63_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ccd_info2; -+ -+/* define the union reg_dhd0_ccd_info3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int p0_en : 1; /* [0] */ -+ unsigned int p1_en : 1; /* [1] */ -+ unsigned int p2_en : 1; /* [2] */ -+ unsigned int p3_en : 1; /* [3] */ -+ unsigned int p4_en : 1; /* [4] */ -+ unsigned int p5_en : 1; /* [5] */ -+ unsigned int p6_en : 1; /* [6] */ -+ unsigned int p7_en : 1; /* [7] */ -+ unsigned int p8_en : 1; /* [8] */ -+ unsigned int p9_en : 1; /* [9] */ -+ unsigned int p10_en : 1; /* [10] */ -+ unsigned int p11_en : 1; /* [11] */ -+ unsigned int p12_en : 1; /* [12] */ -+ unsigned int p13_en : 1; /* [13] */ -+ unsigned int p14_en : 1; /* [14] */ -+ unsigned int p15_en : 1; /* [15] */ -+ unsigned int p16_en : 1; /* [16] */ -+ unsigned int p17_en : 1; /* [17] */ -+ unsigned int p18_en : 1; /* [18] */ -+ unsigned int p19_en : 1; /* [19] */ -+ unsigned int p20_en : 1; /* [20] */ -+ unsigned int p21_en : 1; /* [21] */ -+ unsigned int p22_en : 1; /* [22] */ -+ unsigned int p23_en : 1; /* [23] */ -+ unsigned int p24_en : 1; /* [24] */ -+ unsigned int p25_en : 1; /* [25] */ -+ unsigned int p26_en : 1; /* [26] */ -+ unsigned int p27_en : 1; /* [27] */ -+ unsigned int p28_en : 1; /* [28] */ -+ unsigned int p29_en : 1; /* [29] */ -+ unsigned int p30_en : 1; /* [30] */ -+ unsigned int p31_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd0_ccd_info3; -+ -+/* define the union reg_intf_hdmi_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int hdmi_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_hdmi_ctrl; -+ -+/* define the union reg_intf_hdmi_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_hdmi_upd; -+ -+/* define the union reg_intf_hdmi_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_hdmi_sync_inv; -+ -+/* define the union reg_hdmi_intf_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int r0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_intf_chksum_high; -+ -+/* define the union reg_hdmi_intf1_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int r1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_intf1_chksum_high; -+ -+/* define the union reg_hdmi_hfir_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_hfir_coef0; -+ -+/* define the union reg_hdmi_hfir_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_hfir_coef1; -+ -+/* define the union reg_hdmi_hfir_coef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_hfir_coef2; -+ -+/* define the union reg_hdmi_hfir_coef3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_hfir_coef3; -+ -+/* define the union reg_hdmi_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_idc; -+ -+/* define the union reg_hdmi_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_odc; -+ -+/* define the union reg_hdmi_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_iodc; -+ -+/* define the union reg_hdmi_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_p0; -+ -+/* define the union reg_hdmi_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_p1; -+ -+/* define the union reg_hdmi_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_p2; -+ -+/* define the union reg_hdmi_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_p3; -+ -+/* define the union reg_hdmi_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi_csc_p4; -+ -+/* define the union reg_intf_mipi_del_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_mipi_del_ctrl; -+ -+/* define the union reg_intf_mipi_del_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_mipi_del_upd; -+ -+/* define the union reg_intf_mipi_del_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_mipi_del_sync_inv; -+ -+/* define the union reg_mipi_del_intf_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int b0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int r0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_intf_chksum_high; -+ -+/* define the union reg_mipi_del_intf1_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int b1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int r1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_intf1_chksum_high; -+ -+/* define the union reg_mipi_del_hfir_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_hfir_coef0; -+ -+/* define the union reg_mipi_del_hfir_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_hfir_coef1; -+ -+/* define the union reg_mipi_del_hfir_coef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_hfir_coef2; -+ -+/* define the union reg_mipi_del_hfir_coef3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_hfir_coef3; -+ -+/* define the union reg_mipi_del_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_idc; -+ -+/* define the union reg_mipi_del_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_odc; -+ -+/* define the union reg_mipi_del_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_iodc; -+ -+/* define the union reg_mipi_del_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_p0; -+ -+/* define the union reg_mipi_del_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_p1; -+ -+/* define the union reg_mipi_del_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_p2; -+ -+/* define the union reg_mipi_del_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_p3; -+ -+/* define the union reg_mipi_del_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_del_csc_p4; -+ -+/* define the union reg_intf_bt_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 16; /* [15..0] */ -+ unsigned int data_width : 1; /* [16] */ -+ unsigned int bit_inv : 1; /* [17] */ -+ unsigned int uv_mode : 1; /* [18] */ -+ unsigned int yc_mode : 1; /* [19] */ -+ unsigned int reserved_1 : 10; /* [29..20] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_bt_ctrl; -+ -+/* define the union reg_intf_bt_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_bt_upd; -+ -+/* define the union reg_intf_bt_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_bt_sync_inv; -+ -+/* define the union reg_bt_clip0_l */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int clip_cl0 : 10; /* [9..0] */ -+ unsigned int clip_cl1 : 10; /* [19..10] */ -+ unsigned int clip_cl2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int clip_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_clip0_l; -+ -+/* define the union reg_bt_clip0_h */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int clip_ch0 : 10; /* [9..0] */ -+ unsigned int clip_ch1 : 10; /* [19..10] */ -+ unsigned int clip_ch2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_clip0_h; -+ -+/* define the union reg_bt_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_ctrl; -+ -+/* define the union reg_bt_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_y0; -+ -+/* define the union reg_bt_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_u0; -+ -+/* define the union reg_bt_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_v0; -+ -+/* define the union reg_bt_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_w0; -+ -+/* define the union reg_bt_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_y1; -+ -+/* define the union reg_bt_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_u1; -+ -+/* define the union reg_bt_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_v1; -+ -+/* define the union reg_bt_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_w1; -+ -+/* define the union reg_bt_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_y2; -+ -+/* define the union reg_bt_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_u2; -+ -+/* define the union reg_bt_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_v2; -+ -+/* define the union reg_bt_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_w2; -+ -+/* define the union reg_bt_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_y3; -+ -+/* define the union reg_bt_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_u3; -+ -+/* define the union reg_bt_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_v3; -+ -+/* define the union reg_bt_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_sed_w3; -+ -+/* define the union reg_bt_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_bt_dither_thr; -+ -+/* define the union reg_intf_lcd_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 20; /* [19..0] */ -+ unsigned int lcd_format : 4; /* [23..20] */ -+ unsigned int lcd_bit_inv : 1; /* [24] */ -+ unsigned int lcd_comp_order : 1; /* [25] */ -+ unsigned int lcd_serial_perd : 1; /* [26] */ -+ unsigned int reserved_1 : 3; /* [29..27] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_lcd_ctrl; -+ -+/* define the union reg_intf_lcd_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_lcd_upd; -+ -+/* define the union reg_intf_lcd_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_lcd_sync_inv; -+ -+/* define the union reg_lcd_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_idc; -+ -+/* define the union reg_lcd_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_odc; -+ -+/* define the union reg_lcd_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_iodc; -+ -+/* define the union reg_lcd_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_p0; -+ -+/* define the union reg_lcd_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_p1; -+ -+/* define the union reg_lcd_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_p2; -+ -+/* define the union reg_lcd_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_p3; -+ -+/* define the union reg_lcd_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_csc_p4; -+ -+/* define the union reg_lcd_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_ctrl; -+ -+/* define the union reg_lcd_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_y0; -+ -+/* define the union reg_lcd_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_u0; -+ -+/* define the union reg_lcd_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_v0; -+ -+/* define the union reg_lcd_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_w0; -+ -+/* define the union reg_lcd_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_y1; -+ -+/* define the union reg_lcd_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_u1; -+ -+/* define the union reg_lcd_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_v1; -+ -+/* define the union reg_lcd_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_w1; -+ -+/* define the union reg_lcd_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_y2; -+ -+/* define the union reg_lcd_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_u2; -+ -+/* define the union reg_lcd_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_v2; -+ -+/* define the union reg_lcd_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_w2; -+ -+/* define the union reg_lcd_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_y3; -+ -+/* define the union reg_lcd_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_u3; -+ -+/* define the union reg_lcd_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_v3; -+ -+/* define the union reg_lcd_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_sed_w3; -+ -+/* define the union reg_lcd_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_lcd_dither_thr; -+ -+/* define the union reg_intf_hdmi1_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int hdmi_mode : 2; /* [5..4] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_hdmi1_ctrl; -+ -+/* define the union reg_intf_hdmi1_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_hdmi1_upd; -+ -+/* define the union reg_intf_hdmi1_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_hdmi1_sync_inv; -+ -+/* define the union reg_hdmi1_intf_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int r0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi1_intf_chksum_high; -+ -+/* define the union reg_hdmi1_intf1_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int r1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi1_intf1_chksum_high; -+ -+/* define the union reg_hdmi1_hfir_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi1_hfir_coef0; -+ -+/* define the union reg_hdmi1_hfir_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi1_hfir_coef1; -+ -+/* define the union reg_hdmi1_hfir_coef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi1_hfir_coef2; -+ -+/* define the union reg_hdmi1_hfir_coef3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_hdmi1_hfir_coef3; -+ -+/* define the union reg_intf_vga_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 24; /* [23..0] */ -+ unsigned int yc_mode : 1; /* [24] */ -+ unsigned int lcd_parallel_mode : 1; /* [25] */ -+ unsigned int lcd_data_inv : 1; /* [26] */ -+ unsigned int lcd_parallel_order : 1; /* [27] */ -+ unsigned int lcd_serial_perd : 1; /* [28] */ -+ unsigned int lcd_serial_mode : 1; /* [29] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_vga_ctrl; -+ -+/* define the union reg_intf_vga_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_vga_upd; -+ -+/* define the union reg_intf_vga_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_vga_sync_inv; -+ -+/* define the union reg_vga_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_idc; -+ -+/* define the union reg_vga_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_odc; -+ -+/* define the union reg_vga_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_iodc; -+ -+/* define the union reg_vga_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_p0; -+ -+/* define the union reg_vga_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_p1; -+ -+/* define the union reg_vga_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_p2; -+ -+/* define the union reg_vga_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_p3; -+ -+/* define the union reg_vga_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_csc_p4; -+ -+/* define the union reg_vga_hspcfg0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_tmp0 : 8; /* [7..0] */ -+ unsigned int hsp_hf0_tmp1 : 8; /* [15..8] */ -+ unsigned int hsp_hf0_tmp2 : 8; /* [23..16] */ -+ unsigned int hsp_hf0_tmp3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg0; -+ -+/* define the union reg_vga_hspcfg1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_coring : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int hsp_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg1; -+ -+/* define the union reg_vga_hspcfg5 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_gainpos : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int hsp_hf0_gainneg : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg5; -+ -+/* define the union reg_vga_hspcfg6 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf0_overth : 8; /* [7..0] */ -+ unsigned int hsp_hf0_underth : 8; /* [15..8] */ -+ unsigned int hsp_hf0_mixratio : 8; /* [23..16] */ -+ unsigned int reserved_0 : 4; /* [27..24] */ -+ unsigned int hsp_hf0_winsize : 3; /* [30..28] */ -+ unsigned int hsp_hf0_adpshoot_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg6; -+ -+/* define the union reg_vga_hspcfg7 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_tmp0 : 8; /* [7..0] */ -+ unsigned int hsp_hf1_tmp1 : 8; /* [15..8] */ -+ unsigned int hsp_hf1_tmp2 : 8; /* [23..16] */ -+ unsigned int hsp_hf1_tmp3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg7; -+ -+/* define the union reg_vga_hspcfg8 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_coring : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg8; -+ -+/* define the union reg_vga_hspcfg12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_gainpos : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int hsp_hf1_gainneg : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg12; -+ -+/* define the union reg_vga_hspcfg13 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_hf1_overth : 8; /* [7..0] */ -+ unsigned int hsp_hf1_underth : 8; /* [15..8] */ -+ unsigned int hsp_hf1_mixratio : 8; /* [23..16] */ -+ unsigned int reserved_0 : 4; /* [27..24] */ -+ unsigned int hsp_hf1_winsize : 3; /* [30..28] */ -+ unsigned int hsp_hf1_adpshoot_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg13; -+ -+/* define the union reg_vga_hspcfg14 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_cdti_gain : 8; /* [7..0] */ -+ unsigned int hsp_ldti_gain : 8; /* [15..8] */ -+ unsigned int hsp_lti_ratio : 8; /* [23..16] */ -+ unsigned int hsp_hf_shootdiv : 3; /* [26..24] */ -+ unsigned int reserved_0 : 1; /* [27] */ -+ unsigned int hsp_ctih_en : 1; /* [28] */ -+ unsigned int hsp_ltih_en : 1; /* [29] */ -+ unsigned int hsp_h1_en : 1; /* [30] */ -+ unsigned int hsp_h0_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg14; -+ -+/* define the union reg_vga_hspcfg15 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hsp_glb_underth : 9; /* [8..0] */ -+ unsigned int reserved_0 : 1; /* [9] */ -+ unsigned int hsp_glb_overth : 9; /* [18..10] */ -+ unsigned int reserved_1 : 1; /* [19] */ -+ unsigned int hsp_peak_ratio : 8; /* [27..20] */ -+ unsigned int reserved_2 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vga_hspcfg15; -+ -+/* define the union reg_intf_date_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 23; /* [22..0] */ -+ unsigned int uv_mode : 1; /* [23] */ -+ unsigned int yc_mode : 1; /* [24] */ -+ unsigned int lcd_parallel_mode : 1; /* [25] */ -+ unsigned int lcd_data_inv : 1; /* [26] */ -+ unsigned int lcd_parallel_order : 1; /* [27] */ -+ unsigned int lcd_serial_perd : 1; /* [28] */ -+ unsigned int lcd_serial_mode : 1; /* [29] */ -+ unsigned int dfir_en : 1; /* [30] */ -+ unsigned int hdmi_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_date_ctrl; -+ -+/* define the union reg_intf_date_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_date_upd; -+ -+/* define the union reg_intf_date_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_date_sync_inv; -+ -+/* define the union reg_date_clip0_l */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int clip_cl0 : 10; /* [9..0] */ -+ unsigned int clip_cl1 : 10; /* [19..10] */ -+ unsigned int clip_cl2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 1; /* [30] */ -+ unsigned int clip_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_clip0_l; -+ -+/* define the union reg_date_clip0_h */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int clip_ch0 : 10; /* [9..0] */ -+ unsigned int clip_ch1 : 10; /* [19..10] */ -+ unsigned int clip_ch2 : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_clip0_h; -+ -+/* define the union reg_intf0_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_ctrl; -+ -+/* define the union reg_intf0_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_y0; -+ -+/* define the union reg_intf0_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_u0; -+ -+/* define the union reg_intf0_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_v0; -+ -+/* define the union reg_intf0_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_w0; -+ -+/* define the union reg_intf0_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_y1; -+ -+/* define the union reg_intf0_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_u1; -+ -+/* define the union reg_intf0_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_v1; -+ -+/* define the union reg_intf0_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_w1; -+ -+/* define the union reg_intf0_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_y2; -+ -+/* define the union reg_intf0_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_u2; -+ -+/* define the union reg_intf0_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_v2; -+ -+/* define the union reg_intf0_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_w2; -+ -+/* define the union reg_intf0_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_y3; -+ -+/* define the union reg_intf0_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_u3; -+ -+/* define the union reg_intf0_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_v3; -+ -+/* define the union reg_intf0_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_sed_w3; -+ -+/* define the union reg_intf0_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf0_dither_thr; -+ -+/* define the union reg_intf_mipi_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_422_en : 1; /* [0] */ -+ unsigned int intf_420_en : 1; /* [1] */ -+ unsigned int intf_420_mode : 2; /* [3..2] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_mipi_ctrl; -+ -+/* define the union reg_intf_mipi_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_mipi_upd; -+ -+/* define the union reg_intf_mipi_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dv_inv : 1; /* [0] */ -+ unsigned int hs_inv : 1; /* [1] */ -+ unsigned int vs_inv : 1; /* [2] */ -+ unsigned int f_inv : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf_mipi_sync_inv; -+ -+/* define the union reg_mipi_intf_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int b0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int r0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_intf_chksum_high; -+ -+/* define the union reg_mipi_intf1_chksum_high */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int b1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int r1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_intf1_chksum_high; -+ -+/* define the union reg_mipi_hfir_coef0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef0 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef1 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_hfir_coef0; -+ -+/* define the union reg_mipi_hfir_coef1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef2 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef3 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_hfir_coef1; -+ -+/* define the union reg_mipi_hfir_coef2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef4 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int hfir_coef5 : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_hfir_coef2; -+ -+/* define the union reg_mipi_hfir_coef3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfir_coef6 : 10; /* [9..0] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_hfir_coef3; -+ -+/* define the union reg_mipi_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_idc; -+ -+/* define the union reg_mipi_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_odc; -+ -+/* define the union reg_mipi_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_iodc; -+ -+/* define the union reg_mipi_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_p0; -+ -+/* define the union reg_mipi_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_p1; -+ -+/* define the union reg_mipi_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_p2; -+ -+/* define the union reg_mipi_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_p3; -+ -+/* define the union reg_mipi_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_csc_p4; -+ -+/* define the union reg_mipi_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_ctrl; -+ -+/* define the union reg_mipi_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_y0; -+ -+/* define the union reg_mipi_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_u0; -+ -+/* define the union reg_mipi_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_v0; -+ -+/* define the union reg_mipi_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_w0; -+ -+/* define the union reg_mipi_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_y1; -+ -+/* define the union reg_mipi_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_u1; -+ -+/* define the union reg_mipi_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_v1; -+ -+/* define the union reg_mipi_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_w1; -+ -+/* define the union reg_mipi_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_y2; -+ -+/* define the union reg_mipi_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_u2; -+ -+/* define the union reg_mipi_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_v2; -+ -+/* define the union reg_mipi_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_w2; -+ -+/* define the union reg_mipi_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_y3; -+ -+/* define the union reg_mipi_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_u3; -+ -+/* define the union reg_mipi_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_v3; -+ -+/* define the union reg_mipi_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_sed_w3; -+ -+/* define the union reg_mipi_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mipi_dither_thr; -+ -+/* define the union reg_dhd1_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int disp_mode : 3; /* [3..1] */ -+ unsigned int iop : 1; /* [4] */ -+ unsigned int intf_ivs : 1; /* [5] */ -+ unsigned int intf_ihs : 1; /* [6] */ -+ unsigned int intf_idv : 1; /* [7] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int hdmi420c_sel : 1; /* [9] */ -+ unsigned int hdmi420_en : 1; /* [10] */ -+ unsigned int uf_offline_en : 1; /* [11] */ -+ unsigned int reserved_1 : 2; /* [13..12] */ -+ unsigned int hdmi_mode : 1; /* [14] */ -+ unsigned int twochn_debug : 1; /* [15] */ -+ unsigned int twochn_en : 1; /* [16] */ -+ unsigned int reserved_2 : 1; /* [17] */ -+ unsigned int cbar_mode : 1; /* [18] */ -+ unsigned int sin_en : 1; /* [19] */ -+ unsigned int fpga_lmt_width : 7; /* [26..20] */ -+ unsigned int fpga_lmt_en : 1; /* [27] */ -+ unsigned int p2i_en : 1; /* [28] */ -+ unsigned int cbar_sel : 1; /* [29] */ -+ unsigned int cbar_en : 1; /* [30] */ -+ unsigned int intf_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_ctrl; -+ -+/* define the union reg_dhd1_vsync1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vact : 16; /* [15..0] */ -+ unsigned int vbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vsync1; -+ -+/* define the union reg_dhd1_vsync2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vsync2; -+ -+/* define the union reg_dhd1_hsync1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hact : 16; /* [15..0] */ -+ unsigned int hbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_hsync1; -+ -+/* define the union reg_dhd1_hsync2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfb : 16; /* [15..0] */ -+ unsigned int hmid : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_hsync2; -+ -+/* define the union reg_dhd1_vplus1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvact : 16; /* [15..0] */ -+ unsigned int bvbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vplus1; -+ -+/* define the union reg_dhd1_vplus2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vplus2; -+ -+/* define the union reg_dhd1_pwr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hpw : 16; /* [15..0] */ -+ unsigned int vpw : 8; /* [23..16] */ -+ unsigned int reserved_0 : 3; /* [26..24] */ -+ unsigned int multichn_en : 2; /* [28..27] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_pwr; -+ -+/* define the union reg_dhd1_vtthd3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vtmgthd3 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd3_mode : 1; /* [15] */ -+ unsigned int vtmgthd4 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd4_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vtthd3; -+ -+/* define the union reg_dhd1_vtthd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vtmgthd1 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd1_mode : 1; /* [15] */ -+ unsigned int vtmgthd2 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd2_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vtthd; -+ -+/* define the union reg_dhd1_parathd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int dfs_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_parathd; -+ -+/* define the union reg_dhd1_precharge_thd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tcon_precharge_thd : 17; /* [16..0] */ -+ unsigned int reserved_0 : 3; /* [19..17] */ -+ unsigned int vsync_te_mode : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_precharge_thd; -+ -+/* define the union reg_dhd1_start_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int start_pos : 8; /* [7..0] */ -+ unsigned int timing_start_pos : 8; /* [15..8] */ -+ unsigned int fi_start_pos : 4; /* [19..16] */ -+ unsigned int req_start_pos : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_start_pos; -+ -+/* define the union reg_dhd1_start_pos1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_start_pos1 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_start_pos1; -+ -+/* define the union reg_dhd1_paraup */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int paraup_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_paraup; -+ -+/* define the union reg_dhd1_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lcd_dv_inv : 1; /* [0] */ -+ unsigned int lcd_hs_inv : 1; /* [1] */ -+ unsigned int lcd_vs_inv : 1; /* [2] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int vga_dv_inv : 1; /* [4] */ -+ unsigned int vga_hs_inv : 1; /* [5] */ -+ unsigned int vga_vs_inv : 1; /* [6] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int hdmi_dv_inv : 1; /* [8] */ -+ unsigned int hdmi_hs_inv : 1; /* [9] */ -+ unsigned int hdmi_vs_inv : 1; /* [10] */ -+ unsigned int hdmi_f_inv : 1; /* [11] */ -+ unsigned int date_dv_inv : 1; /* [12] */ -+ unsigned int date_hs_inv : 1; /* [13] */ -+ unsigned int date_vs_inv : 1; /* [14] */ -+ unsigned int date_f_inv : 1; /* [15] */ -+ unsigned int reserved_2 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_sync_inv; -+ -+/* define the union reg_dhd1_clk_dv_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_clk_mux : 1; /* [0] */ -+ unsigned int intf_dv_mux : 1; /* [1] */ -+ unsigned int no_active_area_pos : 16; /* [17..2] */ -+ unsigned int reserved_0 : 14; /* [31..18] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_clk_dv_ctrl; -+ -+/* define the union reg_dhd1_rgb_fix_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fix_b : 10; /* [9..0] */ -+ unsigned int fix_g : 10; /* [19..10] */ -+ unsigned int fix_r : 10; /* [29..20] */ -+ unsigned int rgb_fix_mux : 1; /* [30] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_rgb_fix_ctrl; -+ -+/* define the union reg_dhd1_lockcfg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int measure_en : 1; /* [0] */ -+ unsigned int lock_cnt_en : 1; /* [1] */ -+ unsigned int vdp_measure_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_lockcfg; -+ -+/* define the union reg_dhd1_intf_chksum_high1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int y0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_intf_chksum_high1; -+ -+/* define the union reg_dhd1_intf_chksum_high2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int y1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_intf_chksum_high2; -+ -+/* define the union reg_dhd1_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vback_blank : 1; /* [0] */ -+ unsigned int vblank : 1; /* [1] */ -+ unsigned int bottom_field : 1; /* [2] */ -+ unsigned int vcnt : 13; /* [15..3] */ -+ unsigned int count_int : 8; /* [23..16] */ -+ unsigned int dhd_even : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_state; -+ -+/* define the union reg_dhd1_uf_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ud_first_cnt : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int start_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_uf_state; -+ -+/* define the union reg_dhd1_vsync_te_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vsync_te_start_sta : 8; /* [7..0] */ -+ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ -+ unsigned int vsync_te_end_sta : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vsync_te_state; -+ -+/* define the union reg_dhd1_vsync_te_state1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vsync_te_vfb : 16; /* [15..0] */ -+ unsigned int vsync_te_width : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd1_vsync_te_state1; -+ -+/* define the union reg_intf1_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_ctrl; -+ -+/* define the union reg_intf1_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_y0; -+ -+/* define the union reg_intf1_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_u0; -+ -+/* define the union reg_intf1_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_v0; -+ -+/* define the union reg_intf1_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_w0; -+ -+/* define the union reg_intf1_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_y1; -+ -+/* define the union reg_intf1_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_u1; -+ -+/* define the union reg_intf1_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_v1; -+ -+/* define the union reg_intf1_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_w1; -+ -+/* define the union reg_intf1_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_y2; -+ -+/* define the union reg_intf1_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_u2; -+ -+/* define the union reg_intf1_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_v2; -+ -+/* define the union reg_intf1_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_w2; -+ -+/* define the union reg_intf1_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_y3; -+ -+/* define the union reg_intf1_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_u3; -+ -+/* define the union reg_intf1_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_v3; -+ -+/* define the union reg_intf1_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_sed_w3; -+ -+/* define the union reg_intf1_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf1_dither_thr; -+ -+/* define the union reg_dhd2_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int disp_mode : 3; /* [3..1] */ -+ unsigned int iop : 1; /* [4] */ -+ unsigned int intf_ivs : 1; /* [5] */ -+ unsigned int intf_ihs : 1; /* [6] */ -+ unsigned int intf_idv : 1; /* [7] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int hdmi420c_sel : 1; /* [9] */ -+ unsigned int hdmi420_en : 1; /* [10] */ -+ unsigned int uf_offline_en : 1; /* [11] */ -+ unsigned int reserved_1 : 2; /* [13..12] */ -+ unsigned int hdmi_mode : 1; /* [14] */ -+ unsigned int twochn_debug : 1; /* [15] */ -+ unsigned int twochn_en : 1; /* [16] */ -+ unsigned int reserved_2 : 1; /* [17] */ -+ unsigned int cbar_mode : 1; /* [18] */ -+ unsigned int sin_en : 1; /* [19] */ -+ unsigned int fpga_lmt_width : 7; /* [26..20] */ -+ unsigned int fpga_lmt_en : 1; /* [27] */ -+ unsigned int p2i_en : 1; /* [28] */ -+ unsigned int cbar_sel : 1; /* [29] */ -+ unsigned int cbar_en : 1; /* [30] */ -+ unsigned int intf_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_ctrl; -+ -+/* define the union reg_dhd2_vsync1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vact : 16; /* [15..0] */ -+ unsigned int vbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vsync1; -+ -+/* define the union reg_dhd2_vsync2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vsync2; -+ -+/* define the union reg_dhd2_hsync1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hact : 16; /* [15..0] */ -+ unsigned int hbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_hsync1; -+ -+/* define the union reg_dhd2_hsync2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hfb : 16; /* [15..0] */ -+ unsigned int hmid : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_hsync2; -+ -+/* define the union reg_dhd2_vplus1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvact : 16; /* [15..0] */ -+ unsigned int bvbb : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vplus1; -+ -+/* define the union reg_dhd2_vplus2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvfb : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vplus2; -+ -+/* define the union reg_dhd2_pwr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hpw : 16; /* [15..0] */ -+ unsigned int vpw : 8; /* [23..16] */ -+ unsigned int reserved_0 : 3; /* [26..24] */ -+ unsigned int multichn_en : 2; /* [28..27] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_pwr; -+ -+/* define the union reg_dhd2_vtthd3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vtmgthd3 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd3_mode : 1; /* [15] */ -+ unsigned int vtmgthd4 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd4_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vtthd3; -+ -+/* define the union reg_dhd2_vtthd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vtmgthd1 : 13; /* [12..0] */ -+ unsigned int reserved_0 : 2; /* [14..13] */ -+ unsigned int thd1_mode : 1; /* [15] */ -+ unsigned int vtmgthd2 : 13; /* [28..16] */ -+ unsigned int reserved_1 : 2; /* [30..29] */ -+ unsigned int thd2_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vtthd; -+ -+/* define the union reg_dhd2_parathd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_thd : 8; /* [7..0] */ -+ unsigned int reserved_0 : 23; /* [30..8] */ -+ unsigned int dfs_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_parathd; -+ -+/* define the union reg_dhd2_precharge_thd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tcon_precharge_thd : 17; /* [16..0] */ -+ unsigned int reserved_0 : 3; /* [19..17] */ -+ unsigned int vsync_te_mode : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_precharge_thd; -+ -+/* define the union reg_dhd2_start_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int start_pos : 8; /* [7..0] */ -+ unsigned int timing_start_pos : 8; /* [15..8] */ -+ unsigned int fi_start_pos : 4; /* [19..16] */ -+ unsigned int req_start_pos : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_start_pos; -+ -+/* define the union reg_dhd2_start_pos1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_start_pos1 : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_start_pos1; -+ -+/* define the union reg_dhd2_paraup */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int paraup_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_paraup; -+ -+/* define the union reg_dhd2_sync_inv */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lcd_dv_inv : 1; /* [0] */ -+ unsigned int lcd_hs_inv : 1; /* [1] */ -+ unsigned int lcd_vs_inv : 1; /* [2] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int vga_dv_inv : 1; /* [4] */ -+ unsigned int vga_hs_inv : 1; /* [5] */ -+ unsigned int vga_vs_inv : 1; /* [6] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int hdmi_dv_inv : 1; /* [8] */ -+ unsigned int hdmi_hs_inv : 1; /* [9] */ -+ unsigned int hdmi_vs_inv : 1; /* [10] */ -+ unsigned int hdmi_f_inv : 1; /* [11] */ -+ unsigned int date_dv_inv : 1; /* [12] */ -+ unsigned int date_hs_inv : 1; /* [13] */ -+ unsigned int date_vs_inv : 1; /* [14] */ -+ unsigned int date_f_inv : 1; /* [15] */ -+ unsigned int reserved_2 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_sync_inv; -+ -+/* define the union reg_dhd2_clk_dv_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int intf_clk_mux : 1; /* [0] */ -+ unsigned int intf_dv_mux : 1; /* [1] */ -+ unsigned int no_active_area_pos : 16; /* [17..2] */ -+ unsigned int reserved_0 : 14; /* [31..18] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_clk_dv_ctrl; -+ -+/* define the union reg_dhd2_rgb_fix_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fix_b : 10; /* [9..0] */ -+ unsigned int fix_g : 10; /* [19..10] */ -+ unsigned int fix_r : 10; /* [29..20] */ -+ unsigned int rgb_fix_mux : 1; /* [30] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_rgb_fix_ctrl; -+ -+/* define the union reg_dhd2_lockcfg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int measure_en : 1; /* [0] */ -+ unsigned int lock_cnt_en : 1; /* [1] */ -+ unsigned int vdp_measure_en : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_lockcfg; -+ -+/* define the union reg_dhd2_intf_chksum_high1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int y0_sum_high : 8; /* [7..0] */ -+ unsigned int g0_sum_high : 8; /* [15..8] */ -+ unsigned int b0_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_intf_chksum_high1; -+ -+/* define the union reg_dhd2_intf_chksum_high2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int y1_sum_high : 8; /* [7..0] */ -+ unsigned int g1_sum_high : 8; /* [15..8] */ -+ unsigned int b1_sum_high : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_intf_chksum_high2; -+ -+/* define the union reg_dhd2_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vback_blank : 1; /* [0] */ -+ unsigned int vblank : 1; /* [1] */ -+ unsigned int bottom_field : 1; /* [2] */ -+ unsigned int vcnt : 13; /* [15..3] */ -+ unsigned int count_int : 8; /* [23..16] */ -+ unsigned int dhd_even : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_state; -+ -+/* define the union reg_dhd2_uf_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ud_first_cnt : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int start_pos : 8; /* [23..16] */ -+ unsigned int reserved_1 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_uf_state; -+ -+/* define the union reg_dhd2_vsync_te_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vsync_te_start_sta : 8; /* [7..0] */ -+ unsigned int vsync_te_start_sta1 : 8; /* [15..8] */ -+ unsigned int vsync_te_end_sta : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vsync_te_state; -+ -+/* define the union reg_dhd2_vsync_te_state1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vsync_te_vfb : 16; /* [15..0] */ -+ unsigned int vsync_te_width : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_dhd2_vsync_te_state1; -+ -+/* define the union reg_intf2_dither_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_tap_mode : 2; /* [1..0] */ -+ unsigned int dither_domain_mode : 1; /* [2] */ -+ unsigned int dither_round : 1; /* [3] */ -+ unsigned int dither_mode : 1; /* [4] */ -+ unsigned int dither_en : 1; /* [5] */ -+ unsigned int dither_round_unlim : 1; /* [6] */ -+ unsigned int i_data_width_dither : 3; /* [9..7] */ -+ unsigned int o_data_width_dither : 3; /* [12..10] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_ctrl; -+ -+/* define the union reg_intf2_dither_sed_y0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_y0; -+ -+/* define the union reg_intf2_dither_sed_u0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_u0; -+ -+/* define the union reg_intf2_dither_sed_v0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_v0; -+ -+/* define the union reg_intf2_dither_sed_w0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w0 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_w0; -+ -+/* define the union reg_intf2_dither_sed_y1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_y1; -+ -+/* define the union reg_intf2_dither_sed_u1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_u1; -+ -+/* define the union reg_intf2_dither_sed_v1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_v1; -+ -+/* define the union reg_intf2_dither_sed_w1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w1 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_w1; -+ -+/* define the union reg_intf2_dither_sed_y2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_y2; -+ -+/* define the union reg_intf2_dither_sed_u2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_u2; -+ -+/* define the union reg_intf2_dither_sed_v2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_v2; -+ -+/* define the union reg_intf2_dither_sed_w2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w2 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_w2; -+ -+/* define the union reg_intf2_dither_sed_y3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_y3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_y3; -+ -+/* define the union reg_intf2_dither_sed_u3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_u3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_u3; -+ -+/* define the union reg_intf2_dither_sed_v3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_v3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_v3; -+ -+/* define the union reg_intf2_dither_sed_w3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_sed_w3 : 31; /* [30..0] */ -+ unsigned int reserved_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_sed_w3; -+ -+/* define the union reg_intf2_dither_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dither_thr_min : 16; /* [15..0] */ -+ unsigned int dither_thr_max : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_intf2_dither_thr; -+ -+/* define the union reg_date_coeff0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt_seq : 1; /* [0] */ -+ unsigned int chgain_en : 1; /* [1] */ -+ unsigned int sylp_en : 1; /* [2] */ -+ unsigned int chlp_en : 1; /* [3] */ -+ unsigned int oversam2_en : 1; /* [4] */ -+ unsigned int lunt_en : 1; /* [5] */ -+ unsigned int oversam_en : 2; /* [7..6] */ -+ unsigned int reserved_0 : 1; /* [8] */ -+ unsigned int luma_dl : 4; /* [12..9] */ -+ unsigned int agc_amp_sel : 1; /* [13] */ -+ unsigned int length_sel : 1; /* [14] */ -+ unsigned int sync_mode_scart : 1; /* [15] */ -+ unsigned int sync_mode_sel : 2; /* [17..16] */ -+ unsigned int style_sel : 4; /* [21..18] */ -+ unsigned int fm_sel : 1; /* [22] */ -+ unsigned int vbi_lpf_en : 1; /* [23] */ -+ unsigned int rgb_en : 1; /* [24] */ -+ unsigned int scanline : 1; /* [25] */ -+ unsigned int pbpr_lpf_en : 1; /* [26] */ -+ unsigned int pal_half_en : 1; /* [27] */ -+ unsigned int reserved_1 : 1; /* [28] */ -+ unsigned int dis_ire : 1; /* [29] */ -+ unsigned int clpf_sel : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff0; -+ -+/* define the union reg_date_coeff1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dac_test : 10; /* [9..0] */ -+ unsigned int date_test_mode : 2; /* [11..10] */ -+ unsigned int date_test_en : 1; /* [12] */ -+ unsigned int amp_outside : 10; /* [22..13] */ -+ unsigned int c_limit_en : 1; /* [23] */ -+ unsigned int cc_seq : 1; /* [24] */ -+ unsigned int cgms_seq : 1; /* [25] */ -+ unsigned int vps_seq : 1; /* [26] */ -+ unsigned int wss_seq : 1; /* [27] */ -+ unsigned int cvbs_limit_en : 1; /* [28] */ -+ unsigned int c_gain : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff1; -+ -+/* define the union reg_date_coeff3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef03 : 26; /* [25..0] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff3; -+ -+/* define the union reg_date_coeff4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef04 : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff4; -+ -+/* define the union reg_date_coeff5 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef05 : 29; /* [28..0] */ -+ unsigned int reserved_0 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff5; -+ -+/* define the union reg_date_coeff6 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int coef06_1 : 23; /* [22..0] */ -+ unsigned int reserved_0 : 8; /* [30..23] */ -+ unsigned int coef06_0 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff6; -+ -+/* define the union reg_date_coeff7 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt07_enf2 : 1; /* [0] */ -+ unsigned int tt08_enf2 : 1; /* [1] */ -+ unsigned int tt09_enf2 : 1; /* [2] */ -+ unsigned int tt10_enf2 : 1; /* [3] */ -+ unsigned int tt11_enf2 : 1; /* [4] */ -+ unsigned int tt12_enf2 : 1; /* [5] */ -+ unsigned int tt13_enf2 : 1; /* [6] */ -+ unsigned int tt14_enf2 : 1; /* [7] */ -+ unsigned int tt15_enf2 : 1; /* [8] */ -+ unsigned int tt16_enf2 : 1; /* [9] */ -+ unsigned int tt17_enf2 : 1; /* [10] */ -+ unsigned int tt18_enf2 : 1; /* [11] */ -+ unsigned int tt19_enf2 : 1; /* [12] */ -+ unsigned int tt20_enf2 : 1; /* [13] */ -+ unsigned int tt21_enf2 : 1; /* [14] */ -+ unsigned int tt22_enf2 : 1; /* [15] */ -+ unsigned int tt07_enf1 : 1; /* [16] */ -+ unsigned int tt08_enf1 : 1; /* [17] */ -+ unsigned int tt09_enf1 : 1; /* [18] */ -+ unsigned int tt10_enf1 : 1; /* [19] */ -+ unsigned int tt11_enf1 : 1; /* [20] */ -+ unsigned int tt12_enf1 : 1; /* [21] */ -+ unsigned int tt13_enf1 : 1; /* [22] */ -+ unsigned int tt14_enf1 : 1; /* [23] */ -+ unsigned int tt15_enf1 : 1; /* [24] */ -+ unsigned int tt16_enf1 : 1; /* [25] */ -+ unsigned int tt17_enf1 : 1; /* [26] */ -+ unsigned int tt18_enf1 : 1; /* [27] */ -+ unsigned int tt19_enf1 : 1; /* [28] */ -+ unsigned int tt20_enf1 : 1; /* [29] */ -+ unsigned int tt21_enf1 : 1; /* [30] */ -+ unsigned int tt22_enf1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff7; -+ -+/* define the union reg_date_coeff10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt_pktoff : 8; /* [7..0] */ -+ unsigned int tt_mode : 2; /* [9..8] */ -+ unsigned int tt_highest : 1; /* [10] */ -+ unsigned int full_page : 1; /* [11] */ -+ unsigned int nabts_100ire : 1; /* [12] */ -+ unsigned int reserved_0 : 18; /* [30..13] */ -+ unsigned int tt_ready : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff10; -+ -+/* define the union reg_date_coeff11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int date_clf2 : 10; /* [9..0] */ -+ unsigned int date_clf1 : 10; /* [19..10] */ -+ unsigned int cc_enf2 : 1; /* [20] */ -+ unsigned int cc_enf1 : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff11; -+ -+/* define the union reg_date_coeff12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cc_f2data : 16; /* [15..0] */ -+ unsigned int cc_f1data : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff12; -+ -+/* define the union reg_date_coeff13 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cg_f1data : 20; /* [19..0] */ -+ unsigned int cg_enf2 : 1; /* [20] */ -+ unsigned int cg_enf1 : 1; /* [21] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff13; -+ -+/* define the union reg_date_coeff14 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cg_f2data : 20; /* [19..0] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff14; -+ -+/* define the union reg_date_coeff15 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wss_data : 14; /* [13..0] */ -+ unsigned int wss_en : 1; /* [14] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff15; -+ -+/* define the union reg_date_coeff16 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vps_data : 24; /* [23..0] */ -+ unsigned int vps_en : 1; /* [24] */ -+ unsigned int reserved_0 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff16; -+ -+/* define the union reg_date_coeff19 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vps_data : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff19; -+ -+/* define the union reg_date_coeff20 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt05_enf2 : 1; /* [0] */ -+ unsigned int tt06_enf2 : 1; /* [1] */ -+ unsigned int tt06_enf1 : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff20; -+ -+/* define the union reg_date_coeff21 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dac0_in_sel : 3; /* [2..0] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int dac1_in_sel : 3; /* [6..4] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int dac2_in_sel : 3; /* [10..8] */ -+ unsigned int reserved_2 : 1; /* [11] */ -+ unsigned int dac3_in_sel : 3; /* [14..12] */ -+ unsigned int reserved_3 : 1; /* [15] */ -+ unsigned int dac4_in_sel : 3; /* [18..16] */ -+ unsigned int reserved_4 : 1; /* [19] */ -+ unsigned int dac5_in_sel : 3; /* [22..20] */ -+ unsigned int reserved_5 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff21; -+ -+/* define the union reg_date_coeff22 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int video_phase_delta : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff22; -+ -+/* define the union reg_date_coeff23 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dac0_out_dly : 3; /* [2..0] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int dac1_out_dly : 3; /* [6..4] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int dac2_out_dly : 3; /* [10..8] */ -+ unsigned int reserved_2 : 1; /* [11] */ -+ unsigned int dac3_out_dly : 3; /* [14..12] */ -+ unsigned int reserved_3 : 1; /* [15] */ -+ unsigned int dac4_out_dly : 3; /* [18..16] */ -+ unsigned int reserved_4 : 1; /* [19] */ -+ unsigned int dac5_out_dly : 3; /* [22..20] */ -+ unsigned int reserved_5 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff23; -+ -+/* define the union reg_date_coeff25 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_n_coef : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int x_n_1_coef : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff25; -+ -+/* define the union reg_date_coeff26 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int x_n_1_coef : 13; /* [12..0] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff26; -+ -+/* define the union reg_date_coeff27 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int y_n_coef : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int y_n_1_coef : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff27; -+ -+/* define the union reg_date_coeff28 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int pixel_begin1 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int pixel_begin2 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff28; -+ -+/* define the union reg_date_coeff29 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int pixel_end : 11; /* [10..0] */ -+ unsigned int reserved_0 : 21; /* [31..11] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff29; -+ -+/* define the union reg_date_coeff30 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int g_secam : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff30; -+ -+/* define the union reg_date_isrmask */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt_mask : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_isrmask; -+ -+/* define the union reg_date_isrstate */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt_status : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_isrstate; -+ -+/* define the union reg_date_isr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tt_int : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_isr; -+ -+/* define the union reg_date_coeff37 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fir_y1_coeff0 : 8; /* [7..0] */ -+ unsigned int fir_y1_coeff1 : 8; /* [15..8] */ -+ unsigned int fir_y1_coeff2 : 8; /* [23..16] */ -+ unsigned int fir_y1_coeff3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff37; -+ -+/* define the union reg_date_coeff38 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fir_y2_coeff0 : 16; /* [15..0] */ -+ unsigned int fir_y2_coeff1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff38; -+ -+/* define the union reg_date_coeff39 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fir_y2_coeff2 : 16; /* [15..0] */ -+ unsigned int fir_y2_coeff3 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff39; -+ -+/* define the union reg_date_coeff40 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fir_c1_coeff0 : 8; /* [7..0] */ -+ unsigned int fir_c1_coeff1 : 8; /* [15..8] */ -+ unsigned int fir_c1_coeff2 : 8; /* [23..16] */ -+ unsigned int fir_c1_coeff3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff40; -+ -+/* define the union reg_date_coeff41 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fir_c2_coeff0 : 16; /* [15..0] */ -+ unsigned int fir_c2_coeff1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff41; -+ -+/* define the union reg_date_coeff42 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int fir_c2_coeff2 : 16; /* [15..0] */ -+ unsigned int fir_c2_coeff3 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff42; -+ -+/* define the union reg_date_dacdet1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vdac_det_high : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int det_line : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_dacdet1; -+ -+/* define the union reg_date_dacdet2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int det_pixel_sta : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int det_pixel_wid : 11; /* [26..16] */ -+ unsigned int reserved_1 : 4; /* [30..27] */ -+ unsigned int vdac_det_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_dacdet2; -+ -+/* define the union reg_date_coeff50 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff50; -+ -+/* define the union reg_date_coeff51 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff51; -+ -+/* define the union reg_date_coeff52 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff52; -+ -+/* define the union reg_date_coeff53 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff53; -+ -+/* define the union reg_date_coeff54 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff54; -+ -+/* define the union reg_date_coeff55 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ovs_coeff0 : 11; /* [10..0] */ -+ unsigned int reserved_0 : 5; /* [15..11] */ -+ unsigned int ovs_coeff1 : 11; /* [26..16] */ -+ unsigned int reserved_1 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff55; -+ -+/* define the union reg_date_coeff57 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int v_gain : 8; /* [7..0] */ -+ unsigned int reg_gain : 8; /* [15..8] */ -+ unsigned int ycvbs_gain : 8; /* [23..16] */ -+ unsigned int reserved_0 : 7; /* [30..24] */ -+ unsigned int cvbs_gain_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_date_coeff57; -+ -+/* define the union reg_mac_outstanding */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mstr0_routstanding : 4; /* [3..0] */ -+ unsigned int mstr0_woutstanding : 4; /* [7..4] */ -+ unsigned int mstr1_routstanding : 4; /* [11..8] */ -+ unsigned int mstr1_woutstanding : 4; /* [15..12] */ -+ unsigned int mstr2_routstanding : 4; /* [19..16] */ -+ unsigned int mstr2_woutstanding : 4; /* [23..20] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_outstanding; -+ -+/* define the union reg_mac_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int split_mode : 4; /* [3..0] */ -+ unsigned int arb_mode : 4; /* [7..4] */ -+ unsigned int mid_enable : 1; /* [8] */ -+ unsigned int reserved_0 : 3; /* [11..9] */ -+ unsigned int wport_sel : 4; /* [15..12] */ -+ unsigned int reserved_1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_ctrl; -+ -+/* define the union reg_mac_rchn_prio */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_prio : 1; /* [0] */ -+ unsigned int v0_prio : 1; /* [1] */ -+ unsigned int v0h_prio : 1; /* [2] */ -+ unsigned int v0t_prio : 1; /* [3] */ -+ unsigned int v1_prio : 1; /* [4] */ -+ unsigned int v1t_prio : 1; /* [5] */ -+ unsigned int v2_prio : 1; /* [6] */ -+ unsigned int g0_prio : 1; /* [7] */ -+ unsigned int g1_prio : 1; /* [8] */ -+ unsigned int g3_prio : 1; /* [9] */ -+ unsigned int rchn31_prio : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_rchn_prio; -+ -+/* define the union reg_mac_wchn_prio */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wchn_prio : 1; /* [0] */ -+ unsigned int wchnh_prio : 1; /* [1] */ -+ unsigned int wchn31_prio : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_wchn_prio; -+ -+/* define the union reg_mac_rchn_sel0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int para_sel : 2; /* [1..0] */ -+ unsigned int v0_sel : 2; /* [3..2] */ -+ unsigned int v1_sel : 2; /* [5..4] */ -+ unsigned int v2_sel : 2; /* [7..6] */ -+ unsigned int v3_sel : 2; /* [9..8] */ -+ unsigned int g0_sel : 2; /* [11..10] */ -+ unsigned int g1_sel : 2; /* [13..12] */ -+ unsigned int g2_sel : 2; /* [15..14] */ -+ unsigned int g3_sel : 2; /* [17..16] */ -+ unsigned int g4_sel : 2; /* [19..18] */ -+ unsigned int rchn10_sel : 2; /* [21..20] */ -+ unsigned int rchn11_sel : 2; /* [23..22] */ -+ unsigned int rchn12_sel : 2; /* [25..24] */ -+ unsigned int rchn13_sel : 2; /* [27..26] */ -+ unsigned int rchn14_sel : 2; /* [29..28] */ -+ unsigned int rchn15_sel : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_rchn_sel0; -+ -+/* define the union reg_mac_wchn_sel0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wchn0_sel : 2; /* [1..0] */ -+ unsigned int wchn15_sel : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_wchn_sel0; -+ -+/* define the union reg_mac_bus_err_clr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bus_error_clr : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_bus_err_clr; -+ -+/* define the union reg_mac_bus_err */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mst0_r_error : 1; /* [0] */ -+ unsigned int mst0_w_error : 1; /* [1] */ -+ unsigned int mst1_r_error : 1; /* [2] */ -+ unsigned int mst1_w_error : 1; /* [3] */ -+ unsigned int mst2_r_error : 1; /* [4] */ -+ unsigned int mst2_w_error : 1; /* [5] */ -+ unsigned int reserved_0 : 26; /* [31..6] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_bus_err; -+ -+/* define the union reg_mac_debug_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int axi_det_enable : 1; /* [0] */ -+ unsigned int reserved_0 : 3; /* [3..1] */ -+ unsigned int fifo_det_mode : 4; /* [7..4] */ -+ unsigned int reserved_1 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_debug_ctrl; -+ -+/* define the union reg_mac_debug_clr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int axi_det_clr : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_debug_clr; -+ -+/* define the union reg_mac_axi_press0_ctrl0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int awvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int awvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 14; /* [30..17] */ -+ unsigned int bypass_flag : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press0_ctrl0; -+ -+/* define the union reg_mac_axi_press0_ctrl1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int arvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int arvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press0_ctrl1; -+ -+/* define the union reg_mac_axi_press0_ctrl2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int wvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press0_ctrl2; -+ -+/* define the union reg_mac_axi_press0_ctrl3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int rvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press0_ctrl3; -+ -+/* define the union reg_mac_axi_press0_ctrl4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int bvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press0_ctrl4; -+ -+/* define the union reg_mac_axi_press0_ctrl5 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int axi_press_st : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press0_ctrl5; -+ -+/* define the union reg_mac_axi_press1_ctrl0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int awvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int awvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 14; /* [30..17] */ -+ unsigned int bypass_flag : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press1_ctrl0; -+ -+/* define the union reg_mac_axi_press1_ctrl1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int arvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int arvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press1_ctrl1; -+ -+/* define the union reg_mac_axi_press1_ctrl2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int wvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press1_ctrl2; -+ -+/* define the union reg_mac_axi_press1_ctrl3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int rvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press1_ctrl3; -+ -+/* define the union reg_mac_axi_press1_ctrl4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int bvalid_delay_cfg : 16; /* [15..0] */ -+ unsigned int bvalid_delay_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press1_ctrl4; -+ -+/* define the union reg_mac_axi_press1_ctrl5 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int axi_press_st : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_mac_axi_press1_ctrl5; -+ -+/* define the union reg_vid_read_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int chm_rmode : 3; /* [2..0] */ -+ unsigned int reserved_0 : 1; /* [3] */ -+ unsigned int lm_rmode : 3; /* [6..4] */ -+ unsigned int reserved_1 : 1; /* [7] */ -+ unsigned int chm_draw_mode : 2; /* [9..8] */ -+ unsigned int lm_draw_mode : 2; /* [11..10] */ -+ unsigned int flip_en : 1; /* [12] */ -+ unsigned int chm_copy_en : 1; /* [13] */ -+ unsigned int reserved_2 : 2; /* [15..14] */ -+ unsigned int mute_en : 1; /* [16] */ -+ unsigned int mute_req_en : 1; /* [17] */ -+ unsigned int vicap_mute_en : 1; /* [18] */ -+ unsigned int mrg_enable : 1; /* [19] */ -+ unsigned int mrg_mute_mode : 1; /* [20] */ -+ unsigned int fdr_ck_gt_en : 1; /* [21] */ -+ unsigned int reserved_3 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_read_ctrl; -+ -+/* define the union reg_vid_mac_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_ctrl : 2; /* [1..0] */ -+ unsigned int req_len : 2; /* [3..2] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int ofl_master : 1; /* [8] */ -+ unsigned int reserved_1 : 22; /* [30..9] */ -+ unsigned int pre_rd_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_mac_ctrl; -+ -+/* define the union reg_vid_out_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int draw_pixel_mode : 3; /* [2..0] */ -+ unsigned int draw_pixel_en : 1; /* [3] */ -+ unsigned int uv_order_en : 1; /* [4] */ -+ unsigned int single_port_mode : 1; /* [5] */ -+ unsigned int testpattern_en : 1; /* [6] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_out_ctrl; -+ -+/* define the union reg_vid_mute_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_mute_alpha; -+ -+/* define the union reg_vid_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_mute_bk; -+ -+/* define the union reg_vid_src_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int data_type : 3; /* [2..0] */ -+ unsigned int data_fmt : 2; /* [4..3] */ -+ unsigned int reserved_0 : 3; /* [7..5] */ -+ unsigned int data_width : 2; /* [9..8] */ -+ unsigned int reserved_1 : 2; /* [11..10] */ -+ unsigned int field_type : 1; /* [12] */ -+ unsigned int reserved_2 : 3; /* [15..13] */ -+ unsigned int disp_mode : 4; /* [19..16] */ -+ unsigned int dcmp_en : 2; /* [21..20] */ -+ unsigned int compact_en : 1; /* [22] */ -+ unsigned int compact_req_mode : 1; /* [23] */ -+ unsigned int reserved_3 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_src_info; -+ -+/* define the union reg_vid_src_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int src_w : 16; /* [15..0] */ -+ unsigned int src_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_src_reso; -+ -+/* define the union reg_vid_src_crop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int src_crop_x : 16; /* [15..0] */ -+ unsigned int src_crop_y : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_src_crop; -+ -+/* define the union reg_vid_in_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ireso_w : 16; /* [15..0] */ -+ unsigned int ireso_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_in_reso; -+ -+/* define the union reg_vid_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lm_stride : 16; /* [15..0] */ -+ unsigned int chm_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_stride; -+ -+/* define the union reg_vid_2bit_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lm_tile_stride : 16; /* [15..0] */ -+ unsigned int chm_tile_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_2bit_stride; -+ -+/* define the union reg_vid_head_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lm_head_stride : 16; /* [15..0] */ -+ unsigned int chm_head_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_head_stride; -+ -+/* define the union reg_vid_smmu_bypass */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lm_bypass_2d : 1; /* [0] */ -+ unsigned int chm_bypass_2d : 1; /* [1] */ -+ unsigned int lm_bypass_3d : 1; /* [2] */ -+ unsigned int chm_bypass_3d : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_smmu_bypass; -+ -+/* define the union reg_vid_testpat_cfg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tp_speed : 10; /* [9..0] */ -+ unsigned int reserved_0 : 2; /* [11..10] */ -+ unsigned int tp_line_w : 1; /* [12] */ -+ unsigned int tp_color_mode : 1; /* [13] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int tp_mode : 2; /* [17..16] */ -+ unsigned int reserved_2 : 14; /* [31..18] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_testpat_cfg; -+ -+/* define the union reg_vid_testpat_seed */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tp_seed : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_testpat_seed; -+ -+/* define the union reg_vid_tunl_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tunl_interval : 8; /* [7..0] */ -+ unsigned int tunl_thd : 16; /* [23..8] */ -+ unsigned int reserved_0 : 6; /* [29..24] */ -+ unsigned int tunl_uf : 1; /* [30] */ -+ unsigned int rtunl_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_tunl_ctrl; -+ -+/* define the union reg_vid_tunl_crop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tunl_crop_line : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_tunl_crop; -+ -+/* define the union reg_vid_tunl_errsta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int l_tunl_err : 1; /* [0] */ -+ unsigned int c_tunl_err : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_tunl_errsta; -+ -+/* define the union reg_vid_tunl_debug */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int l_tunl_err_num : 16; /* [15..0] */ -+ unsigned int c_tunl_err_num : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_tunl_debug; -+ -+/* define the union reg_vid_dcmp_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int c_is_lossless : 1; /* [0] */ -+ unsigned int l_is_lossless : 1; /* [1] */ -+ unsigned int c_cmp_mode : 1; /* [2] */ -+ unsigned int l_cmp_mode : 1; /* [3] */ -+ unsigned int c_cmp_rate : 2; /* [5..4] */ -+ unsigned int l_cmp_rate : 2; /* [7..6] */ -+ unsigned int mem_mode : 1; /* [8] */ -+ unsigned int reserved_0 : 23; /* [31..9] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vid_dcmp_ctrl; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int is_lossless : 1; /* [1] */ -+ unsigned int cmp_mode : 1; /* [2] */ -+ unsigned int max_mb_qp_y : 3; /* [5..3] */ -+ unsigned int reserved_0 : 10; /* [15..6] */ -+ unsigned int max_mb_qp_c : 3; /* [18..16] */ -+ unsigned int seg_en : 1; /* [19] */ -+ unsigned int bit_depth : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_glb_info; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_height : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_width : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_frame_size; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_error_sta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dcmp_error : 1; /* [0] */ -+ unsigned int forgive : 1; /* [1] */ -+ unsigned int consume : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_error_sta; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_glb_info_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int is_lossless : 1; /* [1] */ -+ unsigned int cmp_mode : 1; /* [2] */ -+ unsigned int max_mb_qp_y : 3; /* [5..3] */ -+ unsigned int reserved_0 : 10; /* [15..6] */ -+ unsigned int max_mb_qp_c : 3; /* [18..16] */ -+ unsigned int seg_en : 1; /* [19] */ -+ unsigned int bit_depth : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_glb_info_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_frame_size_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_height : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_width : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_frame_size_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smooth_deltabits_thr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_dcmp_error_sta_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dcmp_error : 1; /* [0] */ -+ unsigned int forgive : 1; /* [1] */ -+ unsigned int consume : 1; /* [2] */ -+ unsigned int reserved_0 : 29; /* [31..3] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_dcmp_error_sta_c; -+ -+/* define the union reg_gfx_read_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int read_mode : 2; /* [1..0] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int draw_mode : 2; /* [5..4] */ -+ unsigned int reserved_1 : 2; /* [7..6] */ -+ unsigned int flip_en : 1; /* [8] */ -+ unsigned int reserved_2 : 1; /* [9] */ -+ unsigned int mute_en : 1; /* [10] */ -+ unsigned int mute_req_en : 1; /* [11] */ -+ unsigned int fdr_ck_gt_en : 1; /* [12] */ -+ unsigned int reserved_3 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_read_ctrl; -+ -+/* define the union reg_gfx_mac_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_ctrl : 2; /* [1..0] */ -+ unsigned int req_len : 2; /* [3..2] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int ofl_master : 1; /* [8] */ -+ unsigned int dcmp_thd_close : 1; /* [9] */ -+ unsigned int dcmp_mute_ctrl : 1; /* [10] */ -+ unsigned int reserved_1 : 13; /* [23..11] */ -+ unsigned int req_ld_mode : 2; /* [25..24] */ -+ unsigned int reserved_2 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_mac_ctrl; -+ -+/* define the union reg_gfx_out_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int palpha_range : 1; /* [0] */ -+ unsigned int palpha_en : 1; /* [1] */ -+ unsigned int reserved_0 : 2; /* [3..2] */ -+ unsigned int key_mode : 1; /* [4] */ -+ unsigned int key_en : 1; /* [5] */ -+ unsigned int reserved_1 : 2; /* [7..6] */ -+ unsigned int bitext : 2; /* [9..8] */ -+ unsigned int premulti_en : 1; /* [10] */ -+ unsigned int testpattern_en : 1; /* [11] */ -+ unsigned int reserved_2 : 20; /* [31..12] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_out_ctrl; -+ -+/* define the union reg_gfx_mute_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_alpha : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_mute_alpha; -+ -+/* define the union reg_gfx_mute_bk */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mute_cr : 10; /* [9..0] */ -+ unsigned int mute_cb : 10; /* [19..10] */ -+ unsigned int mute_y : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_mute_bk; -+ -+/* define the union reg_gfx_smmu_bypass */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smmu_bypass_2d : 1; /* [0] */ -+ unsigned int smmu_bypass_3d : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_smmu_bypass; -+ -+/* define the union reg_gfx_1555_alpha */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int alpha_0 : 8; /* [7..0] */ -+ unsigned int alpha_1 : 8; /* [15..8] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_1555_alpha; -+ -+/* define the union reg_gfx_src_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ifmt : 8; /* [7..0] */ -+ unsigned int reserved_0 : 8; /* [15..8] */ -+ unsigned int disp_mode : 4; /* [19..16] */ -+ unsigned int dcmp_en : 1; /* [20] */ -+ unsigned int reserved_1 : 11; /* [31..21] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_src_info; -+ -+/* define the union reg_gfx_src_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int src_w : 16; /* [15..0] */ -+ unsigned int src_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_src_reso; -+ -+/* define the union reg_gfx_src_crop */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int src_crop_x : 16; /* [15..0] */ -+ unsigned int src_crop_y : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_src_crop; -+ -+/* define the union reg_gfx_ireso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ireso_w : 16; /* [15..0] */ -+ unsigned int ireso_h : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ireso; -+ -+/* define the union reg_gfx_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int surface_stride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_stride; -+ -+/* define the union reg_gfx_ckey_max */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int key_b_max : 8; /* [7..0] */ -+ unsigned int key_g_max : 8; /* [15..8] */ -+ unsigned int key_r_max : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ckey_max; -+ -+/* define the union reg_gfx_ckey_min */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int key_b_min : 8; /* [7..0] */ -+ unsigned int key_g_min : 8; /* [15..8] */ -+ unsigned int key_r_min : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ckey_min; -+ -+/* define the union reg_gfx_ckey_mask */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int key_b_msk : 8; /* [7..0] */ -+ unsigned int key_g_msk : 8; /* [15..8] */ -+ unsigned int key_r_msk : 8; /* [23..16] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ckey_mask; -+ -+/* define the union reg_gfx_testpat_cfg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tp_speed : 10; /* [9..0] */ -+ unsigned int reserved_0 : 2; /* [11..10] */ -+ unsigned int tp_line_w : 1; /* [12] */ -+ unsigned int tp_color_mode : 1; /* [13] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int tp_mode : 2; /* [17..16] */ -+ unsigned int reserved_2 : 14; /* [31..18] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_testpat_cfg; -+ -+/* define the union reg_gfx_testpat_seed */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int tp_seed : 30; /* [29..0] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_testpat_seed; -+ -+/* define the union reg_gfx_ld_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 1; /* [0] */ -+ unsigned int hw_mute_clr : 1; /* [1] */ -+ unsigned int ld_mute_en : 1; /* [2] */ -+ unsigned int ld_err_mute_en : 1; /* [3] */ -+ unsigned int reserved_1 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ld_ctrl; -+ -+/* define the union reg_gfx_ld_smute_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int sw_mute_clr : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ld_smute_ctrl; -+ -+/* define the union reg_gfx_ld_err_sta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ld_err_clr : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_ld_err_sta; -+ -+/* define the union reg_vdp_v3r2_line_osd_dcmp_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int conv_en : 1; /* [2] */ -+ unsigned int is_lossless : 1; /* [3] */ -+ unsigned int osd_mode : 2; /* [5..4] */ -+ unsigned int max_mb_qp : 3; /* [8..6] */ -+ unsigned int excess_err_mask : 1; /* [9] */ -+ unsigned int rw_reg_add : 6; /* [15..10] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_line_osd_dcmp_glb_info; -+ -+/* define the union reg_vdp_v3r2_line_osd_dcmp_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_height : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_line_osd_dcmp_frame_size; -+ -+/* define the union reg_vdp_v3r2_line_osd_dcmp_error_sta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dcmp_error : 1; /* [0] */ -+ unsigned int o_pix_forgive : 1; /* [1] */ -+ unsigned int o_pix_consume : 1; /* [2] */ -+ unsigned int o_mb_qp_error : 1; /* [3] */ -+ unsigned int o_dcmp_excess_err : 1; /* [4] */ -+ unsigned int o_dcmp_err_add : 5; /* [9..5] */ -+ unsigned int o_dcmp_debug : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_line_osd_dcmp_error_sta; -+ -+/* define the union reg_wbc_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 4; /* [3..0] */ -+ unsigned int data_width : 1; /* [4] */ -+ unsigned int reserved_1 : 3; /* [7..5] */ -+ unsigned int uv_order : 1; /* [8] */ -+ unsigned int flip_en : 1; /* [9] */ -+ unsigned int align_mode : 1; /* [10] */ -+ unsigned int reserved_2 : 3; /* [13..11] */ -+ unsigned int cap_ck_gt_en : 1; /* [14] */ -+ unsigned int reserved_3 : 14; /* [28..15] */ -+ unsigned int wbc_cmp_en : 1; /* [29] */ -+ unsigned int reserved_4 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_ctrl; -+ -+/* define the union reg_wbc_mac_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 2; /* [11..10] */ -+ unsigned int wbc_len : 2; /* [13..12] */ -+ unsigned int reserved_1 : 18; /* [31..14] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_mac_ctrl; -+ -+/* define the union reg_wbc_smmu_bypass */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int l_bypass : 1; /* [0] */ -+ unsigned int c_bypass : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_smmu_bypass; -+ -+/* define the union reg_wbc_lowdlyctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wb_per_line_num : 12; /* [11..0] */ -+ unsigned int partfns_line_num : 12; /* [23..12] */ -+ unsigned int reserved_0 : 6; /* [29..24] */ -+ unsigned int lowdly_test : 1; /* [30] */ -+ unsigned int lowdly_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_lowdlyctrl; -+ -+/* define the union reg_wbc_lowdlysta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 31; /* [30..0] */ -+ unsigned int part_finish : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_lowdlysta; -+ -+/* define the union reg_wbc_ystride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_ystride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_ystride; -+ -+/* define the union reg_wbc_cstride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_cstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cstride; -+ -+/* define the union reg_wbc_ynstride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_ynstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_ynstride; -+ -+/* define the union reg_wbc_cnstride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_cnstride : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cnstride; -+ -+/* define the union reg_wbc_sta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_l_busy : 1; /* [0] */ -+ unsigned int wbc_c_busy : 1; /* [1] */ -+ unsigned int wbc_lh_busy : 1; /* [2] */ -+ unsigned int wbc_ch_busy : 1; /* [3] */ -+ unsigned int reserved_0 : 28; /* [31..4] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_sta; -+ -+/* define the union reg_wbc_line_num */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int wbc_l_linenum : 16; /* [15..0] */ -+ unsigned int wbc_c_linenum : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_line_num; -+ -+/* define the union reg_wbc_cap_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cap_width : 16; /* [15..0] */ -+ unsigned int cap_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cap_reso; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int is_lossless : 1; /* [2] */ -+ unsigned int chroma_en : 1; /* [3] */ -+ unsigned int esl_qp : 3; /* [6..4] */ -+ unsigned int bit_depth : 1; /* [7] */ -+ unsigned int mirror_en : 1; /* [8] */ -+ unsigned int seg_en : 1; /* [9] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_glb_info; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_height : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_frame_size; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int big_grad_thr : 8; /* [7..0] */ -+ unsigned int diff_thr : 8; /* [15..8] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg0; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg1; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int buffer_init_bits : 16; /* [15..0] */ -+ unsigned int buffer_size : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg12; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg13 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int budget_mb_bits : 10; /* [9..0] */ -+ unsigned int budget_mb_bits_last : 10; /* [19..10] */ -+ unsigned int min_mb_bits : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg13; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg16 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smooth_status_thr : 4; /* [3..0] */ -+ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ -+ unsigned int max_mb_qp : 3; /* [14..12] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg16; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_glb_st */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_left_bits_buffer : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_glb_st; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_glb_info_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ice_en : 1; /* [0] */ -+ unsigned int cmp_mode : 1; /* [1] */ -+ unsigned int is_lossless : 1; /* [2] */ -+ unsigned int chroma_en : 1; /* [3] */ -+ unsigned int esl_qp : 3; /* [6..4] */ -+ unsigned int bit_depth : 1; /* [7] */ -+ unsigned int mirror_en : 1; /* [8] */ -+ unsigned int seg_en : 1; /* [9] */ -+ unsigned int reserved_0 : 22; /* [31..10] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_glb_info_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_frame_size_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 14; /* [13..0] */ -+ unsigned int reserved_0 : 2; /* [15..14] */ -+ unsigned int frame_height : 14; /* [29..16] */ -+ unsigned int reserved_1 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_frame_size_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg0_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int big_grad_thr : 8; /* [7..0] */ -+ unsigned int diff_thr : 8; /* [15..8] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg0_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg1_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg1_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg12_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int buffer_init_bits : 16; /* [15..0] */ -+ unsigned int buffer_size : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg12_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg13_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int budget_mb_bits : 10; /* [9..0] */ -+ unsigned int budget_mb_bits_last : 10; /* [19..10] */ -+ unsigned int min_mb_bits : 10; /* [29..20] */ -+ unsigned int reserved_0 : 2; /* [31..30] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg13_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_rc_cfg16_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smooth_status_thr : 4; /* [3..0] */ -+ unsigned int smooth_deltabits_thr : 8; /* [11..4] */ -+ unsigned int max_mb_qp : 3; /* [14..12] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_rc_cfg16_c; -+ -+/* define the union reg_vdp_v3r2_lineseg_cmp_glb_st_c */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_left_bits_buffer : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_vdp_v3r2_lineseg_cmp_glb_st_c; -+ -+/* define the union reg_wbc_cmp_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int req_interval : 10; /* [9..0] */ -+ unsigned int reserved_0 : 17; /* [26..10] */ -+ unsigned int mem_mode : 1; /* [27] */ -+ unsigned int data_width : 1; /* [28] */ -+ unsigned int reserved_1 : 1; /* [29] */ -+ unsigned int l_cmp_en : 1; /* [30] */ -+ unsigned int wbc_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_ctrl; -+ -+/* define the union reg_wbc_cmp_upd */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int regup : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_upd; -+ -+/* define the union reg_wbc_cmp_height */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int c_max_height : 13; /* [12..0] */ -+ unsigned int l_max_height : 13; /* [25..13] */ -+ unsigned int addr_mode : 1; /* [26] */ -+ unsigned int fsize_mode : 1; /* [27] */ -+ unsigned int rgb_cmp_mode : 2; /* [29..28] */ -+ unsigned int pause_mode : 1; /* [30] */ -+ unsigned int buffer_mode : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_height; -+ -+/* define the union reg_wbc_cmp_oreso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int ow : 12; /* [11..0] */ -+ unsigned int oh : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_cmp_oreso; -+ -+/* define the union reg_wbc_od_state */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int addr_err : 1; /* [0] */ -+ unsigned int he_addr_err0 : 1; /* [1] */ -+ unsigned int he_addr_err1 : 1; /* [2] */ -+ unsigned int he_addr_err2 : 1; /* [3] */ -+ unsigned int w_addr_err : 1; /* [4] */ -+ unsigned int he_fsize_err0 : 1; /* [5] */ -+ unsigned int he_fsize_err1 : 1; /* [6] */ -+ unsigned int he_fsize_err2 : 1; /* [7] */ -+ unsigned int w_fsize_err : 1; /* [8] */ -+ unsigned int he_fsize_war0 : 1; /* [9] */ -+ unsigned int he_fsize_war1 : 1; /* [10] */ -+ unsigned int he_fsize_war2 : 1; /* [11] */ -+ unsigned int w_fsize_war : 1; /* [12] */ -+ unsigned int reserved_0 : 19; /* [31..13] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_wbc_od_state; -+ -+/* define the union reg_od_pic_osd_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int is_lossless : 1; /* [0] */ -+ unsigned int is_lossless_a : 1; /* [1] */ -+ unsigned int cmp_mode : 1; /* [2] */ -+ unsigned int source_mode : 3; /* [5..3] */ -+ unsigned int part_cmp_en : 1; /* [6] */ -+ unsigned int top_pred_en : 1; /* [7] */ -+ unsigned int graphic_en : 1; /* [8] */ -+ unsigned int reserved_0 : 23; /* [31..9] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_glb_info; -+ -+/* define the union reg_od_pic_osd_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int frame_height : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_frame_size; -+ -+/* define the union reg_od_pic_osd_rc_cfg0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mb_bits : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int min_mb_bits : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg0; -+ -+/* define the union reg_od_pic_osd_rc_cfg1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_qp : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int sad_bits_gain : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int rc_smth_ngain : 3; /* [18..16] */ -+ unsigned int reserved_2 : 5; /* [23..19] */ -+ unsigned int max_trow_bits : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg1; -+ -+/* define the union reg_od_pic_osd_rc_cfg2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_sad_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int min_sad_thr : 7; /* [22..16] */ -+ unsigned int reserved_1 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg2; -+ -+/* define the union reg_od_pic_osd_rc_cfg3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smth_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int still_thr : 7; /* [14..8] */ -+ unsigned int reserved_1 : 1; /* [15] */ -+ unsigned int big_grad_thr : 10; /* [25..16] */ -+ unsigned int reserved_2 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg3; -+ -+/* define the union reg_od_pic_osd_rc_cfg4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int smth_pix_num_thr : 6; /* [5..0] */ -+ unsigned int reserved_0 : 2; /* [7..6] */ -+ unsigned int still_pix_num_thr : 6; /* [13..8] */ -+ unsigned int reserved_1 : 2; /* [15..14] */ -+ unsigned int noise_pix_num_thr : 6; /* [21..16] */ -+ unsigned int reserved_2 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg4; -+ -+/* define the union reg_od_pic_osd_rc_cfg5 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int noise_sad : 7; /* [6..0] */ -+ unsigned int reserved_0 : 9; /* [15..7] */ -+ unsigned int pix_diff_thr : 10; /* [25..16] */ -+ unsigned int reserved_1 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg5; -+ -+/* define the union reg_od_pic_osd_rc_cfg6 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int adj_sad_bits_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg6; -+ -+/* define the union reg_od_pic_osd_rc_cfg7 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int qp_inc1_bits_thr : 8; /* [7..0] */ -+ unsigned int qp_inc2_bits_thr : 8; /* [15..8] */ -+ unsigned int qp_dec1_bits_thr : 8; /* [23..16] */ -+ unsigned int qp_dec2_bits_thr : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg7; -+ -+/* define the union reg_od_pic_osd_rc_cfg8 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int est_err_gain : 5; /* [4..0] */ -+ unsigned int reserved_0 : 11; /* [15..5] */ -+ unsigned int max_est_err_level : 9; /* [24..16] */ -+ unsigned int reserved_1 : 7; /* [31..25] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg8; -+ -+/* define the union reg_od_pic_osd_rc_cfg9 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 16; /* [15..0] */ -+ unsigned int vbv_buf_loss1_thr : 7; /* [22..16] */ -+ unsigned int reserved_1 : 1; /* [23] */ -+ unsigned int vbv_buf_loss2_thr : 7; /* [30..24] */ -+ unsigned int reserved_2 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg9; -+ -+/* define the union reg_od_pic_osd_rc_cfg10 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int qp_thr0 : 3; /* [2..0] */ -+ unsigned int reserved_0 : 5; /* [7..3] */ -+ unsigned int qp_thr1 : 3; /* [10..8] */ -+ unsigned int reserved_1 : 5; /* [15..11] */ -+ unsigned int qp_thr2 : 3; /* [18..16] */ -+ unsigned int reserved_2 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg10; -+ -+/* define the union reg_od_pic_osd_rc_cfg11 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int grph_bias_bit_thr0 : 8; /* [7..0] */ -+ unsigned int grph_bias_bit_thr1 : 8; /* [15..8] */ -+ unsigned int grph_ideal_bit_thr : 10; /* [25..16] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg11; -+ -+/* define the union reg_od_pic_osd_rc_cfg12 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int force_rc_en : 1; /* [0] */ -+ unsigned int reserved_0 : 7; /* [7..1] */ -+ unsigned int forcerc_bits_diff_thr : 8; /* [15..8] */ -+ unsigned int reserved_1 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg12; -+ -+/* define the union reg_od_pic_osd_rc_cfg13 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int maxdiff_ctrl_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg13; -+ -+/* define the union reg_od_pic_osd_rc_cfg14 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mb_bits_cap : 10; /* [9..0] */ -+ unsigned int reserved_0 : 6; /* [15..10] */ -+ unsigned int init_buf_bits_cap : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg14; -+ -+/* define the union reg_od_pic_osd_rc_cfg15 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lfw_mb_len : 7; /* [6..0] */ -+ unsigned int reserved_0 : 1; /* [7] */ -+ unsigned int cmplx_sad_thr : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int err_thr0 : 4; /* [19..16] */ -+ unsigned int reserved_2 : 4; /* [23..20] */ -+ unsigned int err_thr1 : 4; /* [27..24] */ -+ unsigned int reserved_3 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg15; -+ -+/* define the union reg_od_pic_osd_rc_cfg16 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int sim_num_thr : 3; /* [2..0] */ -+ unsigned int reserved_0 : 5; /* [7..3] */ -+ unsigned int sum_y_err_thr : 7; /* [14..8] */ -+ unsigned int reserved_1 : 1; /* [15] */ -+ unsigned int sum_c_err_thr : 7; /* [22..16] */ -+ unsigned int reserved_2 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg16; -+ -+/* define the union reg_od_pic_osd_rc_cfg17 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cpmlx_sad_thr_y : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int smpl_sad_thr_c : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int smpl_sumsad_thr_y : 8; /* [23..16] */ -+ unsigned int smpl_sumsad_thr_c : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg17; -+ -+/* define the union reg_od_pic_osd_rc_cfg18 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int future_sad_y_thr0 : 4; /* [3..0] */ -+ unsigned int reserved_0 : 4; /* [7..4] */ -+ unsigned int future_sad_c_thr0 : 4; /* [11..8] */ -+ unsigned int reserved_1 : 4; /* [15..12] */ -+ unsigned int future_sad_y_thr1 : 4; /* [19..16] */ -+ unsigned int reserved_2 : 4; /* [23..20] */ -+ unsigned int future_sad_c_thr1 : 4; /* [27..24] */ -+ unsigned int reserved_3 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg18; -+ -+/* define the union reg_od_pic_osd_rc_cfg19 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cmplx_sumsad_thr_y : 8; /* [7..0] */ -+ unsigned int cmplx_sumsad_thr_c : 8; /* [15..8] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_rc_cfg19; -+ -+/* define the union reg_od_pic_osd_stat_thr */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_gap_bw_row_len_thr : 7; /* [6..0] */ -+ unsigned int reserved_0 : 25; /* [31..7] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_stat_thr; -+ -+/* define the union reg_od_pic_osd_pcmp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int pcmp_start_hpos : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int pcmp_end_hpos : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_pcmp; -+ -+/* define the union reg_od_pic_osd_bs_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_size_reg : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_bs_size; -+ -+/* define the union reg_od_pic_osd_worst_row */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_frm_row_len : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_worst_row; -+ -+/* define the union reg_od_pic_osd_best_row */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int min_frm_row_len : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_best_row; -+ -+/* define the union reg_od_pic_osd_stat_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int max_gap_bw_row_len_cnt : 16; /* [15..0] */ -+ unsigned int reserved_0 : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_od_pic_osd_stat_info; -+ -+/* define the union reg_v0_mrg_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ -+ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ -+ unsigned int reserved_0 : 12; /* [19..8] */ -+ unsigned int mrg_edge_en : 1; /* [20] */ -+ unsigned int reserved_1 : 4; /* [24..21] */ -+ unsigned int mrg_edge_typ : 1; /* [25] */ -+ unsigned int reserved_2 : 2; /* [27..26] */ -+ unsigned int mrg_crop_en : 1; /* [28] */ -+ unsigned int mrg_dcmp_en : 1; /* [29] */ -+ unsigned int mrg_mute_en : 1; /* [30] */ -+ unsigned int mrg_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_ctrl; -+ -+/* define the union reg_v0_mrg_disp_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_xpos : 16; /* [15..0] */ -+ unsigned int mrg_ypos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_disp_pos; -+ -+/* define the union reg_v0_mrg_disp_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_width : 16; /* [15..0] */ -+ unsigned int mrg_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_disp_reso; -+ -+/* define the union reg_v0_mrg_src_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_src_width : 16; /* [15..0] */ -+ unsigned int mrg_src_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_src_reso; -+ -+/* define the union reg_v0_mrg_src_offset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_src_hoffset : 16; /* [15..0] */ -+ unsigned int mrg_src_voffset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_src_offset; -+ -+/* define the union reg_v0_mrg_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_c_stride : 16; /* [15..0] */ -+ unsigned int mrg_y_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_stride; -+ -+/* define the union reg_v0_mrg_hstride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_ch_stride : 16; /* [15..0] */ -+ unsigned int mrg_yh_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_hstride; -+ -+/* define the union reg_v0_mrg_read_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rd_region : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_read_ctrl; -+ -+/* define the union reg_v0_mrg_read_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_mrg_read_en; -+ -+/* define the union reg_v1_mrg_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_y_l4_addr : 4; /* [3..0] */ -+ unsigned int mrg_c_l4_addr : 4; /* [7..4] */ -+ unsigned int reserved_0 : 12; /* [19..8] */ -+ unsigned int mrg_edge_en : 1; /* [20] */ -+ unsigned int reserved_1 : 4; /* [24..21] */ -+ unsigned int mrg_edge_typ : 1; /* [25] */ -+ unsigned int reserved_2 : 2; /* [27..26] */ -+ unsigned int mrg_crop_en : 1; /* [28] */ -+ unsigned int mrg_dcmp_en : 1; /* [29] */ -+ unsigned int mrg_mute_en : 1; /* [30] */ -+ unsigned int mrg_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_ctrl; -+ -+/* define the union reg_v1_mrg_disp_pos */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_xpos : 16; /* [15..0] */ -+ unsigned int mrg_ypos : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_disp_pos; -+ -+/* define the union reg_v1_mrg_disp_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_width : 16; /* [15..0] */ -+ unsigned int mrg_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_disp_reso; -+ -+/* define the union reg_v1_mrg_src_reso */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_src_width : 16; /* [15..0] */ -+ unsigned int mrg_src_height : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_src_reso; -+ -+/* define the union reg_v1_mrg_src_offset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_src_hoffset : 16; /* [15..0] */ -+ unsigned int mrg_src_voffset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_src_offset; -+ -+/* define the union reg_v1_mrg_stride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_c_stride : 16; /* [15..0] */ -+ unsigned int mrg_y_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_stride; -+ -+/* define the union reg_v1_mrg_hstride */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mrg_ch_stride : 16; /* [15..0] */ -+ unsigned int mrg_yh_stride : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_hstride; -+ -+/* define the union reg_v1_mrg_read_ctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rd_region : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_read_ctrl; -+ -+/* define the union reg_v1_mrg_read_en */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int rd_en : 1; /* [0] */ -+ unsigned int reserved_0 : 31; /* [31..1] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_mrg_read_en; -+ -+/* define the union reg_g1_osb_ctrl1_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mode_0 : 2; /* [1..0] */ -+ unsigned int thick_w_0 : 6; /* [7..2] */ -+ unsigned int arm_w_0 : 8; /* [15..8] */ -+ unsigned int edge_v_0 : 4; /* [19..16] */ -+ unsigned int edge_u_0 : 4; /* [23..20] */ -+ unsigned int edge_y_0 : 4; /* [27..24] */ -+ unsigned int edge_alpha_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_osb_ctrl1_box_0; -+ -+/* define the union reg_g1_osb_ctrl2_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int hend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_osb_ctrl2_box_0; -+ -+/* define the union reg_g1_osb_ctrl3_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int vend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_osb_ctrl3_box_0; -+ -+/* define the union reg_g3_osb_ctrl1_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mode_0 : 2; /* [1..0] */ -+ unsigned int thick_w_0 : 6; /* [7..2] */ -+ unsigned int arm_w_0 : 8; /* [15..8] */ -+ unsigned int edge_v_0 : 4; /* [19..16] */ -+ unsigned int edge_u_0 : 4; /* [23..20] */ -+ unsigned int edge_y_0 : 4; /* [27..24] */ -+ unsigned int edge_alpha_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_osb_ctrl1_box_0; -+ -+/* define the union reg_g3_osb_ctrl2_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int hend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_osb_ctrl2_box_0; -+ -+/* define the union reg_g3_osb_ctrl3_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int vend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_osb_ctrl3_box_0; -+ -+/* define the union reg_g4_osb_ctrl1_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int mode_0 : 2; /* [1..0] */ -+ unsigned int thick_w_0 : 6; /* [7..2] */ -+ unsigned int arm_w_0 : 8; /* [15..8] */ -+ unsigned int edge_v_0 : 4; /* [19..16] */ -+ unsigned int edge_u_0 : 4; /* [23..20] */ -+ unsigned int edge_y_0 : 4; /* [27..24] */ -+ unsigned int edge_alpha_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_osb_ctrl1_box_0; -+ -+/* define the union reg_g4_osb_ctrl2_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int hend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_osb_ctrl2_box_0; -+ -+/* define the union reg_g4_osb_ctrl3_box_0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vstr_pos_0 : 12; /* [11..0] */ -+ unsigned int reserved_0 : 4; /* [15..12] */ -+ unsigned int vend_pos_0 : 12; /* [27..16] */ -+ unsigned int reserved_1 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g4_osb_ctrl3_box_0; -+ -+/* define the union reg_v1_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_idc; -+ -+/* define the union reg_v1_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_odc; -+ -+/* define the union reg_v1_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_iodc; -+ -+/* define the union reg_v1_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_p0; -+ -+/* define the union reg_v1_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_p1; -+ -+/* define the union reg_v1_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_p2; -+ -+/* define the union reg_v1_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_p3; -+ -+/* define the union reg_v1_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc_p4; -+ -+/* define the union reg_v1_csc1_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_idc; -+ -+/* define the union reg_v1_csc1_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_odc; -+ -+/* define the union reg_v1_csc1_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_iodc; -+ -+/* define the union reg_v1_csc1_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_p0; -+ -+/* define the union reg_v1_csc1_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_p1; -+ -+/* define the union reg_v1_csc1_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_p2; -+ -+/* define the union reg_v1_csc1_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_p3; -+ -+/* define the union reg_v1_csc1_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v1_csc1_p4; -+ -+/* define the union reg_v2_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_idc; -+ -+/* define the union reg_v2_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_odc; -+ -+/* define the union reg_v2_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_iodc; -+ -+/* define the union reg_v2_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_p0; -+ -+/* define the union reg_v2_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_p1; -+ -+/* define the union reg_v2_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_p2; -+ -+/* define the union reg_v2_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_p3; -+ -+/* define the union reg_v2_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc_p4; -+ -+/* define the union reg_v2_csc1_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_idc; -+ -+/* define the union reg_v2_csc1_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_odc; -+ -+/* define the union reg_v2_csc1_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_iodc; -+ -+/* define the union reg_v2_csc1_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_p0; -+ -+/* define the union reg_v2_csc1_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_p1; -+ -+/* define the union reg_v2_csc1_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_p2; -+ -+/* define the union reg_v2_csc1_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_p3; -+ -+/* define the union reg_v2_csc1_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v2_csc1_p4; -+ -+/* define the union reg_g1_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_idc; -+ -+/* define the union reg_g1_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_odc; -+ -+/* define the union reg_g1_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_iodc; -+ -+/* define the union reg_g1_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_p0; -+ -+/* define the union reg_g1_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_p1; -+ -+/* define the union reg_g1_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_p2; -+ -+/* define the union reg_g1_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_p3; -+ -+/* define the union reg_g1_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc_p4; -+ -+/* define the union reg_g1_csc1_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_idc; -+ -+/* define the union reg_g1_csc1_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_odc; -+ -+/* define the union reg_g1_csc1_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_iodc; -+ -+/* define the union reg_g1_csc1_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_p0; -+ -+/* define the union reg_g1_csc1_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_p1; -+ -+/* define the union reg_g1_csc1_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_p2; -+ -+/* define the union reg_g1_csc1_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_p3; -+ -+/* define the union reg_g1_csc1_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g1_csc1_p4; -+ -+/* define the union reg_g3_csc_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int csc_ck_gt_en : 1; /* [26] */ -+ unsigned int reserved_0 : 5; /* [31..27] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_idc; -+ -+/* define the union reg_g3_csc_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_odc; -+ -+/* define the union reg_g3_csc_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_iodc; -+ -+/* define the union reg_g3_csc_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_p0; -+ -+/* define the union reg_g3_csc_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_p1; -+ -+/* define the union reg_g3_csc_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_p2; -+ -+/* define the union reg_g3_csc_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_p3; -+ -+/* define the union reg_g3_csc_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc_p4; -+ -+/* define the union reg_g3_csc1_idc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc0 : 11; /* [10..0] */ -+ unsigned int cscidc1 : 11; /* [21..11] */ -+ unsigned int csc_en : 1; /* [22] */ -+ unsigned int csc_mode : 3; /* [25..23] */ -+ unsigned int reserved_0 : 6; /* [31..26] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_idc; -+ -+/* define the union reg_g3_csc1_odc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscodc0 : 11; /* [10..0] */ -+ unsigned int cscodc1 : 11; /* [21..11] */ -+ unsigned int csc_sign_mode : 1; /* [22] */ -+ unsigned int reserved_0 : 9; /* [31..23] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_odc; -+ -+/* define the union reg_g3_csc1_iodc */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscidc2 : 11; /* [10..0] */ -+ unsigned int cscodc2 : 11; /* [21..11] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_iodc; -+ -+/* define the union reg_g3_csc1_p0 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp00 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp01 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_p0; -+ -+/* define the union reg_g3_csc1_p1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp02 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp10 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_p1; -+ -+/* define the union reg_g3_csc1_p2 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp11 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp12 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_p2; -+ -+/* define the union reg_g3_csc1_p3 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp20 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 1; /* [15] */ -+ unsigned int cscp21 : 15; /* [30..16] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_p3; -+ -+/* define the union reg_g3_csc1_p4 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int cscp22 : 15; /* [14..0] */ -+ unsigned int reserved_0 : 17; /* [31..15] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_g3_csc1_p4; -+ -+/* define the union reg_v0_zme_hinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_width : 16; /* [15..0] */ -+ unsigned int hzme_ck_gt_en : 1; /* [16] */ -+ unsigned int reserved_0 : 15; /* [31..17] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hinfo; -+ -+/* define the union reg_v0_zme_hsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hratio : 24; /* [23..0] */ -+ unsigned int hfir_order : 1; /* [24] */ -+ unsigned int chfir_mode : 1; /* [25] */ -+ unsigned int lhfir_mode : 1; /* [26] */ -+ unsigned int non_lnr_en : 1; /* [27] */ -+ unsigned int chmid_en : 1; /* [28] */ -+ unsigned int lhmid_en : 1; /* [29] */ -+ unsigned int chfir_en : 1; /* [30] */ -+ unsigned int lhfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hsp; -+ -+/* define the union reg_v0_zme_hloffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int lhfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hloffset; -+ -+/* define the union reg_v0_zme_hcoffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int chfir_offset : 28; /* [27..0] */ -+ unsigned int reserved_0 : 4; /* [31..28] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hcoffset; -+ -+/* define the union reg_v0_zme_hzone0delta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int zone0_delta : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hzone0delta; -+ -+/* define the union reg_v0_zme_hzone2delta */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int zone2_delta : 22; /* [21..0] */ -+ unsigned int reserved_0 : 10; /* [31..22] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hzone2delta; -+ -+/* define the union reg_v0_zme_hzoneend */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int zone0_end : 12; /* [11..0] */ -+ unsigned int zone1_end : 12; /* [23..12] */ -+ unsigned int reserved_0 : 8; /* [31..24] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hzoneend; -+ -+/* define the union reg_v0_zme_hl_shootctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hl_coring : 8; /* [7..0] */ -+ unsigned int hl_gain : 6; /* [13..8] */ -+ unsigned int hl_coringadj_en : 1; /* [14] */ -+ unsigned int hl_flatdect_mode : 1; /* [15] */ -+ unsigned int hl_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int hl_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hl_shootctrl; -+ -+/* define the union reg_v0_zme_hc_shootctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int hc_coring : 8; /* [7..0] */ -+ unsigned int hc_gain : 6; /* [13..8] */ -+ unsigned int hc_coringadj_en : 1; /* [14] */ -+ unsigned int hc_flatdect_mode : 1; /* [15] */ -+ unsigned int hc_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int hc_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hc_shootctrl; -+ -+/* define the union reg_v0_zme_hcoef_ren */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_hf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hcoef_ren; -+ -+/* define the union reg_v0_zme_hcoef_rdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_hcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_hcoef_rdata; -+ -+/* define the union reg_v0_zme_vinfo */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int out_height : 16; /* [15..0] */ -+ unsigned int out_fmt : 2; /* [17..16] */ -+ unsigned int out_pro : 1; /* [18] */ -+ unsigned int vzme_ck_gt_en : 1; /* [19] */ -+ unsigned int reserved_0 : 12; /* [31..20] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vinfo; -+ -+/* define the union reg_v0_zme_vsp */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vratio : 16; /* [15..0] */ -+ unsigned int graphdet_en : 1; /* [16] */ -+ unsigned int reserved_0 : 8; /* [24..17] */ -+ unsigned int cvfir_mode : 1; /* [25] */ -+ unsigned int lvfir_mode : 1; /* [26] */ -+ unsigned int vfir_1tap_en : 1; /* [27] */ -+ unsigned int cvmid_en : 1; /* [28] */ -+ unsigned int lvmid_en : 1; /* [29] */ -+ unsigned int cvfir_en : 1; /* [30] */ -+ unsigned int lvfir_en : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vsp; -+ -+/* define the union reg_v0_zme_voffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vchroma_offset : 16; /* [15..0] */ -+ unsigned int vluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_voffset; -+ -+/* define the union reg_v0_zme_vboffset */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vbchroma_offset : 16; /* [15..0] */ -+ unsigned int vbluma_offset : 16; /* [31..16] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vboffset; -+ -+/* define the union reg_v0_zme_vl_shootctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vl_coring : 8; /* [7..0] */ -+ unsigned int vl_gain : 6; /* [13..8] */ -+ unsigned int vl_coringadj_en : 1; /* [14] */ -+ unsigned int vl_flatdect_mode : 1; /* [15] */ -+ unsigned int vl_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int vl_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vl_shootctrl; -+ -+/* define the union reg_v0_zme_vc_shootctrl */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int vc_coring : 8; /* [7..0] */ -+ unsigned int vc_gain : 6; /* [13..8] */ -+ unsigned int vc_coringadj_en : 1; /* [14] */ -+ unsigned int vc_flatdect_mode : 1; /* [15] */ -+ unsigned int vc_shootctrl_mode : 1; /* [16] */ -+ unsigned int reserved_0 : 1; /* [17] */ -+ unsigned int vc_shootctrl_en : 1; /* [18] */ -+ unsigned int reserved_1 : 13; /* [31..19] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vc_shootctrl; -+ -+/* define the union reg_v0_zme_vcoef_ren */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vf_cren : 1; /* [0] */ -+ unsigned int apb_vhd_vf_lren : 1; /* [1] */ -+ unsigned int reserved_0 : 30; /* [31..2] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vcoef_ren; -+ -+/* define the union reg_v0_zme_vcoef_rdata */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int apb_vhd_vcoef_raddr : 8; /* [7..0] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_v0_zme_vcoef_rdata; -+ -+/* define the union reg_gfx_osd_glb_info */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int dcmp_en : 1; /* [0] */ -+ unsigned int is_lossless : 1; /* [1] */ -+ unsigned int is_lossless_a : 1; /* [2] */ -+ unsigned int cmp_mode : 1; /* [3] */ -+ unsigned int source_mode : 3; /* [6..4] */ -+ unsigned int tpred_en : 1; /* [7] */ -+ unsigned int reserved_0 : 24; /* [31..8] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_osd_glb_info; -+ -+/* define the union reg_gfx_osd_frame_size */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int frame_width : 13; /* [12..0] */ -+ unsigned int reserved_0 : 3; /* [15..13] */ -+ unsigned int frame_height : 13; /* [28..16] */ -+ unsigned int reserved_1 : 3; /* [31..29] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_osd_frame_size; -+ -+/* define the union reg_gfx_osd_dbg_reg */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 30; /* [29..0] */ -+ unsigned int dcmp_err0 : 1; /* [30] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_osd_dbg_reg; -+ -+/* define the union reg_gfx_osd_dbg_reg1 */ -+typedef union { -+ /* define the struct bits */ -+ struct { -+ unsigned int reserved_0 : 30; /* [29..0] */ -+ unsigned int dcmp_err1 : 1; /* [30] */ -+ unsigned int reserved_1 : 1; /* [31] */ -+ } bits; -+ -+ /* define an unsigned member */ -+ unsigned int u32; -+} reg_gfx_osd_dbg_reg1; -+ -+// ============================================================================== -+/* define the global struct */ -+typedef struct { -+ volatile reg_voctrl voctrl; /* 0x0 */ -+ volatile reg_vointsta vointsta; /* 0x4 */ -+ volatile reg_vomskintsta vomskintsta; /* 0x8 */ -+ volatile reg_vointmsk vointmsk; /* 0xc */ -+ volatile reg_vodebug vodebug; /* 0x10 */ -+ volatile reg_vointsta1 vointsta1; /* 0x14 */ -+ volatile reg_vomskintsta1 vomskintsta1; /* 0x18 */ -+ volatile reg_vointmsk1 vointmsk1; /* 0x1c */ -+ volatile unsigned int vdpversion1; /* 0x20 */ -+ volatile unsigned int vdpversion2; /* 0x24 */ -+ volatile reg_volowpower_ctrl volowpower_ctrl; /* 0x28 */ -+ volatile reg_voufsta voufsta; /* 0x2c */ -+ volatile reg_voufclr voufclr; /* 0x30 */ -+ volatile reg_vointproc_tim vointproc_tim; /* 0x34 */ -+ volatile unsigned int vofpgatest; /* 0x38 */ -+ volatile unsigned int reserved_0[3]; /* 0x3c~0x44 3 regs */ -+ volatile reg_volowpower_ctrl1 volowpower_ctrl1; /* 0x48 */ -+ volatile reg_vofpgadef vofpgadef; /* 0x4c */ -+ volatile reg_volowpower_ctrl2 volowpower_ctrl2; /* 0x50 */ -+ volatile reg_volowpower_ctrl3 volowpower_ctrl3; /* 0x54 */ -+ volatile unsigned int reserved_1[43]; /* 0x58~0x100 43 regs */ -+ volatile reg_vomux_dac vomux_dac; /* 0x104 */ -+ volatile reg_vomux_testsync vomux_testsync; /* 0x108 */ -+ volatile reg_vomux_testdata vomux_testdata; /* 0x10c */ -+ volatile unsigned int reserved_2[4]; /* 0x110~0x11c 4 regs */ -+ volatile reg_vo_dac_ctrl vo_dac_ctrl; /* 0x120 */ -+ volatile reg_vo_dac_otp vo_dac_otp; /* 0x124 */ -+ volatile unsigned int reserved_3[2]; /* 0x128~0x12c 2 regs */ -+ volatile reg_vo_dac0_ctrl vo_dac0_ctrl; /* 0x130 */ -+ volatile reg_vo_dac1_ctrl vo_dac1_ctrl; /* 0x134 */ -+ volatile reg_vo_dac2_ctrl vo_dac2_ctrl; /* 0x138 */ -+ volatile reg_vo_dac3_ctrl vo_dac3_ctrl; /* 0x13c */ -+ volatile reg_vo_dac_stat0 vo_dac_stat0; /* 0x140 */ -+ volatile unsigned int reserved_4[111]; /* 0x144~0x2fc 111 regs */ -+ volatile reg_cbm_bkg1 cbm_bkg1; /* 0x300 */ -+ volatile unsigned int reserved_5; /* 0x304 */ -+ volatile reg_cbm_mix1 cbm_mix1; /* 0x308 */ -+ volatile unsigned int reserved_6[14]; /* 0x30c~0x340 14 regs */ -+ volatile reg_wbc_bmp_thd wbc_bmp_thd; /* 0x344 */ -+ volatile unsigned int reserved_7[2]; /* 0x348~0x34c 2 regs */ -+ volatile unsigned int cbm1_lay0_debug; /* 0x350 */ -+ volatile unsigned int cbm1_lay1_debug; /* 0x354 */ -+ volatile unsigned int cbm1_lay2_debug; /* 0x358 */ -+ volatile unsigned int cbm1_lay3_debug; /* 0x35c */ -+ volatile unsigned int cbm1_lay4_debug; /* 0x360 */ -+ volatile unsigned int cbm1_lay0_last_debug; /* 0x364 */ -+ volatile unsigned int cbm1_lay1_last_debug; /* 0x368 */ -+ volatile unsigned int cbm1_lay2_last_debug; /* 0x36c */ -+ volatile unsigned int cbm1_lay3_last_debug; /* 0x370 */ -+ volatile unsigned int cbm1_lay4_last_debug; /* 0x374 */ -+ volatile unsigned int reserved_8[2]; /* 0x378~0x37c 2 regs */ -+ volatile reg_cbm_bkg2 cbm_bkg2; /* 0x380 */ -+ volatile unsigned int reserved_9; /* 0x384 */ -+ volatile reg_cbm_mix2 cbm_mix2; /* 0x388 */ -+ volatile unsigned int reserved_10[14]; /* 0x38c~0x3c0 14 regs */ -+ volatile reg_hc_bmp_thd hc_bmp_thd; /* 0x3c4 */ -+ volatile unsigned int reserved_11[2]; /* 0x3c8~0x3cc 2 regs */ -+ volatile unsigned int cbm2_lay0_debug; /* 0x3d0 */ -+ volatile unsigned int cbm2_lay1_debug; /* 0x3d4 */ -+ volatile unsigned int cbm2_lay2_debug; /* 0x3d8 */ -+ volatile unsigned int cbm2_lay3_debug; /* 0x3dc */ -+ volatile unsigned int cbm2_lay4_debug; /* 0x3e0 */ -+ volatile unsigned int cbm2_lay0_last_debug; /* 0x3e4 */ -+ volatile unsigned int cbm2_lay1_last_debug; /* 0x3e8 */ -+ volatile unsigned int cbm2_lay2_last_debug; /* 0x3ec */ -+ volatile unsigned int cbm2_lay3_last_debug; /* 0x3f0 */ -+ volatile unsigned int cbm2_lay4_last_debug; /* 0x3f4 */ -+ volatile unsigned int reserved_12[2]; /* 0x3f8~0x3fc 2 regs */ -+ volatile reg_cbm_bkg3 cbm_bkg3; /* 0x400 */ -+ volatile unsigned int reserved_13; /* 0x404 */ -+ volatile reg_cbm_mix3 cbm_mix3; /* 0x408 */ -+ volatile unsigned int reserved_14[17]; /* 0x40c~0x44c 17 regs */ -+ volatile unsigned int cbm3_lay0_debug; /* 0x450 */ -+ volatile unsigned int cbm3_lay1_debug; /* 0x454 */ -+ volatile unsigned int cbm3_lay2_debug; /* 0x458 */ -+ volatile unsigned int cbm3_lay3_debug; /* 0x45c */ -+ volatile unsigned int cbm3_lay4_debug; /* 0x460 */ -+ volatile unsigned int cbm3_lay0_last_debug; /* 0x464 */ -+ volatile unsigned int cbm3_lay1_last_debug; /* 0x468 */ -+ volatile unsigned int cbm3_lay2_last_debug; /* 0x46c */ -+ volatile unsigned int cbm3_lay3_last_debug; /* 0x470 */ -+ volatile unsigned int cbm3_lay4_last_debug; /* 0x474 */ -+ volatile unsigned int reserved_15[98]; /* 0x478~0x5fc 98 regs */ -+ volatile reg_mixv0_bkg mixv0_bkg; /* 0x600 */ -+ volatile unsigned int reserved_16; /* 0x604 */ -+ volatile reg_mixv0_mix mixv0_mix; /* 0x608 */ -+ volatile unsigned int reserved_17[189]; /* 0x60c~0x8fc 189 regs */ -+ volatile reg_mixg0_bkg mixg0_bkg; /* 0x900 */ -+ volatile reg_mixg0_bkalpha mixg0_bkalpha; /* 0x904 */ -+ volatile reg_mixg0_mix mixg0_mix; /* 0x908 */ -+ volatile unsigned int reserved_18[189]; /* 0x90c~0xbfc 189 regs */ -+ volatile reg_link_ctrl link_ctrl; /* 0xc00 */ -+ volatile unsigned int reserved_19[63]; /* 0xc04~0xcfc 63 regs */ -+ volatile reg_vpss_ctrl vpss_ctrl; /* 0xd00 */ -+ volatile reg_vpss_miscellaneous vpss_miscellaneous; /* 0xd04 */ -+ volatile reg_vpss_ftconfig vpss_ftconfig; /* 0xd08 */ -+ volatile unsigned int reserved_20[5]; /* 0xd0c~0xd1c 5 regs */ -+ volatile unsigned int vpss_version; /* 0xd20 */ -+ volatile unsigned int vpss_debug0; /* 0xd24 */ -+ volatile unsigned int vpss_debug1; /* 0xd28 */ -+ volatile unsigned int vpss_debug2; /* 0xd2c */ -+ volatile unsigned int vpss_debug3; /* 0xd30 */ -+ volatile unsigned int vpss_debug4; /* 0xd34 */ -+ volatile unsigned int vpss_debug5; /* 0xd38 */ -+ volatile unsigned int vpss_debug6; /* 0xd3c */ -+ volatile unsigned int reserved_21[48]; /* 0xd40~0xdfc 48 regs */ -+ volatile unsigned int para_haddr_vhd_chn00; /* 0xe00 */ -+ volatile unsigned int para_addr_vhd_chn00; /* 0xe04 */ -+ volatile unsigned int para_haddr_vhd_chn01; /* 0xe08 */ -+ volatile unsigned int para_addr_vhd_chn01; /* 0xe0c */ -+ volatile unsigned int para_haddr_vhd_chn02; /* 0xe10 */ -+ volatile unsigned int para_addr_vhd_chn02; /* 0xe14 */ -+ volatile unsigned int para_haddr_vhd_chn03; /* 0xe18 */ -+ volatile unsigned int para_addr_vhd_chn03; /* 0xe1c */ -+ volatile unsigned int para_haddr_vhd_chn04; /* 0xe20 */ -+ volatile unsigned int para_addr_vhd_chn04; /* 0xe24 */ -+ volatile unsigned int para_haddr_vhd_chn05; /* 0xe28 */ -+ volatile unsigned int para_addr_vhd_chn05; /* 0xe2c */ -+ volatile unsigned int para_haddr_vhd_chn06; /* 0xe30 */ -+ volatile unsigned int para_addr_vhd_chn06; /* 0xe34 */ -+ volatile unsigned int para_haddr_vhd_chn07; /* 0xe38 */ -+ volatile unsigned int para_addr_vhd_chn07; /* 0xe3c */ -+ volatile unsigned int para_haddr_vhd_chn08; /* 0xe40 */ -+ volatile unsigned int para_addr_vhd_chn08; /* 0xe44 */ -+ volatile unsigned int para_haddr_vhd_chn09; /* 0xe48 */ -+ volatile unsigned int para_addr_vhd_chn09; /* 0xe4c */ -+ volatile unsigned int para_haddr_vhd_chn10; /* 0xe50 */ -+ volatile unsigned int para_addr_vhd_chn10; /* 0xe54 */ -+ volatile unsigned int para_haddr_vhd_chn11; /* 0xe58 */ -+ volatile unsigned int para_addr_vhd_chn11; /* 0xe5c */ -+ volatile unsigned int para_haddr_vhd_chn12; /* 0xe60 */ -+ volatile unsigned int para_addr_vhd_chn12; /* 0xe64 */ -+ volatile unsigned int para_haddr_vhd_chn13; /* 0xe68 */ -+ volatile unsigned int para_addr_vhd_chn13; /* 0xe6c */ -+ volatile unsigned int para_haddr_vhd_chn14; /* 0xe70 */ -+ volatile unsigned int para_addr_vhd_chn14; /* 0xe74 */ -+ volatile unsigned int para_haddr_vhd_chn15; /* 0xe78 */ -+ volatile unsigned int para_addr_vhd_chn15; /* 0xe7c */ -+ volatile unsigned int para_haddr_vhd_chn16; /* 0xe80 */ -+ volatile unsigned int para_addr_vhd_chn16; /* 0xe84 */ -+ volatile unsigned int para_haddr_vhd_chn17; /* 0xe88 */ -+ volatile unsigned int para_addr_vhd_chn17; /* 0xe8c */ -+ volatile unsigned int para_haddr_vhd_chn18; /* 0xe90 */ -+ volatile unsigned int para_addr_vhd_chn18; /* 0xe94 */ -+ volatile unsigned int para_haddr_vhd_chn19; /* 0xe98 */ -+ volatile unsigned int para_addr_vhd_chn19; /* 0xe9c */ -+ volatile unsigned int para_haddr_vhd_chn20; /* 0xea0 */ -+ volatile unsigned int para_addr_vhd_chn20; /* 0xea4 */ -+ volatile unsigned int para_haddr_vhd_chn21; /* 0xea8 */ -+ volatile unsigned int para_addr_vhd_chn21; /* 0xeac */ -+ volatile unsigned int para_haddr_vhd_chn22; /* 0xeb0 */ -+ volatile unsigned int para_addr_vhd_chn22; /* 0xeb4 */ -+ volatile unsigned int para_haddr_vhd_chn23; /* 0xeb8 */ -+ volatile unsigned int para_addr_vhd_chn23; /* 0xebc */ -+ volatile unsigned int para_haddr_vhd_chn24; /* 0xec0 */ -+ volatile unsigned int para_addr_vhd_chn24; /* 0xec4 */ -+ volatile unsigned int para_haddr_vhd_chn25; /* 0xec8 */ -+ volatile unsigned int para_addr_vhd_chn25; /* 0xecc */ -+ volatile unsigned int para_haddr_vhd_chn26; /* 0xed0 */ -+ volatile unsigned int para_addr_vhd_chn26; /* 0xed4 */ -+ volatile unsigned int para_haddr_vhd_chn27; /* 0xed8 */ -+ volatile unsigned int para_addr_vhd_chn27; /* 0xedc */ -+ volatile unsigned int para_haddr_vhd_chn28; /* 0xee0 */ -+ volatile unsigned int para_addr_vhd_chn28; /* 0xee4 */ -+ volatile unsigned int para_haddr_vhd_chn29; /* 0xee8 */ -+ volatile unsigned int para_addr_vhd_chn29; /* 0xeec */ -+ volatile unsigned int para_haddr_vhd_chn30; /* 0xef0 */ -+ volatile unsigned int para_addr_vhd_chn30; /* 0xef4 */ -+ volatile unsigned int para_haddr_vhd_chn31; /* 0xef8 */ -+ volatile unsigned int para_addr_vhd_chn31; /* 0xefc */ -+ volatile reg_para_up_vhd para_up_vhd; /* 0xf00 */ -+ volatile unsigned int para_haddr_vsd_chn00; /* 0xf04 */ -+ volatile unsigned int para_addr_vsd_chn00; /* 0xf08 */ -+ volatile unsigned int para_haddr_vsd_chn01; /* 0xf0c */ -+ volatile unsigned int para_addr_vsd_chn01; /* 0xf10 */ -+ volatile unsigned int para_haddr_vsd_chn02; /* 0xf14 */ -+ volatile unsigned int para_addr_vsd_chn02; /* 0xf18 */ -+ volatile unsigned int para_haddr_vsd_chn03; /* 0xf1c */ -+ volatile unsigned int para_addr_vsd_chn03; /* 0xf20 */ -+ volatile unsigned int para_haddr_vsd_chn04; /* 0xf24 */ -+ volatile unsigned int para_addr_vsd_chn04; /* 0xf28 */ -+ volatile unsigned int para_haddr_vsd_chn05; /* 0xf2c */ -+ volatile unsigned int para_addr_vsd_chn05; /* 0xf30 */ -+ volatile unsigned int para_haddr_vsd_chn06; /* 0xf34 */ -+ volatile unsigned int para_addr_vsd_chn06; /* 0xf38 */ -+ volatile unsigned int para_haddr_vsd_chn07; /* 0xf3c */ -+ volatile unsigned int para_addr_vsd_chn07; /* 0xf40 */ -+ volatile reg_para_up_vsd para_up_vsd; /* 0xf44 */ -+ volatile reg_para_conflict_clr para_conflict_clr; /* 0xf48 */ -+ volatile reg_para_conflict_sta para_conflict_sta; /* 0xf4c */ -+ volatile unsigned int reserved_22[44]; /* 0xf50~0xffc 44 regs */ -+ volatile reg_v0_ctrl v0_ctrl; /* 0x1000 */ -+ volatile reg_v0_upd v0_upd; /* 0x1004 */ -+ volatile reg_v0_0reso_read v0_0reso_read; /* 0x1008 */ -+ volatile unsigned int reserved_23; /* 0x100c */ -+ volatile reg_v0_ireso v0_ireso; /* 0x1010 */ -+ volatile unsigned int reserved_24[27]; /* 0x1014~0x107c 27 regs */ -+ volatile reg_v0_dfpos v0_dfpos; /* 0x1080 */ -+ volatile reg_v0_dlpos v0_dlpos; /* 0x1084 */ -+ volatile reg_v0_vfpos v0_vfpos; /* 0x1088 */ -+ volatile reg_v0_vlpos v0_vlpos; /* 0x108c */ -+ volatile reg_v0_bk v0_bk; /* 0x1090 */ -+ volatile reg_v0_alpha v0_alpha; /* 0x1094 */ -+ volatile reg_v0_mute_bk v0_mute_bk; /* 0x1098 */ -+ volatile unsigned int reserved_25; /* 0x109c */ -+ volatile reg_v0_rimwidth v0_rimwidth; /* 0x10a0 */ -+ volatile reg_v0_rimcol0 v0_rimcol0; /* 0x10a4 */ -+ volatile reg_v0_rimcol1 v0_rimcol1; /* 0x10a8 */ -+ volatile unsigned int reserved_26[85]; /* 0x10ac~0x11fc 85 regs */ -+ volatile reg_v0_ot_pp_csc_ctrl v0_ot_pp_csc_ctrl; /* 0x1200 */ -+ volatile reg_v0_ot_pp_csc_coef00 v0_ot_pp_csc_coef00; /* 0x1204 */ -+ volatile reg_v0_ot_pp_csc_coef01 v0_ot_pp_csc_coef01; /* 0x1208 */ -+ volatile reg_v0_ot_pp_csc_coef02 v0_ot_pp_csc_coef02; /* 0x120c */ -+ volatile reg_v0_ot_pp_csc_coef10 v0_ot_pp_csc_coef10; /* 0x1210 */ -+ volatile reg_v0_ot_pp_csc_coef11 v0_ot_pp_csc_coef11; /* 0x1214 */ -+ volatile reg_v0_ot_pp_csc_coef12 v0_ot_pp_csc_coef12; /* 0x1218 */ -+ volatile reg_v0_ot_pp_csc_coef20 v0_ot_pp_csc_coef20; /* 0x121c */ -+ volatile reg_v0_ot_pp_csc_coef21 v0_ot_pp_csc_coef21; /* 0x1220 */ -+ volatile reg_v0_ot_pp_csc_coef22 v0_ot_pp_csc_coef22; /* 0x1224 */ -+ volatile reg_v0_ot_pp_csc_scale v0_ot_pp_csc_scale; /* 0x1228 */ -+ volatile reg_v0_ot_pp_csc_idc0 v0_ot_pp_csc_idc0; /* 0x122c */ -+ volatile reg_v0_ot_pp_csc_idc1 v0_ot_pp_csc_idc1; /* 0x1230 */ -+ volatile reg_v0_ot_pp_csc_idc2 v0_ot_pp_csc_idc2; /* 0x1234 */ -+ volatile reg_v0_ot_pp_csc_odc0 v0_ot_pp_csc_odc0; /* 0x1238 */ -+ volatile reg_v0_ot_pp_csc_odc1 v0_ot_pp_csc_odc1; /* 0x123c */ -+ volatile reg_v0_ot_pp_csc_odc2 v0_ot_pp_csc_odc2; /* 0x1240 */ -+ volatile reg_v0_ot_pp_csc_min_y v0_ot_pp_csc_min_y; /* 0x1244 */ -+ volatile reg_v0_ot_pp_csc_min_c v0_ot_pp_csc_min_c; /* 0x1248 */ -+ volatile reg_v0_ot_pp_csc_max_y v0_ot_pp_csc_max_y; /* 0x124c */ -+ volatile reg_v0_ot_pp_csc_max_c v0_ot_pp_csc_max_c; /* 0x1250 */ -+ volatile reg_v0_ot_pp_csc2_coef00 v0_ot_pp_csc2_coef00; /* 0x1254 */ -+ volatile reg_v0_ot_pp_csc2_coef01 v0_ot_pp_csc2_coef01; /* 0x1258 */ -+ volatile reg_v0_ot_pp_csc2_coef02 v0_ot_pp_csc2_coef02; /* 0x125c */ -+ volatile reg_v0_ot_pp_csc2_coef10 v0_ot_pp_csc2_coef10; /* 0x1260 */ -+ volatile reg_v0_ot_pp_csc2_coef11 v0_ot_pp_csc2_coef11; /* 0x1264 */ -+ volatile reg_v0_ot_pp_csc2_coef12 v0_ot_pp_csc2_coef12; /* 0x1268 */ -+ volatile reg_v0_ot_pp_csc2_coef20 v0_ot_pp_csc2_coef20; /* 0x126c */ -+ volatile reg_v0_ot_pp_csc2_coef21 v0_ot_pp_csc2_coef21; /* 0x1270 */ -+ volatile reg_v0_ot_pp_csc2_coef22 v0_ot_pp_csc2_coef22; /* 0x1274 */ -+ volatile reg_v0_ot_pp_csc2_scale v0_ot_pp_csc2_scale; /* 0x1278 */ -+ volatile reg_v0_ot_pp_csc2_idc0 v0_ot_pp_csc2_idc0; /* 0x127c */ -+ volatile reg_v0_ot_pp_csc2_idc1 v0_ot_pp_csc2_idc1; /* 0x1280 */ -+ volatile reg_v0_ot_pp_csc2_idc2 v0_ot_pp_csc2_idc2; /* 0x1284 */ -+ volatile reg_v0_ot_pp_csc2_odc0 v0_ot_pp_csc2_odc0; /* 0x1288 */ -+ volatile reg_v0_ot_pp_csc2_odc1 v0_ot_pp_csc2_odc1; /* 0x128c */ -+ volatile reg_v0_ot_pp_csc2_odc2 v0_ot_pp_csc2_odc2; /* 0x1290 */ -+ volatile reg_v0_ot_pp_csc2_min_y v0_ot_pp_csc2_min_y; /* 0x1294 */ -+ volatile reg_v0_ot_pp_csc2_min_c v0_ot_pp_csc2_min_c; /* 0x1298 */ -+ volatile reg_v0_ot_pp_csc2_max_y v0_ot_pp_csc2_max_y; /* 0x129c */ -+ volatile reg_v0_ot_pp_csc2_max_c v0_ot_pp_csc2_max_c; /* 0x12a0 */ -+ volatile unsigned int reserved_27[19]; /* 0x12a4~0x12ec 19 regs */ -+ volatile reg_v0_ot_pp_csc_ink_ctrl v0_ot_pp_csc_ink_ctrl; /* 0x12f0 */ -+ volatile reg_v0_ot_pp_csc_ink_pos v0_ot_pp_csc_ink_pos; /* 0x12f4 */ -+ volatile unsigned int v0_ot_pp_csc_ink_data; /* 0x12f8 */ -+ volatile unsigned int v0_ot_pp_csc_ink_data2; /* 0x12fc */ -+ volatile unsigned int reserved_28[64]; /* 0x1300~0x13fc 64 regs */ -+ volatile reg_v0_cvfir_vinfo v0_cvfir_vinfo; /* 0x1400 */ -+ volatile reg_v0_cvfir_vsp v0_cvfir_vsp; /* 0x1404 */ -+ volatile reg_v0_cvfir_voffset v0_cvfir_voffset; /* 0x1408 */ -+ volatile reg_v0_cvfir_vboffset v0_cvfir_vboffset; /* 0x140c */ -+ volatile unsigned int reserved_29[8]; /* 0x1410~0x142c 8 regs */ -+ volatile reg_v0_cvfir_vcoef0 v0_cvfir_vcoef0; /* 0x1430 */ -+ volatile reg_v0_cvfir_vcoef1 v0_cvfir_vcoef1; /* 0x1434 */ -+ volatile reg_v0_cvfir_vcoef2 v0_cvfir_vcoef2; /* 0x1438 */ -+ volatile unsigned int reserved_30[49]; /* 0x143c~0x14fc 49 regs */ -+ volatile reg_v0_hfir_ctrl v0_hfir_ctrl; /* 0x1500 */ -+ volatile reg_v0_hfircoef01 v0_hfircoef01; /* 0x1504 */ -+ volatile reg_v0_hfircoef23 v0_hfircoef23; /* 0x1508 */ -+ volatile reg_v0_hfircoef45 v0_hfircoef45; /* 0x150c */ -+ volatile reg_v0_hfircoef67 v0_hfircoef67; /* 0x1510 */ -+ volatile unsigned int reserved_31[699]; /* 0x1514~0x1ffc 699 regs */ -+ volatile reg_v1_ctrl v1_ctrl; /* 0x2000 */ -+ volatile reg_v1_upd v1_upd; /* 0x2004 */ -+ volatile reg_v1_0reso_read v1_0reso_read; /* 0x2008 */ -+ volatile unsigned int reserved_32; /* 0x200c */ -+ volatile reg_v1_ireso v1_ireso; /* 0x2010 */ -+ volatile unsigned int reserved_33[27]; /* 0x2014~0x207c 27 regs */ -+ volatile reg_v1_dfpos v1_dfpos; /* 0x2080 */ -+ volatile reg_v1_dlpos v1_dlpos; /* 0x2084 */ -+ volatile reg_v1_vfpos v1_vfpos; /* 0x2088 */ -+ volatile reg_v1_vlpos v1_vlpos; /* 0x208c */ -+ volatile reg_v1_bk v1_bk; /* 0x2090 */ -+ volatile reg_v1_alpha v1_alpha; /* 0x2094 */ -+ volatile reg_v1_mute_bk v1_mute_bk; /* 0x2098 */ -+ volatile unsigned int reserved_34; /* 0x209c */ -+ volatile reg_v1_rimwidth v1_rimwidth; /* 0x20a0 */ -+ volatile reg_v1_rimcol0 v1_rimcol0; /* 0x20a4 */ -+ volatile reg_v1_rimcol1 v1_rimcol1; /* 0x20a8 */ -+ volatile unsigned int reserved_35[85]; /* 0x20ac~0x21fc 85 regs */ -+ volatile reg_v1_ot_pp_csc_ctrl v1_ot_pp_csc_ctrl; /* 0x2200 */ -+ volatile reg_v1_ot_pp_csc_coef00 v1_ot_pp_csc_coef00; /* 0x2204 */ -+ volatile reg_v1_ot_pp_csc_coef01 v1_ot_pp_csc_coef01; /* 0x2208 */ -+ volatile reg_v1_ot_pp_csc_coef02 v1_ot_pp_csc_coef02; /* 0x220c */ -+ volatile reg_v1_ot_pp_csc_coef10 v1_ot_pp_csc_coef10; /* 0x2210 */ -+ volatile reg_v1_ot_pp_csc_coef11 v1_ot_pp_csc_coef11; /* 0x2214 */ -+ volatile reg_v1_ot_pp_csc_coef12 v1_ot_pp_csc_coef12; /* 0x2218 */ -+ volatile reg_v1_ot_pp_csc_coef20 v1_ot_pp_csc_coef20; /* 0x221c */ -+ volatile reg_v1_ot_pp_csc_coef21 v1_ot_pp_csc_coef21; /* 0x2220 */ -+ volatile reg_v1_ot_pp_csc_coef22 v1_ot_pp_csc_coef22; /* 0x2224 */ -+ volatile reg_v1_ot_pp_csc_scale v1_ot_pp_csc_scale; /* 0x2228 */ -+ volatile reg_v1_ot_pp_csc_idc0 v1_ot_pp_csc_idc0; /* 0x222c */ -+ volatile reg_v1_ot_pp_csc_idc1 v1_ot_pp_csc_idc1; /* 0x2230 */ -+ volatile reg_v1_ot_pp_csc_idc2 v1_ot_pp_csc_idc2; /* 0x2234 */ -+ volatile reg_v1_ot_pp_csc_odc0 v1_ot_pp_csc_odc0; /* 0x2238 */ -+ volatile reg_v1_ot_pp_csc_odc1 v1_ot_pp_csc_odc1; /* 0x223c */ -+ volatile reg_v1_ot_pp_csc_odc2 v1_ot_pp_csc_odc2; /* 0x2240 */ -+ volatile reg_v1_ot_pp_csc_min_y v1_ot_pp_csc_min_y; /* 0x2244 */ -+ volatile reg_v1_ot_pp_csc_min_c v1_ot_pp_csc_min_c; /* 0x2248 */ -+ volatile reg_v1_ot_pp_csc_max_y v1_ot_pp_csc_max_y; /* 0x224c */ -+ volatile reg_v1_ot_pp_csc_max_c v1_ot_pp_csc_max_c; /* 0x2250 */ -+ volatile reg_v1_ot_pp_csc2_coef00 v1_ot_pp_csc2_coef00; /* 0x2254 */ -+ volatile reg_v1_ot_pp_csc2_coef01 v1_ot_pp_csc2_coef01; /* 0x2258 */ -+ volatile reg_v1_ot_pp_csc2_coef02 v1_ot_pp_csc2_coef02; /* 0x225c */ -+ volatile reg_v1_ot_pp_csc2_coef10 v1_ot_pp_csc2_coef10; /* 0x2260 */ -+ volatile reg_v1_ot_pp_csc2_coef11 v1_ot_pp_csc2_coef11; /* 0x2264 */ -+ volatile reg_v1_ot_pp_csc2_coef12 v1_ot_pp_csc2_coef12; /* 0x2268 */ -+ volatile reg_v1_ot_pp_csc2_coef20 v1_ot_pp_csc2_coef20; /* 0x226c */ -+ volatile reg_v1_ot_pp_csc2_coef21 v1_ot_pp_csc2_coef21; /* 0x2270 */ -+ volatile reg_v1_ot_pp_csc2_coef22 v1_ot_pp_csc2_coef22; /* 0x2274 */ -+ volatile reg_v1_ot_pp_csc2_scale v1_ot_pp_csc2_scale; /* 0x2278 */ -+ volatile reg_v1_ot_pp_csc2_idc0 v1_ot_pp_csc2_idc0; /* 0x227c */ -+ volatile reg_v1_ot_pp_csc2_idc1 v1_ot_pp_csc2_idc1; /* 0x2280 */ -+ volatile reg_v1_ot_pp_csc2_idc2 v1_ot_pp_csc2_idc2; /* 0x2284 */ -+ volatile reg_v1_ot_pp_csc2_odc0 v1_ot_pp_csc2_odc0; /* 0x2288 */ -+ volatile reg_v1_ot_pp_csc2_odc1 v1_ot_pp_csc2_odc1; /* 0x228c */ -+ volatile reg_v1_ot_pp_csc2_odc2 v1_ot_pp_csc2_odc2; /* 0x2290 */ -+ volatile reg_v1_ot_pp_csc2_min_y v1_ot_pp_csc2_min_y; /* 0x2294 */ -+ volatile reg_v1_ot_pp_csc2_min_c v1_ot_pp_csc2_min_c; /* 0x2298 */ -+ volatile reg_v1_ot_pp_csc2_max_y v1_ot_pp_csc2_max_y; /* 0x229c */ -+ volatile reg_v1_ot_pp_csc2_max_c v1_ot_pp_csc2_max_c; /* 0x22a0 */ -+ volatile unsigned int reserved_36[19]; /* 0x22a4~0x22ec 19 regs */ -+ volatile reg_v1_ot_pp_csc_ink_ctrl v1_ot_pp_csc_ink_ctrl; /* 0x22f0 */ -+ volatile reg_v1_ot_pp_csc_ink_pos v1_ot_pp_csc_ink_pos; /* 0x22f4 */ -+ volatile unsigned int v1_ot_pp_csc_ink_data; /* 0x22f8 */ -+ volatile unsigned int v1_ot_pp_csc_ink_data2; /* 0x22fc */ -+ volatile unsigned int reserved_37[64]; /* 0x2300~0x23fc 64 regs */ -+ volatile reg_v1_cvfir_vinfo v1_cvfir_vinfo; /* 0x2400 */ -+ volatile reg_v1_cvfir_vsp v1_cvfir_vsp; /* 0x2404 */ -+ volatile reg_v1_cvfir_voffset v1_cvfir_voffset; /* 0x2408 */ -+ volatile reg_v1_cvfir_vboffset v1_cvfir_vboffset; /* 0x240c */ -+ volatile unsigned int reserved_38[8]; /* 0x2410~0x242c 8 regs */ -+ volatile reg_v1_cvfir_vcoef0 v1_cvfir_vcoef0; /* 0x2430 */ -+ volatile reg_v1_cvfir_vcoef1 v1_cvfir_vcoef1; /* 0x2434 */ -+ volatile reg_v1_cvfir_vcoef2 v1_cvfir_vcoef2; /* 0x2438 */ -+ volatile unsigned int reserved_39[49]; /* 0x243c~0x24fc 49 regs */ -+ volatile reg_v1_hfir_ctrl v1_hfir_ctrl; /* 0x2500 */ -+ volatile reg_v1_hfircoef01 v1_hfircoef01; /* 0x2504 */ -+ volatile reg_v1_hfircoef23 v1_hfircoef23; /* 0x2508 */ -+ volatile reg_v1_hfircoef45 v1_hfircoef45; /* 0x250c */ -+ volatile reg_v1_hfircoef67 v1_hfircoef67; /* 0x2510 */ -+ volatile unsigned int reserved_40[699]; /* 0x2514~0x2ffc 699 regs */ -+ volatile reg_v2_ctrl v2_ctrl; /* 0x3000 */ -+ volatile reg_v2_upd v2_upd; /* 0x3004 */ -+ volatile reg_v2_0reso_read v2_0reso_read; /* 0x3008 */ -+ volatile unsigned int reserved_41; /* 0x300c */ -+ volatile reg_v2_ireso v2_ireso; /* 0x3010 */ -+ volatile unsigned int reserved_42[27]; /* 0x3014~0x307c 27 regs */ -+ volatile reg_v2_dfpos v2_dfpos; /* 0x3080 */ -+ volatile reg_v2_dlpos v2_dlpos; /* 0x3084 */ -+ volatile reg_v2_vfpos v2_vfpos; /* 0x3088 */ -+ volatile reg_v2_vlpos v2_vlpos; /* 0x308c */ -+ volatile reg_v2_bk v2_bk; /* 0x3090 */ -+ volatile reg_v2_alpha v2_alpha; /* 0x3094 */ -+ volatile reg_v2_mute_bk v2_mute_bk; /* 0x3098 */ -+ volatile unsigned int reserved_43[89]; /* 0x309c~0x31fc 89 regs */ -+ volatile reg_v2_ot_pp_csc_ctrl v2_ot_pp_csc_ctrl; /* 0x3200 */ -+ volatile reg_v2_ot_pp_csc_coef00 v2_ot_pp_csc_coef00; /* 0x3204 */ -+ volatile reg_v2_ot_pp_csc_coef01 v2_ot_pp_csc_coef01; /* 0x3208 */ -+ volatile reg_v2_ot_pp_csc_coef02 v2_ot_pp_csc_coef02; /* 0x320c */ -+ volatile reg_v2_ot_pp_csc_coef10 v2_ot_pp_csc_coef10; /* 0x3210 */ -+ volatile reg_v2_ot_pp_csc_coef11 v2_ot_pp_csc_coef11; /* 0x3214 */ -+ volatile reg_v2_ot_pp_csc_coef12 v2_ot_pp_csc_coef12; /* 0x3218 */ -+ volatile reg_v2_ot_pp_csc_coef20 v2_ot_pp_csc_coef20; /* 0x321c */ -+ volatile reg_v2_ot_pp_csc_coef21 v2_ot_pp_csc_coef21; /* 0x3220 */ -+ volatile reg_v2_ot_pp_csc_coef22 v2_ot_pp_csc_coef22; /* 0x3224 */ -+ volatile reg_v2_ot_pp_csc_scale v2_ot_pp_csc_scale; /* 0x3228 */ -+ volatile reg_v2_ot_pp_csc_idc0 v2_ot_pp_csc_idc0; /* 0x322c */ -+ volatile reg_v2_ot_pp_csc_idc1 v2_ot_pp_csc_idc1; /* 0x3230 */ -+ volatile reg_v2_ot_pp_csc_idc2 v2_ot_pp_csc_idc2; /* 0x3234 */ -+ volatile reg_v2_ot_pp_csc_odc0 v2_ot_pp_csc_odc0; /* 0x3238 */ -+ volatile reg_v2_ot_pp_csc_odc1 v2_ot_pp_csc_odc1; /* 0x323c */ -+ volatile reg_v2_ot_pp_csc_odc2 v2_ot_pp_csc_odc2; /* 0x3240 */ -+ volatile reg_v2_ot_pp_csc_min_y v2_ot_pp_csc_min_y; /* 0x3244 */ -+ volatile reg_v2_ot_pp_csc_min_c v2_ot_pp_csc_min_c; /* 0x3248 */ -+ volatile reg_v2_ot_pp_csc_max_y v2_ot_pp_csc_max_y; /* 0x324c */ -+ volatile reg_v2_ot_pp_csc_max_c v2_ot_pp_csc_max_c; /* 0x3250 */ -+ volatile reg_v2_ot_pp_csc2_coef00 v2_ot_pp_csc2_coef00; /* 0x3254 */ -+ volatile reg_v2_ot_pp_csc2_coef01 v2_ot_pp_csc2_coef01; /* 0x3258 */ -+ volatile reg_v2_ot_pp_csc2_coef02 v2_ot_pp_csc2_coef02; /* 0x325c */ -+ volatile reg_v2_ot_pp_csc2_coef10 v2_ot_pp_csc2_coef10; /* 0x3260 */ -+ volatile reg_v2_ot_pp_csc2_coef11 v2_ot_pp_csc2_coef11; /* 0x3264 */ -+ volatile reg_v2_ot_pp_csc2_coef12 v2_ot_pp_csc2_coef12; /* 0x3268 */ -+ volatile reg_v2_ot_pp_csc2_coef20 v2_ot_pp_csc2_coef20; /* 0x326c */ -+ volatile reg_v2_ot_pp_csc2_coef21 v2_ot_pp_csc2_coef21; /* 0x3270 */ -+ volatile reg_v2_ot_pp_csc2_coef22 v2_ot_pp_csc2_coef22; /* 0x3274 */ -+ volatile reg_v2_ot_pp_csc2_scale v2_ot_pp_csc2_scale; /* 0x3278 */ -+ volatile reg_v2_ot_pp_csc2_idc0 v2_ot_pp_csc2_idc0; /* 0x327c */ -+ volatile reg_v2_ot_pp_csc2_idc1 v2_ot_pp_csc2_idc1; /* 0x3280 */ -+ volatile reg_v2_ot_pp_csc2_idc2 v2_ot_pp_csc2_idc2; /* 0x3284 */ -+ volatile reg_v2_ot_pp_csc2_odc0 v2_ot_pp_csc2_odc0; /* 0x3288 */ -+ volatile reg_v2_ot_pp_csc2_odc1 v2_ot_pp_csc2_odc1; /* 0x328c */ -+ volatile reg_v2_ot_pp_csc2_odc2 v2_ot_pp_csc2_odc2; /* 0x3290 */ -+ volatile reg_v2_ot_pp_csc2_min_y v2_ot_pp_csc2_min_y; /* 0x3294 */ -+ volatile reg_v2_ot_pp_csc2_min_c v2_ot_pp_csc2_min_c; /* 0x3298 */ -+ volatile reg_v2_ot_pp_csc2_max_y v2_ot_pp_csc2_max_y; /* 0x329c */ -+ volatile reg_v2_ot_pp_csc2_max_c v2_ot_pp_csc2_max_c; /* 0x32a0 */ -+ volatile unsigned int reserved_44[19]; /* 0x32a4~0x32ec 19 regs */ -+ volatile reg_v2_ot_pp_csc_ink_ctrl v2_ot_pp_csc_ink_ctrl; /* 0x32f0 */ -+ volatile reg_v2_ot_pp_csc_ink_pos v2_ot_pp_csc_ink_pos; /* 0x32f4 */ -+ volatile unsigned int v2_ot_pp_csc_ink_data; /* 0x32f8 */ -+ volatile unsigned int v2_ot_pp_csc_ink_data2; /* 0x32fc */ -+ volatile unsigned int reserved_45[64]; /* 0x3300~0x33fc 64 regs */ -+ volatile reg_v2_cvfir_vinfo v2_cvfir_vinfo; /* 0x3400 */ -+ volatile reg_v2_cvfir_vsp v2_cvfir_vsp; /* 0x3404 */ -+ volatile reg_v2_cvfir_voffset v2_cvfir_voffset; /* 0x3408 */ -+ volatile reg_v2_cvfir_vboffset v2_cvfir_vboffset; /* 0x340c */ -+ volatile unsigned int reserved_46[8]; /* 0x3410~0x342c 8 regs */ -+ volatile reg_v2_cvfir_vcoef0 v2_cvfir_vcoef0; /* 0x3430 */ -+ volatile reg_v2_cvfir_vcoef1 v2_cvfir_vcoef1; /* 0x3434 */ -+ volatile reg_v2_cvfir_vcoef2 v2_cvfir_vcoef2; /* 0x3438 */ -+ volatile unsigned int reserved_47[49]; /* 0x343c~0x34fc 49 regs */ -+ volatile reg_v2_hfir_ctrl v2_hfir_ctrl; /* 0x3500 */ -+ volatile reg_v2_hfircoef01 v2_hfircoef01; /* 0x3504 */ -+ volatile reg_v2_hfircoef23 v2_hfircoef23; /* 0x3508 */ -+ volatile reg_v2_hfircoef45 v2_hfircoef45; /* 0x350c */ -+ volatile reg_v2_hfircoef67 v2_hfircoef67; /* 0x3510 */ -+ volatile unsigned int reserved_48[699]; /* 0x3514~0x3ffc 699 regs */ -+ volatile reg_v3_ctrl v3_ctrl; /* 0x4000 */ -+ volatile reg_v3_upd v3_upd; /* 0x4004 */ -+ volatile reg_v3_0reso_read v3_0reso_read; /* 0x4008 */ -+ volatile unsigned int reserved_49; /* 0x400c */ -+ volatile reg_v3_ireso v3_ireso; /* 0x4010 */ -+ volatile unsigned int reserved_50[27]; /* 0x4014~0x407c 27 regs */ -+ volatile reg_v3_dfpos v3_dfpos; /* 0x4080 */ -+ volatile reg_v3_dlpos v3_dlpos; /* 0x4084 */ -+ volatile reg_v3_vfpos v3_vfpos; /* 0x4088 */ -+ volatile reg_v3_vlpos v3_vlpos; /* 0x408c */ -+ volatile reg_v3_bk v3_bk; /* 0x4090 */ -+ volatile reg_v3_alpha v3_alpha; /* 0x4094 */ -+ volatile reg_v3_mute_bk v3_mute_bk; /* 0x4098 */ -+ volatile unsigned int reserved_51; /* 0x409c */ -+ volatile reg_v3_rimwidth v3_rimwidth; /* 0x40a0 */ -+ volatile reg_v3_rimcol0 v3_rimcol0; /* 0x40a4 */ -+ volatile reg_v3_rimcol1 v3_rimcol1; /* 0x40a8 */ -+ volatile unsigned int reserved_52[85]; /* 0x40ac~0x41fc 85 regs */ -+ volatile reg_v3_ot_pp_csc_ctrl v3_ot_pp_csc_ctrl; /* 0x4200 */ -+ volatile reg_v3_ot_pp_csc_coef00 v3_ot_pp_csc_coef00; /* 0x4204 */ -+ volatile reg_v3_ot_pp_csc_coef01 v3_ot_pp_csc_coef01; /* 0x4208 */ -+ volatile reg_v3_ot_pp_csc_coef02 v3_ot_pp_csc_coef02; /* 0x420c */ -+ volatile reg_v3_ot_pp_csc_coef10 v3_ot_pp_csc_coef10; /* 0x4210 */ -+ volatile reg_v3_ot_pp_csc_coef11 v3_ot_pp_csc_coef11; /* 0x4214 */ -+ volatile reg_v3_ot_pp_csc_coef12 v3_ot_pp_csc_coef12; /* 0x4218 */ -+ volatile reg_v3_ot_pp_csc_coef20 v3_ot_pp_csc_coef20; /* 0x421c */ -+ volatile reg_v3_ot_pp_csc_coef21 v3_ot_pp_csc_coef21; /* 0x4220 */ -+ volatile reg_v3_ot_pp_csc_coef22 v3_ot_pp_csc_coef22; /* 0x4224 */ -+ volatile reg_v3_ot_pp_csc_scale v3_ot_pp_csc_scale; /* 0x4228 */ -+ volatile reg_v3_ot_pp_csc_idc0 v3_ot_pp_csc_idc0; /* 0x422c */ -+ volatile reg_v3_ot_pp_csc_idc1 v3_ot_pp_csc_idc1; /* 0x4230 */ -+ volatile reg_v3_ot_pp_csc_idc2 v3_ot_pp_csc_idc2; /* 0x4234 */ -+ volatile reg_v3_ot_pp_csc_odc0 v3_ot_pp_csc_odc0; /* 0x4238 */ -+ volatile reg_v3_ot_pp_csc_odc1 v3_ot_pp_csc_odc1; /* 0x423c */ -+ volatile reg_v3_ot_pp_csc_odc2 v3_ot_pp_csc_odc2; /* 0x4240 */ -+ volatile reg_v3_ot_pp_csc_min_y v3_ot_pp_csc_min_y; /* 0x4244 */ -+ volatile reg_v3_ot_pp_csc_min_c v3_ot_pp_csc_min_c; /* 0x4248 */ -+ volatile reg_v3_ot_pp_csc_max_y v3_ot_pp_csc_max_y; /* 0x424c */ -+ volatile reg_v3_ot_pp_csc_max_c v3_ot_pp_csc_max_c; /* 0x4250 */ -+ volatile reg_v3_ot_pp_csc2_coef00 v3_ot_pp_csc2_coef00; /* 0x4254 */ -+ volatile reg_v3_ot_pp_csc2_coef01 v3_ot_pp_csc2_coef01; /* 0x4258 */ -+ volatile reg_v3_ot_pp_csc2_coef02 v3_ot_pp_csc2_coef02; /* 0x425c */ -+ volatile reg_v3_ot_pp_csc2_coef10 v3_ot_pp_csc2_coef10; /* 0x4260 */ -+ volatile reg_v3_ot_pp_csc2_coef11 v3_ot_pp_csc2_coef11; /* 0x4264 */ -+ volatile reg_v3_ot_pp_csc2_coef12 v3_ot_pp_csc2_coef12; /* 0x4268 */ -+ volatile reg_v3_ot_pp_csc2_coef20 v3_ot_pp_csc2_coef20; /* 0x426c */ -+ volatile reg_v3_ot_pp_csc2_coef21 v3_ot_pp_csc2_coef21; /* 0x4270 */ -+ volatile reg_v3_ot_pp_csc2_coef22 v3_ot_pp_csc2_coef22; /* 0x4274 */ -+ volatile reg_v3_ot_pp_csc2_scale v3_ot_pp_csc2_scale; /* 0x4278 */ -+ volatile reg_v3_ot_pp_csc2_idc0 v3_ot_pp_csc2_idc0; /* 0x427c */ -+ volatile reg_v3_ot_pp_csc2_idc1 v3_ot_pp_csc2_idc1; /* 0x4280 */ -+ volatile reg_v3_ot_pp_csc2_idc2 v3_ot_pp_csc2_idc2; /* 0x4284 */ -+ volatile reg_v3_ot_pp_csc2_odc0 v3_ot_pp_csc2_odc0; /* 0x4288 */ -+ volatile reg_v3_ot_pp_csc2_odc1 v3_ot_pp_csc2_odc1; /* 0x428c */ -+ volatile reg_v3_ot_pp_csc2_odc2 v3_ot_pp_csc2_odc2; /* 0x4290 */ -+ volatile reg_v3_ot_pp_csc2_min_y v3_ot_pp_csc2_min_y; /* 0x4294 */ -+ volatile reg_v3_ot_pp_csc2_min_c v3_ot_pp_csc2_min_c; /* 0x4298 */ -+ volatile reg_v3_ot_pp_csc2_max_y v3_ot_pp_csc2_max_y; /* 0x429c */ -+ volatile reg_v3_ot_pp_csc2_max_c v3_ot_pp_csc2_max_c; /* 0x42a0 */ -+ volatile unsigned int reserved_53[19]; /* 0x42a4~0x42ec 19 regs */ -+ volatile reg_v3_ot_pp_csc_ink_ctrl v3_ot_pp_csc_ink_ctrl; /* 0x42f0 */ -+ volatile reg_v3_ot_pp_csc_ink_pos v3_ot_pp_csc_ink_pos; /* 0x42f4 */ -+ volatile unsigned int v3_ot_pp_csc_ink_data; /* 0x42f8 */ -+ volatile unsigned int v3_ot_pp_csc_ink_data2; /* 0x42fc */ -+ volatile unsigned int reserved_54[64]; /* 0x4300~0x43fc 64 regs */ -+ volatile reg_v3_cvfir_vinfo v3_cvfir_vinfo; /* 0x4400 */ -+ volatile reg_v3_cvfir_vsp v3_cvfir_vsp; /* 0x4404 */ -+ volatile reg_v3_cvfir_voffset v3_cvfir_voffset; /* 0x4408 */ -+ volatile reg_v3_cvfir_vboffset v3_cvfir_vboffset; /* 0x440c */ -+ volatile unsigned int reserved_55[8]; /* 0x4410~0x442c 8 regs */ -+ volatile reg_v3_cvfir_vcoef0 v3_cvfir_vcoef0; /* 0x4430 */ -+ volatile reg_v3_cvfir_vcoef1 v3_cvfir_vcoef1; /* 0x4434 */ -+ volatile reg_v3_cvfir_vcoef2 v3_cvfir_vcoef2; /* 0x4438 */ -+ volatile unsigned int reserved_56[49]; /* 0x443c~0x44fc 49 regs */ -+ volatile reg_v3_hfir_ctrl v3_hfir_ctrl; /* 0x4500 */ -+ volatile reg_v3_hfircoef01 v3_hfircoef01; /* 0x4504 */ -+ volatile reg_v3_hfircoef23 v3_hfircoef23; /* 0x4508 */ -+ volatile reg_v3_hfircoef45 v3_hfircoef45; /* 0x450c */ -+ volatile reg_v3_hfircoef67 v3_hfircoef67; /* 0x4510 */ -+ volatile unsigned int reserved_57[1211]; /* 0x4514~0x57fc 1211 regs */ -+ volatile unsigned int vp0_ctrl; /* 0x5800 */ -+ volatile reg_vp0_upd vp0_upd; /* 0x5804 */ -+ volatile reg_vp0_ireso vp0_ireso; /* 0x5808 */ -+ volatile unsigned int reserved_58[29]; /* 0x580c~0x587c 29 regs */ -+ volatile reg_vp0_lbox_ctrl vp0_lbox_ctrl; /* 0x5880 */ -+ volatile reg_vp0_galpha vp0_galpha; /* 0x5884 */ -+ volatile reg_vp0_dfpos vp0_dfpos; /* 0x5888 */ -+ volatile reg_vp0_dlpos vp0_dlpos; /* 0x588c */ -+ volatile reg_vp0_vfpos vp0_vfpos; /* 0x5890 */ -+ volatile reg_vp0_vlpos vp0_vlpos; /* 0x5894 */ -+ volatile reg_vp0_bk vp0_bk; /* 0x5898 */ -+ volatile reg_vp0_alpha vp0_alpha; /* 0x589c */ -+ volatile reg_vp0_mute_bk vp0_mute_bk; /* 0x58a0 */ -+ volatile unsigned int reserved_59[1495]; /* 0x58a4~0x6ffc 1495 regs */ -+ volatile reg_g0_ctrl g0_ctrl; /* 0x7000 */ -+ volatile reg_g0_upd g0_upd; /* 0x7004 */ -+ volatile unsigned int g0_galpha_sum; /* 0x7008 */ -+ volatile reg_g0_0reso_read g0_0reso_read; /* 0x700c */ -+ volatile reg_g0_ireso g0_ireso; /* 0x7010 */ -+ volatile unsigned int reserved_60[27]; /* 0x7014~0x707c 27 regs */ -+ volatile reg_g0_dfpos g0_dfpos; /* 0x7080 */ -+ volatile reg_g0_dlpos g0_dlpos; /* 0x7084 */ -+ volatile reg_g0_vfpos g0_vfpos; /* 0x7088 */ -+ volatile reg_g0_vlpos g0_vlpos; /* 0x708c */ -+ volatile reg_g0_bk g0_bk; /* 0x7090 */ -+ volatile reg_g0_alpha g0_alpha; /* 0x7094 */ -+ volatile reg_g0_mute_bk g0_mute_bk; /* 0x7098 */ -+ volatile reg_g0_lbox_ctrl g0_lbox_ctrl; /* 0x709c */ -+ volatile unsigned int reserved_61[24]; /* 0x70a0~0x70fc 24 regs */ -+ volatile reg_g0_ot_pp_csc_ctrl g0_ot_pp_csc_ctrl; /* 0x7100 */ -+ volatile reg_g0_ot_pp_csc_coef00 g0_ot_pp_csc_coef00; /* 0x7104 */ -+ volatile reg_g0_ot_pp_csc_coef01 g0_ot_pp_csc_coef01; /* 0x7108 */ -+ volatile reg_g0_ot_pp_csc_coef02 g0_ot_pp_csc_coef02; /* 0x710c */ -+ volatile reg_g0_ot_pp_csc_coef10 g0_ot_pp_csc_coef10; /* 0x7110 */ -+ volatile reg_g0_ot_pp_csc_coef11 g0_ot_pp_csc_coef11; /* 0x7114 */ -+ volatile reg_g0_ot_pp_csc_coef12 g0_ot_pp_csc_coef12; /* 0x7118 */ -+ volatile reg_g0_ot_pp_csc_coef20 g0_ot_pp_csc_coef20; /* 0x711c */ -+ volatile reg_g0_ot_pp_csc_coef21 g0_ot_pp_csc_coef21; /* 0x7120 */ -+ volatile reg_g0_ot_pp_csc_coef22 g0_ot_pp_csc_coef22; /* 0x7124 */ -+ volatile reg_g0_ot_pp_csc_scale g0_ot_pp_csc_scale; /* 0x7128 */ -+ volatile reg_g0_ot_pp_csc_idc0 g0_ot_pp_csc_idc0; /* 0x712c */ -+ volatile reg_g0_ot_pp_csc_idc1 g0_ot_pp_csc_idc1; /* 0x7130 */ -+ volatile reg_g0_ot_pp_csc_idc2 g0_ot_pp_csc_idc2; /* 0x7134 */ -+ volatile reg_g0_ot_pp_csc_odc0 g0_ot_pp_csc_odc0; /* 0x7138 */ -+ volatile reg_g0_ot_pp_csc_odc1 g0_ot_pp_csc_odc1; /* 0x713c */ -+ volatile reg_g0_ot_pp_csc_odc2 g0_ot_pp_csc_odc2; /* 0x7140 */ -+ volatile reg_g0_ot_pp_csc_min_y g0_ot_pp_csc_min_y; /* 0x7144 */ -+ volatile reg_g0_ot_pp_csc_min_c g0_ot_pp_csc_min_c; /* 0x7148 */ -+ volatile reg_g0_ot_pp_csc_max_y g0_ot_pp_csc_max_y; /* 0x714c */ -+ volatile reg_g0_ot_pp_csc_max_c g0_ot_pp_csc_max_c; /* 0x7150 */ -+ volatile reg_g0_ot_pp_csc2_coef00 g0_ot_pp_csc2_coef00; /* 0x7154 */ -+ volatile reg_g0_ot_pp_csc2_coef01 g0_ot_pp_csc2_coef01; /* 0x7158 */ -+ volatile reg_g0_ot_pp_csc2_coef02 g0_ot_pp_csc2_coef02; /* 0x715c */ -+ volatile reg_g0_ot_pp_csc2_coef10 g0_ot_pp_csc2_coef10; /* 0x7160 */ -+ volatile reg_g0_ot_pp_csc2_coef11 g0_ot_pp_csc2_coef11; /* 0x7164 */ -+ volatile reg_g0_ot_pp_csc2_coef12 g0_ot_pp_csc2_coef12; /* 0x7168 */ -+ volatile reg_g0_ot_pp_csc2_coef20 g0_ot_pp_csc2_coef20; /* 0x716c */ -+ volatile reg_g0_ot_pp_csc2_coef21 g0_ot_pp_csc2_coef21; /* 0x7170 */ -+ volatile reg_g0_ot_pp_csc2_coef22 g0_ot_pp_csc2_coef22; /* 0x7174 */ -+ volatile reg_g0_ot_pp_csc2_scale g0_ot_pp_csc2_scale; /* 0x7178 */ -+ volatile reg_g0_ot_pp_csc2_idc0 g0_ot_pp_csc2_idc0; /* 0x717c */ -+ volatile reg_g0_ot_pp_csc2_idc1 g0_ot_pp_csc2_idc1; /* 0x7180 */ -+ volatile reg_g0_ot_pp_csc2_idc2 g0_ot_pp_csc2_idc2; /* 0x7184 */ -+ volatile reg_g0_ot_pp_csc2_odc0 g0_ot_pp_csc2_odc0; /* 0x7188 */ -+ volatile reg_g0_ot_pp_csc2_odc1 g0_ot_pp_csc2_odc1; /* 0x718c */ -+ volatile reg_g0_ot_pp_csc2_odc2 g0_ot_pp_csc2_odc2; /* 0x7190 */ -+ volatile reg_g0_ot_pp_csc2_min_y g0_ot_pp_csc2_min_y; /* 0x7194 */ -+ volatile reg_g0_ot_pp_csc2_min_c g0_ot_pp_csc2_min_c; /* 0x7198 */ -+ volatile reg_g0_ot_pp_csc2_max_y g0_ot_pp_csc2_max_y; /* 0x719c */ -+ volatile reg_g0_ot_pp_csc2_max_c g0_ot_pp_csc2_max_c; /* 0x71a0 */ -+ volatile unsigned int reserved_62[19]; /* 0x71a4~0x71ec 19 regs */ -+ volatile reg_g0_ot_pp_csc_ink_ctrl g0_ot_pp_csc_ink_ctrl; /* 0x71f0 */ -+ volatile reg_g0_ot_pp_csc_ink_pos g0_ot_pp_csc_ink_pos; /* 0x71f4 */ -+ volatile unsigned int g0_ot_pp_csc_ink_data; /* 0x71f8 */ -+ volatile unsigned int g0_ot_pp_csc_ink_data2; /* 0x71fc */ -+ volatile reg_osb_mute_bk osb_mute_bk; /* 0x7200 */ -+ volatile reg_osb_bk_alpha osb_bk_alpha; /* 0x7204 */ -+ volatile reg_osb_coef_rd_en osb_coef_rd_en; /* 0x7208 */ -+ volatile unsigned int osb_coef_rd_addr; /* 0x720c */ -+ volatile unsigned int reserved_63[60]; /* 0x7210~0x72fc 60 regs */ -+ volatile reg_g0_zme_hinfo g0_zme_hinfo; /* 0x7300 */ -+ volatile reg_g0_zme_hsp g0_zme_hsp; /* 0x7304 */ -+ volatile reg_g0_zme_hloffset g0_zme_hloffset; /* 0x7308 */ -+ volatile reg_g0_zme_hcoffset g0_zme_hcoffset; /* 0x730c */ -+ volatile unsigned int reserved_64[5]; /* 0x7310~0x7320 5 regs */ -+ volatile reg_g0_zme_coef_ren g0_zme_coef_ren; /* 0x7324 */ -+ volatile reg_g0_zme_coef_rdata g0_zme_coef_rdata; /* 0x7328 */ -+ volatile unsigned int reserved_65[21]; /* 0x732c~0x737c 21 regs */ -+ volatile reg_g0_zme_vinfo g0_zme_vinfo; /* 0x7380 */ -+ volatile reg_g0_zme_vsp g0_zme_vsp; /* 0x7384 */ -+ volatile reg_g0_zme_voffset g0_zme_voffset; /* 0x7388 */ -+ volatile unsigned int reserved_66[285]; /* 0x738c~0x77fc 285 regs */ -+ volatile reg_g1_ctrl g1_ctrl; /* 0x7800 */ -+ volatile reg_g1_upd g1_upd; /* 0x7804 */ -+ volatile unsigned int g1_galpha_sum; /* 0x7808 */ -+ volatile reg_g1_0reso_read g1_0reso_read; /* 0x780c */ -+ volatile reg_g1_ireso g1_ireso; /* 0x7810 */ -+ volatile unsigned int reserved_67[27]; /* 0x7814~0x787c 27 regs */ -+ volatile reg_g1_dfpos g1_dfpos; /* 0x7880 */ -+ volatile reg_g1_dlpos g1_dlpos; /* 0x7884 */ -+ volatile reg_g1_vfpos g1_vfpos; /* 0x7888 */ -+ volatile reg_g1_vlpos g1_vlpos; /* 0x788c */ -+ volatile reg_g1_bk g1_bk; /* 0x7890 */ -+ volatile reg_g1_alpha g1_alpha; /* 0x7894 */ -+ volatile reg_g1_mute_bk g1_mute_bk; /* 0x7898 */ -+ volatile reg_g1_lbox_ctrl g1_lbox_ctrl; /* 0x789c */ -+ volatile unsigned int reserved_68[24]; /* 0x78a0~0x78fc 24 regs */ -+ volatile reg_g1_ot_pp_csc_ctrl g1_ot_pp_csc_ctrl; /* 0x7900 */ -+ volatile reg_g1_ot_pp_csc_coef00 g1_ot_pp_csc_coef00; /* 0x7904 */ -+ volatile reg_g1_ot_pp_csc_coef01 g1_ot_pp_csc_coef01; /* 0x7908 */ -+ volatile reg_g1_ot_pp_csc_coef02 g1_ot_pp_csc_coef02; /* 0x790c */ -+ volatile reg_g1_ot_pp_csc_coef10 g1_ot_pp_csc_coef10; /* 0x7910 */ -+ volatile reg_g1_ot_pp_csc_coef11 g1_ot_pp_csc_coef11; /* 0x7914 */ -+ volatile reg_g1_ot_pp_csc_coef12 g1_ot_pp_csc_coef12; /* 0x7918 */ -+ volatile reg_g1_ot_pp_csc_coef20 g1_ot_pp_csc_coef20; /* 0x791c */ -+ volatile reg_g1_ot_pp_csc_coef21 g1_ot_pp_csc_coef21; /* 0x7920 */ -+ volatile reg_g1_ot_pp_csc_coef22 g1_ot_pp_csc_coef22; /* 0x7924 */ -+ volatile reg_g1_ot_pp_csc_scale g1_ot_pp_csc_scale; /* 0x7928 */ -+ volatile reg_g1_ot_pp_csc_idc0 g1_ot_pp_csc_idc0; /* 0x792c */ -+ volatile reg_g1_ot_pp_csc_idc1 g1_ot_pp_csc_idc1; /* 0x7930 */ -+ volatile reg_g1_ot_pp_csc_idc2 g1_ot_pp_csc_idc2; /* 0x7934 */ -+ volatile reg_g1_ot_pp_csc_odc0 g1_ot_pp_csc_odc0; /* 0x7938 */ -+ volatile reg_g1_ot_pp_csc_odc1 g1_ot_pp_csc_odc1; /* 0x793c */ -+ volatile reg_g1_ot_pp_csc_odc2 g1_ot_pp_csc_odc2; /* 0x7940 */ -+ volatile reg_g1_ot_pp_csc_min_y g1_ot_pp_csc_min_y; /* 0x7944 */ -+ volatile reg_g1_ot_pp_csc_min_c g1_ot_pp_csc_min_c; /* 0x7948 */ -+ volatile reg_g1_ot_pp_csc_max_y g1_ot_pp_csc_max_y; /* 0x794c */ -+ volatile reg_g1_ot_pp_csc_max_c g1_ot_pp_csc_max_c; /* 0x7950 */ -+ volatile reg_g1_ot_pp_csc2_coef00 g1_ot_pp_csc2_coef00; /* 0x7954 */ -+ volatile reg_g1_ot_pp_csc2_coef01 g1_ot_pp_csc2_coef01; /* 0x7958 */ -+ volatile reg_g1_ot_pp_csc2_coef02 g1_ot_pp_csc2_coef02; /* 0x795c */ -+ volatile reg_g1_ot_pp_csc2_coef10 g1_ot_pp_csc2_coef10; /* 0x7960 */ -+ volatile reg_g1_ot_pp_csc2_coef11 g1_ot_pp_csc2_coef11; /* 0x7964 */ -+ volatile reg_g1_ot_pp_csc2_coef12 g1_ot_pp_csc2_coef12; /* 0x7968 */ -+ volatile reg_g1_ot_pp_csc2_coef20 g1_ot_pp_csc2_coef20; /* 0x796c */ -+ volatile reg_g1_ot_pp_csc2_coef21 g1_ot_pp_csc2_coef21; /* 0x7970 */ -+ volatile reg_g1_ot_pp_csc2_coef22 g1_ot_pp_csc2_coef22; /* 0x7974 */ -+ volatile reg_g1_ot_pp_csc2_scale g1_ot_pp_csc2_scale; /* 0x7978 */ -+ volatile reg_g1_ot_pp_csc2_idc0 g1_ot_pp_csc2_idc0; /* 0x797c */ -+ volatile reg_g1_ot_pp_csc2_idc1 g1_ot_pp_csc2_idc1; /* 0x7980 */ -+ volatile reg_g1_ot_pp_csc2_idc2 g1_ot_pp_csc2_idc2; /* 0x7984 */ -+ volatile reg_g1_ot_pp_csc2_odc0 g1_ot_pp_csc2_odc0; /* 0x7988 */ -+ volatile reg_g1_ot_pp_csc2_odc1 g1_ot_pp_csc2_odc1; /* 0x798c */ -+ volatile reg_g1_ot_pp_csc2_odc2 g1_ot_pp_csc2_odc2; /* 0x7990 */ -+ volatile reg_g1_ot_pp_csc2_min_y g1_ot_pp_csc2_min_y; /* 0x7994 */ -+ volatile reg_g1_ot_pp_csc2_min_c g1_ot_pp_csc2_min_c; /* 0x7998 */ -+ volatile reg_g1_ot_pp_csc2_max_y g1_ot_pp_csc2_max_y; /* 0x799c */ -+ volatile reg_g1_ot_pp_csc2_max_c g1_ot_pp_csc2_max_c; /* 0x79a0 */ -+ volatile unsigned int reserved_69[19]; /* 0x79a4~0x79ec 19 regs */ -+ volatile reg_g1_ot_pp_csc_ink_ctrl g1_ot_pp_csc_ink_ctrl; /* 0x79f0 */ -+ volatile reg_g1_ot_pp_csc_ink_pos g1_ot_pp_csc_ink_pos; /* 0x79f4 */ -+ volatile unsigned int g1_ot_pp_csc_ink_data; /* 0x79f8 */ -+ volatile unsigned int g1_ot_pp_csc_ink_data2; /* 0x79fc */ -+ volatile reg_g1_osb_mute_bk g1_osb_mute_bk; /* 0x7a00 */ -+ volatile reg_g1_osb_bk_alpha g1_osb_bk_alpha; /* 0x7a04 */ -+ volatile reg_g1_osb_coef_rd_en g1_osb_coef_rd_en; /* 0x7a08 */ -+ volatile unsigned int g1_osb_coef_rd_addr; /* 0x7a0c */ -+ volatile unsigned int reserved_70[60]; /* 0x7a10~0x7afc 60 regs */ -+ volatile reg_g1_zme_hinfo g1_zme_hinfo; /* 0x7b00 */ -+ volatile reg_g1_zme_hsp g1_zme_hsp; /* 0x7b04 */ -+ volatile reg_g1_zme_hloffset g1_zme_hloffset; /* 0x7b08 */ -+ volatile reg_g1_zme_hcoffset g1_zme_hcoffset; /* 0x7b0c */ -+ volatile unsigned int reserved_71[5]; /* 0x7b10~0x7b20 5 regs */ -+ volatile reg_g1_zme_coef_ren g1_zme_coef_ren; /* 0x7b24 */ -+ volatile reg_g1_zme_coef_rdata g1_zme_coef_rdata; /* 0x7b28 */ -+ volatile unsigned int reserved_72[21]; /* 0x7b2c~0x7b7c 21 regs */ -+ volatile reg_g1_zme_vinfo g1_zme_vinfo; /* 0x7b80 */ -+ volatile reg_g1_zme_vsp g1_zme_vsp; /* 0x7b84 */ -+ volatile reg_g1_zme_voffset g1_zme_voffset; /* 0x7b88 */ -+ volatile unsigned int reserved_73[285]; /* 0x7b8c~0x7ffc 285 regs */ -+ volatile reg_g2_ctrl g2_ctrl; /* 0x8000 */ -+ volatile reg_g2_upd g2_upd; /* 0x8004 */ -+ volatile unsigned int g2_galpha_sum; /* 0x8008 */ -+ volatile reg_g2_0reso_read g2_0reso_read; /* 0x800c */ -+ volatile reg_g2_ireso g2_ireso; /* 0x8010 */ -+ volatile unsigned int reserved_74[27]; /* 0x8014~0x807c 27 regs */ -+ volatile reg_g2_dfpos g2_dfpos; /* 0x8080 */ -+ volatile reg_g2_dlpos g2_dlpos; /* 0x8084 */ -+ volatile reg_g2_vfpos g2_vfpos; /* 0x8088 */ -+ volatile reg_g2_vlpos g2_vlpos; /* 0x808c */ -+ volatile reg_g2_bk g2_bk; /* 0x8090 */ -+ volatile reg_g2_alpha g2_alpha; /* 0x8094 */ -+ volatile reg_g2_mute_bk g2_mute_bk; /* 0x8098 */ -+ volatile reg_g2_lbox_ctrl g2_lbox_ctrl; /* 0x809c */ -+ volatile unsigned int reserved_75[24]; /* 0x80a0~0x80fc 24 regs */ -+ volatile reg_g2_ot_pp_csc_ctrl g2_ot_pp_csc_ctrl; /* 0x8100 */ -+ volatile reg_g2_ot_pp_csc_coef00 g2_ot_pp_csc_coef00; /* 0x8104 */ -+ volatile reg_g2_ot_pp_csc_coef01 g2_ot_pp_csc_coef01; /* 0x8108 */ -+ volatile reg_g2_ot_pp_csc_coef02 g2_ot_pp_csc_coef02; /* 0x810c */ -+ volatile reg_g2_ot_pp_csc_coef10 g2_ot_pp_csc_coef10; /* 0x8110 */ -+ volatile reg_g2_ot_pp_csc_coef11 g2_ot_pp_csc_coef11; /* 0x8114 */ -+ volatile reg_g2_ot_pp_csc_coef12 g2_ot_pp_csc_coef12; /* 0x8118 */ -+ volatile reg_g2_ot_pp_csc_coef20 g2_ot_pp_csc_coef20; /* 0x811c */ -+ volatile reg_g2_ot_pp_csc_coef21 g2_ot_pp_csc_coef21; /* 0x8120 */ -+ volatile reg_g2_ot_pp_csc_coef22 g2_ot_pp_csc_coef22; /* 0x8124 */ -+ volatile reg_g2_ot_pp_csc_scale g2_ot_pp_csc_scale; /* 0x8128 */ -+ volatile reg_g2_ot_pp_csc_idc0 g2_ot_pp_csc_idc0; /* 0x812c */ -+ volatile reg_g2_ot_pp_csc_idc1 g2_ot_pp_csc_idc1; /* 0x8130 */ -+ volatile reg_g2_ot_pp_csc_idc2 g2_ot_pp_csc_idc2; /* 0x8134 */ -+ volatile reg_g2_ot_pp_csc_odc0 g2_ot_pp_csc_odc0; /* 0x8138 */ -+ volatile reg_g2_ot_pp_csc_odc1 g2_ot_pp_csc_odc1; /* 0x813c */ -+ volatile reg_g2_ot_pp_csc_odc2 g2_ot_pp_csc_odc2; /* 0x8140 */ -+ volatile reg_g2_ot_pp_csc_min_y g2_ot_pp_csc_min_y; /* 0x8144 */ -+ volatile reg_g2_ot_pp_csc_min_c g2_ot_pp_csc_min_c; /* 0x8148 */ -+ volatile reg_g2_ot_pp_csc_max_y g2_ot_pp_csc_max_y; /* 0x814c */ -+ volatile reg_g2_ot_pp_csc_max_c g2_ot_pp_csc_max_c; /* 0x8150 */ -+ volatile reg_g2_ot_pp_csc2_coef00 g2_ot_pp_csc2_coef00; /* 0x8154 */ -+ volatile reg_g2_ot_pp_csc2_coef01 g2_ot_pp_csc2_coef01; /* 0x8158 */ -+ volatile reg_g2_ot_pp_csc2_coef02 g2_ot_pp_csc2_coef02; /* 0x815c */ -+ volatile reg_g2_ot_pp_csc2_coef10 g2_ot_pp_csc2_coef10; /* 0x8160 */ -+ volatile reg_g2_ot_pp_csc2_coef11 g2_ot_pp_csc2_coef11; /* 0x8164 */ -+ volatile reg_g2_ot_pp_csc2_coef12 g2_ot_pp_csc2_coef12; /* 0x8168 */ -+ volatile reg_g2_ot_pp_csc2_coef20 g2_ot_pp_csc2_coef20; /* 0x816c */ -+ volatile reg_g2_ot_pp_csc2_coef21 g2_ot_pp_csc2_coef21; /* 0x8170 */ -+ volatile reg_g2_ot_pp_csc2_coef22 g2_ot_pp_csc2_coef22; /* 0x8174 */ -+ volatile reg_g2_ot_pp_csc2_scale g2_ot_pp_csc2_scale; /* 0x8178 */ -+ volatile reg_g2_ot_pp_csc2_idc0 g2_ot_pp_csc2_idc0; /* 0x817c */ -+ volatile reg_g2_ot_pp_csc2_idc1 g2_ot_pp_csc2_idc1; /* 0x8180 */ -+ volatile reg_g2_ot_pp_csc2_idc2 g2_ot_pp_csc2_idc2; /* 0x8184 */ -+ volatile reg_g2_ot_pp_csc2_odc0 g2_ot_pp_csc2_odc0; /* 0x8188 */ -+ volatile reg_g2_ot_pp_csc2_odc1 g2_ot_pp_csc2_odc1; /* 0x818c */ -+ volatile reg_g2_ot_pp_csc2_odc2 g2_ot_pp_csc2_odc2; /* 0x8190 */ -+ volatile reg_g2_ot_pp_csc2_min_y g2_ot_pp_csc2_min_y; /* 0x8194 */ -+ volatile reg_g2_ot_pp_csc2_min_c g2_ot_pp_csc2_min_c; /* 0x8198 */ -+ volatile reg_g2_ot_pp_csc2_max_y g2_ot_pp_csc2_max_y; /* 0x819c */ -+ volatile reg_g2_ot_pp_csc2_max_c g2_ot_pp_csc2_max_c; /* 0x81a0 */ -+ volatile unsigned int reserved_76[19]; /* 0x81a4~0x81ec 19 regs */ -+ volatile reg_g2_ot_pp_csc_ink_ctrl g2_ot_pp_csc_ink_ctrl; /* 0x81f0 */ -+ volatile reg_g2_ot_pp_csc_ink_pos g2_ot_pp_csc_ink_pos; /* 0x81f4 */ -+ volatile unsigned int g2_ot_pp_csc_ink_data; /* 0x81f8 */ -+ volatile unsigned int g2_ot_pp_csc_ink_data2; /* 0x81fc */ -+ volatile unsigned int reserved_77[384]; /* 0x8200~0x87fc 384 regs */ -+ volatile reg_g3_ctrl g3_ctrl; /* 0x8800 */ -+ volatile reg_g3_upd g3_upd; /* 0x8804 */ -+ volatile unsigned int g3_galpha_sum; /* 0x8808 */ -+ volatile reg_g3_0reso_read g3_0reso_read; /* 0x880c */ -+ volatile reg_g3_ireso g3_ireso; /* 0x8810 */ -+ volatile unsigned int reserved_78[27]; /* 0x8814~0x887c 27 regs */ -+ volatile reg_g3_dfpos g3_dfpos; /* 0x8880 */ -+ volatile reg_g3_dlpos g3_dlpos; /* 0x8884 */ -+ volatile reg_g3_vfpos g3_vfpos; /* 0x8888 */ -+ volatile reg_g3_vlpos g3_vlpos; /* 0x888c */ -+ volatile reg_g3_bk g3_bk; /* 0x8890 */ -+ volatile reg_g3_alpha g3_alpha; /* 0x8894 */ -+ volatile reg_g3_mute_bk g3_mute_bk; /* 0x8898 */ -+ volatile reg_g3_lbox_ctrl g3_lbox_ctrl; /* 0x889c */ -+ volatile unsigned int reserved_79[24]; /* 0x88a0~0x88fc 24 regs */ -+ volatile reg_g3_ot_pp_csc_ctrl g3_ot_pp_csc_ctrl; /* 0x8900 */ -+ volatile reg_g3_ot_pp_csc_coef00 g3_ot_pp_csc_coef00; /* 0x8904 */ -+ volatile reg_g3_ot_pp_csc_coef01 g3_ot_pp_csc_coef01; /* 0x8908 */ -+ volatile reg_g3_ot_pp_csc_coef02 g3_ot_pp_csc_coef02; /* 0x890c */ -+ volatile reg_g3_ot_pp_csc_coef10 g3_ot_pp_csc_coef10; /* 0x8910 */ -+ volatile reg_g3_ot_pp_csc_coef11 g3_ot_pp_csc_coef11; /* 0x8914 */ -+ volatile reg_g3_ot_pp_csc_coef12 g3_ot_pp_csc_coef12; /* 0x8918 */ -+ volatile reg_g3_ot_pp_csc_coef20 g3_ot_pp_csc_coef20; /* 0x891c */ -+ volatile reg_g3_ot_pp_csc_coef21 g3_ot_pp_csc_coef21; /* 0x8920 */ -+ volatile reg_g3_ot_pp_csc_coef22 g3_ot_pp_csc_coef22; /* 0x8924 */ -+ volatile reg_g3_ot_pp_csc_scale g3_ot_pp_csc_scale; /* 0x8928 */ -+ volatile reg_g3_ot_pp_csc_idc0 g3_ot_pp_csc_idc0; /* 0x892c */ -+ volatile reg_g3_ot_pp_csc_idc1 g3_ot_pp_csc_idc1; /* 0x8930 */ -+ volatile reg_g3_ot_pp_csc_idc2 g3_ot_pp_csc_idc2; /* 0x8934 */ -+ volatile reg_g3_ot_pp_csc_odc0 g3_ot_pp_csc_odc0; /* 0x8938 */ -+ volatile reg_g3_ot_pp_csc_odc1 g3_ot_pp_csc_odc1; /* 0x893c */ -+ volatile reg_g3_ot_pp_csc_odc2 g3_ot_pp_csc_odc2; /* 0x8940 */ -+ volatile reg_g3_ot_pp_csc_min_y g3_ot_pp_csc_min_y; /* 0x8944 */ -+ volatile reg_g3_ot_pp_csc_min_c g3_ot_pp_csc_min_c; /* 0x8948 */ -+ volatile reg_g3_ot_pp_csc_max_y g3_ot_pp_csc_max_y; /* 0x894c */ -+ volatile reg_g3_ot_pp_csc_max_c g3_ot_pp_csc_max_c; /* 0x8950 */ -+ volatile reg_g3_ot_pp_csc2_coef00 g3_ot_pp_csc2_coef00; /* 0x8954 */ -+ volatile reg_g3_ot_pp_csc2_coef01 g3_ot_pp_csc2_coef01; /* 0x8958 */ -+ volatile reg_g3_ot_pp_csc2_coef02 g3_ot_pp_csc2_coef02; /* 0x895c */ -+ volatile reg_g3_ot_pp_csc2_coef10 g3_ot_pp_csc2_coef10; /* 0x8960 */ -+ volatile reg_g3_ot_pp_csc2_coef11 g3_ot_pp_csc2_coef11; /* 0x8964 */ -+ volatile reg_g3_ot_pp_csc2_coef12 g3_ot_pp_csc2_coef12; /* 0x8968 */ -+ volatile reg_g3_ot_pp_csc2_coef20 g3_ot_pp_csc2_coef20; /* 0x896c */ -+ volatile reg_g3_ot_pp_csc2_coef21 g3_ot_pp_csc2_coef21; /* 0x8970 */ -+ volatile reg_g3_ot_pp_csc2_coef22 g3_ot_pp_csc2_coef22; /* 0x8974 */ -+ volatile reg_g3_ot_pp_csc2_scale g3_ot_pp_csc2_scale; /* 0x8978 */ -+ volatile reg_g3_ot_pp_csc2_idc0 g3_ot_pp_csc2_idc0; /* 0x897c */ -+ volatile reg_g3_ot_pp_csc2_idc1 g3_ot_pp_csc2_idc1; /* 0x8980 */ -+ volatile reg_g3_ot_pp_csc2_idc2 g3_ot_pp_csc2_idc2; /* 0x8984 */ -+ volatile reg_g3_ot_pp_csc2_odc0 g3_ot_pp_csc2_odc0; /* 0x8988 */ -+ volatile reg_g3_ot_pp_csc2_odc1 g3_ot_pp_csc2_odc1; /* 0x898c */ -+ volatile reg_g3_ot_pp_csc2_odc2 g3_ot_pp_csc2_odc2; /* 0x8990 */ -+ volatile reg_g3_ot_pp_csc2_min_y g3_ot_pp_csc2_min_y; /* 0x8994 */ -+ volatile reg_g3_ot_pp_csc2_min_c g3_ot_pp_csc2_min_c; /* 0x8998 */ -+ volatile reg_g3_ot_pp_csc2_max_y g3_ot_pp_csc2_max_y; /* 0x899c */ -+ volatile reg_g3_ot_pp_csc2_max_c g3_ot_pp_csc2_max_c; /* 0x89a0 */ -+ volatile unsigned int reserved_80[19]; /* 0x89a4~0x89ec 19 regs */ -+ volatile reg_g3_ot_pp_csc_ink_ctrl g3_ot_pp_csc_ink_ctrl; /* 0x89f0 */ -+ volatile reg_g3_ot_pp_csc_ink_pos g3_ot_pp_csc_ink_pos; /* 0x89f4 */ -+ volatile unsigned int g3_ot_pp_csc_ink_data; /* 0x89f8 */ -+ volatile unsigned int g3_ot_pp_csc_ink_data2; /* 0x89fc */ -+ volatile reg_g3_osb_mute_bk g3_osb_mute_bk; /* 0x8a00 */ -+ volatile reg_g3_osb_bk_alpha g3_osb_bk_alpha; /* 0x8a04 */ -+ volatile reg_g3_osb_coef_rd_en g3_osb_coef_rd_en; /* 0x8a08 */ -+ volatile unsigned int g3_osb_coef_rd_addr; /* 0x8a0c */ -+ volatile unsigned int reserved_81[380]; /* 0x8a10~0x8ffc 380 regs */ -+ volatile reg_g4_ctrl g4_ctrl; /* 0x9000 */ -+ volatile reg_g4_upd g4_upd; /* 0x9004 */ -+ volatile unsigned int g4_galpha_sum; /* 0x9008 */ -+ volatile reg_g4_0reso_read g4_0reso_read; /* 0x900c */ -+ volatile reg_g4_ireso g4_ireso; /* 0x9010 */ -+ volatile unsigned int reserved_82[27]; /* 0x9014~0x907c 27 regs */ -+ volatile reg_g4_dfpos g4_dfpos; /* 0x9080 */ -+ volatile reg_g4_dlpos g4_dlpos; /* 0x9084 */ -+ volatile reg_g4_vfpos g4_vfpos; /* 0x9088 */ -+ volatile reg_g4_vlpos g4_vlpos; /* 0x908c */ -+ volatile reg_g4_bk g4_bk; /* 0x9090 */ -+ volatile reg_g4_alpha g4_alpha; /* 0x9094 */ -+ volatile reg_g4_mute_bk g4_mute_bk; /* 0x9098 */ -+ volatile reg_g4_lbox_ctrl g4_lbox_ctrl; /* 0x909c */ -+ volatile unsigned int reserved_83[24]; /* 0x90a0~0x90fc 24 regs */ -+ volatile reg_g4_ot_pp_csc_ctrl g4_ot_pp_csc_ctrl; /* 0x9100 */ -+ volatile reg_g4_ot_pp_csc_coef00 g4_ot_pp_csc_coef00; /* 0x9104 */ -+ volatile reg_g4_ot_pp_csc_coef01 g4_ot_pp_csc_coef01; /* 0x9108 */ -+ volatile reg_g4_ot_pp_csc_coef02 g4_ot_pp_csc_coef02; /* 0x910c */ -+ volatile reg_g4_ot_pp_csc_coef10 g4_ot_pp_csc_coef10; /* 0x9110 */ -+ volatile reg_g4_ot_pp_csc_coef11 g4_ot_pp_csc_coef11; /* 0x9114 */ -+ volatile reg_g4_ot_pp_csc_coef12 g4_ot_pp_csc_coef12; /* 0x9118 */ -+ volatile reg_g4_ot_pp_csc_coef20 g4_ot_pp_csc_coef20; /* 0x911c */ -+ volatile reg_g4_ot_pp_csc_coef21 g4_ot_pp_csc_coef21; /* 0x9120 */ -+ volatile reg_g4_ot_pp_csc_coef22 g4_ot_pp_csc_coef22; /* 0x9124 */ -+ volatile reg_g4_ot_pp_csc_scale g4_ot_pp_csc_scale; /* 0x9128 */ -+ volatile reg_g4_ot_pp_csc_idc0 g4_ot_pp_csc_idc0; /* 0x912c */ -+ volatile reg_g4_ot_pp_csc_idc1 g4_ot_pp_csc_idc1; /* 0x9130 */ -+ volatile reg_g4_ot_pp_csc_idc2 g4_ot_pp_csc_idc2; /* 0x9134 */ -+ volatile reg_g4_ot_pp_csc_odc0 g4_ot_pp_csc_odc0; /* 0x9138 */ -+ volatile reg_g4_ot_pp_csc_odc1 g4_ot_pp_csc_odc1; /* 0x913c */ -+ volatile reg_g4_ot_pp_csc_odc2 g4_ot_pp_csc_odc2; /* 0x9140 */ -+ volatile reg_g4_ot_pp_csc_min_y g4_ot_pp_csc_min_y; /* 0x9144 */ -+ volatile reg_g4_ot_pp_csc_min_c g4_ot_pp_csc_min_c; /* 0x9148 */ -+ volatile reg_g4_ot_pp_csc_max_y g4_ot_pp_csc_max_y; /* 0x914c */ -+ volatile reg_g4_ot_pp_csc_max_c g4_ot_pp_csc_max_c; /* 0x9150 */ -+ volatile reg_g4_ot_pp_csc2_coef00 g4_ot_pp_csc2_coef00; /* 0x9154 */ -+ volatile reg_g4_ot_pp_csc2_coef01 g4_ot_pp_csc2_coef01; /* 0x9158 */ -+ volatile reg_g4_ot_pp_csc2_coef02 g4_ot_pp_csc2_coef02; /* 0x915c */ -+ volatile reg_g4_ot_pp_csc2_coef10 g4_ot_pp_csc2_coef10; /* 0x9160 */ -+ volatile reg_g4_ot_pp_csc2_coef11 g4_ot_pp_csc2_coef11; /* 0x9164 */ -+ volatile reg_g4_ot_pp_csc2_coef12 g4_ot_pp_csc2_coef12; /* 0x9168 */ -+ volatile reg_g4_ot_pp_csc2_coef20 g4_ot_pp_csc2_coef20; /* 0x916c */ -+ volatile reg_g4_ot_pp_csc2_coef21 g4_ot_pp_csc2_coef21; /* 0x9170 */ -+ volatile reg_g4_ot_pp_csc2_coef22 g4_ot_pp_csc2_coef22; /* 0x9174 */ -+ volatile reg_g4_ot_pp_csc2_scale g4_ot_pp_csc2_scale; /* 0x9178 */ -+ volatile reg_g4_ot_pp_csc2_idc0 g4_ot_pp_csc2_idc0; /* 0x917c */ -+ volatile reg_g4_ot_pp_csc2_idc1 g4_ot_pp_csc2_idc1; /* 0x9180 */ -+ volatile reg_g4_ot_pp_csc2_idc2 g4_ot_pp_csc2_idc2; /* 0x9184 */ -+ volatile reg_g4_ot_pp_csc2_odc0 g4_ot_pp_csc2_odc0; /* 0x9188 */ -+ volatile reg_g4_ot_pp_csc2_odc1 g4_ot_pp_csc2_odc1; /* 0x918c */ -+ volatile reg_g4_ot_pp_csc2_odc2 g4_ot_pp_csc2_odc2; /* 0x9190 */ -+ volatile reg_g4_ot_pp_csc2_min_y g4_ot_pp_csc2_min_y; /* 0x9194 */ -+ volatile reg_g4_ot_pp_csc2_min_c g4_ot_pp_csc2_min_c; /* 0x9198 */ -+ volatile reg_g4_ot_pp_csc2_max_y g4_ot_pp_csc2_max_y; /* 0x919c */ -+ volatile reg_g4_ot_pp_csc2_max_c g4_ot_pp_csc2_max_c; /* 0x91a0 */ -+ volatile unsigned int reserved_84[19]; /* 0x91a4~0x91ec 19 regs */ -+ volatile reg_g4_ot_pp_csc_ink_ctrl g4_ot_pp_csc_ink_ctrl; /* 0x91f0 */ -+ volatile reg_g4_ot_pp_csc_ink_pos g4_ot_pp_csc_ink_pos; /* 0x91f4 */ -+ volatile unsigned int g4_ot_pp_csc_ink_data; /* 0x91f8 */ -+ volatile unsigned int g4_ot_pp_csc_ink_data2; /* 0x91fc */ -+ volatile reg_g4_osb_mute_bk g4_osb_mute_bk; /* 0x9200 */ -+ volatile reg_g4_osb_bk_alpha g4_osb_bk_alpha; /* 0x9204 */ -+ volatile reg_g4_osb_coef_rd_en g4_osb_coef_rd_en; /* 0x9208 */ -+ volatile unsigned int g4_osb_coef_rd_addr; /* 0x920c */ -+ volatile unsigned int reserved_85[380]; /* 0x9210~0x97fc 380 regs */ -+ volatile unsigned int gp0_ctrl; /* 0x9800 */ -+ volatile reg_gp0_upd gp0_upd; /* 0x9804 */ -+ volatile reg_gp0_ireso gp0_ireso; /* 0x9808 */ -+ volatile unsigned int reserved_86[29]; /* 0x980c~0x987c 29 regs */ -+ volatile reg_gp0_lbox_ctrl gp0_lbox_ctrl; /* 0x9880 */ -+ volatile reg_gp0_galpha gp0_galpha; /* 0x9884 */ -+ volatile unsigned int gp0_galpha_sum; /* 0x9888 */ -+ volatile reg_gp0_dfpos gp0_dfpos; /* 0x988c */ -+ volatile reg_gp0_dlpos gp0_dlpos; /* 0x9890 */ -+ volatile reg_gp0_vfpos gp0_vfpos; /* 0x9894 */ -+ volatile reg_gp0_vlpos gp0_vlpos; /* 0x9898 */ -+ volatile reg_gp0_bk gp0_bk; /* 0x989c */ -+ volatile reg_gp0_alpha gp0_alpha; /* 0x98a0 */ -+ volatile reg_gp0_mute_bk gp0_mute_bk; /* 0x98a4 */ -+ volatile unsigned int reserved_87[22]; /* 0x98a8~0x98fc 22 regs */ -+ volatile reg_gp0_csc_idc gp0_csc_idc; /* 0x9900 */ -+ volatile reg_gp0_csc_odc gp0_csc_odc; /* 0x9904 */ -+ volatile reg_gp0_csc_iodc gp0_csc_iodc; /* 0x9908 */ -+ volatile reg_gp0_csc_p0 gp0_csc_p0; /* 0x990c */ -+ volatile reg_gp0_csc_p1 gp0_csc_p1; /* 0x9910 */ -+ volatile reg_gp0_csc_p2 gp0_csc_p2; /* 0x9914 */ -+ volatile reg_gp0_csc_p3 gp0_csc_p3; /* 0x9918 */ -+ volatile reg_gp0_csc_p4 gp0_csc_p4; /* 0x991c */ -+ volatile unsigned int reserved_88[1464]; /* 0x9920~0xaffc 1464 regs */ -+ volatile reg_wbc_g0_ctrl wbc_g0_ctrl; /* 0xb000 */ -+ volatile reg_wbc_g0_upd wbc_g0_upd; /* 0xb004 */ -+ volatile reg_wbc_g0_cmp wbc_g0_cmp; /* 0xb008 */ -+ volatile unsigned int reserved_89; /* 0xb00c */ -+ volatile unsigned int wbc_g0_ar_addr; /* 0xb010 */ -+ volatile unsigned int wbc_g0_gb_addr; /* 0xb014 */ -+ volatile reg_wbc_g0_stride wbc_g0_stride; /* 0xb018 */ -+ volatile unsigned int wbc_g0_offset; /* 0xb01c */ -+ volatile reg_wbc_g0_oreso wbc_g0_oreso; /* 0xb020 */ -+ volatile reg_wbc_g0_fcrop wbc_g0_fcrop; /* 0xb024 */ -+ volatile reg_wbc_g0_lcrop wbc_g0_lcrop; /* 0xb028 */ -+ volatile unsigned int reserved_90[501]; /* 0xb02c~0xb7fc 501 regs */ -+ volatile reg_wbc_gp0_ctrl wbc_gp0_ctrl; /* 0xb800 */ -+ volatile reg_wbc_gp0_upd wbc_gp0_upd; /* 0xb804 */ -+ volatile unsigned int reserved_91[2]; /* 0xb808~0xb80c 2 regs */ -+ volatile unsigned int wbc_gp0_yaddr; /* 0xb810 */ -+ volatile unsigned int wbc_gp0_caddr; /* 0xb814 */ -+ volatile reg_wbc_gp0_stride wbc_gp0_stride; /* 0xb818 */ -+ volatile unsigned int reserved_92; /* 0xb81c */ -+ volatile reg_wbc_gp0_oreso wbc_gp0_oreso; /* 0xb820 */ -+ volatile reg_wbc_gp0_fcrop wbc_gp0_fcrop; /* 0xb824 */ -+ volatile reg_wbc_gp0_lcrop wbc_gp0_lcrop; /* 0xb828 */ -+ volatile unsigned int reserved_93[53]; /* 0xb82c~0xb8fc 53 regs */ -+ volatile reg_wbc_gp0_dither_ctrl wbc_gp0_dither_ctrl; /* 0xb900 */ -+ volatile reg_wbc_gp0_dither_coef0 wbc_gp0_dither_coef0; /* 0xb904 */ -+ volatile reg_wbc_gp0_dither_coef1 wbc_gp0_dither_coef1; /* 0xb908 */ -+ volatile unsigned int reserved_94[17]; /* 0xb90c~0xb94c 17 regs */ -+ volatile reg_wbc_gp0_hpzme wbc_gp0_hpzme; /* 0xb950 */ -+ volatile unsigned int reserved_95[43]; /* 0xb954~0xb9fc 43 regs */ -+ volatile reg_wbc_me_ctrl wbc_me_ctrl; /* 0xba00 */ -+ volatile reg_wbc_me_upd wbc_me_upd; /* 0xba04 */ -+ volatile reg_wbc_me_wlen_sel wbc_me_wlen_sel; /* 0xba08 */ -+ volatile unsigned int reserved_96; /* 0xba0c */ -+ volatile unsigned int wbc_me_yaddr; /* 0xba10 */ -+ volatile unsigned int wbc_me_caddr; /* 0xba14 */ -+ volatile reg_wbc_me_stride wbc_me_stride; /* 0xba18 */ -+ volatile unsigned int reserved_97; /* 0xba1c */ -+ volatile reg_wbc_me_oreso wbc_me_oreso; /* 0xba20 */ -+ volatile unsigned int reserved_98[2]; /* 0xba24~0xba28 2 regs */ -+ volatile reg_wbc_me_smmu_bypass wbc_me_smmu_bypass; /* 0xba2c */ -+ volatile unsigned int reserved_99[4]; /* 0xba30~0xba3c 4 regs */ -+ volatile reg_wbc_me_paraup wbc_me_paraup; /* 0xba40 */ -+ volatile unsigned int reserved_100[3]; /* 0xba44~0xba4c 3 regs */ -+ volatile unsigned int wbc_me_hlcoefad; /* 0xba50 */ -+ volatile unsigned int wbc_me_hccoefad; /* 0xba54 */ -+ volatile unsigned int wbc_me_vlcoefad; /* 0xba58 */ -+ volatile unsigned int wbc_me_vccoefad; /* 0xba5c */ -+ volatile unsigned int reserved_101[36]; /* 0xba60~0xbaec 36 regs */ -+ volatile unsigned int wbc_me_checksum_y; /* 0xbaf0 */ -+ volatile unsigned int wbc_me_checksum_c; /* 0xbaf4 */ -+ volatile unsigned int reserved_102[2]; /* 0xbaf8~0xbafc 2 regs */ -+ volatile reg_wbc_me_dither_ctrl wbc_me_dither_ctrl; /* 0xbb00 */ -+ volatile reg_wbc_me_dither_coef0 wbc_me_dither_coef0; /* 0xbb04 */ -+ volatile reg_wbc_me_dither_coef1 wbc_me_dither_coef1; /* 0xbb08 */ -+ volatile unsigned int reserved_103[109]; /* 0xbb0c~0xbcbc 109 regs */ -+ volatile reg_wbc_me_zme_hsp wbc_me_zme_hsp; /* 0xbcc0 */ -+ volatile reg_wbc_me_zme_hloffset wbc_me_zme_hloffset; /* 0xbcc4 */ -+ volatile reg_wbc_me_zme_hcoffset wbc_me_zme_hcoffset; /* 0xbcc8 */ -+ volatile unsigned int reserved_104[3]; /* 0xbccc~0xbcd4 3 regs */ -+ volatile reg_wbc_me_zme_vsp wbc_me_zme_vsp; /* 0xbcd8 */ -+ volatile reg_wbc_me_zme_vsr wbc_me_zme_vsr; /* 0xbcdc */ -+ volatile reg_wbc_me_zme_voffset wbc_me_zme_voffset; /* 0xbce0 */ -+ volatile reg_wbc_me_zme_vboffset wbc_me_zme_vboffset; /* 0xbce4 */ -+ volatile unsigned int reserved_105[6]; /* 0xbce8~0xbcfc 6 regs */ -+ volatile reg_wbc_fi_ctrl wbc_fi_ctrl; /* 0xbd00 */ -+ volatile reg_wbc_fi_upd wbc_fi_upd; /* 0xbd04 */ -+ volatile reg_wbc_fi_wlen_sel wbc_fi_wlen_sel; /* 0xbd08 */ -+ volatile unsigned int reserved_106; /* 0xbd0c */ -+ volatile unsigned int wbc_fi_yaddr; /* 0xbd10 */ -+ volatile unsigned int wbc_fi_caddr; /* 0xbd14 */ -+ volatile reg_wbc_fi_stride wbc_fi_stride; /* 0xbd18 */ -+ volatile unsigned int reserved_107; /* 0xbd1c */ -+ volatile reg_wbc_fi_oreso wbc_fi_oreso; /* 0xbd20 */ -+ volatile unsigned int reserved_108[2]; /* 0xbd24~0xbd28 2 regs */ -+ volatile reg_wbc_fi_smmu_bypass wbc_fi_smmu_bypass; /* 0xbd2c */ -+ volatile unsigned int reserved_109[5]; /* 0xbd30~0xbd40 5 regs */ -+ volatile reg_wbc_fi_frame_size wbc_fi_frame_size; /* 0xbd44 */ -+ volatile unsigned int wbc_fi_y_raddr; /* 0xbd48 */ -+ volatile unsigned int wbc_fi_c_raddr; /* 0xbd4c */ -+ volatile unsigned int reserved_110[40]; /* 0xbd50~0xbdec 40 regs */ -+ volatile unsigned int wbc_fi_checksum_y; /* 0xbdf0 */ -+ volatile unsigned int wbc_fi_checksum_c; /* 0xbdf4 */ -+ volatile unsigned int reserved_111[6]; /* 0xbdf8~0xbe0c 6 regs */ -+ volatile reg_wbc_fi_hcds wbc_fi_hcds; /* 0xbe10 */ -+ volatile reg_wbc_fi_hcds_coef0 wbc_fi_hcds_coef0; /* 0xbe14 */ -+ volatile reg_wbc_fi_hcds_coef1 wbc_fi_hcds_coef1; /* 0xbe18 */ -+ volatile unsigned int reserved_112; /* 0xbe1c */ -+ volatile reg_wbc_fi_cmp_mb wbc_fi_cmp_mb; /* 0xbe20 */ -+ volatile reg_wbc_fi_cmp_max_min wbc_fi_cmp_max_min; /* 0xbe24 */ -+ volatile reg_wbc_fi_cmp_adj_thr wbc_fi_cmp_adj_thr; /* 0xbe28 */ -+ volatile reg_wbc_fi_cmp_big_grad wbc_fi_cmp_big_grad; /* 0xbe2c */ -+ volatile reg_wbc_fi_cmp_blk wbc_fi_cmp_blk; /* 0xbe30 */ -+ volatile reg_wbc_fi_cmp_graphic_judge wbc_fi_cmp_graphic_judge; /* 0xbe34 */ -+ volatile reg_wbc_fi_cmp_rc wbc_fi_cmp_rc; /* 0xbe38 */ -+ volatile reg_wbc_fi_cmp_frame_size wbc_fi_cmp_frame_size; /* 0xbe3c */ -+ volatile unsigned int reserved_113[48]; /* 0xbe40~0xbefc 48 regs */ -+ volatile reg_wbc_cmp_glb_info wbc_cmp_glb_info; /* 0xbf00 */ -+ volatile reg_wbc_cmp_framesize wbc_cmp_framesize; /* 0xbf04 */ -+ volatile reg_wbc_cmp_rc_cfg0 wbc_cmp_rc_cfg0; /* 0xbf08 */ -+ volatile reg_wbc_cmp_rc_cfg2 wbc_cmp_rc_cfg2; /* 0xbf0c */ -+ volatile reg_wbc_cmp_rc_cfg3 wbc_cmp_rc_cfg3; /* 0xbf10 */ -+ volatile reg_wbc_cmp_rc_cfg4 wbc_cmp_rc_cfg4; /* 0xbf14 */ -+ volatile reg_wbc_cmp_rc_cfg5 wbc_cmp_rc_cfg5; /* 0xbf18 */ -+ volatile reg_wbc_cmp_rc_cfg6 wbc_cmp_rc_cfg6; /* 0xbf1c */ -+ volatile reg_wbc_cmp_rc_cfg7 wbc_cmp_rc_cfg7; /* 0xbf20 */ -+ volatile reg_wbc_cmp_rc_cfg8 wbc_cmp_rc_cfg8; /* 0xbf24 */ -+ volatile reg_wbc_cmp_rc_cfg10 wbc_cmp_rc_cfg10; /* 0xbf28 */ -+ volatile reg_wbc_cmp_outsize0 wbc_cmp_outsize0; /* 0xbf2c */ -+ volatile unsigned int wbc_cmp_dbg_reg0; /* 0xbf30 */ -+ volatile reg_wbc_cmp_max_row wbc_cmp_max_row; /* 0xbf34 */ -+ volatile reg_wbc_bmp_ctrl wbc_bmp_ctrl; /* 0xbf38 */ -+ volatile reg_wbc_bmp_upd wbc_bmp_upd; /* 0xbf3c */ -+ volatile unsigned int wbc_bmp_yaddr; /* 0xbf40 */ -+ volatile unsigned int reserved_114[23]; /* 0xbf44~0xbf9c 23 regs */ -+ volatile reg_wbc_bmp_oreso wbc_bmp_oreso; /* 0xbfa0 */ -+ volatile reg_wbc_bmp_sum wbc_bmp_sum; /* 0xbfa4 */ -+ volatile unsigned int reserved_115[18]; /* 0xbfa8~0xbfec 18 regs */ -+ volatile unsigned int wbc_bmp_checksum_y; /* 0xbff0 */ -+ volatile unsigned int wbc_bmp_checksum_c; /* 0xbff4 */ -+ volatile unsigned int reserved_116[2]; /* 0xbff8~0xbffc 2 regs */ -+ volatile reg_wbc_dhd0_ctrl wbc_dhd0_ctrl; /* 0xc000 */ -+ volatile reg_wbc_dhd0_upd wbc_dhd0_upd; /* 0xc004 */ -+ volatile reg_wbc_dhd0_oreso wbc_dhd0_oreso; /* 0xc008 */ -+ volatile unsigned int reserved_117[29]; /* 0xc00c~0xc07c 29 regs */ -+ volatile reg_wd_hpzme_ctrl wd_hpzme_ctrl; /* 0xc080 */ -+ volatile reg_wd_hpzmecoef01 wd_hpzmecoef01; /* 0xc084 */ -+ volatile reg_wd_hpzmecoef23 wd_hpzmecoef23; /* 0xc088 */ -+ volatile reg_wd_hpzmecoef45 wd_hpzmecoef45; /* 0xc08c */ -+ volatile reg_wd_hpzmecoef67 wd_hpzmecoef67; /* 0xc090 */ -+ volatile unsigned int reserved_118[91]; /* 0xc094~0xc1fc 91 regs */ -+ volatile reg_wd_hcds_ctrl wd_hcds_ctrl; /* 0xc200 */ -+ volatile reg_wd_hcdscoef01 wd_hcdscoef01; /* 0xc204 */ -+ volatile reg_wd_hcdscoef23 wd_hcdscoef23; /* 0xc208 */ -+ volatile reg_wd_hcdscoef45 wd_hcdscoef45; /* 0xc20c */ -+ volatile reg_wd_hcdscoef67 wd_hcdscoef67; /* 0xc210 */ -+ volatile unsigned int reserved_119[27]; /* 0xc214~0xc27c 27 regs */ -+ volatile reg_dither_ctrl dither_ctrl; /* 0xc280 */ -+ volatile reg_dither_sed_y0 dither_sed_y0; /* 0xc284 */ -+ volatile reg_dither_sed_u0 dither_sed_u0; /* 0xc288 */ -+ volatile reg_dither_sed_v0 dither_sed_v0; /* 0xc28c */ -+ volatile reg_dither_sed_w0 dither_sed_w0; /* 0xc290 */ -+ volatile reg_dither_sed_y1 dither_sed_y1; /* 0xc294 */ -+ volatile reg_dither_sed_u1 dither_sed_u1; /* 0xc298 */ -+ volatile reg_dither_sed_v1 dither_sed_v1; /* 0xc29c */ -+ volatile reg_dither_sed_w1 dither_sed_w1; /* 0xc2a0 */ -+ volatile reg_dither_sed_y2 dither_sed_y2; /* 0xc2a4 */ -+ volatile reg_dither_sed_u2 dither_sed_u2; /* 0xc2a8 */ -+ volatile reg_dither_sed_v2 dither_sed_v2; /* 0xc2ac */ -+ volatile reg_dither_sed_w2 dither_sed_w2; /* 0xc2b0 */ -+ volatile reg_dither_sed_y3 dither_sed_y3; /* 0xc2b4 */ -+ volatile reg_dither_sed_u3 dither_sed_u3; /* 0xc2b8 */ -+ volatile reg_dither_sed_v3 dither_sed_v3; /* 0xc2bc */ -+ volatile reg_dither_sed_w3 dither_sed_w3; /* 0xc2c0 */ -+ volatile reg_dither_thr dither_thr; /* 0xc2c4 */ -+ volatile unsigned int reserved_120[14]; /* 0xc2c8~0xc2fc 14 regs */ -+ volatile reg_wd_zme_hinfo wd_zme_hinfo; /* 0xc300 */ -+ volatile reg_wd_zme_hsp wd_zme_hsp; /* 0xc304 */ -+ volatile reg_wd_zme_hloffset wd_zme_hloffset; /* 0xc308 */ -+ volatile reg_wd_zme_hcoffset wd_zme_hcoffset; /* 0xc30c */ -+ volatile unsigned int reserved_121[5]; /* 0xc310~0xc320 5 regs */ -+ volatile reg_wd_zme_hcoef_ren wd_zme_hcoef_ren; /* 0xc324 */ -+ volatile reg_wd_zme_hcoef_rdata wd_zme_hcoef_rdata; /* 0xc328 */ -+ volatile reg_wd_zme_hdraw wd_zme_hdraw; /* 0xc32c */ -+ volatile reg_wd_zme_hratio wd_zme_hratio; /* 0xc330 */ -+ volatile unsigned int reserved_122[51]; /* 0xc334~0xc3fc 51 regs */ -+ volatile reg_wd_zme_vinfo wd_zme_vinfo; /* 0xc400 */ -+ volatile reg_wd_zme_vsp wd_zme_vsp; /* 0xc404 */ -+ volatile reg_wd_zme_voffset wd_zme_voffset; /* 0xc408 */ -+ volatile reg_wd_zme_vboffset wd_zme_vboffset; /* 0xc40c */ -+ volatile unsigned int reserved_123[5]; /* 0xc410~0xc420 5 regs */ -+ volatile reg_wd_zme_vcoef_ren wd_zme_vcoef_ren; /* 0xc424 */ -+ volatile reg_wd_zme_vcoef_rdata wd_zme_vcoef_rdata; /* 0xc428 */ -+ volatile reg_wd_zme_vdraw wd_zme_vdraw; /* 0xc42c */ -+ volatile reg_wd_zme_vratio wd_zme_vratio; /* 0xc430 */ -+ volatile unsigned int reserved_124[755]; /* 0xc434~0xcffc 755 regs */ -+ volatile reg_dhd0_ctrl dhd0_ctrl; /* 0xd000 */ -+ volatile reg_dhd0_vsync1 dhd0_vsync1; /* 0xd004 */ -+ volatile reg_dhd0_vsync2 dhd0_vsync2; /* 0xd008 */ -+ volatile reg_dhd0_hsync1 dhd0_hsync1; /* 0xd00c */ -+ volatile reg_dhd0_hsync2 dhd0_hsync2; /* 0xd010 */ -+ volatile reg_dhd0_vplus1 dhd0_vplus1; /* 0xd014 */ -+ volatile reg_dhd0_vplus2 dhd0_vplus2; /* 0xd018 */ -+ volatile reg_dhd0_pwr dhd0_pwr; /* 0xd01c */ -+ volatile reg_dhd0_vtthd3 dhd0_vtthd3; /* 0xd020 */ -+ volatile reg_dhd0_vtthd dhd0_vtthd; /* 0xd024 */ -+ volatile reg_dhd0_parathd dhd0_parathd; /* 0xd028 */ -+ volatile reg_dhd0_precharge_thd dhd0_precharge_thd; /* 0xd02c */ -+ volatile reg_dhd0_start_pos dhd0_start_pos; /* 0xd030 */ -+ volatile reg_dhd0_start_pos1 dhd0_start_pos1; /* 0xd034 */ -+ volatile reg_dhd0_paraup dhd0_paraup; /* 0xd038 */ -+ volatile reg_dhd0_sync_inv dhd0_sync_inv; /* 0xd03c */ -+ volatile reg_dhd0_clk_dv_ctrl dhd0_clk_dv_ctrl; /* 0xd040 */ -+ volatile reg_dhd0_rgb_fix_ctrl dhd0_rgb_fix_ctrl; /* 0xd044 */ -+ volatile reg_dhd0_lockcfg dhd0_lockcfg; /* 0xd048 */ -+ volatile unsigned int dhd0_cap_frm_cnt; /* 0xd04c */ -+ volatile unsigned int dhd0_vdp_frm_cnt; /* 0xd050 */ -+ volatile unsigned int dhd0_vsync_cap_vdp_cnt; /* 0xd054 */ -+ volatile unsigned int dhd0_intf_chksum_y; /* 0xd058 */ -+ volatile unsigned int dhd0_intf_chksum_u; /* 0xd05c */ -+ volatile unsigned int dhd0_intf_chksum_v; /* 0xd060 */ -+ volatile unsigned int dhd0_intf1_chksum_y; /* 0xd064 */ -+ volatile unsigned int dhd0_intf1_chksum_u; /* 0xd068 */ -+ volatile unsigned int dhd0_intf1_chksum_v; /* 0xd06c */ -+ volatile reg_dhd0_intf_chksum_high1 dhd0_intf_chksum_high1; /* 0xd070 */ -+ volatile reg_dhd0_intf_chksum_high2 dhd0_intf_chksum_high2; /* 0xd074 */ -+ volatile unsigned int reserved_125[3]; /* 0xd078~0xd080 3 regs */ -+ volatile unsigned int dhd0_afifo_pre_thd; /* 0xd084 */ -+ volatile reg_dhd0_state dhd0_state; /* 0xd088 */ -+ volatile reg_dhd0_uf_state dhd0_uf_state; /* 0xd08c */ -+ volatile reg_vo_mux vo_mux; /* 0xd090 */ -+ volatile reg_vo_mux_sync vo_mux_sync; /* 0xd094 */ -+ volatile reg_vo_mux_data vo_mux_data; /* 0xd098 */ -+ volatile unsigned int reserved_126; /* 0xd09c */ -+ volatile reg_dhd0_vsync_te_state dhd0_vsync_te_state; /* 0xd0a0 */ -+ volatile reg_dhd0_vsync_te_state1 dhd0_vsync_te_state1; /* 0xd0a4 */ -+ volatile unsigned int reserved_127[6]; /* 0xd0a8~0xd0bc 6 regs */ -+ volatile reg_dhd0_ccdoimgmod dhd0_ccdoimgmod; /* 0xd0c0 */ -+ volatile reg_dhd0_ccdoposmskh dhd0_ccdoposmskh; /* 0xd0c4 */ -+ volatile reg_dhd0_ccdoposmskl dhd0_ccdoposmskl; /* 0xd0c8 */ -+ volatile unsigned int reserved_128; /* 0xd0cc */ -+ volatile reg_dhd0_dacdet1 dhd0_dacdet1; /* 0xd0d0 */ -+ volatile reg_dhd0_dacdet2 dhd0_dacdet2; /* 0xd0d4 */ -+ volatile unsigned int reserved_129[2]; /* 0xd0d8~0xd0dc 2 regs */ -+ volatile reg_dhd0_ccd_info1 dhd0_ccd_info1; /* 0xd0e0 */ -+ volatile reg_dhd0_ccd_info2 dhd0_ccd_info2; /* 0xd0e4 */ -+ volatile reg_dhd0_ccd_info3 dhd0_ccd_info3; /* 0xd0e8 */ -+ volatile unsigned int reserved_130[5]; /* 0xd0ec~0xd0fc 5 regs */ -+ volatile reg_intf_hdmi_ctrl intf_hdmi_ctrl; /* 0xd100 */ -+ volatile reg_intf_hdmi_upd intf_hdmi_upd; /* 0xd104 */ -+ volatile reg_intf_hdmi_sync_inv intf_hdmi_sync_inv; /* 0xd108 */ -+ volatile unsigned int reserved_131; /* 0xd10c */ -+ volatile unsigned int hdmi_intf_chksum_y; /* 0xd110 */ -+ volatile unsigned int hdmi_intf_chksum_u; /* 0xd114 */ -+ volatile unsigned int hdmi_intf_chksum_v; /* 0xd118 */ -+ volatile reg_hdmi_intf_chksum_high hdmi_intf_chksum_high; /* 0xd11c */ -+ volatile unsigned int hdmi_intf1_chksum_y; /* 0xd120 */ -+ volatile unsigned int hdmi_intf1_chksum_u; /* 0xd124 */ -+ volatile unsigned int hdmi_intf1_chksum_v; /* 0xd128 */ -+ volatile reg_hdmi_intf1_chksum_high hdmi_intf1_chksum_high; /* 0xd12c */ -+ volatile unsigned int reserved_132[8]; /* 0xd130~0xd14c 8 regs */ -+ volatile reg_hdmi_hfir_coef0 hdmi_hfir_coef0; /* 0xd150 */ -+ volatile reg_hdmi_hfir_coef1 hdmi_hfir_coef1; /* 0xd154 */ -+ volatile reg_hdmi_hfir_coef2 hdmi_hfir_coef2; /* 0xd158 */ -+ volatile reg_hdmi_hfir_coef3 hdmi_hfir_coef3; /* 0xd15c */ -+ volatile reg_hdmi_csc_idc hdmi_csc_idc; /* 0xd160 */ -+ volatile reg_hdmi_csc_odc hdmi_csc_odc; /* 0xd164 */ -+ volatile reg_hdmi_csc_iodc hdmi_csc_iodc; /* 0xd168 */ -+ volatile reg_hdmi_csc_p0 hdmi_csc_p0; /* 0xd16c */ -+ volatile reg_hdmi_csc_p1 hdmi_csc_p1; /* 0xd170 */ -+ volatile reg_hdmi_csc_p2 hdmi_csc_p2; /* 0xd174 */ -+ volatile reg_hdmi_csc_p3 hdmi_csc_p3; /* 0xd178 */ -+ volatile reg_hdmi_csc_p4 hdmi_csc_p4; /* 0xd17c */ -+ volatile reg_intf_mipi_del_ctrl intf_mipi_del_ctrl; /* 0xd180 */ -+ volatile reg_intf_mipi_del_upd intf_mipi_del_upd; /* 0xd184 */ -+ volatile reg_intf_mipi_del_sync_inv intf_mipi_del_sync_inv; /* 0xd188 */ -+ volatile unsigned int reserved_133; /* 0xd18c */ -+ volatile unsigned int mipi_del_intf_chksum_y; /* 0xd190 */ -+ volatile unsigned int mipi_del_intf_chksum_u; /* 0xd194 */ -+ volatile unsigned int mipi_del_intf_chksum_v; /* 0xd198 */ -+ volatile reg_mipi_del_intf_chksum_high mipi_del_intf_chksum_high; /* 0xd19c */ -+ volatile unsigned int mipi_del_intf1_chksum_y; /* 0xd1a0 */ -+ volatile unsigned int mipi_del_intf1_chksum_u; /* 0xd1a4 */ -+ volatile unsigned int mipi_del_intf1_chksum_v; /* 0xd1a8 */ -+ volatile reg_mipi_del_intf1_chksum_high mipi_del_intf1_chksum_high; /* 0xd1ac */ -+ volatile unsigned int reserved_134[8]; /* 0xd1b0~0xd1cc 8 regs */ -+ volatile reg_mipi_del_hfir_coef0 mipi_del_hfir_coef0; /* 0xd1d0 */ -+ volatile reg_mipi_del_hfir_coef1 mipi_del_hfir_coef1; /* 0xd1d4 */ -+ volatile reg_mipi_del_hfir_coef2 mipi_del_hfir_coef2; /* 0xd1d8 */ -+ volatile reg_mipi_del_hfir_coef3 mipi_del_hfir_coef3; /* 0xd1dc */ -+ volatile reg_mipi_del_csc_idc mipi_del_csc_idc; /* 0xd1e0 */ -+ volatile reg_mipi_del_csc_odc mipi_del_csc_odc; /* 0xd1e4 */ -+ volatile reg_mipi_del_csc_iodc mipi_del_csc_iodc; /* 0xd1e8 */ -+ volatile reg_mipi_del_csc_p0 mipi_del_csc_p0; /* 0xd1ec */ -+ volatile reg_mipi_del_csc_p1 mipi_del_csc_p1; /* 0xd1f0 */ -+ volatile reg_mipi_del_csc_p2 mipi_del_csc_p2; /* 0xd1f4 */ -+ volatile reg_mipi_del_csc_p3 mipi_del_csc_p3; /* 0xd1f8 */ -+ volatile reg_mipi_del_csc_p4 mipi_del_csc_p4; /* 0xd1fc */ -+ volatile reg_intf_bt_ctrl intf_bt_ctrl; /* 0xd200 */ -+ volatile reg_intf_bt_upd intf_bt_upd; /* 0xd204 */ -+ volatile reg_intf_bt_sync_inv intf_bt_sync_inv; /* 0xd208 */ -+ volatile unsigned int reserved_135; /* 0xd20c */ -+ volatile reg_bt_clip0_l bt_clip0_l; /* 0xd210 */ -+ volatile reg_bt_clip0_h bt_clip0_h; /* 0xd214 */ -+ volatile unsigned int reserved_136[26]; /* 0xd218~0xd27c 26 regs */ -+ volatile reg_bt_dither_ctrl bt_dither_ctrl; /* 0xd280 */ -+ volatile reg_bt_dither_sed_y0 bt_dither_sed_y0; /* 0xd284 */ -+ volatile reg_bt_dither_sed_u0 bt_dither_sed_u0; /* 0xd288 */ -+ volatile reg_bt_dither_sed_v0 bt_dither_sed_v0; /* 0xd28c */ -+ volatile reg_bt_dither_sed_w0 bt_dither_sed_w0; /* 0xd290 */ -+ volatile reg_bt_dither_sed_y1 bt_dither_sed_y1; /* 0xd294 */ -+ volatile reg_bt_dither_sed_u1 bt_dither_sed_u1; /* 0xd298 */ -+ volatile reg_bt_dither_sed_v1 bt_dither_sed_v1; /* 0xd29c */ -+ volatile reg_bt_dither_sed_w1 bt_dither_sed_w1; /* 0xd2a0 */ -+ volatile reg_bt_dither_sed_y2 bt_dither_sed_y2; /* 0xd2a4 */ -+ volatile reg_bt_dither_sed_u2 bt_dither_sed_u2; /* 0xd2a8 */ -+ volatile reg_bt_dither_sed_v2 bt_dither_sed_v2; /* 0xd2ac */ -+ volatile reg_bt_dither_sed_w2 bt_dither_sed_w2; /* 0xd2b0 */ -+ volatile reg_bt_dither_sed_y3 bt_dither_sed_y3; /* 0xd2b4 */ -+ volatile reg_bt_dither_sed_u3 bt_dither_sed_u3; /* 0xd2b8 */ -+ volatile reg_bt_dither_sed_v3 bt_dither_sed_v3; /* 0xd2bc */ -+ volatile reg_bt_dither_sed_w3 bt_dither_sed_w3; /* 0xd2c0 */ -+ volatile reg_bt_dither_thr bt_dither_thr; /* 0xd2c4 */ -+ volatile unsigned int reserved_137[10]; /* 0xd2c8~0xd2ec 10 regs */ -+ volatile unsigned int bt_intf_chksum_y; /* 0xd2f0 */ -+ volatile unsigned int bt_intf_chksum_u; /* 0xd2f4 */ -+ volatile unsigned int bt_intf_chksum_v; /* 0xd2f8 */ -+ volatile unsigned int reserved_138; /* 0xd2fc */ -+ volatile reg_intf_lcd_ctrl intf_lcd_ctrl; /* 0xd300 */ -+ volatile reg_intf_lcd_upd intf_lcd_upd; /* 0xd304 */ -+ volatile reg_intf_lcd_sync_inv intf_lcd_sync_inv; /* 0xd308 */ -+ volatile unsigned int reserved_139[5]; /* 0xd30c~0xd31c 5 regs */ -+ volatile reg_lcd_csc_idc lcd_csc_idc; /* 0xd320 */ -+ volatile reg_lcd_csc_odc lcd_csc_odc; /* 0xd324 */ -+ volatile reg_lcd_csc_iodc lcd_csc_iodc; /* 0xd328 */ -+ volatile reg_lcd_csc_p0 lcd_csc_p0; /* 0xd32c */ -+ volatile reg_lcd_csc_p1 lcd_csc_p1; /* 0xd330 */ -+ volatile reg_lcd_csc_p2 lcd_csc_p2; /* 0xd334 */ -+ volatile reg_lcd_csc_p3 lcd_csc_p3; /* 0xd338 */ -+ volatile reg_lcd_csc_p4 lcd_csc_p4; /* 0xd33c */ -+ volatile unsigned int reserved_140[16]; /* 0xd340~0xd37c 16 regs */ -+ volatile reg_lcd_dither_ctrl lcd_dither_ctrl; /* 0xd380 */ -+ volatile reg_lcd_dither_sed_y0 lcd_dither_sed_y0; /* 0xd384 */ -+ volatile reg_lcd_dither_sed_u0 lcd_dither_sed_u0; /* 0xd388 */ -+ volatile reg_lcd_dither_sed_v0 lcd_dither_sed_v0; /* 0xd38c */ -+ volatile reg_lcd_dither_sed_w0 lcd_dither_sed_w0; /* 0xd390 */ -+ volatile reg_lcd_dither_sed_y1 lcd_dither_sed_y1; /* 0xd394 */ -+ volatile reg_lcd_dither_sed_u1 lcd_dither_sed_u1; /* 0xd398 */ -+ volatile reg_lcd_dither_sed_v1 lcd_dither_sed_v1; /* 0xd39c */ -+ volatile reg_lcd_dither_sed_w1 lcd_dither_sed_w1; /* 0xd3a0 */ -+ volatile reg_lcd_dither_sed_y2 lcd_dither_sed_y2; /* 0xd3a4 */ -+ volatile reg_lcd_dither_sed_u2 lcd_dither_sed_u2; /* 0xd3a8 */ -+ volatile reg_lcd_dither_sed_v2 lcd_dither_sed_v2; /* 0xd3ac */ -+ volatile reg_lcd_dither_sed_w2 lcd_dither_sed_w2; /* 0xd3b0 */ -+ volatile reg_lcd_dither_sed_y3 lcd_dither_sed_y3; /* 0xd3b4 */ -+ volatile reg_lcd_dither_sed_u3 lcd_dither_sed_u3; /* 0xd3b8 */ -+ volatile reg_lcd_dither_sed_v3 lcd_dither_sed_v3; /* 0xd3bc */ -+ volatile reg_lcd_dither_sed_w3 lcd_dither_sed_w3; /* 0xd3c0 */ -+ volatile reg_lcd_dither_thr lcd_dither_thr; /* 0xd3c4 */ -+ volatile unsigned int reserved_141[10]; /* 0xd3c8~0xd3ec 10 regs */ -+ volatile unsigned int lcd_intf_chksum_y; /* 0xd3f0 */ -+ volatile unsigned int lcd_intf_chksum_u; /* 0xd3f4 */ -+ volatile unsigned int lcd_intf_chksum_v; /* 0xd3f8 */ -+ volatile unsigned int reserved_142; /* 0xd3fc */ -+ volatile reg_intf_hdmi1_ctrl intf_hdmi1_ctrl; /* 0xd400 */ -+ volatile reg_intf_hdmi1_upd intf_hdmi1_upd; /* 0xd404 */ -+ volatile reg_intf_hdmi1_sync_inv intf_hdmi1_sync_inv; /* 0xd408 */ -+ volatile unsigned int reserved_143; /* 0xd40c */ -+ volatile unsigned int hdmi1_intf_chksum_y; /* 0xd410 */ -+ volatile unsigned int hdmi1_intf_chksum_u; /* 0xd414 */ -+ volatile unsigned int hdmi1_intf_chksum_v; /* 0xd418 */ -+ volatile reg_hdmi1_intf_chksum_high hdmi1_intf_chksum_high; /* 0xd41c */ -+ volatile unsigned int hdmi1_intf1_chksum_y; /* 0xd420 */ -+ volatile unsigned int hdmi1_intf1_chksum_u; /* 0xd424 */ -+ volatile unsigned int hdmi1_intf1_chksum_v; /* 0xd428 */ -+ volatile reg_hdmi1_intf1_chksum_high hdmi1_intf1_chksum_high; /* 0xd42c */ -+ volatile unsigned int reserved_144[8]; /* 0xd430~0xd44c 8 regs */ -+ volatile reg_hdmi1_hfir_coef0 hdmi1_hfir_coef0; /* 0xd450 */ -+ volatile reg_hdmi1_hfir_coef1 hdmi1_hfir_coef1; /* 0xd454 */ -+ volatile reg_hdmi1_hfir_coef2 hdmi1_hfir_coef2; /* 0xd458 */ -+ volatile reg_hdmi1_hfir_coef3 hdmi1_hfir_coef3; /* 0xd45c */ -+ volatile unsigned int reserved_145[40]; /* 0xd460~0xd4fc 40 regs */ -+ volatile reg_intf_vga_ctrl intf_vga_ctrl; /* 0xd500 */ -+ volatile reg_intf_vga_upd intf_vga_upd; /* 0xd504 */ -+ volatile reg_intf_vga_sync_inv intf_vga_sync_inv; /* 0xd508 */ -+ volatile unsigned int reserved_146[5]; /* 0xd50c~0xd51c 5 regs */ -+ volatile reg_vga_csc_idc vga_csc_idc; /* 0xd520 */ -+ volatile reg_vga_csc_odc vga_csc_odc; /* 0xd524 */ -+ volatile reg_vga_csc_iodc vga_csc_iodc; /* 0xd528 */ -+ volatile reg_vga_csc_p0 vga_csc_p0; /* 0xd52c */ -+ volatile reg_vga_csc_p1 vga_csc_p1; /* 0xd530 */ -+ volatile reg_vga_csc_p2 vga_csc_p2; /* 0xd534 */ -+ volatile reg_vga_csc_p3 vga_csc_p3; /* 0xd538 */ -+ volatile reg_vga_csc_p4 vga_csc_p4; /* 0xd53c */ -+ volatile reg_vga_hspcfg0 vga_hspcfg0; /* 0xd540 */ -+ volatile reg_vga_hspcfg1 vga_hspcfg1; /* 0xd544 */ -+ volatile unsigned int reserved_147[3]; /* 0xd548~0xd550 3 regs */ -+ volatile reg_vga_hspcfg5 vga_hspcfg5; /* 0xd554 */ -+ volatile reg_vga_hspcfg6 vga_hspcfg6; /* 0xd558 */ -+ volatile reg_vga_hspcfg7 vga_hspcfg7; /* 0xd55c */ -+ volatile reg_vga_hspcfg8 vga_hspcfg8; /* 0xd560 */ -+ volatile unsigned int reserved_148[3]; /* 0xd564~0xd56c 3 regs */ -+ volatile reg_vga_hspcfg12 vga_hspcfg12; /* 0xd570 */ -+ volatile reg_vga_hspcfg13 vga_hspcfg13; /* 0xd574 */ -+ volatile reg_vga_hspcfg14 vga_hspcfg14; /* 0xd578 */ -+ volatile reg_vga_hspcfg15 vga_hspcfg15; /* 0xd57c */ -+ volatile unsigned int reserved_149[28]; /* 0xd580~0xd5ec 28 regs */ -+ volatile unsigned int vga_intf_chksum_y; /* 0xd5f0 */ -+ volatile unsigned int vga_intf_chksum_u; /* 0xd5f4 */ -+ volatile unsigned int vga_intf_chksum_v; /* 0xd5f8 */ -+ volatile unsigned int reserved_150; /* 0xd5fc */ -+ volatile reg_intf_date_ctrl intf_date_ctrl; /* 0xd600 */ -+ volatile reg_intf_date_upd intf_date_upd; /* 0xd604 */ -+ volatile reg_intf_date_sync_inv intf_date_sync_inv; /* 0xd608 */ -+ volatile unsigned int reserved_151; /* 0xd60c */ -+ volatile reg_date_clip0_l date_clip0_l; /* 0xd610 */ -+ volatile reg_date_clip0_h date_clip0_h; /* 0xd614 */ -+ volatile unsigned int reserved_152[58]; /* 0xd618~0xd6fc 58 regs */ -+ volatile reg_intf0_dither_ctrl intf0_dither_ctrl; /* 0xd700 */ -+ volatile reg_intf0_dither_sed_y0 intf0_dither_sed_y0; /* 0xd704 */ -+ volatile reg_intf0_dither_sed_u0 intf0_dither_sed_u0; /* 0xd708 */ -+ volatile reg_intf0_dither_sed_v0 intf0_dither_sed_v0; /* 0xd70c */ -+ volatile reg_intf0_dither_sed_w0 intf0_dither_sed_w0; /* 0xd710 */ -+ volatile reg_intf0_dither_sed_y1 intf0_dither_sed_y1; /* 0xd714 */ -+ volatile reg_intf0_dither_sed_u1 intf0_dither_sed_u1; /* 0xd718 */ -+ volatile reg_intf0_dither_sed_v1 intf0_dither_sed_v1; /* 0xd71c */ -+ volatile reg_intf0_dither_sed_w1 intf0_dither_sed_w1; /* 0xd720 */ -+ volatile reg_intf0_dither_sed_y2 intf0_dither_sed_y2; /* 0xd724 */ -+ volatile reg_intf0_dither_sed_u2 intf0_dither_sed_u2; /* 0xd728 */ -+ volatile reg_intf0_dither_sed_v2 intf0_dither_sed_v2; /* 0xd72c */ -+ volatile reg_intf0_dither_sed_w2 intf0_dither_sed_w2; /* 0xd730 */ -+ volatile reg_intf0_dither_sed_y3 intf0_dither_sed_y3; /* 0xd734 */ -+ volatile reg_intf0_dither_sed_u3 intf0_dither_sed_u3; /* 0xd738 */ -+ volatile reg_intf0_dither_sed_v3 intf0_dither_sed_v3; /* 0xd73c */ -+ volatile reg_intf0_dither_sed_w3 intf0_dither_sed_w3; /* 0xd740 */ -+ volatile reg_intf0_dither_thr intf0_dither_thr; /* 0xd744 */ -+ volatile unsigned int reserved_153[14]; /* 0xd748~0xd77c 14 regs */ -+ volatile reg_intf_mipi_ctrl intf_mipi_ctrl; /* 0xd780 */ -+ volatile reg_intf_mipi_upd intf_mipi_upd; /* 0xd784 */ -+ volatile reg_intf_mipi_sync_inv intf_mipi_sync_inv; /* 0xd788 */ -+ volatile unsigned int reserved_154; /* 0xd78c */ -+ volatile unsigned int mipi_intf_chksum_y; /* 0xd790 */ -+ volatile unsigned int mipi_intf_chksum_u; /* 0xd794 */ -+ volatile unsigned int mipi_intf_chksum_v; /* 0xd798 */ -+ volatile reg_mipi_intf_chksum_high mipi_intf_chksum_high; /* 0xd79c */ -+ volatile unsigned int mipi_intf1_chksum_y; /* 0xd7a0 */ -+ volatile unsigned int mipi_intf1_chksum_u; /* 0xd7a4 */ -+ volatile unsigned int mipi_intf1_chksum_v; /* 0xd7a8 */ -+ volatile reg_mipi_intf1_chksum_high mipi_intf1_chksum_high; /* 0xd7ac */ -+ volatile unsigned int reserved_155[8]; /* 0xd7b0~0xd7cc 8 regs */ -+ volatile reg_mipi_hfir_coef0 mipi_hfir_coef0; /* 0xd7d0 */ -+ volatile reg_mipi_hfir_coef1 mipi_hfir_coef1; /* 0xd7d4 */ -+ volatile reg_mipi_hfir_coef2 mipi_hfir_coef2; /* 0xd7d8 */ -+ volatile reg_mipi_hfir_coef3 mipi_hfir_coef3; /* 0xd7dc */ -+ volatile reg_mipi_csc_idc mipi_csc_idc; /* 0xd7e0 */ -+ volatile reg_mipi_csc_odc mipi_csc_odc; /* 0xd7e4 */ -+ volatile reg_mipi_csc_iodc mipi_csc_iodc; /* 0xd7e8 */ -+ volatile reg_mipi_csc_p0 mipi_csc_p0; /* 0xd7ec */ -+ volatile reg_mipi_csc_p1 mipi_csc_p1; /* 0xd7f0 */ -+ volatile reg_mipi_csc_p2 mipi_csc_p2; /* 0xd7f4 */ -+ volatile reg_mipi_csc_p3 mipi_csc_p3; /* 0xd7f8 */ -+ volatile reg_mipi_csc_p4 mipi_csc_p4; /* 0xd7fc */ -+ volatile reg_mipi_dither_ctrl mipi_dither_ctrl; /* 0xd800 */ -+ volatile reg_mipi_dither_sed_y0 mipi_dither_sed_y0; /* 0xd804 */ -+ volatile reg_mipi_dither_sed_u0 mipi_dither_sed_u0; /* 0xd808 */ -+ volatile reg_mipi_dither_sed_v0 mipi_dither_sed_v0; /* 0xd80c */ -+ volatile reg_mipi_dither_sed_w0 mipi_dither_sed_w0; /* 0xd810 */ -+ volatile reg_mipi_dither_sed_y1 mipi_dither_sed_y1; /* 0xd814 */ -+ volatile reg_mipi_dither_sed_u1 mipi_dither_sed_u1; /* 0xd818 */ -+ volatile reg_mipi_dither_sed_v1 mipi_dither_sed_v1; /* 0xd81c */ -+ volatile reg_mipi_dither_sed_w1 mipi_dither_sed_w1; /* 0xd820 */ -+ volatile reg_mipi_dither_sed_y2 mipi_dither_sed_y2; /* 0xd824 */ -+ volatile reg_mipi_dither_sed_u2 mipi_dither_sed_u2; /* 0xd828 */ -+ volatile reg_mipi_dither_sed_v2 mipi_dither_sed_v2; /* 0xd82c */ -+ volatile reg_mipi_dither_sed_w2 mipi_dither_sed_w2; /* 0xd830 */ -+ volatile reg_mipi_dither_sed_y3 mipi_dither_sed_y3; /* 0xd834 */ -+ volatile reg_mipi_dither_sed_u3 mipi_dither_sed_u3; /* 0xd838 */ -+ volatile reg_mipi_dither_sed_v3 mipi_dither_sed_v3; /* 0xd83c */ -+ volatile reg_mipi_dither_sed_w3 mipi_dither_sed_w3; /* 0xd840 */ -+ volatile reg_mipi_dither_thr mipi_dither_thr; /* 0xd844 */ -+ volatile unsigned int reserved_156[494]; /* 0xd848~0xdffc 494 regs */ -+ volatile reg_dhd1_ctrl dhd1_ctrl; /* 0xe000 */ -+ volatile reg_dhd1_vsync1 dhd1_vsync1; /* 0xe004 */ -+ volatile reg_dhd1_vsync2 dhd1_vsync2; /* 0xe008 */ -+ volatile reg_dhd1_hsync1 dhd1_hsync1; /* 0xe00c */ -+ volatile reg_dhd1_hsync2 dhd1_hsync2; /* 0xe010 */ -+ volatile reg_dhd1_vplus1 dhd1_vplus1; /* 0xe014 */ -+ volatile reg_dhd1_vplus2 dhd1_vplus2; /* 0xe018 */ -+ volatile reg_dhd1_pwr dhd1_pwr; /* 0xe01c */ -+ volatile reg_dhd1_vtthd3 dhd1_vtthd3; /* 0xe020 */ -+ volatile reg_dhd1_vtthd dhd1_vtthd; /* 0xe024 */ -+ volatile reg_dhd1_parathd dhd1_parathd; /* 0xe028 */ -+ volatile reg_dhd1_precharge_thd dhd1_precharge_thd; /* 0xe02c */ -+ volatile reg_dhd1_start_pos dhd1_start_pos; /* 0xe030 */ -+ volatile reg_dhd1_start_pos1 dhd1_start_pos1; /* 0xe034 */ -+ volatile reg_dhd1_paraup dhd1_paraup; /* 0xe038 */ -+ volatile reg_dhd1_sync_inv dhd1_sync_inv; /* 0xe03c */ -+ volatile reg_dhd1_clk_dv_ctrl dhd1_clk_dv_ctrl; /* 0xe040 */ -+ volatile reg_dhd1_rgb_fix_ctrl dhd1_rgb_fix_ctrl; /* 0xe044 */ -+ volatile reg_dhd1_lockcfg dhd1_lockcfg; /* 0xe048 */ -+ volatile unsigned int dhd1_cap_frm_cnt; /* 0xe04c */ -+ volatile unsigned int dhd1_vdp_frm_cnt; /* 0xe050 */ -+ volatile unsigned int dhd1_vsync_cap_vdp_cnt; /* 0xe054 */ -+ volatile unsigned int dhd1_intf_chksum_y; /* 0xe058 */ -+ volatile unsigned int dhd1_intf_chksum_u; /* 0xe05c */ -+ volatile unsigned int dhd1_intf_chksum_v; /* 0xe060 */ -+ volatile unsigned int dhd1_intf1_chksum_y; /* 0xe064 */ -+ volatile unsigned int dhd1_intf1_chksum_u; /* 0xe068 */ -+ volatile unsigned int dhd1_intf1_chksum_v; /* 0xe06c */ -+ volatile reg_dhd1_intf_chksum_high1 dhd1_intf_chksum_high1; /* 0xe070 */ -+ volatile reg_dhd1_intf_chksum_high2 dhd1_intf_chksum_high2; /* 0xe074 */ -+ volatile unsigned int reserved_157[3]; /* 0xe078~0xe080 3 regs */ -+ volatile unsigned int dhd1_afifo_pre_thd; /* 0xe084 */ -+ volatile reg_dhd1_state dhd1_state; /* 0xe088 */ -+ volatile reg_dhd1_uf_state dhd1_uf_state; /* 0xe08c */ -+ volatile unsigned int reserved_158[4]; /* 0xe090~0xe09c 4 regs */ -+ volatile reg_dhd1_vsync_te_state dhd1_vsync_te_state; /* 0xe0a0 */ -+ volatile reg_dhd1_vsync_te_state1 dhd1_vsync_te_state1; /* 0xe0a4 */ -+ volatile unsigned int reserved_159[406]; /* 0xe0a8~0xe6fc 406 regs */ -+ volatile reg_intf1_dither_ctrl intf1_dither_ctrl; /* 0xe700 */ -+ volatile reg_intf1_dither_sed_y0 intf1_dither_sed_y0; /* 0xe704 */ -+ volatile reg_intf1_dither_sed_u0 intf1_dither_sed_u0; /* 0xe708 */ -+ volatile reg_intf1_dither_sed_v0 intf1_dither_sed_v0; /* 0xe70c */ -+ volatile reg_intf1_dither_sed_w0 intf1_dither_sed_w0; /* 0xe710 */ -+ volatile reg_intf1_dither_sed_y1 intf1_dither_sed_y1; /* 0xe714 */ -+ volatile reg_intf1_dither_sed_u1 intf1_dither_sed_u1; /* 0xe718 */ -+ volatile reg_intf1_dither_sed_v1 intf1_dither_sed_v1; /* 0xe71c */ -+ volatile reg_intf1_dither_sed_w1 intf1_dither_sed_w1; /* 0xe720 */ -+ volatile reg_intf1_dither_sed_y2 intf1_dither_sed_y2; /* 0xe724 */ -+ volatile reg_intf1_dither_sed_u2 intf1_dither_sed_u2; /* 0xe728 */ -+ volatile reg_intf1_dither_sed_v2 intf1_dither_sed_v2; /* 0xe72c */ -+ volatile reg_intf1_dither_sed_w2 intf1_dither_sed_w2; /* 0xe730 */ -+ volatile reg_intf1_dither_sed_y3 intf1_dither_sed_y3; /* 0xe734 */ -+ volatile reg_intf1_dither_sed_u3 intf1_dither_sed_u3; /* 0xe738 */ -+ volatile reg_intf1_dither_sed_v3 intf1_dither_sed_v3; /* 0xe73c */ -+ volatile reg_intf1_dither_sed_w3 intf1_dither_sed_w3; /* 0xe740 */ -+ volatile reg_intf1_dither_thr intf1_dither_thr; /* 0xe744 */ -+ volatile unsigned int reserved_160[558]; /* 0xe748~0xeffc 558 regs */ -+ volatile reg_dhd2_ctrl dhd2_ctrl; /* 0xf000 */ -+ volatile reg_dhd2_vsync1 dhd2_vsync1; /* 0xf004 */ -+ volatile reg_dhd2_vsync2 dhd2_vsync2; /* 0xf008 */ -+ volatile reg_dhd2_hsync1 dhd2_hsync1; /* 0xf00c */ -+ volatile reg_dhd2_hsync2 dhd2_hsync2; /* 0xf010 */ -+ volatile reg_dhd2_vplus1 dhd2_vplus1; /* 0xf014 */ -+ volatile reg_dhd2_vplus2 dhd2_vplus2; /* 0xf018 */ -+ volatile reg_dhd2_pwr dhd2_pwr; /* 0xf01c */ -+ volatile reg_dhd2_vtthd3 dhd2_vtthd3; /* 0xf020 */ -+ volatile reg_dhd2_vtthd dhd2_vtthd; /* 0xf024 */ -+ volatile reg_dhd2_parathd dhd2_parathd; /* 0xf028 */ -+ volatile reg_dhd2_precharge_thd dhd2_precharge_thd; /* 0xf02c */ -+ volatile reg_dhd2_start_pos dhd2_start_pos; /* 0xf030 */ -+ volatile reg_dhd2_start_pos1 dhd2_start_pos1; /* 0xf034 */ -+ volatile reg_dhd2_paraup dhd2_paraup; /* 0xf038 */ -+ volatile reg_dhd2_sync_inv dhd2_sync_inv; /* 0xf03c */ -+ volatile reg_dhd2_clk_dv_ctrl dhd2_clk_dv_ctrl; /* 0xf040 */ -+ volatile reg_dhd2_rgb_fix_ctrl dhd2_rgb_fix_ctrl; /* 0xf044 */ -+ volatile reg_dhd2_lockcfg dhd2_lockcfg; /* 0xf048 */ -+ volatile unsigned int dhd2_cap_frm_cnt; /* 0xf04c */ -+ volatile unsigned int dhd2_vdp_frm_cnt; /* 0xf050 */ -+ volatile unsigned int dhd2_vsync_cap_vdp_cnt; /* 0xf054 */ -+ volatile unsigned int dhd2_intf_chksum_y; /* 0xf058 */ -+ volatile unsigned int dhd2_intf_chksum_u; /* 0xf05c */ -+ volatile unsigned int dhd2_intf_chksum_v; /* 0xf060 */ -+ volatile unsigned int dhd2_intf1_chksum_y; /* 0xf064 */ -+ volatile unsigned int dhd2_intf1_chksum_u; /* 0xf068 */ -+ volatile unsigned int dhd2_intf1_chksum_v; /* 0xf06c */ -+ volatile reg_dhd2_intf_chksum_high1 dhd2_intf_chksum_high1; /* 0xf070 */ -+ volatile reg_dhd2_intf_chksum_high2 dhd2_intf_chksum_high2; /* 0xf074 */ -+ volatile unsigned int reserved_161[3]; /* 0xf078~0xf080 3 regs */ -+ volatile unsigned int dhd2_afifo_pre_thd; /* 0xf084 */ -+ volatile reg_dhd2_state dhd2_state; /* 0xf088 */ -+ volatile reg_dhd2_uf_state dhd2_uf_state; /* 0xf08c */ -+ volatile unsigned int reserved_162[4]; /* 0xf090~0xf09c 4 regs */ -+ volatile reg_dhd2_vsync_te_state dhd2_vsync_te_state; /* 0xf0a0 */ -+ volatile reg_dhd2_vsync_te_state1 dhd2_vsync_te_state1; /* 0xf0a4 */ -+ volatile unsigned int reserved_163[406]; /* 0xf0a8~0xf6fc 406 regs */ -+ volatile reg_intf2_dither_ctrl intf2_dither_ctrl; /* 0xf700 */ -+ volatile reg_intf2_dither_sed_y0 intf2_dither_sed_y0; /* 0xf704 */ -+ volatile reg_intf2_dither_sed_u0 intf2_dither_sed_u0; /* 0xf708 */ -+ volatile reg_intf2_dither_sed_v0 intf2_dither_sed_v0; /* 0xf70c */ -+ volatile reg_intf2_dither_sed_w0 intf2_dither_sed_w0; /* 0xf710 */ -+ volatile reg_intf2_dither_sed_y1 intf2_dither_sed_y1; /* 0xf714 */ -+ volatile reg_intf2_dither_sed_u1 intf2_dither_sed_u1; /* 0xf718 */ -+ volatile reg_intf2_dither_sed_v1 intf2_dither_sed_v1; /* 0xf71c */ -+ volatile reg_intf2_dither_sed_w1 intf2_dither_sed_w1; /* 0xf720 */ -+ volatile reg_intf2_dither_sed_y2 intf2_dither_sed_y2; /* 0xf724 */ -+ volatile reg_intf2_dither_sed_u2 intf2_dither_sed_u2; /* 0xf728 */ -+ volatile reg_intf2_dither_sed_v2 intf2_dither_sed_v2; /* 0xf72c */ -+ volatile reg_intf2_dither_sed_w2 intf2_dither_sed_w2; /* 0xf730 */ -+ volatile reg_intf2_dither_sed_y3 intf2_dither_sed_y3; /* 0xf734 */ -+ volatile reg_intf2_dither_sed_u3 intf2_dither_sed_u3; /* 0xf738 */ -+ volatile reg_intf2_dither_sed_v3 intf2_dither_sed_v3; /* 0xf73c */ -+ volatile reg_intf2_dither_sed_w3 intf2_dither_sed_w3; /* 0xf740 */ -+ volatile reg_intf2_dither_thr intf2_dither_thr; /* 0xf744 */ -+ volatile unsigned int reserved_164[46]; /* 0xf748~0xf7fc 46 regs */ -+ volatile reg_date_coeff0 date_coeff0; /* 0xf800 */ -+ volatile reg_date_coeff1 date_coeff1; /* 0xf804 */ -+ volatile unsigned int date_coeff2; /* 0xf808 */ -+ volatile reg_date_coeff3 date_coeff3; /* 0xf80c */ -+ volatile reg_date_coeff4 date_coeff4; /* 0xf810 */ -+ volatile reg_date_coeff5 date_coeff5; /* 0xf814 */ -+ volatile reg_date_coeff6 date_coeff6; /* 0xf818 */ -+ volatile reg_date_coeff7 date_coeff7; /* 0xf81c */ -+ volatile unsigned int date_coeff8; /* 0xf820 */ -+ volatile unsigned int date_coeff9; /* 0xf824 */ -+ volatile reg_date_coeff10 date_coeff10; /* 0xf828 */ -+ volatile reg_date_coeff11 date_coeff11; /* 0xf82c */ -+ volatile reg_date_coeff12 date_coeff12; /* 0xf830 */ -+ volatile reg_date_coeff13 date_coeff13; /* 0xf834 */ -+ volatile reg_date_coeff14 date_coeff14; /* 0xf838 */ -+ volatile reg_date_coeff15 date_coeff15; /* 0xf83c */ -+ volatile reg_date_coeff16 date_coeff16; /* 0xf840 */ -+ volatile unsigned int date_coeff17; /* 0xf844 */ -+ volatile unsigned int date_coeff18; /* 0xf848 */ -+ volatile reg_date_coeff19 date_coeff19; /* 0xf84c */ -+ volatile reg_date_coeff20 date_coeff20; /* 0xf850 */ -+ volatile reg_date_coeff21 date_coeff21; /* 0xf854 */ -+ volatile reg_date_coeff22 date_coeff22; /* 0xf858 */ -+ volatile reg_date_coeff23 date_coeff23; /* 0xf85c */ -+ volatile unsigned int date_coeff24; /* 0xf860 */ -+ volatile reg_date_coeff25 date_coeff25; /* 0xf864 */ -+ volatile reg_date_coeff26 date_coeff26; /* 0xf868 */ -+ volatile reg_date_coeff27 date_coeff27; /* 0xf86c */ -+ volatile reg_date_coeff28 date_coeff28; /* 0xf870 */ -+ volatile reg_date_coeff29 date_coeff29; /* 0xf874 */ -+ volatile reg_date_coeff30 date_coeff30; /* 0xf878 */ -+ volatile unsigned int reserved_165; /* 0xf87c */ -+ volatile reg_date_isrmask date_isrmask; /* 0xf880 */ -+ volatile reg_date_isrstate date_isrstate; /* 0xf884 */ -+ volatile reg_date_isr date_isr; /* 0xf888 */ -+ volatile unsigned int reserved_166; /* 0xf88c */ -+ volatile unsigned int date_version; /* 0xf890 */ -+ volatile reg_date_coeff37 date_coeff37; /* 0xf894 */ -+ volatile reg_date_coeff38 date_coeff38; /* 0xf898 */ -+ volatile reg_date_coeff39 date_coeff39; /* 0xf89c */ -+ volatile reg_date_coeff40 date_coeff40; /* 0xf8a0 */ -+ volatile reg_date_coeff41 date_coeff41; /* 0xf8a4 */ -+ volatile reg_date_coeff42 date_coeff42; /* 0xf8a8 */ -+ volatile unsigned int reserved_167[5]; /* 0xf8ac~0xf8bc 5 regs */ -+ volatile reg_date_dacdet1 date_dacdet1; /* 0xf8c0 */ -+ volatile reg_date_dacdet2 date_dacdet2; /* 0xf8c4 */ -+ volatile reg_date_coeff50 date_coeff50; /* 0xf8c8 */ -+ volatile reg_date_coeff51 date_coeff51; /* 0xf8cc */ -+ volatile reg_date_coeff52 date_coeff52; /* 0xf8d0 */ -+ volatile reg_date_coeff53 date_coeff53; /* 0xf8d4 */ -+ volatile reg_date_coeff54 date_coeff54; /* 0xf8d8 */ -+ volatile reg_date_coeff55 date_coeff55; /* 0xf8dc */ -+ volatile unsigned int reserved_168_1; /* 0xf8e0 */ -+ volatile reg_date_coeff57 date_coeff57; /* 0xf8e4 */ -+ volatile unsigned int reserved_168_2[454]; /* 0xf8e8~0xfffc 454 regs */ -+ volatile reg_mac_outstanding mac_outstanding; /* 0x10000 */ -+ volatile reg_mac_ctrl mac_ctrl; /* 0x10004 */ -+ volatile unsigned int reserved_169[2]; /* 0x10008~0x1000c 2 regs */ -+ volatile reg_mac_rchn_prio mac_rchn_prio; /* 0x10010 */ -+ volatile unsigned int reserved_170; /* 0x10014 */ -+ volatile reg_mac_wchn_prio mac_wchn_prio; /* 0x10018 */ -+ volatile unsigned int reserved_171; /* 0x1001c */ -+ volatile reg_mac_rchn_sel0 mac_rchn_sel0; /* 0x10020 */ -+ volatile unsigned int mac_rchn_sel1; /* 0x10024 */ -+ volatile unsigned int reserved_172[2]; /* 0x10028~0x1002c 2 regs */ -+ volatile reg_mac_wchn_sel0 mac_wchn_sel0; /* 0x10030 */ -+ volatile unsigned int reserved_173[3]; /* 0x10034~0x1003c 3 regs */ -+ volatile reg_mac_bus_err_clr mac_bus_err_clr; /* 0x10040 */ -+ volatile reg_mac_bus_err mac_bus_err; /* 0x10044 */ -+ volatile unsigned int reserved_174[2]; /* 0x10048~0x1004c 2 regs */ -+ volatile unsigned int mac_src0_status0; /* 0x10050 */ -+ volatile unsigned int mac_src0_status1; /* 0x10054 */ -+ volatile unsigned int mac_src1_status0; /* 0x10058 */ -+ volatile unsigned int mac_src1_status1; /* 0x1005c */ -+ volatile unsigned int mac_src2_status0; /* 0x10060 */ -+ volatile unsigned int mac_src2_status1; /* 0x10064 */ -+ volatile unsigned int reserved_175[2]; /* 0x10068~0x1006c 2 regs */ -+ volatile reg_mac_debug_ctrl mac_debug_ctrl; /* 0x10070 */ -+ volatile reg_mac_debug_clr mac_debug_clr; /* 0x10074 */ -+ volatile unsigned int reserved_176[2]; /* 0x10078~0x1007c 2 regs */ -+ volatile unsigned int mac0_debug_info; /* 0x10080 */ -+ volatile unsigned int reserved_177[3]; /* 0x10084~0x1008c 3 regs */ -+ volatile unsigned int mac0_rd_info; /* 0x10090 */ -+ volatile unsigned int mac0_wr_info; /* 0x10094 */ -+ volatile unsigned int mac1_rd_info; /* 0x10098 */ -+ volatile unsigned int mac1_wr_info; /* 0x1009c */ -+ volatile unsigned int mac2_rd_info; /* 0x100a0 */ -+ volatile unsigned int mac2_wr_info; /* 0x100a4 */ -+ volatile unsigned int reserved_178[2]; /* 0x100a8~0x100ac 2 regs */ -+ volatile unsigned int mac0_det_latency0; /* 0x100b0 */ -+ volatile unsigned int mac0_det_latency1; /* 0x100b4 */ -+ volatile unsigned int mac0_det_latency2; /* 0x100b8 */ -+ volatile unsigned int mac0_det_latency3; /* 0x100bc */ -+ volatile unsigned int mac0_det_latency4; /* 0x100c0 */ -+ volatile unsigned int mac0_det_latency5; /* 0x100c4 */ -+ volatile unsigned int mac1_det_latency0; /* 0x100c8 */ -+ volatile unsigned int mac1_det_latency1; /* 0x100cc */ -+ volatile unsigned int mac1_det_latency2; /* 0x100d0 */ -+ volatile unsigned int mac1_det_latency3; /* 0x100d4 */ -+ volatile unsigned int mac1_det_latency4; /* 0x100d8 */ -+ volatile unsigned int mac1_det_latency5; /* 0x100dc */ -+ volatile unsigned int reserved_179[8]; /* 0x100e0~0x100fc 8 regs */ -+ volatile reg_mac_axi_press0_ctrl0 mac_axi_press0_ctrl0; /* 0x10100 */ -+ volatile reg_mac_axi_press0_ctrl1 mac_axi_press0_ctrl1; /* 0x10104 */ -+ volatile reg_mac_axi_press0_ctrl2 mac_axi_press0_ctrl2; /* 0x10108 */ -+ volatile reg_mac_axi_press0_ctrl3 mac_axi_press0_ctrl3; /* 0x1010c */ -+ volatile reg_mac_axi_press0_ctrl4 mac_axi_press0_ctrl4; /* 0x10110 */ -+ volatile unsigned int reserved_180[3]; /* 0x10114~0x1011c 3 regs */ -+ volatile reg_mac_axi_press0_ctrl5 mac_axi_press0_ctrl5; /* 0x10120 */ -+ volatile unsigned int reserved_181[23]; /* 0x10124~0x1017c 23 regs */ -+ volatile reg_mac_axi_press1_ctrl0 mac_axi_press1_ctrl0; /* 0x10180 */ -+ volatile reg_mac_axi_press1_ctrl1 mac_axi_press1_ctrl1; /* 0x10184 */ -+ volatile reg_mac_axi_press1_ctrl2 mac_axi_press1_ctrl2; /* 0x10188 */ -+ volatile reg_mac_axi_press1_ctrl3 mac_axi_press1_ctrl3; /* 0x1018c */ -+ volatile reg_mac_axi_press1_ctrl4 mac_axi_press1_ctrl4; /* 0x10190 */ -+ volatile unsigned int reserved_182[3]; /* 0x10194~0x1019c 3 regs */ -+ volatile reg_mac_axi_press1_ctrl5 mac_axi_press1_ctrl5; /* 0x101a0 */ -+ volatile unsigned int reserved_183[23]; /* 0x101a4~0x101fc 23 regs */ -+ volatile reg_vid_read_ctrl vid_read_ctrl; /* 0x10200 */ -+ volatile reg_vid_mac_ctrl vid_mac_ctrl; /* 0x10204 */ -+ volatile unsigned int reserved_184[2]; /* 0x10208~0x1020c 2 regs */ -+ volatile reg_vid_out_ctrl vid_out_ctrl; /* 0x10210 */ -+ volatile reg_vid_mute_alpha vid_mute_alpha; /* 0x10214 */ -+ volatile unsigned int reserved_185; /* 0x10218 */ -+ volatile reg_vid_mute_bk vid_mute_bk; /* 0x1021c */ -+ volatile unsigned int reserved_186[8]; /* 0x10220~0x1023c 8 regs */ -+ volatile reg_vid_src_info vid_src_info; /* 0x10240 */ -+ volatile reg_vid_src_reso vid_src_reso; /* 0x10244 */ -+ volatile reg_vid_src_crop vid_src_crop; /* 0x10248 */ -+ volatile reg_vid_in_reso vid_in_reso; /* 0x1024c */ -+ volatile unsigned int vid_addr_h; /* 0x10250 */ -+ volatile unsigned int vid_addr_l; /* 0x10254 */ -+ volatile unsigned int vid_caddr_h; /* 0x10258 */ -+ volatile unsigned int vid_caddr_l; /* 0x1025c */ -+ volatile unsigned int vid_naddr_h; /* 0x10260 */ -+ volatile unsigned int vid_naddr_l; /* 0x10264 */ -+ volatile unsigned int vid_ncaddr_h; /* 0x10268 */ -+ volatile unsigned int vid_ncaddr_l; /* 0x1026c */ -+ volatile reg_vid_stride vid_stride; /* 0x10270 */ -+ volatile reg_vid_2bit_stride vid_2bit_stride; /* 0x10274 */ -+ volatile reg_vid_head_stride vid_head_stride; /* 0x10278 */ -+ volatile unsigned int reserved_187; /* 0x1027c */ -+ volatile reg_vid_smmu_bypass vid_smmu_bypass; /* 0x10280 */ -+ volatile unsigned int reserved_188[3]; /* 0x10284~0x1028c 3 regs */ -+ volatile unsigned int vid_head_addr_h; /* 0x10290 */ -+ volatile unsigned int vid_head_addr_l; /* 0x10294 */ -+ volatile unsigned int vid_head_caddr_h; /* 0x10298 */ -+ volatile unsigned int vid_head_caddr_l; /* 0x1029c */ -+ volatile reg_vid_testpat_cfg vid_testpat_cfg; /* 0x102a0 */ -+ volatile reg_vid_testpat_seed vid_testpat_seed; /* 0x102a4 */ -+ volatile unsigned int vid_testpat_chksum_y; /* 0x102a8 */ -+ volatile unsigned int vid_testpat_chksum_c; /* 0x102ac */ -+ volatile unsigned int vid_work_addr_y; /* 0x102b0 */ -+ volatile unsigned int reserved_189[3]; /* 0x102b4~0x102bc 3 regs */ -+ volatile reg_vid_tunl_ctrl vid_tunl_ctrl; /* 0x102c0 */ -+ volatile reg_vid_tunl_crop vid_tunl_crop; /* 0x102c4 */ -+ volatile unsigned int reserved_190[2]; /* 0x102c8~0x102cc 2 regs */ -+ volatile unsigned int vid_tunl_addr_h; /* 0x102d0 */ -+ volatile unsigned int vid_tunl_addr_l; /* 0x102d4 */ -+ volatile unsigned int reserved_191[2]; /* 0x102d8~0x102dc 2 regs */ -+ volatile reg_vid_tunl_errsta vid_tunl_errsta; /* 0x102e0 */ -+ volatile reg_vid_tunl_debug vid_tunl_debug; /* 0x102e4 */ -+ volatile unsigned int reserved_192[6]; /* 0x102e8~0x102fc 6 regs */ -+ volatile unsigned int vid_l_cur_flow; /* 0x10300 */ -+ volatile unsigned int vid_l_cur_sreq_time; /* 0x10304 */ -+ volatile unsigned int vid_c_cur_flow; /* 0x10308 */ -+ volatile unsigned int vid_c_cur_sreq_time; /* 0x1030c */ -+ volatile unsigned int vid_l_last_flow; /* 0x10310 */ -+ volatile unsigned int vid_l_last_sreq_time; /* 0x10314 */ -+ volatile unsigned int vid_c_last_flow; /* 0x10318 */ -+ volatile unsigned int vid_c_last_sreq_time; /* 0x1031c */ -+ volatile unsigned int vid_l_busy_time; /* 0x10320 */ -+ volatile unsigned int vid_l_neednordy_time; /* 0x10324 */ -+ volatile unsigned int vid_l2_neednordy_time; /* 0x10328 */ -+ volatile unsigned int vid_c_busy_time; /* 0x1032c */ -+ volatile unsigned int vid_c_neednordy_time; /* 0x10330 */ -+ volatile unsigned int vid_c2_neednordy_time; /* 0x10334 */ -+ volatile unsigned int reserved_193[2]; /* 0x10338~0x1033c 2 regs */ -+ volatile reg_vid_dcmp_ctrl vid_dcmp_ctrl; /* 0x10340 */ -+ volatile unsigned int vid_dcmp_l_fsize; /* 0x10344 */ -+ volatile unsigned int reserved_194[14]; /* 0x10348~0x1037c 14 regs */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_glb_info vdp_v3r2_lineseg_dcmp_glb_info; /* 0x10380 */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_frame_size vdp_v3r2_lineseg_dcmp_frame_size; /* 0x10384 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0; /* 0x10388 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1; /* 0x1038c */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr vdp_v3r2_lineseg_dcmp_smth_deltabits_thr; /* 0x10390 */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_error_sta vdp_v3r2_lineseg_dcmp_error_sta; /* 0x10394 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra; /* 0x10398 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg; /* 0x1039c */ -+ volatile unsigned int reserved_195[8]; /* 0x103a0~0x103bc 8 regs */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_glb_info_c vdp_v3r2_lineseg_dcmp_glb_info_c; /* 0x103c0 */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_frame_size_c vdp_v3r2_lineseg_dcmp_frame_size_c; /* 0x103c4 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr0_c; /* 0x103c8 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_adpqp_thr1_c; /* 0x103cc */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c vdp_v3r2_lineseg_dcmp_smth_deltabits_thr_c; /* 0x103d0 */ -+ volatile reg_vdp_v3r2_lineseg_dcmp_error_sta_c vdp_v3r2_lineseg_dcmp_error_sta_c; /* 0x103d4 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_extra_c; /* 0x103d8 */ -+ volatile unsigned int vdp_v3r2_lineseg_dcmp_dbg_reg_c; /* 0x103dc */ -+ volatile unsigned int reserved_196[648]; /* 0x103e0~0x10dfc 648 regs */ -+ volatile reg_gfx_read_ctrl gfx_read_ctrl; /* 0x10e00 */ -+ volatile reg_gfx_mac_ctrl gfx_mac_ctrl; /* 0x10e04 */ -+ volatile reg_gfx_out_ctrl gfx_out_ctrl; /* 0x10e08 */ -+ volatile unsigned int reserved_197; /* 0x10e0c */ -+ volatile reg_gfx_mute_alpha gfx_mute_alpha; /* 0x10e10 */ -+ volatile reg_gfx_mute_bk gfx_mute_bk; /* 0x10e14 2 regs */ -+ volatile unsigned int reserved_198[2]; /* 0x10e18~0x10e1c */ -+ volatile reg_gfx_smmu_bypass gfx_smmu_bypass; /* 0x10e20 */ -+ volatile unsigned int reserved_199; /* 0x10e24 */ -+ volatile reg_gfx_1555_alpha gfx_1555_alpha; /* 0x10e28 */ -+ volatile unsigned int reserved_200[5]; /* 0x10e2c~0x10e3c 5 regs */ -+ volatile reg_gfx_src_info gfx_src_info; /* 0x10e40 */ -+ volatile reg_gfx_src_reso gfx_src_reso; /* 0x10e44 */ -+ volatile reg_gfx_src_crop gfx_src_crop; /* 0x10e48 */ -+ volatile reg_gfx_ireso gfx_ireso; /* 0x10e4c */ -+ volatile unsigned int gfx_addr_h; /* 0x10e50 */ -+ volatile unsigned int gfx_addr_l; /* 0x10e54 */ -+ volatile unsigned int gfx_naddr_h; /* 0x10e58 */ -+ volatile unsigned int gfx_naddr_l; /* 0x10e5c */ -+ volatile reg_gfx_stride gfx_stride; /* 0x10e60 */ -+ volatile unsigned int reserved_201[3]; /* 0x10e64~0x10e6c 3 regs */ -+ volatile unsigned int gfx_dcmp_addr_h; /* 0x10e70 */ -+ volatile unsigned int gfx_dcmp_addr_l; /* 0x10e74 */ -+ volatile unsigned int gfx_dcmp_naddr_h; /* 0x10e78 */ -+ volatile unsigned int gfx_dcmp_naddr_l; /* 0x10e7c */ -+ volatile unsigned int reserved_202[28]; /* 0x10e80~0x10eec 28 regs */ -+ volatile unsigned int gfx_work_addr; /* 0x10ef0 */ -+ volatile unsigned int reserved_203[3]; /* 0x10ef4~0x10efc 3 regs */ -+ volatile reg_gfx_ckey_max gfx_ckey_max; /* 0x10f00 */ -+ volatile reg_gfx_ckey_min gfx_ckey_min; /* 0x10f04 */ -+ volatile reg_gfx_ckey_mask gfx_ckey_mask; /* 0x10f08 */ -+ volatile unsigned int reserved_204; /* 0x10f0c */ -+ volatile reg_gfx_testpat_cfg gfx_testpat_cfg; /* 0x10f10 */ -+ volatile reg_gfx_testpat_seed gfx_testpat_seed; /* 0x10f14 */ -+ volatile unsigned int reserved_205[2]; /* 0x10f18~0x10f1c 2 regs */ -+ volatile unsigned int gfx_dcmp_framesize0; /* 0x10f20 */ -+ volatile unsigned int gfx_dcmp_framesize1; /* 0x10f24 */ -+ volatile unsigned int reserved_206[2]; /* 0x10f28~0x10f2c 2 regs */ -+ volatile unsigned int gfx_cur_flow; /* 0x10f30 */ -+ volatile unsigned int gfx_cur_sreq_time; /* 0x10f34 */ -+ volatile unsigned int gfx_last_flow; /* 0x10f38 */ -+ volatile unsigned int gfx_last_sreq_time; /* 0x10f3c */ -+ volatile unsigned int gfx_busy_time; /* 0x10f40 */ -+ volatile unsigned int gfx_ar_neednordy_time; /* 0x10f44 */ -+ volatile unsigned int gfx_gb_neednordy_time; /* 0x10f48 */ -+ volatile unsigned int reserved_207; /* 0x10f4c */ -+ volatile reg_gfx_ld_ctrl gfx_ld_ctrl; /* 0x10f50 */ -+ volatile unsigned int gfx_tde_safe_dis; /* 0x10f54 */ -+ volatile reg_gfx_ld_smute_ctrl gfx_ld_smute_ctrl; /* 0x10f58 */ -+ volatile reg_gfx_ld_err_sta gfx_ld_err_sta; /* 0x10f5c */ -+ volatile unsigned int gfx_ld_debug0; /* 0x10f60 */ -+ volatile unsigned int gfx_ld_debug1; /* 0x10f64 */ -+ volatile unsigned int gfx_ld_debug2; /* 0x10f68 */ -+ volatile unsigned int gfx_ld_debug3; /* 0x10f6c */ -+ volatile unsigned int gfx_ld_debug4; /* 0x10f70 */ -+ volatile unsigned int gfx_ld_debug5; /* 0x10f74 */ -+ volatile unsigned int reserved_208[2]; /* 0x10f78~0x10f7c 2 regs */ -+ volatile reg_vdp_v3r2_line_osd_dcmp_glb_info vdp_v3r2_line_osd_dcmp_glb_info; /* 0x10f80 */ -+ volatile reg_vdp_v3r2_line_osd_dcmp_frame_size vdp_v3r2_line_osd_dcmp_frame_size; /* 0x10f84 */ -+ volatile reg_vdp_v3r2_line_osd_dcmp_error_sta vdp_v3r2_line_osd_dcmp_error_sta; /* 0x10f88 */ -+ volatile unsigned int reserved_209[541]; /* 0x10f8c~0x117fc 541 regs */ -+ volatile reg_wbc_ctrl wbc_ctrl; /* 0x11800 */ -+ volatile reg_wbc_mac_ctrl wbc_mac_ctrl; /* 0x11804 */ -+ volatile unsigned int reserved_210[3]; /* 0x11808~0x11810 3 regs */ -+ volatile reg_wbc_smmu_bypass wbc_smmu_bypass; /* 0x11814 */ -+ volatile unsigned int reserved_211[2]; /* 0x11818~0x1181c 2 regs */ -+ volatile reg_wbc_lowdlyctrl wbc_lowdlyctrl; /* 0x11820 */ -+ volatile unsigned int wbc_tunladdr_h; /* 0x11824 */ -+ volatile unsigned int wbc_tunladdr_l; /* 0x11828 */ -+ volatile reg_wbc_lowdlysta wbc_lowdlysta; /* 0x1182c */ -+ volatile unsigned int reserved_212[8]; /* 0x11830~0x1184c 8 regs */ -+ volatile unsigned int wbc_yaddr_h; /* 0x11850 */ -+ volatile unsigned int wbc_yaddr_l; /* 0x11854 */ -+ volatile unsigned int wbc_caddr_h; /* 0x11858 */ -+ volatile unsigned int wbc_caddr_l; /* 0x1185c */ -+ volatile reg_wbc_ystride wbc_ystride; /* 0x11860 */ -+ volatile reg_wbc_cstride wbc_cstride; /* 0x11864 */ -+ volatile unsigned int reserved_213[2]; /* 0x11868~0x1186c 2 regs */ -+ volatile unsigned int wbc_ynaddr_h; /* 0x11870 */ -+ volatile unsigned int wbc_ynaddr_l; /* 0x11874 */ -+ volatile unsigned int wbc_cnaddr_h; /* 0x11878 */ -+ volatile unsigned int wbc_cnaddr_l; /* 0x1187c */ -+ volatile reg_wbc_ynstride wbc_ynstride; /* 0x11880 */ -+ volatile reg_wbc_cnstride wbc_cnstride; /* 0x11884 */ -+ volatile unsigned int reserved_214[10]; /* 0x11888~0x118ac 10 regs */ -+ volatile reg_wbc_sta wbc_sta; /* 0x118b0 */ -+ volatile reg_wbc_line_num wbc_line_num; /* 0x118b4 */ -+ volatile reg_wbc_cap_reso wbc_cap_reso; /* 0x118b8 */ -+ volatile unsigned int wbc_cap_info; /* 0x118bc */ -+ volatile unsigned int reserved_215[16]; /* 0x118c0~0x118fc 16 regs */ -+ volatile reg_vdp_v3r2_lineseg_cmp_glb_info vdp_v3r2_lineseg_cmp_glb_info; /* 0x11900 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_frame_size vdp_v3r2_lineseg_cmp_frame_size; /* 0x11904 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg0 vdp_v3r2_lineseg_cmp_rc_cfg0; /* 0x11908 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg1 vdp_v3r2_lineseg_cmp_rc_cfg1; /* 0x1190c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2; /* 0x11910 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3; /* 0x11914 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4; /* 0x11918 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5; /* 0x1191c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6; /* 0x11920 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7; /* 0x11924 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8; /* 0x11928 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9; /* 0x1192c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10; /* 0x11930 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11; /* 0x11934 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg12 vdp_v3r2_lineseg_cmp_rc_cfg12; /* 0x11938 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg13 vdp_v3r2_lineseg_cmp_rc_cfg13; /* 0x1193c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14; /* 0x11940 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15; /* 0x11944 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0; /* 0x11948 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1; /* 0x1194c */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg16 vdp_v3r2_lineseg_cmp_rc_cfg16; /* 0x11950 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg; /* 0x11954 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_glb_st vdp_v3r2_lineseg_cmp_glb_st; /* 0x11958 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg; /* 0x1195c */ -+ volatile unsigned int reserved_216[8]; /* 0x11960~0x1197c 8 regs */ -+ volatile reg_vdp_v3r2_lineseg_cmp_glb_info_c vdp_v3r2_lineseg_cmp_glb_info_c; /* 0x11980 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_frame_size_c vdp_v3r2_lineseg_cmp_frame_size_c; /* 0x11984 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg0_c vdp_v3r2_lineseg_cmp_rc_cfg0_c; /* 0x11988 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg1_c vdp_v3r2_lineseg_cmp_rc_cfg1_c; /* 0x1198c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg2_c; /* 0x11990 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg3_c; /* 0x11994 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg4_c; /* 0x11998 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg5_c; /* 0x1199c */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg6_c; /* 0x119a0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg7_c; /* 0x119a4 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg8_c; /* 0x119a8 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg9_c; /* 0x119ac */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg10_c; /* 0x119b0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg11_c; /* 0x119b4 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg12_c vdp_v3r2_lineseg_cmp_rc_cfg12_c; /* 0x119b8 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg13_c vdp_v3r2_lineseg_cmp_rc_cfg13_c; /* 0x119bc */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg14_c; /* 0x119c0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_rc_cfg15_c; /* 0x119c4 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr0_c; /* 0x119c8 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_adpqp_thr1_c; /* 0x119cc */ -+ volatile reg_vdp_v3r2_lineseg_cmp_rc_cfg16_c vdp_v3r2_lineseg_cmp_rc_cfg16_c; /* 0x119d0 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_glb_cfg_c; /* 0x119d4 */ -+ volatile reg_vdp_v3r2_lineseg_cmp_glb_st_c vdp_v3r2_lineseg_cmp_glb_st_c; /* 0x119d8 */ -+ volatile unsigned int vdp_v3r2_lineseg_cmp_dbg_reg_c; /* 0x119dc */ -+ volatile unsigned int reserved_217[264]; /* 0x119e0~0x11dfc 264 regs */ -+ volatile reg_wbc_cmp_ctrl wbc_cmp_ctrl; /* 0x11e00 */ -+ volatile reg_wbc_cmp_upd wbc_cmp_upd; /* 0x11e04 */ -+ volatile reg_wbc_cmp_height wbc_cmp_height; /* 0x11e08 */ -+ volatile reg_wbc_cmp_oreso wbc_cmp_oreso; /* 0x11e0c */ -+ volatile unsigned int wbc_cmp_yaddr; /* 0x11e10 */ -+ volatile unsigned int wbc_cmp_yaddr1; /* 0x11e14 */ -+ volatile unsigned int wbc_cmp_caddr; /* 0x11e18 */ -+ volatile unsigned int wbc_cmp_caddr1; /* 0x11e1c */ -+ volatile unsigned int wbc_cmp_addr0_t0; /* 0x11e20 */ -+ volatile unsigned int wbc_cmp_addr1_t0; /* 0x11e24 */ -+ volatile unsigned int wbc_cmp_addr0_t1; /* 0x11e28 */ -+ volatile unsigned int wbc_cmp_addr1_t1; /* 0x11e2c */ -+ volatile unsigned int wbc_cmp_l_fsize; /* 0x11e30 */ -+ volatile unsigned int wbc_cmp_c_fsize; /* 0x11e34 */ -+ volatile unsigned int wbc_cmp_t0_fsize; /* 0x11e38 */ -+ volatile unsigned int wbc_cmp_t1_fsize; /* 0x11e3c */ -+ volatile unsigned int wbc_sety_fsize; /* 0x11e40 */ -+ volatile unsigned int wbc_setc_fsize; /* 0x11e44 */ -+ volatile unsigned int wbc_sett0_fsize; /* 0x11e48 */ -+ volatile unsigned int wbc_sett1_fsize; /* 0x11e4c */ -+ volatile reg_wbc_od_state wbc_od_state; /* 0x11e50 */ -+ volatile unsigned int reserved_218[43]; /* 0x11e54~0x11efc 43 regs */ -+ volatile reg_od_pic_osd_glb_info od_pic_osd_glb_info; /* 0x11f00 */ -+ volatile reg_od_pic_osd_frame_size od_pic_osd_frame_size; /* 0x11f04 */ -+ volatile reg_od_pic_osd_rc_cfg0 od_pic_osd_rc_cfg0; /* 0x11f08 */ -+ volatile reg_od_pic_osd_rc_cfg1 od_pic_osd_rc_cfg1; /* 0x11f0c */ -+ volatile reg_od_pic_osd_rc_cfg2 od_pic_osd_rc_cfg2; /* 0x11f10 */ -+ volatile reg_od_pic_osd_rc_cfg3 od_pic_osd_rc_cfg3; /* 0x11f14 */ -+ volatile reg_od_pic_osd_rc_cfg4 od_pic_osd_rc_cfg4; /* 0x11f18 */ -+ volatile reg_od_pic_osd_rc_cfg5 od_pic_osd_rc_cfg5; /* 0x11f1c */ -+ volatile reg_od_pic_osd_rc_cfg6 od_pic_osd_rc_cfg6; /* 0x11f20 */ -+ volatile reg_od_pic_osd_rc_cfg7 od_pic_osd_rc_cfg7; /* 0x11f24 */ -+ volatile reg_od_pic_osd_rc_cfg8 od_pic_osd_rc_cfg8; /* 0x11f28 */ -+ volatile reg_od_pic_osd_rc_cfg9 od_pic_osd_rc_cfg9; /* 0x11f2c */ -+ volatile reg_od_pic_osd_rc_cfg10 od_pic_osd_rc_cfg10; /* 0x11f30 */ -+ volatile reg_od_pic_osd_rc_cfg11 od_pic_osd_rc_cfg11; /* 0x11f34 */ -+ volatile reg_od_pic_osd_rc_cfg12 od_pic_osd_rc_cfg12; /* 0x11f38 */ -+ volatile reg_od_pic_osd_rc_cfg13 od_pic_osd_rc_cfg13; /* 0x11f3c */ -+ volatile reg_od_pic_osd_rc_cfg14 od_pic_osd_rc_cfg14; /* 0x11f40 */ -+ volatile reg_od_pic_osd_rc_cfg15 od_pic_osd_rc_cfg15; /* 0x11f44 */ -+ volatile reg_od_pic_osd_rc_cfg16 od_pic_osd_rc_cfg16; /* 0x11f48 */ -+ volatile reg_od_pic_osd_rc_cfg17 od_pic_osd_rc_cfg17; /* 0x11f4c */ -+ volatile reg_od_pic_osd_rc_cfg18 od_pic_osd_rc_cfg18; /* 0x11f50 */ -+ volatile reg_od_pic_osd_rc_cfg19 od_pic_osd_rc_cfg19; /* 0x11f54 */ -+ volatile unsigned int reserved_219[2]; /* 0x11f58~0x11f5c 2 regs */ -+ volatile reg_od_pic_osd_stat_thr od_pic_osd_stat_thr; /* 0x11f60 */ -+ volatile reg_od_pic_osd_pcmp od_pic_osd_pcmp; /* 0x11f64 */ -+ volatile unsigned int reserved_220[6]; /* 0x11f68~0x11f7c 6 regs */ -+ volatile reg_od_pic_osd_bs_size od_pic_osd_bs_size; /* 0x11f80 */ -+ volatile reg_od_pic_osd_worst_row od_pic_osd_worst_row; /* 0x11f84 */ -+ volatile reg_od_pic_osd_best_row od_pic_osd_best_row; /* 0x11f88 */ -+ volatile reg_od_pic_osd_stat_info od_pic_osd_stat_info; /* 0x11f8c */ -+ volatile unsigned int od_pic_osd_debug0; /* 0x11f90 */ -+ volatile unsigned int od_pic_osd_debug1; /* 0x11f94 */ -+ volatile unsigned int reserved_221[26]; /* 0x11f98~0x11ffc 26 regs */ -+ volatile reg_v0_mrg_ctrl v0_mrg_ctrl; /* 0x12000 */ -+ volatile reg_v0_mrg_disp_pos v0_mrg_disp_pos; /* 0x12004 */ -+ volatile reg_v0_mrg_disp_reso v0_mrg_disp_reso; /* 0x12008 */ -+ volatile reg_v0_mrg_src_reso v0_mrg_src_reso; /* 0x1200c */ -+ volatile reg_v0_mrg_src_offset v0_mrg_src_offset; /* 0x12010 */ -+ volatile unsigned int v0_mrg_y_addr; /* 0x12014 */ -+ volatile unsigned int v0_mrg_c_addr; /* 0x12018 */ -+ volatile reg_v0_mrg_stride v0_mrg_stride; /* 0x1201c */ -+ volatile unsigned int v0_mrg_yh_addr; /* 0x12020 */ -+ volatile unsigned int v0_mrg_ch_addr; /* 0x12024 */ -+ volatile reg_v0_mrg_hstride v0_mrg_hstride; /* 0x12028 */ -+ volatile unsigned int reserved_222[5]; /* 0x1202c~0x1203c 5 regs */ -+ volatile reg_v0_mrg_read_ctrl v0_mrg_read_ctrl; /* 0x12040 */ -+ volatile reg_v0_mrg_read_en v0_mrg_read_en; /* 0x12044 */ -+ volatile unsigned int reserved_223[750]; /* 0x12048~0x12bfc 750 regs */ -+ volatile reg_v1_mrg_ctrl v1_mrg_ctrl; /* 0x12c00 */ -+ volatile reg_v1_mrg_disp_pos v1_mrg_disp_pos; /* 0x12c04 */ -+ volatile reg_v1_mrg_disp_reso v1_mrg_disp_reso; /* 0x12c08 */ -+ volatile reg_v1_mrg_src_reso v1_mrg_src_reso; /* 0x12c0c */ -+ volatile reg_v1_mrg_src_offset v1_mrg_src_offset; /* 0x12c10 */ -+ volatile unsigned int v1_mrg_y_addr; /* 0x12c14 */ -+ volatile unsigned int v1_mrg_c_addr; /* 0x12c18 */ -+ volatile reg_v1_mrg_stride v1_mrg_stride; /* 0x12c1c */ -+ volatile unsigned int v1_mrg_yh_addr; /* 0x12c20 */ -+ volatile unsigned int v1_mrg_ch_addr; /* 0x12c24 */ -+ volatile reg_v1_mrg_hstride v1_mrg_hstride; /* 0x12c28 */ -+ volatile unsigned int reserved_224[5]; /* 0x12c2c~0x12c3c 5 regs */ -+ volatile reg_v1_mrg_read_ctrl v1_mrg_read_ctrl; /* 0x12c40 */ -+ volatile reg_v1_mrg_read_en v1_mrg_read_en; /* 0x12c44 */ -+ volatile unsigned int reserved_225[1262]; /* 0x12c48~0x13ffc 1262 regs */ -+ volatile reg_g1_osb_ctrl1_box_0 g1_osb_ctrl1_box_0; /* 0x14000 */ -+ volatile reg_g1_osb_ctrl2_box_0 g1_osb_ctrl2_box_0; /* 0x14004 */ -+ volatile reg_g1_osb_ctrl3_box_0 g1_osb_ctrl3_box_0; /* 0x14008 */ -+ volatile unsigned int reserved_226[509]; /* 0x1400c~0x147fc 509 regs */ -+ volatile reg_g3_osb_ctrl1_box_0 g3_osb_ctrl1_box_0; /* 0x14800 */ -+ volatile reg_g3_osb_ctrl2_box_0 g3_osb_ctrl2_box_0; /* 0x14804 */ -+ volatile reg_g3_osb_ctrl3_box_0 g3_osb_ctrl3_box_0; /* 0x14808 */ -+ volatile unsigned int reserved_227[509]; /* 0x1480c~0x14ffc 509 regs */ -+ volatile reg_g4_osb_ctrl1_box_0 g4_osb_ctrl1_box_0; /* 0x15000 */ -+ volatile reg_g4_osb_ctrl2_box_0 g4_osb_ctrl2_box_0; /* 0x15004 */ -+ volatile reg_g4_osb_ctrl3_box_0 g4_osb_ctrl3_box_0; /* 0x15008 */ -+ volatile unsigned int reserved_228[1021]; /* 0x1500c~0x15ffc 1021 regs */ -+ volatile reg_v1_csc_idc v1_csc_idc; /* 0x16000 */ -+ volatile reg_v1_csc_odc v1_csc_odc; /* 0x16004 */ -+ volatile reg_v1_csc_iodc v1_csc_iodc; /* 0x16008 */ -+ volatile reg_v1_csc_p0 v1_csc_p0; /* 0x1600c */ -+ volatile reg_v1_csc_p1 v1_csc_p1; /* 0x16010 */ -+ volatile reg_v1_csc_p2 v1_csc_p2; /* 0x16014 */ -+ volatile reg_v1_csc_p3 v1_csc_p3; /* 0x16018 */ -+ volatile reg_v1_csc_p4 v1_csc_p4; /* 0x1601c */ -+ volatile reg_v1_csc1_idc v1_csc1_idc; /* 0x16020 */ -+ volatile reg_v1_csc1_odc v1_csc1_odc; /* 0x16024 */ -+ volatile reg_v1_csc1_iodc v1_csc1_iodc; /* 0x16028 */ -+ volatile reg_v1_csc1_p0 v1_csc1_p0; /* 0x1602c */ -+ volatile reg_v1_csc1_p1 v1_csc1_p1; /* 0x16030 */ -+ volatile reg_v1_csc1_p2 v1_csc1_p2; /* 0x16034 */ -+ volatile reg_v1_csc1_p3 v1_csc1_p3; /* 0x16038 */ -+ volatile reg_v1_csc1_p4 v1_csc1_p4; /* 0x1603c */ -+ volatile unsigned int reserved_229[48]; /* 0x16040~0x160fc 48 regs */ -+ volatile reg_v2_csc_idc v2_csc_idc; /* 0x16100 */ -+ volatile reg_v2_csc_odc v2_csc_odc; /* 0x16104 */ -+ volatile reg_v2_csc_iodc v2_csc_iodc; /* 0x16108 */ -+ volatile reg_v2_csc_p0 v2_csc_p0; /* 0x1610c */ -+ volatile reg_v2_csc_p1 v2_csc_p1; /* 0x16110 */ -+ volatile reg_v2_csc_p2 v2_csc_p2; /* 0x16114 */ -+ volatile reg_v2_csc_p3 v2_csc_p3; /* 0x16118 */ -+ volatile reg_v2_csc_p4 v2_csc_p4; /* 0x1611c */ -+ volatile reg_v2_csc1_idc v2_csc1_idc; /* 0x16120 */ -+ volatile reg_v2_csc1_odc v2_csc1_odc; /* 0x16124 */ -+ volatile reg_v2_csc1_iodc v2_csc1_iodc; /* 0x16128 */ -+ volatile reg_v2_csc1_p0 v2_csc1_p0; /* 0x1612c */ -+ volatile reg_v2_csc1_p1 v2_csc1_p1; /* 0x16130 */ -+ volatile reg_v2_csc1_p2 v2_csc1_p2; /* 0x16134 */ -+ volatile reg_v2_csc1_p3 v2_csc1_p3; /* 0x16138 */ -+ volatile reg_v2_csc1_p4 v2_csc1_p4; /* 0x1613c */ -+ volatile unsigned int reserved_230[48]; /* 0x16140~0x161fc 48 regs */ -+ volatile reg_g1_csc_idc g1_csc_idc; /* 0x16200 */ -+ volatile reg_g1_csc_odc g1_csc_odc; /* 0x16204 */ -+ volatile reg_g1_csc_iodc g1_csc_iodc; /* 0x16208 */ -+ volatile reg_g1_csc_p0 g1_csc_p0; /* 0x1620c */ -+ volatile reg_g1_csc_p1 g1_csc_p1; /* 0x16210 */ -+ volatile reg_g1_csc_p2 g1_csc_p2; /* 0x16214 */ -+ volatile reg_g1_csc_p3 g1_csc_p3; /* 0x16218 */ -+ volatile reg_g1_csc_p4 g1_csc_p4; /* 0x1621c */ -+ volatile reg_g1_csc1_idc g1_csc1_idc; /* 0x16220 */ -+ volatile reg_g1_csc1_odc g1_csc1_odc; /* 0x16224 */ -+ volatile reg_g1_csc1_iodc g1_csc1_iodc; /* 0x16228 */ -+ volatile reg_g1_csc1_p0 g1_csc1_p0; /* 0x1622c */ -+ volatile reg_g1_csc1_p1 g1_csc1_p1; /* 0x16230 */ -+ volatile reg_g1_csc1_p2 g1_csc1_p2; /* 0x16234 */ -+ volatile reg_g1_csc1_p3 g1_csc1_p3; /* 0x16238 */ -+ volatile reg_g1_csc1_p4 g1_csc1_p4; /* 0x1623c */ -+ volatile unsigned int reserved_231[48]; /* 0x16240~0x162fc 48 regs */ -+ volatile reg_g3_csc_idc g3_csc_idc; /* 0x16300 */ -+ volatile reg_g3_csc_odc g3_csc_odc; /* 0x16304 */ -+ volatile reg_g3_csc_iodc g3_csc_iodc; /* 0x16308 */ -+ volatile reg_g3_csc_p0 g3_csc_p0; /* 0x1630c */ -+ volatile reg_g3_csc_p1 g3_csc_p1; /* 0x16310 */ -+ volatile reg_g3_csc_p2 g3_csc_p2; /* 0x16314 */ -+ volatile reg_g3_csc_p3 g3_csc_p3; /* 0x16318 */ -+ volatile reg_g3_csc_p4 g3_csc_p4; /* 0x1631c */ -+ volatile reg_g3_csc1_idc g3_csc1_idc; /* 0x16320 */ -+ volatile reg_g3_csc1_odc g3_csc1_odc; /* 0x16324 */ -+ volatile reg_g3_csc1_iodc g3_csc1_iodc; /* 0x16328 */ -+ volatile reg_g3_csc1_p0 g3_csc1_p0; /* 0x1632c */ -+ volatile reg_g3_csc1_p1 g3_csc1_p1; /* 0x16330 */ -+ volatile reg_g3_csc1_p2 g3_csc1_p2; /* 0x16334 */ -+ volatile reg_g3_csc1_p3 g3_csc1_p3; /* 0x16338 */ -+ volatile reg_g3_csc1_p4 g3_csc1_p4; /* 0x1633c */ -+ volatile unsigned int reserved_232[176]; /* 0x16340~0x165fc 176 regs */ -+ volatile reg_v0_zme_hinfo v0_zme_hinfo; /* 0x16600 */ -+ volatile reg_v0_zme_hsp v0_zme_hsp; /* 0x16604 */ -+ volatile reg_v0_zme_hloffset v0_zme_hloffset; /* 0x16608 */ -+ volatile reg_v0_zme_hcoffset v0_zme_hcoffset; /* 0x1660c */ -+ volatile reg_v0_zme_hzone0delta v0_zme_hzone0delta; /* 0x16610 */ -+ volatile reg_v0_zme_hzone2delta v0_zme_hzone2delta; /* 0x16614 */ -+ volatile reg_v0_zme_hzoneend v0_zme_hzoneend; /* 0x16618 */ -+ volatile reg_v0_zme_hl_shootctrl v0_zme_hl_shootctrl; /* 0x1661c */ -+ volatile reg_v0_zme_hc_shootctrl v0_zme_hc_shootctrl; /* 0x16620 */ -+ volatile reg_v0_zme_hcoef_ren v0_zme_hcoef_ren; /* 0x16624 */ -+ volatile reg_v0_zme_hcoef_rdata v0_zme_hcoef_rdata; /* 0x16628 */ -+ volatile unsigned int reserved_233[53]; /* 0x1662c~0x166fc 53 regs */ -+ volatile reg_v0_zme_vinfo v0_zme_vinfo; /* 0x16700 */ -+ volatile reg_v0_zme_vsp v0_zme_vsp; /* 0x16704 */ -+ volatile reg_v0_zme_voffset v0_zme_voffset; /* 0x16708 */ -+ volatile reg_v0_zme_vboffset v0_zme_vboffset; /* 0x1670c */ -+ volatile unsigned int reserved_234[3]; /* 0x16710~0x16718 3 regs */ -+ volatile reg_v0_zme_vl_shootctrl v0_zme_vl_shootctrl; /* 0x1671c */ -+ volatile reg_v0_zme_vc_shootctrl v0_zme_vc_shootctrl; /* 0x16720 */ -+ volatile reg_v0_zme_vcoef_ren v0_zme_vcoef_ren; /* 0x16724 */ -+ volatile reg_v0_zme_vcoef_rdata v0_zme_vcoef_rdata; /* 0x16728 */ -+ volatile unsigned int reserved_235[533]; /* 0x1672c~0x16f7c 533 regs */ -+ volatile reg_gfx_osd_glb_info gfx_osd_glb_info; /* 0x16f80 */ -+ volatile reg_gfx_osd_frame_size gfx_osd_frame_size; /* 0x16f84 */ -+ volatile unsigned int reserved_236[2]; /* 0x16f88~0x16f8c 2 regs */ -+ volatile reg_gfx_osd_dbg_reg gfx_osd_dbg_reg; /* 0x16f90 */ -+ volatile reg_gfx_osd_dbg_reg1 gfx_osd_dbg_reg1; /* 0x16f94 */ -+} reg_vdp_regs; -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#endif /* HAL_VO_REG_H */ -diff --git a/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_video.h b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_video.h -new file mode 100755 -index 0000000..98e1672 ---- /dev/null -+++ b/drivers/gpu/drm/hisilicon/smart_vision/vo/hi3403v100/include/hal_vo_video.h -@@ -0,0 +1,50 @@ -+/* -+ * Copyright (c) 2025 HiSilicon (Shanghai) Technologies Co., Ltd. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ * . -+ */ -+ -+#ifndef HAL_VO_VIDEO_H -+#define HAL_VO_VIDEO_H -+ -+#include "hal_vo_video_comm.h" -+#include "ot_inner_video.h" -+ -+#ifdef __cplusplus -+#if __cplusplus -+extern "C" { -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#if vo_desc("UBOOT_VO") -+td_void hal_cbm_set_cbm_attr(hal_disp_layer layer, ot_vo_dev dev); -+td_void hal_cbm_set_cbm_bkg(hal_cbmmix mixer, const hal_disp_bkcolor *bkg); -+td_void hal_cbm_set_cbm_mixer_prio(ot_vo_layer layer, td_u8 prio, td_u8 mixer_id); -+#endif /* #if vo_desc("UBOOT_VO") */ -+ -+#if vo_desc("KERNEL_VO") -+td_void hal_write_mrg_reg(td_u32 *address, td_u32 value); -+td_u32 hal_read_mrg_reg(const td_u32 *address); -+td_u32 hal_layer_get_layer_max_area_num(hal_disp_layer layer); -+td_void hal_para_set_para_addr_vhd_chn08(td_phys_addr_t para_addr_vhd_chn08); -+#endif /* #if vo_desc("KERNEL_VO") */ -+ -+#ifdef __cplusplus -+#if __cplusplus -+} -+#endif -+#endif /* end of #ifdef __cplusplus */ -+ -+#endif /* end of HAL_VO_VIDEO_H */ diff --git a/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/patch_hispark_aifly.sh b/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/patch_hispark_aifly.sh index d7884427..af1da4b7 100755 --- a/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/patch_hispark_aifly.sh +++ b/os/OpenHarmony/kernel/linux/patches/linux-6.6/hispark_aifly_patch/patch_hispark_aifly.sh @@ -22,5 +22,6 @@ patch -p1 < ${patch_dir}/0001-kernel-hispark_aifly.patch patch -p1 < ${patch_dir}/0002-kernel-compile-support.patch patch -p1 < ${patch_dir}/0003-support-eulerpi-uvc-and-ethernet.patch patch -p1 < ${patch_dir}/0004-kernel-drm-support.patch +patch -p1 < ${patch_dir}/0004-kernel-drm-driver-support.patch patch -p1 < ${patch_dir}/0005-kernel-dhcp-support.patch echo "patching aifly finished..." diff --git a/vendor/rkh/patches/foundation/multimedia/media_lite/media_lite_002.patch b/vendor/rkh/patches/foundation/multimedia/media_lite/media_lite_002.patch index 3bda0152..634bf6be 100644 --- a/vendor/rkh/patches/foundation/multimedia/media_lite/media_lite_002.patch +++ b/vendor/rkh/patches/foundation/multimedia/media_lite/media_lite_002.patch @@ -12,11 +12,89 @@ index c368a5a..d19ad4d 100755 ], "inner_kits": [], "test": [] +diff --git a/services/player_lite/BUILD.gn b/services/player_lite/BUILD.gn +index 87ea173..ef24cda 100755 +--- a/services/player_lite/BUILD.gn ++++ b/services/player_lite/BUILD.gn +@@ -11,6 +11,9 @@ + + import("//build/lite/config/component/lite_component.gni") + import("//foundation/multimedia/media_utils_lite/config.gni") ++declare_args() { ++ enable_player_hdmi_hot_swap = true ++} + + shared_library("player_impl") { + sources = [ +@@ -68,8 +71,13 @@ shared_library("player_impl") { + "-Wno-format", + ] + cflags_cc = cflags ++ defines = [] + if (enable_distributed_dfx == true) { +- defines = ["ENABLE_DFX"] ++ defines += ["ENABLE_DFX"] ++ } ++ ++ if (enable_player_hdmi_hot_swap) { ++ defines += ["ENABLE_PLAYER_HDMI_HOT_SWAP"] + } + } + diff --git a/services/player_lite/impl/player_control/player/liteplayer.cpp b/services/player_lite/impl/player_control/player/liteplayer.cpp -index bc12785..ef4273a 100644 +index bc12785..1304b4f 100644 --- a/services/player_lite/impl/player_control/player/liteplayer.cpp +++ b/services/player_lite/impl/player_control/player/liteplayer.cpp -@@ -2089,5 +2089,13 @@ int32_t PlayerControl::DoSetAudioStreamType(int32_t type) +@@ -152,7 +152,8 @@ PlayerControl::PlayerControl() : stateMachine_(nullptr), observer_(nullptr), isI + schThreadExit_(false), loop_(false), hasRenderAudioEos_(false), hasRenderVideoEos_(false), renderSleepTime_(0), + leftVolume_(-1.0f), rightVolume_(-1.0f), schProcess_(0), seekToTimeMs_(-1), firstAudioFrameAfterSeek_(false), + firstVideoFrameAfterSeek_(false), sourceType_(SOURCE_TYPE_BUT), fd_(-1), playerSource_(nullptr), +- sinkManager_(nullptr), audioDecoder_(nullptr), videoDecoder_(nullptr), audioStreamType_(0), continuousAudFull_(0) ++ sinkManager_(nullptr), audioDecoder_(nullptr), videoDecoder_(nullptr), audioStreamType_(0), continuousAudFull_(0), ++ isPaused_(false) + { + eventCallback_.player = nullptr; + eventCallback_.callbackFun = nullptr; +@@ -344,6 +345,7 @@ int32_t PlayerControl::Prepare() + int32_t PlayerControl::Play() + { + CHECK_NULL_RETURN(stateMachine_, HI_ERR_PLAYERCONTROL_NULL_PTR, "stateMachine_ nullptr"); ++ isPaused_ = false; + int32_t ret = stateMachine_->Send(PLAYERCONTROL_MSG_PLAY); + CHECK_FAILED_PRINT(ret, HI_SUCCESS, "play failed"); + return ret; +@@ -372,6 +374,10 @@ int32_t PlayerControl::Pause() + return stateMachine_->Send(PLAYERCONTROL_MSG_PAUSE); + } + ++bool PlayerControl::IsPaused(void) ++{ ++ return isPaused_; ++} + int32_t PlayerControl::Seek(int64_t timeInMs) + { + CHECK_NULL_RETURN(stateMachine_, HI_ERR_PLAYERCONTROL_NULL_PTR, "stateMachine_ nullptr"); +@@ -1027,6 +1033,9 @@ void PlayerControl::RenderAudioFrame(void) + if (IsPlayEos() == true) { + isPlayEnd_ = true; + } ++ } else if (ret == SINK_RENDER_PAUSED) { ++ MEDIA_INFO_LOG("audio sink render paused, pause player"); ++ isPaused_ = true; + } + } + +@@ -1115,6 +1124,9 @@ void *PlayerControl::DataSchProcess(void *priv) + pthread_mutex_unlock(&play->schMutex_); + play->EventQueueProcess(); + play->ReortRenderPosition(); ++ if (play->isPaused_) { ++ play->Pause(); ++ } + if (play->isPlayEnd_) { + play->DealPlayEnd(); + play->isPlayEnd_ = false; +@@ -2089,5 +2101,13 @@ int32_t PlayerControl::DoSetAudioStreamType(int32_t type) } return 0; } @@ -31,10 +109,19 @@ index bc12785..ef4273a 100644 } } diff --git a/services/player_lite/impl/player_control/player/liteplayer.h b/services/player_lite/impl/player_control/player/liteplayer.h -index 6b06218..13cba65 100644 +index 6b06218..1017d57 100644 --- a/services/player_lite/impl/player_control/player/liteplayer.h +++ b/services/player_lite/impl/player_control/player/liteplayer.h -@@ -85,6 +85,7 @@ public: +@@ -66,6 +66,8 @@ public: + + int32_t Pause(void); + ++ bool IsPaused(void); ++ + int32_t Seek(int64_t timeInMs); + + int32_t GetFileInfo(FormatFileInfo &formatInfo); +@@ -85,6 +87,7 @@ public: void OnVideoEndOfStream(void); void StateChangeCallback(PlayerStatus state) override; int32_t SetAudioStreamType(int32_t type); @@ -42,11 +129,29 @@ index 6b06218..13cba65 100644 protected: int32_t DoRegCallback(PlayerCtrlCallbackParam &observer) override; +@@ -223,6 +226,7 @@ private: + int64_t seekToTimeMs_; + bool firstAudioFrameAfterSeek_; + bool firstVideoFrameAfterSeek_; ++ bool isPaused_; + SourceType sourceType_; + int32_t fd_; + std::string filePath_; diff --git a/services/player_lite/impl/player_control/sink/player_audio_sink.cpp b/services/player_lite/impl/player_control/sink/player_audio_sink.cpp -index b6a78f8..f1cf374 100644 +index b6a78f8..e61b066 100644 --- a/services/player_lite/impl/player_control/sink/player_audio_sink.cpp +++ b/services/player_lite/impl/player_control/sink/player_audio_sink.cpp -@@ -104,15 +104,20 @@ int32_t AudioSink::Init(SinkAttr &atrr) +@@ -48,7 +48,8 @@ AudioSink::AudioSink() + pauseAfterPlay_(false), syncHdl_(nullptr), renderMode_(RENDER_MODE_NORMAL), + rendStartTime_(-1), lastRendPts_(AV_INVALID_PTS), lastRendSysTimeMs_(-1), renderDelay_(0), + leftVolume_(0.0f), rightVolume_(0.0f), eosPts_(AV_INVALID_PTS), receivedEos_(false), audioManager_(nullptr), +- audioAdapter_(nullptr), audioRender_(nullptr), reportedFirstFrame(false), audioStreamType_(0) ++ audioAdapter_(nullptr), audioRender_(nullptr), reportedFirstFrame(false), audioStreamType_(0), ++ hdmiConnected_(false), hdmiQueryCnt_(0) + { + ResetRendStartTime(); + frameCacheQue_.clear(); +@@ -104,15 +105,20 @@ int32_t AudioSink::Init(SinkAttr &atrr) } for (int index = 0; index < size; index++) { struct AudioAdapterDescriptor *desc = &descs[index]; @@ -57,7 +162,7 @@ index b6a78f8..f1cf374 100644 - if (memcpy_s(&renderPort_, sizeof(struct AudioPort), - &desc->ports[port], sizeof(struct AudioPort)) != 0) { - MEDIA_ERR_LOG("memcpy_s failed"); -+ MEDIA_ERR_LOG("index = %d, desc->adapterName = %s", index, desc->adapterName); ++ MEDIA_INFO_LOG("index = %d, desc->adapterName = %s", index, desc->adapterName); + // if(strcmp(desc->adapterName, "USB") == 0) { + if(strcmp(desc->adapterName, "Primary") == 0) { + for (int port = 0; (desc != nullptr && port < static_cast(desc->portNum)); port++) { @@ -75,7 +180,7 @@ index b6a78f8..f1cf374 100644 } } } -@@ -122,7 +127,7 @@ int32_t AudioSink::Init(SinkAttr &atrr) +@@ -122,22 +128,45 @@ int32_t AudioSink::Init(SinkAttr &atrr) } struct AudioSampleAttributes param; @@ -84,22 +189,89 @@ index b6a78f8..f1cf374 100644 param.format = AUDIO_FORMAT_TYPE_PCM_16_BIT; param.channelCount = attr_.audAttr.channel; param.interleaved = false; -@@ -131,6 +136,8 @@ int32_t AudioSink::Init(SinkAttr &atrr) + param.type = (audioStreamType_ == 1) ? AUDIO_IN_COMMUNICATION : AUDIO_IN_MEDIA; + MEDIA_INFO_LOG("sampleRate:%u, channelCount:%u", param.sampleRate, param.channelCount); ++#ifdef ENABLE_PLAYER_HDMI_HOT_SWAP struct AudioDeviceDescriptor deviceDesc; deviceDesc.portId = 0; -+ // deviceDesc.pins = PIN_OUT_HDMI; -+ // deviceDesc.pins = PIN_OUT_USB; - deviceDesc.pins = PIN_OUT_SPEAKER; +- deviceDesc.pins = PIN_OUT_SPEAKER; ++ deviceDesc.pins = PIN_OUT_HDMI; deviceDesc.desc = nullptr; ret = audioAdapter_->CreateRender(audioAdapter_, &deviceDesc, ¶m, &audioRender_); -@@ -459,4 +466,4 @@ void AudioSink::SetAudioStreamType(int32_t &type) +- if (ret != 0 || audioRender_ == nullptr) { +- MEDIA_ERR_LOG("AudioDeviceCreateRender failed"); ++ if (ret == HI_SUCCESS && audioRender_ != nullptr) { ++ hdmiConnected_ = true; ++ MEDIA_INFO_LOG("==============HDMI state 1 (connected) playback============="); ++ } else { ++ // deviceDesc.pins = PIN_OUT_USB; // for USB playback ++ deviceDesc.pins = PIN_OUT_SPEAKER; // for speaker playback ++ ret = audioAdapter_->CreateRender(audioAdapter_, &deviceDesc, ¶m, &audioRender_); ++ if (ret != HI_SUCCESS || audioRender_ == nullptr) { ++ MEDIA_ERR_LOG("AudioDeviceCreateRender failed for both HDMI and speaker"); ++ return SINK_OPEN_STREAM_FAILED; ++ } ++ hdmiConnected_ = false; ++ MEDIA_INFO_LOG("==============HDMI state 0 (disconnected) playback============="); ++ } ++#else ++ struct AudioDeviceDescriptor deviceDesc; ++ deviceDesc.portId = 0; ++ // deviceDesc.pins = PIN_OUT_USB; // for USB playback ++ // deviceDesc.pins = PIN_OUT_HDMI; // for HDMI playback ++ deviceDesc.pins = PIN_OUT_SPEAKER; // for speaker playback ++ ret = audioAdapter_->CreateRender(audioAdapter_, &deviceDesc, ¶m, &audioRender_); ++ if (ret != HI_SUCCESS || audioRender_ == nullptr) { ++ MEDIA_ERR_LOG("AudioDeviceCreateRender failed for both HDMI and speaker"); + return SINK_OPEN_STREAM_FAILED; + } ++#endif + MEDIA_DEBUG_LOG("init success"); + return SINK_SUCCESS; + } +@@ -261,6 +290,21 @@ int32_t AudioSink::WriteToAudioDevice(OutputInfo &renderFrame) + MEDIA_ERR_LOG("RenderFrame failed ret: %x", ret); + return SINK_RENDER_ERROR; + } ++#ifdef ENABLE_PLAYER_HDMI_HOT_SWAP ++ hdmiQueryCnt_++; ++ if (hdmiQueryCnt_ >= 50) { ++ hdmiQueryCnt_ = 0; ++ float speed_ = 0.0; ++ ++ if (audioRender_->GetRenderSpeed(audioRender_, &speed_) == HI_SUCCESS) { ++ bool currentHdmiState = (speed_ == 200); // 200 is the speed for HDMI ++ if (currentHdmiState != hdmiConnected_) { ++ ReleaseQueHeadFrame(); ++ return SINK_RENDER_PAUSED; ++ } ++ } ++ } ++#endif + ReleaseQueHeadFrame(); + return HI_SUCCESS; + } +@@ -459,4 +503,4 @@ void AudioSink::SetAudioStreamType(int32_t &type) audioStreamType_ = type; } } -} \ No newline at end of file +} +diff --git a/services/player_lite/impl/player_control/sink/player_audio_sink.h b/services/player_lite/impl/player_control/sink/player_audio_sink.h +index 279f62c..b486345 100644 +--- a/services/player_lite/impl/player_control/sink/player_audio_sink.h ++++ b/services/player_lite/impl/player_control/sink/player_audio_sink.h +@@ -90,6 +90,8 @@ private: + float rightVolume_; + int64_t eosPts_; + bool receivedEos_; ++ bool hdmiConnected_; ++ uint32_t hdmiQueryCnt_; + std::mutex mutex_; + std::vector frameCacheQue_; + std::vector frameReleaseQue_; diff --git a/services/player_lite/impl/player_control/sink/player_sink_manager.cpp b/services/player_lite/impl/player_control/sink/player_sink_manager.cpp index effc3b8..bad03ab 100644 --- a/services/player_lite/impl/player_control/sink/player_sink_manager.cpp @@ -115,7 +287,7 @@ index effc3b8..bad03ab 100644 } diff --git a/services/player_lite/impl/player_control/sink/player_sink_type.h b/services/player_lite/impl/player_control/sink/player_sink_type.h -index 3edf9ef..f4c71ff 100644 +index 3edf9ef..4115ead 100644 --- a/services/player_lite/impl/player_control/sink/player_sink_type.h +++ b/services/player_lite/impl/player_control/sink/player_sink_type.h @@ -29,6 +29,7 @@ namespace Media { @@ -126,6 +298,14 @@ index 3edf9ef..f4c71ff 100644 typedef enum { SINK_STATE_IDLE, +@@ -108,6 +109,7 @@ typedef enum { + SINK_RENDER_DELAY, + SINK_RENDER_ERROR, + SINK_QUE_EMPTY, ++ SINK_RENDER_PAUSED, + SINK_RENDER_EOS, + SINK_INVALID_OP + } SinkRetCode; diff --git a/services/player_lite/impl/player_control/sink/player_video_sink.cpp b/services/player_lite/impl/player_control/sink/player_video_sink.cpp index adbdb33..9ca11c7 100644 --- a/services/player_lite/impl/player_control/sink/player_video_sink.cpp @@ -145,10 +325,20 @@ index adbdb33..9ca11c7 100644 } } diff --git a/services/player_lite/impl/player_impl.cpp b/services/player_lite/impl/player_impl.cpp -index e6d17b4..7614111 100644 +index e6d17b4..f5fc6ca 100644 --- a/services/player_lite/impl/player_impl.cpp +++ b/services/player_lite/impl/player_impl.cpp -@@ -1249,6 +1249,10 @@ int32_t PlayerImpl::SetParameter(const Format ¶ms) +@@ -350,6 +350,9 @@ int32_t PlayerImpl::Play() + MEDIA_INFO_LOG("process in"); + CHECK_FAILED_RETURN(released_, false, -1, "have released or not create"); + CHK_NULL_RETURN(player_); ++ if (player_->IsPaused()) { ++ currentState_ = PLAYER_PAUSED; ++ } + if (currentState_ == PLAYER_STARTED) { + MEDIA_INFO_LOG("no need to repeat operation"); + return 0; +@@ -1249,6 +1252,10 @@ int32_t PlayerImpl::SetParameter(const Format ¶ms) { int32_t value; std::lock_guard valueLock(lock_); @@ -173,9 +363,12 @@ index 91c9431..2afa1cd 100644 default: MEDIA_ERR_LOG("invalid OutputFormatType: %d ", format); return ERR_INVALID_PARAM; +diff --git a/test/BUILD.gn b/test/BUILD.gn +old mode 100644 +new mode 100755 diff --git a/test/demo/BUILD.gn b/test/demo/BUILD.gn -new file mode 100644 -index 0000000..7263a72 +new file mode 100755 +index 0000000..b7e2650 --- /dev/null +++ b/test/demo/BUILD.gn @@ -0,0 +1,87 @@ @@ -268,7 +461,7 @@ index 0000000..7263a72 +} diff --git a/test/demo/aac_player_sample.cpp b/test/demo/aac_player_sample.cpp new file mode 100644 -index 0000000..cd45969 +index 0000000..eeceacd --- /dev/null +++ b/test/demo/aac_player_sample.cpp @@ -0,0 +1,286 @@ @@ -559,8 +752,8 @@ index 0000000..cd45969 + return 0; +} diff --git a/test/demo/plugin_sample/BUILD.gn b/test/demo/plugin_sample/BUILD.gn -new file mode 100644 -index 0000000..38797e8 +new file mode 100755 +index 0000000..a28a29e --- /dev/null +++ b/test/demo/plugin_sample/BUILD.gn @@ -0,0 +1,130 @@ @@ -697,7 +890,7 @@ index 0000000..38797e8 \ No newline at end of file diff --git a/test/demo/plugin_sample/player_sample_common.cpp b/test/demo/plugin_sample/player_sample_common.cpp new file mode 100644 -index 0000000..15dfc14 +index 0000000..06b1f33 --- /dev/null +++ b/test/demo/plugin_sample/player_sample_common.cpp @@ -0,0 +1,272 @@ @@ -976,7 +1169,7 @@ index 0000000..15dfc14 \ No newline at end of file diff --git a/test/demo/plugin_sample/player_sample_common.h b/test/demo/plugin_sample/player_sample_common.h new file mode 100644 -index 0000000..9093c5b +index 0000000..907f673 --- /dev/null +++ b/test/demo/plugin_sample/player_sample_common.h @@ -0,0 +1,60 @@ @@ -1043,7 +1236,7 @@ index 0000000..9093c5b \ No newline at end of file diff --git a/test/demo/plugin_sample/plugin_play.cpp b/test/demo/plugin_sample/plugin_play.cpp new file mode 100644 -index 0000000..4d1d30b +index 0000000..7414104 --- /dev/null +++ b/test/demo/plugin_sample/plugin_play.cpp @@ -0,0 +1,41 @@ @@ -1091,7 +1284,7 @@ index 0000000..4d1d30b \ No newline at end of file diff --git a/test/demo/plugin_sample/plugin_play_two_channe.cpp b/test/demo/plugin_sample/plugin_play_two_channe.cpp new file mode 100644 -index 0000000..704fbe8 +index 0000000..9ce3d7f --- /dev/null +++ b/test/demo/plugin_sample/plugin_play_two_channe.cpp @@ -0,0 +1,49 @@ @@ -1147,7 +1340,7 @@ index 0000000..704fbe8 \ No newline at end of file diff --git a/test/demo/suface_demo.cpp b/test/demo/suface_demo.cpp new file mode 100644 -index 0000000..643f485 +index 0000000..f10a9b6 --- /dev/null +++ b/test/demo/suface_demo.cpp @@ -0,0 +1,101 @@ @@ -1254,7 +1447,7 @@ index 0000000..643f485 +} diff --git a/test/demo/video_player_sample.cpp b/test/demo/video_player_sample.cpp new file mode 100644 -index 0000000..5491246 +index 0000000..3366a09 --- /dev/null +++ b/test/demo/video_player_sample.cpp @@ -0,0 +1,527 @@ diff --git a/vendor/rkh/patches/third_party/alsa-lib/alsa-lib_001.patch b/vendor/rkh/patches/third_party/alsa-lib/alsa-lib_001.patch index a1213fa2..991d7360 100644 --- a/vendor/rkh/patches/third_party/alsa-lib/alsa-lib_001.patch +++ b/vendor/rkh/patches/third_party/alsa-lib/alsa-lib_001.patch @@ -1,5 +1,5 @@ diff --git a/BUILD.gn b/BUILD.gn -index 23a8e72..6b835fc 100644 +index 23a8e720..6b835fcc 100644 --- a/BUILD.gn +++ b/BUILD.gn @@ -11,8 +11,13 @@ @@ -210,7 +210,7 @@ index 23a8e72..6b835fc 100644 + } } diff --git a/include/local.h b/include/local.h -index 512e445..247af1c 100644 +index 512e4455..247af1c4 100644 --- a/include/local.h +++ b/include/local.h @@ -295,8 +295,12 @@ extern snd_lib_error_handler_t snd_err_msg; @@ -230,7 +230,7 @@ index 512e445..247af1c 100644 asm (".pushsection " section_string "\n\t.popsection"); diff --git a/libasound_src.gni b/libasound_src.gni new file mode 100644 -index 0000000..0f395e4 +index 00000000..0f395e41 --- /dev/null +++ b/libasound_src.gni @@ -0,0 +1,150 @@ @@ -385,7 +385,7 @@ index 0000000..0f395e4 + "-fgnu-inline-asm" + ] diff --git a/src/conf/BUILD.gn b/src/conf/BUILD.gn -index 1eca8a9..bc434df 100644 +index 1eca8a92..50b10a23 100644 --- a/src/conf/BUILD.gn +++ b/src/conf/BUILD.gn @@ -1,721 +1,1283 @@ @@ -1117,492 +1117,492 @@ index 1eca8a9..bc434df 100644 + + copy("alsa-lib-prebuilt-smixer.conf") { + sources = ["smixer.conf"] -+ outputs = [ "$root_out_dir/etc/smixer.conf" ] ++ outputs = [ "$root_out_dir/system/etc/smixer.conf" ] + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-smixer.conf" ] + + copy("alsa-lib-prebuilt-alsa.conf") { + sources = ["alsa.conf" ] -+ outputs = [ "$root_out_dir/etc/alsa.conf" ] ++ outputs = [ "$root_out_dir/system/etc/audio/alsa/share/alsa.conf" ] + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-alsa.conf" ] + + copy("alsa-lib-prebuilt-pcm/modem.conf") { + sources = ["pcm/modem.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/modem.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/modem.conf" ] + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/modem.conf" ] + + copy("alsa-lib-prebuilt-pcm/dmix.conf") { + sources = [ "pcm/dmix.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/dmix.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/dmix.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/dmix.conf" ] + + copy("alsa-lib-prebuilt-pcm/surround21.conf") { + sources = [ "pcm/surround21.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/surround21.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/surround21.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/surround21.conf" ] + + copy("alsa-lib-prebuilt-pcm/dsnoop.conf") { + sources = [ "pcm/dsnoop.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/dsnoop.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/dsnoop.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/dsnoop.conf" ] + + copy("alsa-lib-prebuilt-pcm/side.conf") { + sources = [ "pcm/side.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/side.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/side.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/side.conf" ] + + copy("alsa-lib-prebuilt-pcm/dpl.conf") { + sources = [ "pcm/dpl.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/dpl.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/dpl.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/dpl.conf" ] + + copy("alsa-lib-prebuilt-pcm/surround71.conf") { + sources = [ "pcm/surround71.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/surround71.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/surround71.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/surround71.conf" ] + + copy("alsa-lib-prebuilt-pcm/surround40.conf") { + sources = [ "pcm/surround40.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/surround40.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/surround40.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/surround40.conf" ] + + copy("alsa-lib-prebuilt-pcm/rear.conf") { + sources = [ "pcm/rear.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/rear.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/rear.conf" ] + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/rear.conf" ] + + copy("alsa-lib-prebuilt-pcm/surround50.conf") { + sources = [ "pcm/surround50.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/surround50.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/surround50.conf" ] + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/surround50.conf" ] + + copy("alsa-lib-prebuilt-pcm/hdmi.conf") { + sources = [ "pcm/hdmi.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/hdmi.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/hdmi.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/hdmi.conf" ] + + copy("alsa-lib-prebuilt-pcm/surround51.conf") { + sources = [ "pcm/surround51.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/surround51.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/surround51.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/surround51.conf" ] + + copy("alsa-lib-prebuilt-pcm/front.conf") { + sources = [ "pcm/front.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/front.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/front.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/front.conf" ] + + copy("alsa-lib-prebuilt-pcm/iec958.conf") { + sources = [ "pcm/iec958.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/iec958.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/iec958.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/iec958.conf" ] + + copy("alsa-lib-prebuilt-pcm/surround41.conf") { + sources = [ "pcm/surround41.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/surround41.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/surround41.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/surround41.conf" ] + + copy("alsa-lib-prebuilt-pcm/center_lfe.conf") { + sources = [ "pcm/center_lfe.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/center_lfe.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/center_lfe.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/center_lfe.conf" ] + + copy("alsa-lib-prebuilt-pcm/default.conf") { + sources = [ "pcm/default.conf" ] -+ outputs = [ "$root_out_dir/etc/pcm/default.conf" ] ++ outputs = [ "$root_out_dir/system/etc/pcm/default.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-pcm/default.conf" ] + + copy("alsa-lib-prebuilt-ctl/default.conf") { + sources = [ "ctl/default.conf" ] -+ outputs = [ "$root_out_dir/etc/ctl/default.conf" ] ++ outputs = [ "$root_out_dir/system/etc/ctl/default.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-ctl/default.conf" ] + + copy("alsa-lib-prebuilt-cards/AU8820.conf") { + sources = [ "cards/AU8820.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/AU8820.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/AU8820.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/AU8820.conf" ] + + copy("alsa-lib-prebuilt-cards/FireWave.conf") { + sources = [ "cards/FireWave.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/FireWave.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/FireWave.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/FireWave.conf" ] + + copy("alsa-lib-prebuilt-cards/ENS1371.conf") { + sources = [ "cards/ENS1371.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ENS1371.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ENS1371.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ENS1371.conf" ] + + copy("alsa-lib-prebuilt-cards/VX222.conf") { + sources = [ "cards/VX222.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VX222.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VX222.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VX222.conf" ] + + copy("alsa-lib-prebuilt-cards/CMI8788.conf") { + sources = [ "cards/CMI8788.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CMI8788.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CMI8788.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CMI8788.conf" ] + + copy("alsa-lib-prebuilt-cards/pistachio-card.conf") { + sources = [ "cards/pistachio-card.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/pistachio-card.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/pistachio-card.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/pistachio-card.conf" ] + + copy("alsa-lib-prebuilt-cards/CMI8338-SWIEC.conf") { + sources = [ "cards/CMI8338-SWIEC.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CMI8338-SWIEC.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CMI8338-SWIEC.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CMI8338-SWIEC.conf" ] + + copy("alsa-lib-prebuilt-cards/CMI8338.conf") { + sources = [ "cards/CMI8338.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CMI8338.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CMI8338.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CMI8338.conf" ] + + copy("alsa-lib-prebuilt-cards/ATIIXP-MODEM.conf") { + sources = [ "cards/ATIIXP-MODEM.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ATIIXP-MODEM.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ATIIXP-MODEM.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ATIIXP-MODEM.conf" ] + + copy("alsa-lib-prebuilt-cards/AU8830.conf") { + sources = [ "cards/AU8830.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/AU8830.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/AU8830.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/AU8830.conf" ] + + copy("alsa-lib-prebuilt-cards/ATIIXP.conf") { + sources = [ "cards/ATIIXP.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ATIIXP.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ATIIXP.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ATIIXP.conf" ] + + copy("alsa-lib-prebuilt-cards/TRID4DWAVENX.conf") { + sources = [ "cards/TRID4DWAVENX.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/TRID4DWAVENX.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/TRID4DWAVENX.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/TRID4DWAVENX.conf" ] + + copy("alsa-lib-prebuilt-cards/GUS.conf") { + sources = [ "cards/GUS.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/GUS.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/GUS.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/GUS.conf" ] + + copy("alsa-lib-prebuilt-cards/ATIIXP-SPDMA.conf") { + sources = [ "cards/ATIIXP-SPDMA.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ATIIXP-SPDMA.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ATIIXP-SPDMA.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ATIIXP-SPDMA.conf" ] + + copy("alsa-lib-prebuilt-cards/AU8810.conf") { + sources = [ "cards/AU8810.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/AU8810.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/AU8810.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/AU8810.conf" ] + + copy("alsa-lib-prebuilt-cards/aliases.conf") { + sources = [ "cards/aliases.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/aliases.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/aliases.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/aliases.conf" ] + + copy("alsa-lib-prebuilt-cards/VIA686A.conf") { + sources = [ "cards/VIA686A.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VIA686A.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VIA686A.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VIA686A.conf" ] + + copy("alsa-lib-prebuilt-cards/CMI8738-MC8.conf") { + sources = [ "cards/CMI8738-MC8.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CMI8738-MC8.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CMI8738-MC8.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CMI8738-MC8.conf" ] + + copy("alsa-lib-prebuilt-cards/Aureon51.conf") { + sources = [ "cards/Aureon51.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Aureon51.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Aureon51.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Aureon51.conf" ] + + copy("alsa-lib-prebuilt-cards/ENS1370.conf") { + sources = [ "cards/ENS1370.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ENS1370.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ENS1370.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ENS1370.conf" ] + + copy("alsa-lib-prebuilt-cards/Loopback.conf") { + sources = [ "cards/Loopback.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Loopback.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Loopback.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Loopback.conf" ] + + copy("alsa-lib-prebuilt-cards/Maestro3.conf") { + sources = [ "cards/Maestro3.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Maestro3.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Maestro3.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Maestro3.conf" ] + + copy("alsa-lib-prebuilt-cards/FWSpeakers.conf") { + sources = [ "cards/FWSpeakers.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/FWSpeakers.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/FWSpeakers.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/FWSpeakers.conf" ] + + copy("alsa-lib-prebuilt-cards/VIA8233A.conf") { + sources = [ "cards/VIA8233A.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VIA8233A.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VIA8233A.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VIA8233A.conf" ] + + copy("alsa-lib-prebuilt-cards/Audigy.conf") { + sources = [ "cards/Audigy.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Audigy.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Audigy.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Audigy.conf" ] + + copy("alsa-lib-prebuilt-cards/Echo_Echo3G.conf") { + sources = [ "cards/Echo_Echo3G.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Echo_Echo3G.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Echo_Echo3G.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Echo_Echo3G.conf" ] + + copy("alsa-lib-prebuilt-cards/ICH.conf") { + sources = [ "cards/ICH.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ICH.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ICH.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ICH.conf" ] + + copy("alsa-lib-prebuilt-cards/VIA8237.conf") { + sources = [ "cards/VIA8237.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VIA8237.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VIA8237.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VIA8237.conf" ] + + copy("alsa-lib-prebuilt-cards/ES1968.conf") { + sources = [ "cards/ES1968.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ES1968.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ES1968.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ES1968.conf" ] + + copy("alsa-lib-prebuilt-cards/EMU10K1.conf") { + sources = [ "cards/EMU10K1.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/EMU10K1.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/EMU10K1.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/EMU10K1.conf" ] + + copy("alsa-lib-prebuilt-cards/ICH4.conf") { + sources = [ "cards/ICH4.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ICH4.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ICH4.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ICH4.conf" ] + + copy("alsa-lib-prebuilt-cards/ICE1712.conf") { + sources = [ "cards/ICE1712.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ICE1712.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ICE1712.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ICE1712.conf" ] + + copy("alsa-lib-prebuilt-cards/PC-Speaker.conf") { + sources = [ "cards/PC-Speaker.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/PC-Speaker.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/PC-Speaker.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/PC-Speaker.conf" ] + + copy("alsa-lib-prebuilt-cards/EMU10K1X.conf") { + sources = [ "cards/EMU10K1X.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/EMU10K1X.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/EMU10K1X.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/EMU10K1X.conf" ] + + copy("alsa-lib-prebuilt-cards/RME9652.conf") { + sources = [ "cards/RME9652.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/RME9652.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/RME9652.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/RME9652.conf" ] + + copy("alsa-lib-prebuilt-cards/YMF744.conf") { + sources = [ "cards/YMF744.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/YMF744.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/YMF744.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/YMF744.conf" ] + + copy("alsa-lib-prebuilt-cards/CA0106.conf") { + sources = [ "cards/CA0106.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CA0106.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CA0106.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CA0106.conf" ] + + copy("alsa-lib-prebuilt-cards/ICH-MODEM.conf") { + sources = [ "cards/ICH-MODEM.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ICH-MODEM.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ICH-MODEM.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ICH-MODEM.conf" ] + + copy("alsa-lib-prebuilt-cards/VXPocket440.conf") { + sources = [ "cards/VXPocket440.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VXPocket440.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VXPocket440.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VXPocket440.conf" ] + + copy("alsa-lib-prebuilt-cards/PMacToonie.conf") { + sources = [ "cards/PMacToonie.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/PMacToonie.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/PMacToonie.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/PMacToonie.conf" ] + + copy("alsa-lib-prebuilt-cards/PMac.conf") { + sources = [ "cards/PMac.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/PMac.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/PMac.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/PMac.conf" ] + + copy("alsa-lib-prebuilt-cards/vc4-hdmi.conf") { + sources = [ "cards/vc4-hdmi.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/vc4-hdmi.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/vc4-hdmi.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/vc4-hdmi.conf" ] + + copy("alsa-lib-prebuilt-cards/Audigy2.conf") { + sources = [ "cards/Audigy2.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Audigy2.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Audigy2.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Audigy2.conf" ] + + copy("alsa-lib-prebuilt-cards/CS46xx.conf") { + sources = [ "cards/CS46xx.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CS46xx.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CS46xx.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CS46xx.conf" ] + + copy("alsa-lib-prebuilt-cards/RME9636.conf") { + sources = [ "cards/RME9636.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/RME9636.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/RME9636.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/RME9636.conf" ] + + copy("alsa-lib-prebuilt-cards/NFORCE.conf") { + sources = [ "cards/NFORCE.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/NFORCE.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/NFORCE.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/NFORCE.conf" ] + + copy("alsa-lib-prebuilt-cards/PS3.conf") { + sources = [ "cards/PS3.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/PS3.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/PS3.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/PS3.conf" ] + + copy("alsa-lib-prebuilt-cards/FM801.conf") { + sources = [ "cards/FM801.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/FM801.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/FM801.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/FM801.conf" ] + + copy("alsa-lib-prebuilt-cards/SI7018.conf") { + sources = [ "cards/SI7018.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/SI7018.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/SI7018.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/SI7018.conf" ] + + copy("alsa-lib-prebuilt-cards/SB-XFi.conf") { + sources = [ "cards/SB-XFi.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/SB-XFi.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/SB-XFi.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/SB-XFi.conf" ] + + copy("alsa-lib-prebuilt-cards/VXPocket.conf") { + sources = [ "cards/VXPocket.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VXPocket.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VXPocket.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VXPocket.conf" ] @@ -1611,56 +1611,56 @@ index 1eca8a9..bc434df 100644 - deps = alsa_lib_prebuilt_all + copy("alsa-lib-prebuilt-cards/ICE1724.conf") { + sources = [ "cards/ICE1724.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/ICE1724.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/ICE1724.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/ICE1724.conf" ] + + copy("alsa-lib-prebuilt-cards/AACI.conf") { + sources = [ "cards/AACI.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/AACI.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/AACI.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/AACI.conf" ] + + copy("alsa-lib-prebuilt-cards/USB-Audio.conf") { + sources = [ "cards/USB-Audio.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/USB-Audio.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/USB-Audio.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/USB-Audio.conf" ] + + copy("alsa-lib-prebuilt-cards/CMI8738-MC6.conf") { + sources = [ "cards/CMI8738-MC6.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/CMI8738-MC6.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/CMI8738-MC6.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/CMI8738-MC6.conf" ] + + copy("alsa-lib-prebuilt-cards/HDA-Intel.conf") { + sources = [ "cards/HDA-Intel.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/HDA-Intel.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/HDA-Intel.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/HDA-Intel.conf" ] + + copy("alsa-lib-prebuilt-cards/HdmiLpeAudio.conf") { + sources = [ "cards/HdmiLpeAudio.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/HdmiLpeAudio.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/HdmiLpeAudio.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/HdmiLpeAudio.conf" ] + + copy("alsa-lib-prebuilt-cards/Aureon71.conf") { + sources = [ "cards/Aureon71.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/Aureon71.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/Aureon71.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/Aureon71.conf" ] + + copy("alsa-lib-prebuilt-cards/VIA8233.conf") { + sources = [ "cards/VIA8233.conf" ] -+ outputs = [ "$root_out_dir/etc/cards/VIA8233.conf" ] ++ outputs = [ "$root_out_dir/system/etc/cards/VIA8233.conf" ] + + } + alsa_lib_prebuilt_all += [ ":alsa-lib-prebuilt-cards/VIA8233.conf" ] -- Gitee From ce34b6b2ba30955c26847d3474df9b85c7911fe5 Mon Sep 17 00:00:00 2001 From: jia_kongfeng Date: Fri, 15 May 2026 17:22:56 +0800 Subject: [PATCH 2/2] =?UTF-8?q?drm=20hdmi=20=E9=9F=B3=E9=A2=91=E6=8C=87?= =?UTF-8?q?=E5=8D=97?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: jia_kongfeng --- .../drm_hdmi_audio.md" | 331 ++++++++++++++++++ 1 file changed, 331 insertions(+) create mode 100644 "docs/zh-CN/DRM HDMI \351\237\263\351\242\221\346\222\255\346\224\276\345\274\200\345\217\221\346\214\207\345\215\227/drm_hdmi_audio.md" diff --git "a/docs/zh-CN/DRM HDMI \351\237\263\351\242\221\346\222\255\346\224\276\345\274\200\345\217\221\346\214\207\345\215\227/drm_hdmi_audio.md" "b/docs/zh-CN/DRM HDMI \351\237\263\351\242\221\346\222\255\346\224\276\345\274\200\345\217\221\346\214\207\345\215\227/drm_hdmi_audio.md" new file mode 100644 index 00000000..d6d941ad --- /dev/null +++ "b/docs/zh-CN/DRM HDMI \351\237\263\351\242\221\346\222\255\346\224\276\345\274\200\345\217\221\346\214\207\345\215\227/drm_hdmi_audio.md" @@ -0,0 +1,331 @@ +# 基于 DRM 框架的 HDMI 音频播放设计 + +## 背景 + +原有 HDMI 音频相关能力分散在两条链路中： + +- HDMI 驱动链路负责配置 HDMI TX audio path、ACR N/CTS、Audio InfoFrame、HPD/capability 查询等。 +- AO 音频链路负责将 PCM 数据送入 SoC 音频输出模块，并通过 `OT_AIO_I2STYPE_INNERHDMI` 选择内部 HDMI I2S 输出。 + +为了减少 SOC 音频 HAL 对原 HDMI MPI 接口的依赖，本设计将 HDMI 音频 path 配置和 HDMI 连接状态查询迁移到 DRM 私有 ioctl，由 `/dev/dri/card0` 统一承载 HDMI 音频控制能力。 + +## 设计目标 + +1. 在 DRM 驱动 `smart_drm_drv.c` 中实现 HDMI 音频 path 配置能力。 +2. SOC 音频 HAL 不再调用 `ss_mpi_hdmi_get_sink_capability()` / `ot_mpi_hdmi_get_sink_capability()` 做 HDMI caps 检查。 +3. HDMI 输出初始化时通过 DRM ioctl 打开 HDMI TX audio input。 +4. PCM 数据仍通过 AO 模块发送到 `INNERHDMI` I2S，最终进入 HDMI TX。 +5. 保持用户态音频播放主流程不变，降低对上层 Audio Framework 的影响。 + +## 非目标 + +1. 不在 HDMI TX 寄存器中直接写入 PCM 数据。 +2. 不在 DRM 驱动内完整重写 AO/DMA/I2S 播放后端。 +3. 不改变上层播放器、AudioRender、AudioSink 的播放接口语义。 + +HDMI TX 的 audio 寄存器只提供 I2S/SPDIF 输入使能、音频格式配置、Audio InfoFrame 和 ACR 参数配置，不提供 CPU 可写的 PCM data FIFO。因此 PCM 的真实播放路径仍然依赖 AO 硬件。 + +## 总体架构 + +```text +Audio Framework / Player + | + v +Audio HAL Render + | + | 1. HDMI caps/status query + v +/dev/dri/card0 +DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS + | + v +DRM connector detect / HPD + +Audio HAL HDMI output init + | + | 2. HDMI audio path enable + v +/dev/dri/card0 +DRM_IOCTL_HI3403V100_AUDIO_SET_CONFIG + | + v +smart_drm_drv.c +HDMI TX audio path + Audio InfoFrame + ACR + +AudioRenderRenderFrame() + | + | 3. PCM frame + v +ss_mpi_ao_send_frame() + | + v +AO device configured as OT_AIO_I2STYPE_INNERHDMI + | + v +Internal I2S to HDMI TX audio input + | + v +HDMI output +``` + +## 模块职责 + +### DRM 驱动 + +文件： + +- `kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/smart_vision/smart_drm_drv.c` +- `kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_audio_path.*` +- `kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_ctrl.*` +- `kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/smart_vision/ctrl/v100/regs/hdmi_reg_tx.*` + +职责： + +- 提供 HDMI 音频配置 ioctl。 +- 提供 HDMI sink status 查询 ioctl。 +- 配置 HDMI TX audio input、I2S 参数、channel status、ACR N 值。 +- 生成并写入 HDMI Audio InfoFrame。 +- 根据 DRM connector detect 结果返回 HDMI 连接状态。 + +### SOC 音频 HAL + +文件： + +- `device/soc/hisilicon/common/hal/media/audio/source/src/audio_adapter.c` +- `device/soc/hisilicon/common/hal/media/audio/source/src/audio_render.c` +- `device/soc/hisilicon/common/hal/media/audio/source/plugins/hi35xx/audio_primary_sub_port_out/audio_primary_sub_port_out.c` + +职责： + +- 使用 DRM ioctl 查询 HDMI 是否连接。 +- HDMI 输出初始化时调用 DRM ioctl 打开 HDMI audio path。 +- 配置 AO 为 `OT_AIO_I2STYPE_INNERHDMI`。 +- 使用 `ss_mpi_ao_send_frame()` 将 PCM 数据送入 AO。 + +## DRM ioctl 设计 + +### HDMI 音频 path 配置 + +ioctl 编号： + +```c +#define DRM_IOCTL_HI3403V100_AUDIO_SET_CONFIG 2 +``` + +数据结构： + +```c +struct smart_drm_audio_frame { + __u32 enable; + __u32 sample_rate; + __u32 bit_depth; + __u32 channels; + __u32 sound_intf; + __u32 tmds_clk; + __u64 pcm_addr; + __u32 pcm_bytes; + __u32 reserved; +}; +``` + +字段说明： + +- `enable`：`1` 表示打开 HDMI audio path，`0` 表示关闭。 +- `sample_rate`：音频采样率，当前支持 `32000`、`44100`、`48000`。 +- `bit_depth`：采样位宽，当前按 `16bit` 配置。 +- `channels`：声道数，支持 `2` 到 `8`。 +- `sound_intf`：HDMI TX 音频输入接口，当前实际使用 I2S。 +- `tmds_clk`：当前 TMDS clock，用于选择 ACR N 值。 +- `pcm_addr` / `pcm_bytes`：兼容测试接口字段。DRM 驱动不直接将 PCM 写入 HDMI 寄存器，PCM 由 AO 送入 HDMI TX。 + +内核处理流程： + +1. `smart_drm_audio_send_frame_ioctl()` 接收用户态参数。 +2. `smart_hdmi_audio_frame_normalize()` 校验并补齐默认参数。 +3. `smart_hdmi_audio_path_config()` 配置 HDMI TX audio path： + - 关闭 `aud_in_en`。 + - reset HDMI audio FIFO / ACR / AUD。 + - 配置 I2S layout、bit length、channel status。 + - 配置 ACR N。 + - 打开 I2S input。 + - 写入 Audio InfoFrame。 + - 打开 `aud_in_en`。 +4. `smart_hdmi_audio_pcm_receive()` 仅用于接收测试 payload，不承担实际 PCM 播放。 + +### HDMI sink status 查询 + +ioctl 编号： + +```c +#define DRM_HI3403V100_HDMI_GET_SINK_STATUS 3 +``` + +数据结构： + +```c +struct smart_drm_hdmi_sink_status { + __u32 connected; + __u32 sink_has_audio; + __u32 connector_status; + __u32 reserved; +}; +``` + +字段说明： + +- `connected`：HDMI 是否连接。 +- `sink_has_audio`：sink EDID/display info 中是否声明支持音频。 +- `connector_status`：DRM connector 原始状态。 + +内核处理流程： + +1. 遍历 DRM connector。 +2. 查找 `DRM_MODE_CONNECTOR_HDMIA` 或 `DRM_MODE_CONNECTOR_HDMIB`。 +3. 调用 connector `detect()`，底层通过 HPD 状态判断连接。 +4. 将连接状态和 audio capability 返回给用户态。 + +## SOC 音频 HAL 替换点 + +### 替换 HDMI caps 检查 + +原流程： + +```text +CheckHdmiStatus() + -> ss_mpi_hdmi_get_sink_capability() + -> ot_mpi_hdmi_get_sink_capability() +``` + +新流程： + +```text +CheckHdmiStatus() + -> open("/dev/dri/card0") + -> DRM_IOCTL_HI3403V100_HDMI_GET_SINK_STATUS +``` + +这样可以避免音频初始化阶段继续依赖原 HDMI MPI 接口。 + +### HDMI 输出初始化 + +在 `audio_primary_sub_port_out.c` 中，HDMI 输出时执行： + +```text +AudioHdmiPathIoctlSet(true, portAttr) + -> DRM_IOCTL_HI3403V100_AUDIO_SEND_FRAME + +AoSourceAttrConfig() + -> i2s_type = OT_AIO_I2STYPE_INNERHDMI + +AoInit() + -> ss_mpi_ao_set_pub_attr() + -> ss_mpi_ao_enable() + -> ss_mpi_ao_set_track_mode() +``` + +该顺序保证 HDMI TX audio input 已经打开，然后 AO 将 PCM 送到内部 HDMI I2S。 + +### PCM 发送 + +PCM 发送仍使用原 AO 链路： + +```text +AudioRenderRenderFrame() + -> AudioPrimarySubPortOutSendFrame() + -> AudioRenderFillAudioFrame() + -> ss_mpi_ao_send_frame() +``` + +这是实际音频数据通路，不经过 HDMI InfoFrame 寄存器。 + +## Audio InfoFrame 说明 + +Audio InfoFrame 不是 PCM 数据。它是 HDMI 协议中的音频元数据包，用于告诉 sink： + +- 当前音频编码类型。 +- 声道数。 +- channel allocation。 +- 采样相关描述。 + +PCM sample 不写入 `audio_pkt_header` / `audio_pkt0_low` / `audio_pkt0_high` 这些 InfoFrame 寄存器。PCM 数据由 AO 输出到 I2S，再由 HDMI TX 硬件采样并打包成 HDMI audio sample packet。 + +## 播放时序 + +```text +1. 上层选择 HDMI 输出设备。 +2. AudioAdapterCreateRender() 创建 render。 +3. CheckHdmiStatus() 通过 DRM ioctl 查询 HDMI 连接状态。 +4. AudioPrimarySubPortOutCreateTrack() 创建输出 track。 +5. ConfigAndEnableAO()： + 5.1 通过 DRM ioctl 打开 HDMI audio path。 + 5.2 设置 AO i2s_type 为 OT_AIO_I2STYPE_INNERHDMI。 + 5.3 初始化并使能 AO device。 +6. AudioRenderStart() 使能 AO channel。 +7. AudioRenderRenderFrame() 持续送 PCM。 +8. AO 硬件通过内部 I2S 将音频送到 HDMI TX。 +9. HDMI TX 根据 DRM 配置的 audio path 和 InfoFrame 输出音频。 +``` + +## 关闭时序 + +```text +1. AudioRenderStop() 禁用 AO channel。 +2. AudioPrimarySubPortOutClose() 禁用 AO device。 +3. 调用 DRM_IOCTL_HI3403V100_AUDIO_SEND_FRAME，enable = 0。 +4. DRM 驱动关闭 HDMI TX aud_in_en 和 Audio InfoFrame。 +``` + +## 错误处理 + +- DRM 设备打开失败：返回 HAL 错误，阻止 HDMI render 初始化。 +- HDMI sink status ioctl 失败：按 HDMI 未连接处理。 +- HDMI audio path ioctl 失败：不继续初始化 AO，避免 AO 送 PCM 但 HDMI TX 未打开。 +- AO 初始化失败：关闭 HDMI audio path，避免 HDMI TX audio input 残留打开。 +- AO buffer full：沿用 `OT_ERR_AO_BUF_FULL` 处理，调用方稍后重试。 + +## 当前限制 + +1. DRM 驱动没有直接 PCM 播放后端，不能替代 AO/DMA/I2S。 +2. 当前 HDMI 音频配置以 I2S 为主，SPDIF/HBRA 未作为主验证路径。 +3. 当前 sink status 依赖 DRM connector detect/HPD，`sink_has_audio` 依赖 connector display info 是否已正确解析 EDID。 +4. `tmds_clk` 当前由用户态传入默认值，后续可以从 DRM mode/connector 状态中自动获取。 +5. `sample_rate` 当前只开放常用的 `32k/44.1k/48k`。 + +## 验证方案 + +### HDMI 连接状态 + +1. 插入 HDMI 线。 +2. 创建 HDMI render。 +3. 确认日志中不再出现： + +```text +ot_mpi_hdmi_get_sink_capability +ss_mpi_hdmi_get_sink_capability +``` + +1. 确认出现 DRM 查询相关日志，且返回 connected。 + +### HDMI audio path + +1. 创建 HDMI 输出 render。 +2. 确认 `AudioHdmiPathIoctlSet(true, portAttr)` 成功。 +3. 确认 DRM audio ioctl 成功返回。 +4. 检查 HDMI TX 音频寄存器： + - `aud_in_en = 1` + - `aud_i2s_en != 0` + - Audio InfoFrame enable + +### PCM 播放 + +1. 上层播放 48k/16bit/stereo PCM。 +2. 确认 `ss_mpi_ao_send_frame()` 持续成功。 +3. 确认 HDMI 显示设备可听到音频。 + +### 关闭 + +1. 停止播放。 +2. 关闭 render。 +3. 确认 DRM audio ioctl 以 `enable = 0` 调用成功。 +4. 确认 HDMI TX audio input 被关闭。 + -- Gitee